Nonvolatile memory device and method for erasing data in the device

Abstract

In a method for erasing data in a nonvolatile memory device including one or more memory blocks, a plurality of memory cells are arranged in a vertical direction in each memory block. One or more erase cycles are performed on an entire first memory block in the one or more memory blocks. After the erase cycles are successfully completed, a first partial verify operation is performed on one or more of a plurality of groups in the first memory block. After the first partial verify operation is successfully completed, it is determined whether a second partial verify operation is required for a group in the one or more groups. The second partial verify operation is performed on one or more of a plurality of subgroups in the first group that require the second partial verify operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0085403 filed on July 10, 2020, in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Example embodiments relate generally to semiconductor integrated circuits, and more particularly to a method of erasing data in a nonvolatile memory device, a nonvolatile memory device performing the method, and a memory controller performing the method. Background Art

[0004] Semiconductor memory devices can generally be divided into two categories depending on whether they retain stored data when disconnected from the power supply. These categories include volatile memory devices (which lose stored data when disconnected from the power supply) and non-volatile memory devices (which retain stored data when disconnected from the power supply). Volatile memory devices can perform read and write operations at high speed, while the contents stored therein are lost when the power is cut off. Non-volatile memory devices can retain the contents stored therein even when the power is cut off, which means that they can be used to store data that must be retained regardless of whether they are powered on or not. Recently, semiconductor memory devices with memory cells stacked "vertically" (i.e., in three dimensions (3D)) have been studied to improve the capacity and integration density of semiconductor memory devices. Summary of the Invention

[0005] Example embodiments of the present disclosure provide a method of erasing data in a nonvolatile memory device including memory cells stacked in three dimensions, which method can improve characteristics and reliability of a data erasing operation.

[0006] Example embodiments of the present disclosure provide a nonvolatile memory device and a memory controller that perform a method of erasing data.

[0007] According to an example embodiment, in a method for erasing data in a nonvolatile memory device including one or more memory blocks, a plurality of memory cells are arranged in a vertical direction in each memory block. One or more erase cycles are performed on an entire first memory block in the one or more memory blocks. The erase cycles include an erase operation and an erase verify operation. After the erase cycles are successfully completed, a first partial verify operation is performed on one or more of a plurality of groups in the first memory block. The first memory block is divided into a plurality of groups. After the first partial verify operation is successfully completed, it is determined whether a second partial verify operation is required for a group in the one or more groups. A second partial verify operation is performed on one or more of a plurality of subgroups in the first group that require the second partial verify operation within the plurality of groups. The first group is divided into a plurality of subgroups.

[0008] According to example embodiments, a nonvolatile memory device includes a memory block and a control circuit. The memory block includes a plurality of memory cells arranged in a vertical direction. The control circuit performs one or more erase cycles on the entire memory block, performs a first partial verify operation on one or more of a plurality of groups in the memory block, determines whether a second partial verify operation is required for the one or more groups, and performs a second partial verify operation on one or more of a plurality of subgroups in the group requiring the second partial verify operation within the plurality of groups. The erase cycle includes an erase operation and an erase verify operation. The memory block is divided into a plurality of groups. The group requiring the second partial verify operation is divided into a plurality of subgroups.

[0009] According to example embodiments, in a method for erasing data in a nonvolatile memory device including one or more memory blocks, a plurality of memory cells are arranged vertically in each memory block. One or more erase cycles are performed on an entire first memory block in the one or more memory blocks. The erase cycle includes an erase operation performed using an erase voltage and an erase-verify operation performed using a first verify voltage having a first verify level. After the erase cycle is successfully completed, a first local verify operation is performed on one or more of a plurality of groups in the first memory block using a first reference number and a second verify voltage having a second verify level different from the first verify level. The memory block is divided into a plurality of groups. After the first local verify operation is successfully completed, a second reference number less than or equal to the first reference number is used to determine whether a second local verify operation is required for a group in the one or more groups. A second local verify operation is performed on all or some of a plurality of subgroups in a group requiring the second local verify operation in the plurality of groups using a third verify level different from the first verify level and a third verify voltage having a third reference number different from the first and second reference numbers. The group requiring the second local verify operation is divided into a plurality of subgroups. When at least one of the first partial verification operation and the second partial verification operation has failed, the first memory block is indicated as a bad block.

[0010] According to an example embodiment, a memory controller includes a processor and a buffer memory. The processor generates an erase command and an address corresponding to a first memory block of a nonvolatile memory device, causing the nonvolatile memory device to perform the following operations based on the erase command and the address: performing one or more erase cycles on the entire first memory block; performing a first partial verification operation on one or more of a plurality of groups in the memory block after the erase cycle is successfully completed; determining whether a second partial verification operation is required for a group in the one or more groups after the first partial verification operation is successfully completed; and performing a second partial verification operation on one or more of a plurality of subgroups in a first group of the one or more groups that require the second partial verification operation. The erase cycle includes an erase operation and an erase verification operation. The first memory block is divided into a plurality of groups. The first group that requires the second partial verification operation is divided into a plurality of subgroups. The buffer memory stores an address mapping table including address information of the first memory block. When at least one of the first partial verification operation and the second partial verification operation has failed, the processor is configured to receive a bad block indication signal for the first memory block from the non-volatile memory device, load the address mapping table from the buffer memory, update the address mapping table based on the bad block indication signal to invalidate address information of the first memory block, and store the updated address mapping table in the buffer memory.

[0011] In a method of erasing data, a nonvolatile memory device, and a memory controller according to example embodiments, a block erase operation can be performed on a memory block by performing one or more erase cycles on the entire memory block, a first partial verification operation can be performed by applying a predetermined first criterion to the memory block in groups, a second predetermined criterion can be additionally applied to the memory block in groups to determine whether a second partial verification operation is required, and a second partial verification operation can be performed on groups requiring the second partial verification operation in sub-groups. Thus, the performance and reliability of the block erase operation can be improved or enhanced, and a situation can be prevented where an error is not detected during an erase operation and an unrecoverable error occurs during a later programming operation, resulting in loss of user data. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a flowchart illustrating a method of erasing data in a nonvolatile memory device according to example embodiments.

[0014] Figure 2 is a block diagram illustrating a nonvolatile memory device according to example embodiments.

[0015] Figure 3 is a diagram showing a method of including Figure 2 A perspective view of an example of a memory block in a memory cell array of a nonvolatile memory device.

[0016] Figure 4 is a diagram showing a reference according to an example embodiment Figure 3 A circuit diagram depicting the equivalent circuit of the memory block.

[0017] Figure 5 is included in accordance with an example embodiment Figure 3 and Figure 4 A plan view of an example of a cell region in a memory cell array.

[0018] Figure 6A 、 Figure 6B and Figure 6C is used to describe the Figure 5 Figure 2 shows a channel hole formed in the cell area.

[0019] Figure 7 is a diagram showing a method according to an example embodiment Figure 1 A flowchart of an example of performing one or more erase cycles in FIG.

[0020] Figure 8is used to describe the Figure 7 A diagram of the operation of performing one or more erase cycles.

[0021] Figure 9 、 Figure 10 and Figure 11 is a diagram showing a method according to an example embodiment Figure 1 Flowchart of an example of performing a first partial verification operation, determining whether a second partial verification operation is required, and performing the second partial verification operation.

[0022] Figure 12 is a diagram showing a method according to an example embodiment Figure 1 A flowchart of an example of performing a first local verification operation in .

[0023] Figure 13 and Figure 14 is used to describe the Figure 12 Graph of the operation.

[0024] Figure 15 is a diagram showing a method according to an example embodiment Figure 1 A flowchart of an example of determining whether a second partial verification operation is required.

[0025] Figure 16 is used to describe the Figure 15 Graph of the operation.

[0026] Figure 17 is a diagram showing a method according to an example embodiment Figure 1 A flowchart of an example of performing a second local verification operation in .

[0027] Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 19C and Figure 19D is used to describe the Figure 17 Graph of the operation.

[0028] Figure 20 is a block diagram illustrating a memory system according to example embodiments.

[0029] Figure 21 is a flowchart illustrating a method of operating a memory system according to example embodiments.

[0030] Figure 22 is a block diagram illustrating a memory controller according to example embodiments.

[0031] Figure 23A and Figure 23B is used to describe the Figure 22Diagram of the operation of the memory controller.

[0032] Figure 24 is a block diagram illustrating a memory device including a nonvolatile memory device according to example embodiments.

[0033] Figure 25 is a cross-sectional view of a nonvolatile memory device according to example embodiments. DETAILED DESCRIPTION

[0034] Various example embodiments will be described more fully with reference to the accompanying drawings that illustrate embodiments. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, like reference numerals refer to like elements.

[0035] Figure 1 is a flowchart illustrating a method of erasing data in a nonvolatile memory device according to example embodiments.

[0036] Reference Figure 1 The method of erasing data according to an example embodiment is performed by a nonvolatile memory device including one or more memory blocks, and a plurality of memory cells are arranged in a vertical direction in each memory block. For example, each memory block includes a plurality of memory cells stacked in a direction intersecting with a substrate (e.g., substantially perpendicular to the substrate). Figures 2 to 5 as well as Figures 6A to 6C The configuration of the nonvolatile memory device and the memory block is described in detail.

[0037] In a method of erasing data in a nonvolatile memory device according to an example embodiment, an erase cycle including an erase operation and an erase verification operation is performed on the entire memory block one or more times (step S100). For example, the erase operation may be performed using an erase voltage, and the erase verification operation may be performed using an erase verification voltage having a first verification level. Figure 7 and Figure 8 Step S100 will be described in detail.

[0038] After the erase cycle is successfully completed, the memory block is divided into a plurality of groups, and a first local verification operation is performed on one or more of the plurality of groups in the memory block (step S200). For example, the plurality of groups may be divided based on a plurality of word lines connected to the memory cells in the memory block. For example, the first local verification operation may be performed using a first reference number (or amount) and an erase verification voltage having a second verification level different from the first verification level. For example, when performing the first local verification operation, the erase verification voltage may have the second verification level. Figure 12 、 Figure 13 and Figure 14 Step S200 is described in detail.

[0039] In an example embodiment, as will be referred to Figure 14 As described, the first local verification operation may be performed on all of the plurality of groups in the memory block, or may be performed on only some of the plurality of groups in the memory block.

[0040] After the first partial verification operation is successfully completed, it is determined whether a second partial verification operation is required for a group in the one or more groups (step S300). For example, the operation of determining whether a second partial verification operation is required can be performed using a second reference number (or amount). For example, the second reference number can be different from or equal to the first reference number. Figure 15 and Figure 16 Step S300 will be described in detail.

[0041] In an example embodiment, as will be referred to Figure 15 and Figure 16 As described, it is determined whether the second local verification operation is required for all of the plurality of groups in the memory block, or it is determined whether the second local verification operation is required for only some of the plurality of groups.

[0042] The group requiring the second local verification operation is divided into a plurality of sub-groups, and the second local verification operation is performed on one or more of the plurality of sub-groups in the group requiring the second local verification operation among the plurality of groups (step S400). For example, the plurality of sub-groups may also be divided based on a plurality of word lines. For example, the second local verification operation may be performed using an erase verification voltage having a third verification level different from the first verification level and a third reference number (or amount) different from the first and second reference numbers. For example, when performing the second local verification operation, the erase verification voltage may have a third verification level. The reference number may be Figure 17 18 to describe step S400 in detail.

[0043] In some example embodiments, as will be referred to Figure 19A 、 Figure 19B 、 Figure 19C and Figure 19D As described, the second local verification operation may be performed on all of the plurality of subsets, or may be performed on only some of the plurality of subsets.

[0044] In some example embodiments, when at least one of the first partial verification operation and the second partial verification operation has failed, the memory block may be indicated as a bad block. For example, the memory block may be considered or processed as a run-time bad block (RTBB), and the address information of the memory block may be invalidated so that the memory block is no longer used, as will be described with reference to FIG. Figure 21 described.

[0045] In some example embodiments, as will be referred to Figure 9 、 Figure 10 and Figure 11 As described, the order of performing steps S200, S300 and S400 for multiple groups may be changed. The operations of steps S200, S300 and S400 may be referred to as erasure protection code (eg, blocking or recovery code) operations or local verification protection code operations.

[0046] In a method for erasing data in a nonvolatile memory device according to an example embodiment, a block erase operation can be performed on a memory block by performing one or more erase cycles on the entire memory block, a first partial verify operation can be performed by applying a predetermined first criterion (or condition) to the memory block on a group-by-group basis (e.g., for each group), a second partial verify operation can be determined to determine whether a second partial verify operation is required by additionally applying a predetermined second criterion to the memory block on a group-by-group basis, and a second partial verify operation can be performed on a sub-group basis for groups requiring the second partial verify operation. As described above, performing the first partial verify operation after the erase cycle and selectively performing the second partial verify operation after the first partial verify operation can be referred to as post-erase adaptive verify. Therefore, the performance and reliability of block erase operations can be improved or enhanced, and a situation can be prevented where an error is not detected during an erase operation and an unrecoverable error (e.g., an uncorrectable error correction code (UECC)) occurs during a later programming operation, resulting in loss of user data.

[0047] In some example embodiments, the method of erasing data in a nonvolatile memory device according to example embodiments may be performed based on a command and an address for performing a block erase operation on a memory block (eg, when the command and the address are received).

[0048] Although not shown in detail, the remaining memory blocks other than the above-mentioned memory blocks for the nonvolatile memory device may be as described with reference to FIG. Figure 1 The operations of steps S100, S200, S300 and S400 are performed identically as described.

[0049] Figure 2 is a block diagram illustrating a nonvolatile memory device according to example embodiments.

[0050] Reference Figure 2 , the nonvolatile memory device 100 includes a memory cell array 110 , an address decoder 120 , a page buffer circuit 130 , a data input / output (I / O) circuit 140 , a voltage generator 150 , and a control circuit 160 .

[0051] The memory cell array 110 is connected to the address decoder 120 via a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL. The memory cell array 110 is also connected to the page buffer circuit 130 via a plurality of bit lines BL. The memory cell array 110 may include a plurality of memory cells (e.g., a plurality of nonvolatile memory cells) connected to the plurality of word lines WL and the plurality of bit lines BL. The memory cell array 110 may be divided into a plurality of memory blocks BLK1, BLK2, ..., and BLKz, each of which includes memory cells. In addition, each of the plurality of memory blocks BLK1, BLK2, ..., and BLKz may be divided into a plurality of pages.

[0052] In some example embodiments, as will be referred to Figure 3 and Figure 4 As described, the memory cell array 110 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In this example, the memory cell array 110 may include a plurality of cell strings (e.g., a plurality of vertical NAND strings) that are vertically oriented such that at least one memory cell is located above another memory cell.

[0053] The control circuit 160 receives the signal from the outside (e.g. Figure 20 The memory controller 600 in the nonvolatile memory device 100 receives a command CMD and an address ADDR and controls the erase, program, and read operations of the nonvolatile memory device 100 based on the command CMD and the address ADDR. The erase operation may include performing a series of erase cycles, and the program operation may include performing a series of program cycles. Each program cycle may include a program operation and a program verification operation. Each erase cycle may include an erase operation and an erase verification operation. The read operation may include a normal read operation and a data recovery read operation.

[0054] For example, the control circuit 160 may generate a control signal CON for controlling the voltage generator 150, may generate a control signal PBC for controlling the page buffer circuit 130 based on the command CMD, and may generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit 160 may provide the row address R_ADDR to the address decoder 120, and may provide the column address C_ADDR to the data I / O circuit 140.

[0055] In addition, the control circuit 160 may control the address decoder 120, the page buffer circuit 130, the data I / O circuit 140, and the voltage generator 150 so that the nonvolatile memory device 100 performs reference Figure 1 The method of erasing data according to example embodiments is described. For example, the control circuit 160 may perform one or more erase cycles on the entire memory block, may perform a first local verification operation in units of groups after the erase cycles are successfully completed, may determine whether a second local verification operation in units of groups is required after the first local verification operation is successfully completed, and may perform a second local verification operation in units of sub-groups for the groups requiring the second local verification operation.

[0056] The address decoder 120 may be connected to the memory cell array 110 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL.

[0057] For example, in a data erase / write / read operation, based on the row address R_ADDR, the address decoder 120 can determine at least one of the multiple word lines WL as a selected word line, and can determine the remaining or remaining word lines of the multiple word lines WL except the selected word line as unselected word lines.

[0058] In addition, in data erase / write / read operations, based on the row address R_ADDR, the address decoder 120 can determine at least one of the multiple string selection lines SSL as a selected string selection line, and can determine the remaining or remaining string selection lines of the multiple string selection lines SSL except the selected string selection line as unselected string selection lines.

[0059] In addition, in data erase / write / read operations, based on the row address R_ADDR, the address decoder 120 can determine at least one of the multiple ground selection lines GSL as a selected ground selection line, and can determine the remaining or remaining ground selection lines of the multiple ground selection lines GSL except the selected ground selection line as unselected ground selection lines.

[0060] The voltage generator 150 may generate a voltage VS for operation of the nonvolatile memory device 100 based on the power PWR and the control signal CON. The voltage VS may be applied to a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL via the address decoder 120. For example, the voltage VS may include a reference signal. Figure 1In addition, the voltage generator 150 may generate an erase voltage VERS for a data erase operation based on the power PWR and the control signal CON. The erase voltage VERS may be applied to the memory cell array 110 directly or via the bit line BL.

[0061] For example, during an erase operation, the voltage generator 150 may apply an erase voltage VERS to a common source line and / or bit line BL of a memory block (e.g., a selected memory block) via the address decoder 120 and may apply an erase enable voltage (e.g., a ground voltage) to all or a portion of the word lines of the memory block. Furthermore, during an erase verify operation, the voltage generator 150 may apply an erase verify voltage VEVFY to all word lines of the memory block simultaneously or to the word lines one by one in sequence.

[0062] For example, during a program operation, the voltage generator 150 may apply a program voltage VPGM to a selected word line and a program pass voltage VPPASS to unselected word lines via the address decoder 120. Furthermore, during a program verification operation, the voltage generator 150 may apply a program verification voltage VPVFY to a selected word line and a verification pass voltage VVPASS to unselected word lines via the address decoder 120.

[0063] In addition, during a normal read operation, the voltage generator 150 may apply a read voltage VREAD to a selected word line and may apply a read pass voltage VRPASS to unselected word lines via the address decoder 120. During a data recovery read operation, the voltage generator 150 may apply a read voltage VREAD to word lines adjacent to a selected word line and may apply a recovery read voltage VRREAD to the selected word line via the address decoder 120.

[0064] The page buffer circuit 130 may be connected to the memory cell array 110 via a plurality of bit lines BL. The page buffer circuit 130 may include a plurality of page buffers. In some example embodiments, each page buffer may be connected to one bit line. In other example embodiments, each page buffer may be connected to two or more bit lines.

[0065] The page buffer circuit 130 may store data DAT to be programmed into the memory cell array 110 or may read data DAT sensed from the memory cell array 110. For example, the page buffer circuit 130 may operate as a write driver or a sense amplifier according to an operation mode of the nonvolatile memory device 100.

[0066] The data I / O circuit 140 may be connected to the page buffer circuit 130 via a data line DL. Based on the column address C_ADDR, the data I / O circuit 140 may transmit data from the outside of the nonvolatile memory device 100 (eg, from the page buffer circuit 130). Figure 20 The data DAT from the memory cell array 110 may be provided to the memory controller 600 in the nonvolatile memory device 100, or the data DAT from the memory cell array 110 may be provided to the outside of the nonvolatile memory device 100 (eg, to the memory controller 600 in the nonvolatile memory device 100). Figure 20 Memory controller 600 in FIG.

[0067] Figure 3 is a diagram showing a method of including Figure 2 A perspective view of an example of a memory block in a memory cell array of a nonvolatile memory device.

[0068] Reference Figure 3 The memory block BLKi includes a plurality of cell strings (eg, a plurality of vertical NAND strings) formed on a substrate in a three-dimensional structure (or vertical structure). The memory block BLKi includes a structure extending along a first direction D1, a second direction D2, and a third direction D3.

[0069] A substrate 111 is provided. For example, the substrate 111 may have a well having a first type of charge carrier impurity (e.g., a first conductivity type) therein. For example, the substrate 111 may have a p-well formed by implanting a Group 3 element such as boron (B). In particular, the substrate 111 may have a pocket p-well disposed within an n-well. In one embodiment, the substrate 111 has a p-type well (or a p-type pocket well). However, the conductivity type of the substrate 111 is not limited to p-type.

[0070] A plurality of doping regions 311, 312, 313, and 314 are provided in / on the substrate 111, arranged along the second direction D2. These plurality of doping regions 311 to 314 may have a second type of charge carrier impurities (e.g., a second conductivity type) different from the first type of the substrate 111. In one embodiment of the present invention, the first to fourth doping regions 311 to 314 may have an n-type conductivity. However, the conductivity type of the first to fourth doping regions 311 to 314 is not limited to an n-type conductivity type.

[0071] On the substrate 111, a plurality of insulating materials 112 extending along the first direction D1 are sequentially provided along the third direction D3 in the region between the first doping region 311 and the second doping region 312. For example, the plurality of insulating materials 112 are provided along the third direction D3 and are spaced apart at a specific distance. For example, the insulating materials 112 may include an insulating material such as an oxide layer.

[0072] A plurality of pillars 113 penetrating the insulating material along the third direction D3 are sequentially disposed along the first direction D1 on the substrate 111 between the first doping region 311 and the second doping region 312. For example, the plurality of pillars 113 penetrate the insulating material 112 to contact the substrate 111.

[0073] In some example embodiments, each pillar 113 may include a variety of materials. For example, the channel layer 114 of each pillar 113 may include a silicon material having a first conductivity type. For example, the channel layer 114 of each pillar 113 may include a silicon material having the same conductivity type as the substrate 111. In one embodiment of the present invention, the channel layer 114 of each pillar 113 includes p-type silicon. However, the channel layer 114 of each pillar 113 is not limited to p-type silicon.

[0074] The inner material 115 of each pillar 113 includes an insulating material. For example, the inner material 115 of each pillar 113 may include an insulating material such as silicon oxide. In some examples, the inner material 115 of each pillar 113 may include an air gap. As discussed herein, the term "air" may refer to atmospheric air or other gases that may be present during the manufacturing process.

[0075] An insulating layer 116 is provided along the exposed surfaces of the insulating material 112, the pillars 113, and the substrate 111 in the region between the first doping region 311 and the second doping region 312. For example, the insulating layer 116 provided on the surface of the insulating material 112 may be interposed between the pillars 113 and the plurality of stacked first conductive materials 211, 221, 231, 241, 251, 261, 271, 281, and 291, as shown. In some examples, the insulating layer 116 may not be provided along the third direction D3 on the end surface of the insulating material 112. In this example, the ground select line GSL (e.g., 211) is the bottommost of the stack of first conductive materials 211 to 291, while the string select line SSL (e.g., 291) is the topmost of the stack of first conductive materials 211 to 291.

[0076] A plurality of first conductive materials 211 to 291 are provided on a surface of the insulating layer 116 in a region between the first doping region 311 and the second doping region 312. For example, the first conductive material 211 extending along the first direction D1 is provided between the insulating material 112 adjacent to the substrate 111 and the substrate 111. More specifically, the first conductive material 211 extending along the first direction D1 is provided between the insulating layer 116 and the substrate 111 at the bottom of the insulating material 112 adjacent to the substrate 111.

[0077] The first conductive material extending along the first direction D1 is provided between the insulating layer 116 at the top of a specific insulating material among the insulating materials 112 and the insulating layer 116 at the bottom of the specific insulating material among the insulating materials 112. For example, a plurality of first conductive materials 221 to 281 extending along the first direction D1 are provided between the insulating materials 112, and it can be understood that the insulating layer 116 is provided between the insulating material 112 and the first conductive materials 221 to 281. The first conductive materials 211 to 291 can be formed of a conductive metal, but in other embodiments of the present invention, the first conductive materials 211 to 291 can include a conductive material such as polysilicon.

[0078] The same structure as that on the first doping region 311 and the second doping region 312 can be provided in the region between the second doping region 312 and the third doping region 313. In the region between the second doping region 312 and the third doping region 313, a plurality of insulating materials 112 extending along the first direction D1 are provided. A plurality of pillars 113 are provided, which are sequentially arranged along the first direction D1 and penetrate the plurality of insulating materials 112 along the third direction D3. An insulating layer 116 is provided on the exposed surfaces of the plurality of insulating materials 112 and the plurality of pillars 113, and a plurality of first conductive materials 211 to 291 extend along the first direction D1. Similarly, the same structure as that on the first doping region 311 and the second doping region 312 can be provided in the region between the third doping region 313 and the fourth doping region 314.

[0079] A plurality of drain regions 320 are provided on the plurality of pillars 113, respectively. The drain regions 320 may include a silicon material doped with a second type of charge carrier impurity different from the first type of charge carrier impurity. For example, the drain regions 320 may include a silicon material doped with an n-type dopant. In one embodiment of the present invention, the drain regions 320 may include an n-type silicon material. However, the drain regions 320 are not limited to n-type silicon materials.

[0080] A plurality of second conductive materials 331, 332, and 333 extending along the second direction D2 are provided on the drain region. The second conductive materials 331 to 333 are arranged along the first direction D1 and are spaced apart from each other by a specific distance. The second conductive materials 331 to 333 are respectively connected to the drain region 320 in corresponding regions. The drain region 320 and the second conductive material 333 extending along the second direction D2 can be connected by each contact plug. Each contact plug can be, for example, a conductive plug formed of a conductive material such as a metal. The second conductive materials 331 to 333 may include a metal material. In some examples, the second conductive materials 331 to 333 may include a conductive material such as polysilicon.

[0081] exist Figure 3In the example of FIG. 1 , first conductive materials 211 to 291 can be used to form word lines WL, string select lines SSL, and ground select lines GSL. For example, first conductive materials 221 to 281 can be used to form word lines WL, where conductive materials belonging to the same layer can be interconnected. Second conductive materials 331 to 333 can be used to form bit lines BL. The number of layers of first conductive materials 211 to 291 can vary depending on the process and control technology.

[0082] Figure 4 is a diagram showing reference according to an example embodiment Figure 3 A circuit diagram depicting the equivalent circuit of the memory block.

[0083] Figure 4 The memory block BLKi may be formed on a substrate in a three-dimensional structure (or a vertical structure). For example, a plurality of NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

[0084] Reference Figure 4 , the memory block BLKi may include a plurality of NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each NAND string NS11 to NS33 may include a string selection transistor SST; a plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8; and a ground selection transistor GST. For example, the bit lines BL1 to BL3 may correspond to Figure 3 The second conductive materials 331 to 333 in the Figure 3 The first to fourth doping regions 311 to 314 in the transistor are interconnected to form a common source line CSL.

[0085] Each string selection transistor SST can be connected to a corresponding string selection line (one of SSL1, SSL2, and SSL3). A plurality of memory cells MC1 to MC8 can be connected to corresponding word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, respectively. Each ground selection transistor GST can be connected to a corresponding ground selection line (one of GSL1, GSL2, and GSL3). Each string selection transistor SST can be connected to a corresponding bit line (for example, one of BL1 to BL3), and each ground selection transistor GST can be connected to a common source line CSL. Figure 4In the example, some string selection transistors SST are connected to the same bit line (e.g., one of BL1 to BL3) to connect corresponding NAND strings to the same bit line by appropriate selection via selection voltages applied to appropriate string selection lines SSL1 to SSL3 and ground selection lines GSL1 to GSL3.

[0086] Cell strings commonly connected to one bit line may be formed into a column, and cell strings connected to one string selection line may form a row. For example, cell strings NS11, NS21, and NS31 connected to the first bit line BL1 may correspond to the first column, and cell strings NS11, NS12, and NS13 connected to the first string selection line SSL1 may form the first row.

[0087] Word lines (e.g., WL1) of the same height may be connected in common, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 may be separated. Memory cells located in the same semiconductor layer share one word line. Cell strings in the same row share one string select line. A common source line CSL is commonly connected to all cell strings.

[0088] exist Figure 4 , memory block BLKi is shown as being connected to eight word lines WL1 to WL8 and three bit lines BL1 to BL3, and each of NAND strings NS11 to NS33 is shown as including eight memory cells MC1 to MC8. However, the present invention is not limited thereto. In some example embodiments, each memory block may be connected to any number of word lines and bit lines, and each NAND string may include any number of memory cells.

[0089] A three-dimensional vertical array structure may include vertical NAND strings that are vertically oriented such that at least one memory cell is located above another memory cell. At least one memory cell may include a charge trapping layer. The following patent documents are incorporated herein by reference in their entirety and describe suitable configurations for memory cell arrays including a 3D vertical array structure, wherein the three-dimensional memory array is configured in multiple layers with word lines and / or bit lines shared between the layers: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0090] Although the memory cell array included in the nonvolatile memory device according to example embodiments is described based on a NAND flash memory device, the nonvolatile memory device according to example embodiments may be any nonvolatile memory device, for example, a phase random access memory (PRAM), a resistive random access memory (RRAM), a nano-floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a thyristor random access memory (TRAM), etc.

[0091] Figure 5 is included in accordance with an example embodiment Figure 3 and Figure 4 A plan view of an example of a cell region in a memory cell array.

[0092] Reference Figure 5 , the cell region CR may include a plurality of channel holes CH.

[0093] The channel hole size, such as the channel hole diameter, may vary depending on the location within the cell region CR. For example, the portion adjacent to the first edge EDG1 and the second edge EDG2 may have a relatively low circumferential density, and thus the channel holes CHa adjacent to the first edge EDG1 and the second edge EDG2 may have a diameter different from that of the other channel holes CH. The diameter of the channel hole CHb located at the center of the cell region CR may be larger than the diameter of the channel holes CHa adjacent to the first edge EDG1 and the second edge EDG2. The memory block BLKa may be adjacent to the first edge EDG1 and may be spaced apart from the first edge EDG1 by a first distance d1. The memory block BLKb may not be adjacent to the first edge EDG1 and the second edge EDG2, may be at the center of the cell region CR, and may be spaced apart from the first edge EDG1 by a second distance d2. The second distance d2 may be greater than the first distance d1. The first diameter of the channel hole CHa included in the memory block BLKa may be smaller than the second diameter of the channel hole CHb included in the memory block BLKb.

[0094] Figure 6A 、 Figure 6B and Figure 6C is used to describe the formation of Figure 5 Figure 4 shows a diagram of the channel holes in the cell area. Figure 6A and Figure 6B is a plan view of an example of a channel hole. Figure 6C is a cross-sectional view of an example of a channel hole.

[0095] Reference Figure 6A and Figure 6B, pillars including the channel layer 114 and the inner layer 115 may be formed in the first channel hole CHa included in the memory block BLKa and the second channel hole CHb included in the memory block BLKb. A first diameter Da of the first channel hole CHa may be smaller than a second diameter Db of the second channel hole CHb.

[0096] Reference Figure 6C , a column including the channel layer 114 and the inner layer 115 may be formed in each channel hole CH. For example, the channel hole CH may be drilled from top to bottom, and a diameter Dc at a position where formation of the channel hole CH starts (e.g., top) may be greater than a diameter Dd at a position where formation of the channel hole CH ends (e.g., bottom).

[0097] As described above, even within one channel hole, the diameter of the channel hole may vary depending on the position in the cell region CR, and the diameter of the channel hole may also vary depending on the third direction D3. Due to the difference in channel hole diameter, a difference in characteristics of the memory cell and / or a defect in the memory cell may occur. For example, a word line defect caused by a non-open (NOP) string defect may occur due to a Figure 6C The position (eg, bottom) where the formation of the middle channel hole CH ends is not fully opened. Due to such a word line defect, an error may not be detected during an erase operation, and an unrecoverable error may occur during a later program operation, resulting in loss of user data.

[0098] When performing a method of erasing data in a non-volatile memory device according to example embodiments, defects in a specific area (e.g., a lower area) caused by NOPs can be detected by using additional verification after erasure (e.g., a vulnerable area in a memory block can be selected and additional verification can be performed in the selected area), thereby preventing user data loss due to unrecoverable errors.

[0099] Figure 7 is a diagram showing a method according to an example embodiment Figure 1 A flowchart of an example of performing one or more erase cycles in FIG. Figure 8 is used to describe the Figure 7 A diagram of the operation of performing one or more erase cycles.

[0100] Reference Figure 1 、 Figure 7 and Figure 8When one or more erase cycles are performed (step S100), an erase operation may be performed on the entire memory block based on the erase voltage VERS (step S110). For example, a plurality of memory cells included in a memory block may be connected to a plurality of word lines. During the erase operation, the erase voltage VERS may be applied to a common source line and / or a bit line of the memory block, and an erase enable voltage (e.g., a ground voltage) may be applied to all of the plurality of word lines of the memory block.

[0101] Afterwards, an erase verification operation may be performed on the entire memory block based on the erase verification voltage (step S120).For example, during the erase verification operation, an erase verification operation with a first verification level may be applied to all of the plurality of word lines of the memory block.

[0102] Executing the operations of steps S110 and S120 once may represent executing one erase cycle.

[0103] When it is determined that the erase verification operation is successful (step S130: YES), the process may be terminated without further performing an erase cycle.

[0104] When it is determined that the erase verification operation has failed (step S130: No), this means that the plurality of memory cells in the memory block do not have the desired erase state (e.g., the desired threshold voltage distribution), and therefore, an erase cycle may be performed again. For example, at least one of the level of the erase voltage and the level of the erase verification voltage may be changed (step S140), and steps S110 and S120 may be performed again based on the erase voltage level changed and / or the erase verification voltage level changed. The above operations may be repeated until the erase verification operation is successful.

[0105] In some example embodiments, steps S110 , S120 , S130 , and S140 may be performed based on an incremental step pulse erase (ISPE) scheme.

[0106] For example, Figure 8 As shown, a plurality of erase loops ELOOP1, ELOOP2, ELOOP3, ..., and ELOOPK may be sequentially performed, where K is a natural number greater than or equal to 2. For each erase loop, one of erase operations EO1, EO2, EO3, ..., and EOK using an erase voltage VERS and a corresponding one of erase verification operations EV1, EV2, EV3, ..., and EVK using an erase verification voltage VEVFY may be sequentially performed. The level of the erase voltage VERS in the current erase loop may be higher than that of the erase voltage VERS in the previous erase loop, and the erase verification voltage VEVFY may have a constant level (e.g., a first verification level VEVL1).

[0107] For example, in the first erase loop ELOOP1, the erase voltage VERS may have an initial erase level VERL1. In the second erase loop ELOOP2, the erase voltage VERS may have a level increased by a step level ΔVERL from the initial erase level VERL1. In the third erase loop ELOOP3, the erase voltage VERS may have a level increased by a step level ΔVERL from the level of the erase voltage VERS in the second erase loop ELOOP2. In the Kth erase loop ELOOPK as the last erase loop, the erase voltage VERS may have a final erase level VERLF.

[0108] although Figure 8 1 shows that only the level of the erase voltage VERS increases as the erase cycle is repeated, but the present invention is not limited thereto, and the level of the erase verification voltage VEVFY may also increase. In some example embodiments, as the erase cycle is repeated, the level of the erase voltage VERS may decrease and / or the level of the erase verification voltage VEVFY may decrease. In addition, although Figure 8 It is shown that the level of the erase voltage VERS increases at a fixed level (eg, a step level ΔVERL), but the present invention is not limited thereto, and the amount of change of the erase voltage VERS may vary for each erase loop.

[0109] Figure 9 、 Figure 10 and Figure 11 is a diagram showing a method according to an example embodiment Figure 1 Flowchart of an example of performing a first partial verification operation, determining whether a second partial verification operation is required, and performing the second partial verification operation.

[0110] Reference Figure 1 、 Figure 9 、 Figure 10 and Figure 11 In a method of erasing data in a nonvolatile memory device according to example embodiments, a plurality of groups included in a memory block and being targets of a first partial verification operation and a second partial verification operation may include first to X-th groups, where X is a natural number greater than or equal to 2. The order of performing the first partial verification operation, determining whether the second partial verification operation is required, and performing the second partial verification operation on the first to X-th groups may be implemented in various manners.

[0111] In some example embodiments, Figure 9 As shown, the first local verification operation in step S200 and the operation of determining whether the second local verification operation is required in step S300 can be sequentially performed on each of the first to Xth groups, and then the second local verification operation in step S400 can be sequentially performed only on the groups that require the second local verification operation.

[0112] For example, a first partial verification operation may be performed on the first group (step S210). A determination may be made as to whether a second partial verification operation is required for the first group (step S310). If a second partial verification operation is required for the first group (step S310: yes), the first group may be checked (step S315). If a second partial verification operation is not required for the first group (step S310: no), the verification operation for the first group may be terminated.

[0113] Thereafter, a first partial verification operation may be performed on the second group (step S220). A determination may be made as to whether a second partial verification operation is required for the second group (step S320). If a second partial verification operation is required for the second group (step S320: Yes), the second group may be checked (step S325). If a second partial verification operation is not required for the second group (step S320: No), the verification operation for the second group may be terminated.

[0114] In addition, a first partial verification operation for the Xth group may be performed (step S230). It may be determined whether a second partial verification operation is required for the Xth group (step S330). If a second partial verification operation is required for the Xth group (step S330: Yes), the Xth group may be checked (step S335). If a second partial verification operation is not required for the Xth group (step S330: No), the verification operation for the Xth group may be terminated.

[0115] Finally, a second partial verification operation may be sequentially performed on the groups that have passed the checks in steps S315, S325, and S335 (e.g., the groups that require the second partial verification operation) (step S405). In an example embodiment, the address information of the first group may be stored in step S315, the address information of the second group may be stored in step S325, and the address information of the Xth group may be stored in step S335.

[0116] In other example embodiments, Figure 10 As shown, the first partial verification operation in step S200 may be sequentially performed on all the groups in the first to X-th groups, and then the operation of determining whether the second partial verification operation is required in step S300 may be sequentially performed on all the groups in the first to X-th groups, and then the second partial verification operation in step S400 may be sequentially performed only on the groups that require the second partial verification operation. Figure 9 Duplicate description.

[0117] For example, step S210 may be performed on the first group, step S220 may be performed on the second group, and step S230 may be performed on the Xth group. Thereafter, steps S310 and S315 may be performed on the first group, steps S320 and S325 may be performed on the second group, and steps S330 and S335 may be performed on the Xth group. Finally, step S405 may be performed on the groups that pass the checks in steps S315, S325, and S335. In an example embodiment, the address information of the first group may be stored in step S315, the address information of the second group may be stored in step S325, and the address information of the Xth group may be stored in step S335.

[0118] In yet other exemplary embodiments, Figure 11 As shown, the first partial verification operation in step S200, the operation of determining whether the second partial verification operation is required in step S300, and the second partial verification operation in step S400 may be sequentially performed on each of the first to Xth groups. Figure 9 Duplicate description.

[0119] For example, steps S210 and S310 may be performed on the first group, and if a second partial verification operation is required (step S310: Yes), a second partial verification operation may be performed on the first group (step S410). Thereafter, steps S220 and S320 may be performed on the second group, and if a second partial verification operation is required (step S320: Yes), a second partial verification operation may be performed on the second group (step S420). Finally, steps S230 and S330 may be performed on the Xth group, and if a second partial verification operation is required (step S330: Yes), a second partial verification operation may be performed on the Xth group (step S430).

[0120] Figure 12 is a diagram showing a method according to an example embodiment Figure 1 A flowchart of an example of performing a first local verification operation in . Figure 13 and Figure 14 is used to describe the Figure 12 Graph of the operation.

[0121] Reference Figure 1 、 Figure 12 、 Figure 13 and Figure 14 , when a first partial verification operation is performed on one or more groups of the plurality of groups ( Figure 1 Step S200 in the above example), Figure 12 The operation of performing a first partial verification operation on the first group is shown (eg, Figure 9 、 Figure 10 and Figure 11 , step S210 in FIG.

[0122] When the first partial verification operation is performed on the first group (step S210), the first number of cells of the first group can be detected based on the erased state and the second verification level of the memory cells included in the first group (step S211). The second verification level can be different from the first verification level used in the erase verification operation of step S100. For example, step S211 can be performed using an erase verification voltage having the second verification level.

[0123] A first partial verification operation may be performed on the first group based on a first cell number (e.g., N1) and a first reference number (e.g., C1). For example, the first cell number N1 and the first reference number C1 may be compared, and whether the first partial verification operation is successful may be determined based on the comparison result.

[0124] When the first cell number N1 is less than or equal to the first reference number C1 (step S213: No), it may be determined that the first partial verification operation for the first group is successful (step S215), and then it may be determined whether a second partial verification operation is required for the first group.

[0125] When the first cell number N1 is greater than the first reference number C1 (step S213: Yes), it can be determined that the first partial verification operation for the first group has failed (step S217). In this case, the memory block including the first group can be indicated as a bad block as a whole (step S219), and the process according to example embodiments can be terminated.

[0126] In some example embodiments, the first cell number N1 of the first group detected in step S211 may represent the number of memory cells (e.g., the number of disconnected cells) having a threshold voltage higher than the second verification level among the memory cells included in the first group. For example, the first cell number N1 may represent a disconnected cell count value associated with the first group.

[0127] For example, when the memory cells included in the first group have Figure 13 In the case of the first group of erased states (or first group of threshold voltage distributions) GE11 shown, there may not be any memory cells having a threshold voltage higher than the second verification level VEVL2 among the memory cells included in the first group. In this case, the first cell number N1 of the first group may be zero, and it may be determined that the first local verification operation for the first group is successful.

[0128] For another example, when the memory cells included in the first group have Figure 13In the illustrated second group erased state GE12, there may be N12 memory cells having a threshold voltage higher than the second verification level VEVL2 among the memory cells included in the first group. Figure 13 The shaded area in may correspond to N12 memory cells. In this case, the first cell number N1 of the first group may be N12, and when N12>C1, it may be determined that the first local verification operation for the first group has failed.

[0129] In some example embodiments, Figure 13 For example, the first partial verification operation in step S200 using the second verification level VEVL2 may be performed based on a stricter or stronger verification level criterion than the erase verification operation in step S100 using the first verification level VEVL1.

[0130] Although not shown in detail, as shown in FIG. Figure 12 and Figure 13 The following is performed identically to the description: performing the first partial verification operation on the second group (e.g., Figure 9 、 Figure 10 and Figure 11 and performing a first partial verification operation on the Xth group (e.g., Figure 9 、 Figure 10 and Figure 11 , step S230 in the process).

[0131] In some example embodiments, a plurality of groups as targets of the first partial verification operation are divided or classified based on a plurality of word lines connected to memory cells in a memory block. For example, the memory cells included in the first group may be connected to M word lines among the plurality of word lines, where M is a natural number greater than or equal to 2. The first partial verification operation may be sequentially performed for each group.

[0132] For example, Figure 14 As shown, one memory block may be connected to the first to 4M-th word lines. Memory cells connected to the first to M-th word lines may form a first group, memory cells connected to the (M+1)-th to 2M-th word lines may form a second group, memory cells connected to the (2M+1)-th to 3M-th word lines may form a third group, and memory cells connected to the (3M+1)-th to 4M-th word lines may form a fourth group.

[0133] A first partial verification operation PVFY1_1 for the first group, a first partial verification operation PVFY1_2 for the second group, a first partial verification operation PVFY1_3 for the third group, and a first partial verification operation PVFY1_4 for the fourth group may be sequentially performed.

[0134] although Figure 14 An example based on a specific number of word lines, a specific number of groups, and a specific order of performing the first partial verification operation is shown, but the present invention is not limited thereto. In addition, a plurality of groups may be divided based on criteria other than word lines.

[0135] In example embodiments, when the first partial verification operation is performed only on one or more specific groups among a plurality of groups in a memory block, the first partial verification operation PVFY1_1 for only the first group, or the first partial verification operation PVFY1_1 for the first group and the first partial verification operation PVFY1_2 for the second group may be performed. In this case, the memory cells connected to the first to M-th word lines corresponding to the first group may be located in more than one cell string (e.g., Figure 4 The lower area of ​​the memory cells connected to other word lines in NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32 or NS33).

[0136] Figure 15 is a diagram showing a method according to an example embodiment Figure 1 A flowchart of an example of determining whether a second partial verification operation is required. Figure 16 is used to describe the Figure 15 Graph of the operation.

[0137] Reference Figure 1 、 Figure 15 and Figure 16 , when determining whether a second local verification operation is required for the group ( Figure 1 Step S300 in the above example), Figure 15 The operation of determining whether a second partial verification operation is required for the first group (eg, Figure 9 、 Figure 10 and Figure 11 , and then execute step S310 in the process.

[0138] After the first partial verification operation for the first group is successfully completed, when determining whether a second partial verification operation is required for the first group ( Figure 9 、 Figure 10 and Figure 11 Step S310 in the Figure 12Determine whether a second local verification operation is required for the first group based on the first unit number N1 detected in step S211 and the second reference number (e.g., C2). For example, the first unit number N1 and the second reference number C2 can be compared, and based on the result of the comparison, it can be determined whether a second local verification operation is required.

[0139] When the first unit number N1 is greater than the second reference number C2 (step S311: Yes), it can be determined that the second local verification operation for the first group is necessary (step S313). After that, the second local verification operation can be performed on the first group.

[0140] When the first unit number N1 is less than or equal to the second reference number C2 (step S311: No), it can be determined that the second local verification operation for the first group is unnecessary (step S315). In this case, the verification operation for the first group can be terminated.

[0141] In some example embodiments, the second reference number C2 can be less than or equal to the first reference number C1. For example, the second reference number C2 can be less than the first reference number C1 (e.g., C2 < C1). For example, based on a number criterion different from the first local verification operation in step S200 using the first reference number C1, perform the operation of Figure 1 determining whether a second local verification operation is required in step 300.

[0142] For example, when the memory cells included in the first group have Figure 16 the third group erase state GE13 as shown, among the memory cells included in the first group, there may be N13 memory cells having a threshold voltage higher than the second verification level VEVL2. In this case, the first unit number N1 of the first group can be N13, and when N13 < C1 and N13 > C2, it can be determined that the first local verification operation for the first group is successful, but a second local verification operation for the first group is required.

[0143] Although not shown in detail, the operation of determining whether a second local verification operation is required for the second group (e.g., Figure 15 and Figure 16 ), and the operation of determining whether a second local verification operation is required for the Xth group (e.g., Figure 9 、 Figure 10 and Figure 11 in step S320) and the operation of determining whether a second local verification operation is required for the Xth group (e.g., Figure 9 、 Figure 10 and Figure 11 in step S330) can be performed in the same manner as described respectively referring to

[0144] Figure 17 is a diagram showing a method according to an example embodiment Figure 1 A flowchart of an example of performing a second local verification operation in . Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 19C and Figure 19D is used to describe the Figure 17 Graph of the operation.

[0145] Reference Figure 1 、 Figure 17 、 Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 19C and Figure 19D , when a second partial verification operation is performed on at least some of the plurality of sub-groups (step S400), Figure 17 An operation of performing a second partial verification operation on a first subset of a first group when it is determined that a second partial verification operation for the first group is required is shown.

[0146] When the second local verification operation is performed on the first subset, the second number of cells of the first subset can be detected based on the erased state of the memory cells included in the first subset and the third verification level (step S411). The third verification level may be different from the Figure 1 For example, step S411 may be performed using an erase verification voltage having a third verification level.

[0147] A second partial verification operation may be performed on the first subgroup based on the second number of cells (e.g., N2) and the third reference number (e.g., C3). For example, the second number of cells N2 and the third reference number C3 may be compared, and whether the second partial verification operation is successful may be determined based on the result of the comparison. The third reference number C3 may be a reference number for one subgroup, and each of the first reference number C1 and the second reference number C2 may be a reference number for one group, so the third reference number C3 may be different from the first reference number C1 and the second reference number C2. For example, the third reference number C3 may be smaller than the first reference number C1 and the second reference number C2.

[0148] When the second cell number N2 is less than or equal to the third reference number C3 (step S413: No), it can be determined that the second partial verification operation for the first subset is successful (step S415). This may indicate that the memory cells included in the first subset have the desired erase state.

[0149] When the second cell number N2 is greater than the third reference number C3 (step S413: Yes), it can be determined that the second partial verification operation for the first subset has failed (step S417). In this case, the memory block including the first subset can be indicated as a bad block as a whole (step S419), and the erase operation according to example embodiments can be terminated.

[0150] In some example embodiments, the second cell number N2 of the first subset detected in step S411 may represent the number of memory cells having a threshold voltage higher than the third verification level among the memory cells included in the first subset. For example, the second cell number N2 may represent a disconnected cell count value associated with the first subset.

[0151] For example, when the memory cells included in the first subset have Figure 18A and Figure 18B In the first subset erased state (or first subset threshold voltage distribution) SE11 shown, there may not be any memory cells having a threshold voltage higher than the third verification level VEVL3 among the memory cells included in the first subset. In this case, the second number of cells N2 of the first subset may be zero, and it may be determined that the second local verification operation for the first subset is successful.

[0152] For another example, when the memory cells included in the first subset have Figure 18A and Figure 18B When the second subgroup is in the erase state SE12, Figure 18A The example includes that there may be N22 memory cells having a threshold voltage higher than the third verification level VEVL3 among the memory cells in the first subset, and Figure 18B In the example of FIG, N22′ memory cells having a threshold voltage higher than the third verification level VEVL3 may exist among the memory cells in the first subset. In this case, the second number of cells N2 of the first subset may be N22 or N22′, and when N22>C3 or N22′>C3, it may be determined that the second local verification operation for the first subset has failed.

[0153] In some example embodiments, Figure 18A As shown, the third verification level VEVL3 may be equal to the second verification level VEVL2. Figure 18B As shown, the third verification level VEVL3 may be lower than the second verification level VEVL2 .

[0154] Although not shown in detail, it can be seen as Figure 17 、 Figure 18A and Figure 18BThe operation of performing the second partial verification operation on each subgroup in the first group except the first subgroup is performed in the same manner as described above. In addition, the operation of performing the second partial verification operation on another group requiring the second partial verification operation can be performed in the same manner as the operation of performing the second partial verification operation on the first group.

[0155] In some example embodiments, a plurality of subgroups as targets of the second partial verification operation may be divided based on a plurality of word lines connected to memory cells in a memory block. For example, when memory cells included in a first group are connected to M word lines, memory cells included in one or more subgroups may be connected to N word lines, where N is a natural number greater than or equal to 1 and less than M. The second partial verification operation may be sequentially performed for each subgroup.

[0156] For example, Figure 19A 、 Figure 19B 、 Figure 19C and Figure 19D As shown, one or more subgroups may be connected to the first to Nth word lines. In some example embodiments, as Figure 19A and Figure 19D As shown, the memory cells connected to one word line may form a subgroup. In other example embodiments, as Figure 19B and Figure 19C As shown, memory cells connected to two or more word lines may form a subset.

[0157] exist Figure 19A and Figure 19D In the example of , memory cells connected to the first word line may form a first subgroup, memory cells connected to the second word line may form a second subgroup, memory cells connected to the third word line may form a third subgroup, memory cells connected to the fourth word line may form a fourth subgroup, memory cells connected to the (N-1)th word line may form an (N-1)th subgroup, and memory cells connected to the Nth word line may form an Nth subgroup. Figure 19B In the example of , memory cells connected to the first and second word lines may form a first subgroup, memory cells connected to the third and fourth word lines may form a second subgroup, and memory cells connected to the (N-1)th and Nth word lines may form an N / 2th subgroup. Figure 19C In the example, memory cells connected to the first, second, and third word lines may form a first subgroup, memory cells connected to the fourth, fifth, and sixth word lines may form a second subgroup, and memory cells connected to the (N-2), (N-1), and N word lines may form an N / 3 subgroup.

[0158] In some example embodiments, Figure 19A 、 Figure 19B and Figure 19C As shown, the second local verification operation can be sequentially performed on all subgroups included in one group. Figure 19A In the example of , the second local verification operation PVFY2_1 for the first subgroup, the second local verification operation PVFY2_2 for the second subgroup, the second local verification operation PVFY2_3 for the third subgroup, the second local verification operation PVFY2_4 for the fourth subgroup, the second local verification operation PVFY2_(Y1-1) for the (N-1)th subgroup, and the second local verification operation PVFY2_Y1 for the Nth subgroup (for example, Y1=N) can be performed sequentially. Figure 19B In the example of , the second partial verification operation PVFY2_1 for the first subset, the second partial verification operation PVFY2_2 for the second subset, and the second partial verification operation PVFY2_Y2 for the N / 2th subset (eg, Y2=N / 2) may be sequentially performed. Figure 19C In the example, a second local verification operation PVFY2_1 for the first subset, a second local verification operation PVFY2_2 for the second subset, and a second local verification operation PVFY2_Y3 for the N / 3th subset (eg, Y3=N / 3) may be sequentially performed.

[0159] In other example embodiments, Figure 19D As shown, the second partial verification operation may be sequentially performed on only some subgroups included in one group. Figure 19D In the example of FIG, a second partial verification operation PVFY2_1 for the first subgroup, a second partial verification operation PVFY2_2 for the third subgroup, a second partial verification operation PVFY2_3 for the fourth subgroup, and a second partial verification operation PVFY2_Y4 for the Nth subgroup (for example, Y4<N) may be sequentially performed, and the second partial verification operations for the second subgroup and the (N-1)th subgroup may be omitted. For example, the second partial verification operations for the second subgroup and the (N-1)th subgroup may be omitted by providing addresses corresponding to the omitted subgroups.

[0160] although Figure 19A 、 Figure 19B 、 Figure 19C and Figure 19D An example based on a specific number of word lines, a specific number of groups, and a specific order of performing the second partial verification operation is shown, but the present invention is not limited thereto. In addition, a plurality of subgroups may be divided based on criteria other than word lines.

[0161] Figure 20 is a block diagram illustrating a memory system according to example embodiments.

[0162] Reference Figure 20 , the memory system 500 may include a memory controller 600 and at least one nonvolatile memory device 700 .

[0163] The nonvolatile memory device 700 may correspond to the Figures 1 to 5 、 Figures 6A to 6C 、 Figures 7 to 17 、 Figure 18A 、 Figure 18B and 19A to 19D The nonvolatile memory device of the described example embodiment can perform data erasing, programming (or writing) and / or reading operations under the control of the memory controller 600. The nonvolatile memory device 700 can receive commands CMD and addresses ADDR from the memory controller 600 via I / O lines to perform such operations, and can exchange data DAT with the memory controller 600 to perform such programming or reading operations. In addition, the nonvolatile memory device 700 can receive control signals CTRL from the memory controller 600 via control lines. In addition, the nonvolatile memory device 700 receives power PWR from the memory controller 600 via power lines.

[0164] Figure 21 is a flowchart illustrating a method of operating a memory system according to example embodiments.

[0165] Reference Figure 21 , the method for operating a memory system according to example embodiments may be performed by a memory system including a memory controller and a nonvolatile memory device. The nonvolatile memory device may be a memory controller according to a reference Figures 1 to 5 、 Figures 6A to 6C 、 Figures 7 to 17 、 Figure 18A 、 Figure 18B and 19A to 19D Non-volatile memory devices according to example embodiments are described.

[0166] In a method of operating a memory system according to example embodiments, a memory controller generates an erase command and an address corresponding to a memory block to be erased, and provides the erase command and the address to a nonvolatile memory device (step S1100 ).

[0167] The non-volatile memory device performs a block erase operation on the memory block based on the erase command and address (step S1200). The block erase operation includes: an erase cycle, a first local verification operation, and a second local verification operation. Figure 1 to Figure 1 9, the method for erasing data according to the exemplary embodiment described above performs step S1200.

[0168] When at least one of the first partial verification operation and the second partial verification operation has failed, the memory controller receives a bad block indication signal for the memory block from the nonvolatile memory device (step S1300 ).

[0169] The memory controller may load an address mapping table including address information of the memory block from a buffer memory as an internal memory included in the memory controller (step S1400). The memory controller updates the address mapping table based on the bad block indication signal to invalidate the address information of the memory block (step S1500). The memory controller stores the updated address mapping table in the buffer memory (step S1600).

[0170] In some example embodiments, Figure 21 A method of operating a memory system is described as a method of operating a memory controller.

[0171] Figure 22 is a block diagram illustrating a memory controller according to example embodiments. Figure 23A and Figure 23B is used to describe the Figure 22 Diagram of the operation of the memory controller.

[0172] Reference Figure 22 , the memory controller 800 includes at least one processor 810, a buffer memory 820, a host interface 830, a non-volatile memory interface 840, and an error correction code (ECC) block 850. The memory controller 800 may be Figure 20 Memory controller 600.

[0173] The processor 810 may control the operation of the memory controller 800 in response to a command received from an external host device (not shown) via the host interface 830. In some example embodiments, the processor 810 may control the operation of the memory controller 800 by adopting a method for operating a nonvolatile memory device (e.g., Figure 2 The nonvolatile memory device 100 or Figure 20 The firmware of the non-volatile memory device 700) is used to control the corresponding components.

[0174] The buffer memory 820 may store instructions and data executed and processed by the processor 810. For example, the buffer memory 820 may store an address mapping table 822. For example, the buffer memory 820 may be implemented using a volatile memory device (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), cache memory, etc.).

[0175] The host interface 830 may provide a physical connection between the host device and the memory controller 800. The host interface 830 may provide an interface corresponding to the bus format of the host for communication between the host device and the memory controller 800. In some example embodiments, the bus format of the host device may be a small computer system interface (SCSI) or a serial attached SCSI (SAS) interface. In other example embodiments, the bus format of the host device may be a USB, a peripheral component interconnect (PCI) express (PCIe), an advanced technology attachment (ATA), a parallel ATA (PATA), a serial ATA (SATA), a non-volatile memory (NVM) express (NVMe), or the like.

[0176] The non-volatile memory interface 840 can exchange data with the non-volatile memory device. The non-volatile memory interface 840 can transmit data to the non-volatile memory device, or can receive data from the non-volatile memory device. Figure 2 The nonvolatile memory device 100 or Figure 20 The nonvolatile memory device 700 reads data. In some example embodiments, the nonvolatile memory interface 840 may be connected to the nonvolatile memory device via one channel. In other example embodiments, the nonvolatile memory interface 840 may be connected to the nonvolatile memory device via two or more channels.

[0177] The ECC block 850 for error correction may perform coding modulation using Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis code modulation (TCM), block code modulation (BCM), etc., or may perform ECC encoding and ECC decoding using the above codes or other error correction codes.

[0178] The memory controller 800 may perform a reference Figure 21The method described herein. For example, the processor 810 generates an erase command ECMD and an address EADDR based on a request REQ received from a host device via the host interface 830, and provides the erase command ECMD and the address EADDR to the non-volatile memory device via the non-volatile memory interface 840. When at least one of a first partial verification operation and a second partial verification operation fails during a block erase operation in the non-volatile memory device, the processor 810 receives a bad block indication signal BBS via the non-volatile memory interface 840, loads data AMP corresponding to an address mapping table 822 from the buffer memory 820, updates the address mapping table 822 based on the bad block indication signal BBS to invalidate specific address information, and stores updated data AMP′ corresponding to the updated address mapping table in the buffer memory 820.

[0179] Reference Figure 23A and Figure 23B , shows the storage Figure 22 The address mapping table 822 in the buffer memory 820.

[0180] The address mapping table 822 may include: a plurality of memory blocks; corresponding logical addresses LA1, LA2, LA3 and LA4; corresponding physical addresses PA1, PA2, PA3 and PA4; and status information of the plurality of memory blocks. Figure 23A As shown, before receiving the bad block indication signal BBS, all memory blocks may be in or have a valid state VA. Figure 23B As shown, when the bad block indication signal BBS is received, the corresponding memory block (eg, the first memory block) may be converted to an invalid state INVA and may no longer be used.

[0181] Figure 24 is a block diagram illustrating a memory device including a nonvolatile memory device according to example embodiments.

[0182] Reference Figure 24 , the storage device 1000 may include a plurality of non-volatile memory devices 1100 and a controller 1200. For example, the storage device 1000 may be any storage device such as an embedded multimedia card (eMMC), a universal flash memory (UFS), a solid state disk or a solid state drive (SSD), etc.

[0183] The controller 1200 may be connected to the nonvolatile memory device 1100 via a plurality of channels CH1, CH2, CH3, ..., and CHi. The controller 1200 may include Figure 22One or more processors 1210, buffer memory 1220, error correction code (ECC) circuit 1230, host interface 1250 and non-volatile memory interface 1260 corresponding to the processor 810, buffer memory 820, ECC block 850, host interface 830 and non-volatile memory interface 840 in the processor.

[0184] Each nonvolatile memory device 1100 may correspond to a memory device according to example embodiments. Figure 2 and Figure 20 One of the nonvolatile memory devices 100 and 700 and may optionally be provided with an external high voltage VPP.

[0185] Figure 25 is a cross-sectional view of a nonvolatile memory device according to example embodiments.

[0186] Reference Figure 25 , the non-volatile memory device or memory device 2000 may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a memory cell area or a cell area CELL on a first wafer, manufacturing a lower chip including a peripheral circuit area PERI on a second wafer separated from the first wafer, and then bonding the upper chip and the lower chip to each other (bond). Here, the bonding process may include a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal may include copper (Cu) using copper-to-copper bonding. However, example embodiments may not be limited thereto. For example, the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0187] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 2000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0188] The peripheral circuit region PERI may include a first substrate 2210; an interlayer insulating layer 2215; a plurality of circuit elements 2220a, 2220b, and 2220c formed on the first substrate 2210; first metal layers 2230a, 2230b, and 2230c connected to the plurality of circuit elements 2220a, 2220b, and 2220c, respectively; and second metal layers 2240a, 2240b, and 2240c formed on the first metal layers 2230a, 2230b, and 2230c. Each of the circuit elements 2220a, 2220b, and 2220c may include one or more transistors. In an example embodiment, the first metal layers 2230a, 2230b, and 2230c may be formed of tungsten having a relatively high resistivity, and the second metal layers 2240a, 2240b, and 2240c may be formed of copper having a relatively low resistivity.

[0189] exist Figure 25 In the illustrated example embodiment, although only the first metal layers 2230a, 2230b, and 2230c and the second metal layers 2240a, 2240b, and 2240c are shown and described, the present invention is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 2240a, 2240b, and 2240c. At least a portion of the one or more additional metal layers formed on the second metal layers 2240a, 2240b, and 2240c may be formed of aluminum or the like having a lower resistivity than the copper forming the second metal layers 2240a, 2240b, and 2240c.

[0190] An interlayer insulating layer 2215 may be provided on the first substrate 2210 and cover the plurality of circuit elements 2220a, 2220b, and 2220c, the first metal layers 2230a, 2230b, and 2230c, and the second metal layers 2240a, 2240b, and 2240c. The interlayer insulating layer 2215 may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0191] Lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b in the peripheral circuit area PERI may be electrically bonded to the upper bonding metals 2371b and 2372b of the cell area CELL. The lower bonding metals 2271b and 2272b and the upper bonding metals 2371b and 2372b may be formed of aluminum, copper, tungsten, or the like.

[0192] The upper bonding metals 2371b and 2372b in the cell region CELL may be referred to as first metal pads, and the lower bonding metals 2271b and 2272b in the peripheral circuit region PERI may be referred to as second metal pads. Furthermore, the first metal pad and the second metal pad may be connected to each other in a bonding manner.

[0193] The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate 2310 and a common source line 2320. On the second substrate 2310, a plurality of word lines 2331, 2332, 2333, 2334, 2335, 2336, 2337, and 2338 (i.e., 2330) may be stacked in a third direction D3 (e.g., Z-axis direction) perpendicular to the upper surface of the second substrate 2310. At least one string selection line and at least one ground selection line may be arranged above or below the plurality of word lines 2330, respectively, and the plurality of word lines 2330 may be provided between the at least one string selection line and the at least one ground selection line.

[0194] In the bit line bonding area BLBA, the channel structure CH may extend in a third direction D3 (e.g., the Z-axis direction) perpendicular to the upper surface of the second substrate 2310 and pass through a plurality of word lines 2330, at least one string selection line, and at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to the first metal layer 2350c and the second metal layer 2360c. For example, the first metal layer 2350c may be a bit line contact, and the second metal layer 2360c may be a bit line. In example embodiments, the bit line 2360c may extend in a second direction D2 (e.g., the Y-axis direction) parallel to the upper surface of the second substrate 2310.

[0195] exist Figure 25 In the example embodiment shown, a region in which the channel structure CH, the bit line 2360c, and the like are provided may be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA, the bit line 2360c may be electrically connected to the circuit element 2220c providing the page buffer 2393 in the peripheral circuit region PERI. The bit line 2360c may be connected to upper bonding metals 2371c and 2372c in the cell region CELL, and the upper bonding metals 2371c and 2372c may be connected to lower bonding metals 2271c and 2272c, which are connected to the circuit element 2220c of the page buffer 2393.

[0196] In the word line bonding area WLBA, a plurality of word lines 2330 may extend in a first direction D1 (e.g., the X-axis direction) parallel to the upper surface of the second substrate 2310 and perpendicular to the second direction D2, and may be connected to a plurality of cell contact plugs 2341, 2342, 2343, 2344, 2345, 2346, and 2347 (i.e., 2340). The plurality of word lines 2330 and the plurality of cell contact plugs 2340 may be connected to each other in pads provided by at least a portion of the plurality of word lines 2330 extending at different lengths along the first direction D1. The first metal layer 2350b and the second metal layer 2360b may be sequentially connected to the upper portions of the plurality of cell contact plugs 2340 connected to the plurality of word lines 2330. The plurality of cell contact plugs 2340 may be connected to the peripheral circuit region PERI through the upper bonding metals 2371b and 2372b of the cell region CELL and the lower bonding metals 2271b and 2272b of the peripheral circuit region PERI in the word line bonding area WLBA.

[0197] The plurality of cell contact plugs 2340 may be electrically connected to the circuit elements 2220 b forming the row decoder 2394 in the peripheral circuit region PERI. In example embodiments, the operating voltage of the circuit elements 2220 b forming the row decoder 2394 may be different from the operating voltage of the circuit elements 2220 c forming the page buffer 2393. For example, the operating voltage of the circuit elements 2220 c forming the page buffer 2393 may be greater than the operating voltage of the circuit elements 2220 b forming the row decoder 2394.

[0198] A common source line contact plug 2380 may be provided in the external pad landing area PA. The common source line contact plug 2380 may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line 2320. A first metal layer 2350a and a second metal layer 2360a may be sequentially stacked on an upper portion of the common source line contact plug 2380. For example, an area in which the common source line contact plug 2380, the first metal layer 2350a, and the second metal layer 2360a are provided may be defined as the external pad landing area PA.

[0199] Input / output pads 2205 and 2305 may be provided in the external pad landing area PA. A lower insulating film 2201 may be formed below the first substrate 2210 to cover the lower surface of the first substrate 2210, and the first input / output pads 2205 may be formed on the lower insulating film 2201. The first input / output pads 2205 may be connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c provided in the peripheral circuit region PERI via first input / output contact plugs 2203, and may be separated from the first substrate 2210 by the lower insulating film 2201. In addition, a side insulating film may be provided between the first input / output contact plugs 2203 and the first substrate 2210 to electrically separate the first input / output contact plugs 2203 and the first substrate 2210.

[0200] An upper insulating film 2301 covering the upper surface of the second substrate 2310 may be formed on the second substrate 2310, and second input / output pads 2305 may be provided on the upper insulating layer 2301. The second input / output pads 2305 may be connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c provided in the peripheral circuit region PERI through second input / output contact plugs 2303. In example embodiments, the second input / output pads 2305 are electrically connected to the circuit element 2220a.

[0201] According to an embodiment, the second substrate 2310 and the common source line 2320 may not be disposed in the region in which the second input / output contact plug 2303 is disposed. In addition, the second input / output pad 2305 may not overlap with the word line 2330 in the third direction D3 (e.g., the Z-axis direction). The second input / output contact plug 2303 may be separated from the second substrate 2310 in a direction parallel to the upper surface of the second substrate 2310 and may be connected to the second input / output pad 2305 and the upper metal pattern 2372a of the cell region CELL through the interlayer insulating layer 2315 of the cell region CELL.

[0202] According to an embodiment, the first input / output pads 2205 and the second input / output pads 2305 may be selectively formed. For example, the memory device 2000 may include only the first input / output pads 2205 provided on the lower insulating film 2201 in contact with the first substrate 2210 or the second input / output pads 2305 provided on the upper insulating film 2301 in contact with the second substrate 2310. Alternatively, the memory device 2000 may include both the first input / output pads 2205 and the second input / output pads 2305.

[0203] In each of the external pad bonding area PA and the bit line bonding area BLBA respectively included in the cell region CELL and the peripheral circuit region PERI, a metal pattern to be provided on the uppermost metal layer is provided as a dummy pattern, or the uppermost metal layer may not exist.

[0204] In the external pad bonding area PA, the memory device 2000 may include a lower metal pattern 2273a in the uppermost metal layer of the peripheral circuit area PERI, the lower metal pattern 2273a corresponding to the upper metal pattern 2372a formed in the uppermost metal layer of the cell area CELL and having the same cross-sectional shape as the upper metal pattern 2372a of the cell area CELL so as to connect them. In the peripheral circuit area PERI, the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to the contact portion. Similarly, in the external pad bonding area PA, the upper metal pattern 2372a may be formed in the uppermost metal layer of the cell area CELL, the upper metal pattern 2372a corresponding to the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit area PERI and having the same shape as the lower metal pattern 2273a of the peripheral circuit area PERI.

[0205] Lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 2371b and 2372b of the cell area CELL through copper-to-copper bonding.

[0206] In addition, in the bit line bonding area BLBA, an upper metal pattern 2392 may be formed in the uppermost metal layer of the cell region CELL, the upper metal pattern 2392 corresponding to the lower metal pattern 2252 formed in the uppermost metal layer of the peripheral circuit region PERI and having the same cross-sectional shape as the lower metal pattern 2252 of the peripheral circuit region PERI. A contact portion may not be formed on the upper metal pattern 2392 formed in the uppermost metal layer of the cell region CELL.

[0207] In example embodiments, a reinforcement metal pattern having the same cross-sectional shape as the metal pattern may be formed in the uppermost metal layer in the other of the cell region CELL and the peripheral circuit region PERI, corresponding to the metal pattern formed in the uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI. No contact may be formed on the reinforcement metal pattern.

[0208] The methods according to the example embodiments disclosed herein may be applied to or employed in the memory device 2000, and the memory device 2000 may be implemented to perform the methods according to the example embodiments disclosed herein. For example, an erase voltage, an erase verification voltage, and related signals for performing the methods according to the example embodiments may be applied through the bonding structure shown.

[0209] In an example embodiment, such as in Figure 25 The nonvolatile memory device 2000 described in the can operate and can include the previously described Figures 1 to 5 、 Figures 6A to 6C 、 Figures 7 to 17 、 Figure 18A 、 Figure 18B 、 19A to 19D 、 Figures 20 to 22 、 Figure 23A 、 Figure 23B and Figure 24 Device components according to one or more example embodiments are described.

[0210] The present invention can be applied to various devices and systems including non-volatile memory devices. For example, the present invention can be applied to such systems, such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, portable video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0211] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention as defined by the claims. Therefore, it should be understood that the foregoing is illustrative of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments and other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A method for erasing data in a nonvolatile memory device comprising one or more memory blocks, wherein a plurality of memory cells are arranged in a vertical direction in each memory block, the method comprising: performing one or more erase cycles on an entire first memory block of the one or more memory blocks, the erase cycle comprising an erase operation and an erase verify operation; performing a first local verification operation on one or more of a plurality of groups in the first memory block after the erase cycle is successfully completed, the first memory block being divided into the plurality of groups; After the first partial verification operation is successfully completed, determining whether a second partial verification operation is required for a group of the one or more groups; and The second partial verification operation is performed on one or more sub-groups among a plurality of sub-groups in a first group among the plurality of groups into which the first group is divided that require the second partial verification operation.

2. The method according to claim 1, wherein Performing the first partial verification operation on one or more groups of the plurality of groups includes: detecting a first cell number of the first group based on erase states of memory cells included in the first group and an erase verify voltage having a second verify level that is different from an erase verify voltage having a first verify level used in an erase verify operation of the erase loop; and The first partial verification operation is performed on the first group based on the first cell number and a first reference number.

3. The method according to claim 2, wherein: Performing the first local verification operation on the first group includes: determining that the first partial verification operation for the first group is successful when the first cell number is less than or equal to the first reference number; and When the first cell number is greater than the first reference number, it is determined that the first partial verification operation for the first group has failed.

4. The method according to claim 3, wherein: When it is determined that the first partial verification operation has failed, the first memory block is indicated as a bad block.

5. The method according to claim 2, wherein: The plurality of memory cells included in the first memory block are connected to a plurality of word lines; and The memory cells included in the first group are connected to M word lines among the plurality of word lines, where M is a natural number greater than or equal to 2.

6. The method according to claim 2, wherein: The first cell number indicates the number of memory cells in which a level of a threshold voltage is higher than the second verification level among the memory cells included in the first group.

7. The method according to claim 2, wherein: The second verification level is lower than the first verification level.

8. The method according to claim 2, wherein: Determining whether the second partial verification operation is required for a group in the one or more groups includes: Whether the second partial verification operation is required for the first group is determined based on the first cell number and a second reference number.

9. The method according to claim 8, wherein Determining whether the second partial verification operation is required for the first group includes: When the first cell number is greater than the second reference number, determining that a second partial verification operation for the first group is necessary; and When the first cell number is less than or equal to the second reference number, it is determined that a second partial verification operation for the first group is unnecessary.

10. The method according to claim 8, wherein The second reference number is less than or equal to the first reference number.

11. The method according to claim 8, wherein Performing the second partial verification operation on one or more subgroups of the plurality of subgroups in the first group includes: detecting a second number of cells of the first subset based on erased states of memory cells in a first subset of the plurality of subsets included in the first group and an erase verify voltage having a third verify level different from the first verify level when it is determined that a second partial verify operation for the first group is required; and A second partial verification operation is performed on the first subset based on the second cell number and a third reference number different from the first reference number and the second reference number.

12. The method according to claim 11, wherein Performing the second local verification operation on the first subset includes: determining that a second partial verification operation on the first subset is successful when the second cell number is less than or equal to the third reference number; and When the second cell number is greater than the third reference number, it is determined that a second partial verification operation for the first subset has failed.

13. The method according to claim 12, wherein: When it is determined that the second partial verification operation has failed, the first memory block is indicated as a bad block.

14. The method according to claim 11, wherein: The memory cells included in the first group are connected to M word lines, where M is a natural number greater than or equal to 2, and The memory cells included in the first subset are connected to N word lines, where N is a natural number greater than or equal to 1 and less than M.

15. The method according to claim 11, wherein The second cell number represents the number of memory cells in which a level of a threshold voltage is higher than the third verification level among the memory cells included in the first subset.

16. The method according to claim 11, wherein The third verification level is lower than or equal to the second verification level.

17. The method according to claim 11, wherein The third reference number is smaller than the first reference number and the second reference number.

18. The method of claim 1, wherein: The plurality of groups include a first group to an X-th group, wherein X is a natural number greater than or equal to 2, sequentially performing the first partial verification operation and the operation of determining whether the second partial verification operation is required on each of the first to X-th groups, and The second partial verification operation is sequentially performed only on one or more groups requiring the second partial verification operation among the first to X-th groups.

19. A non-volatile memory device comprising: a memory block comprising a plurality of memory cells arranged in a vertical direction; as well as The control circuit is configured as follows: performing one or more erase cycles on the entire memory block, performing a first local verification operation on one or more of the plurality of groups in the memory block, determining whether a second partial verification operation is required for a group of the one or more groups, and performing the second partial verification operation on one or more subgroups of a plurality of subgroups in a group requiring the second partial verification operation among the plurality of groups, The erase cycle includes an erase operation and an erase verification operation. wherein the memory block is divided into the plurality of groups, and The group requiring the second partial verification operation is divided into the plurality of subgroups.

20. A method of erasing data in a nonvolatile memory device comprising one or more memory blocks, wherein a plurality of memory cells are arranged in a vertical direction in each memory block, the method comprising: performing one or more erase cycles on an entire first memory block of the one or more memory blocks, the erase cycle including an erase operation performed using an erase voltage and an erase verify operation performed using a first verify voltage having a first verify level; performing a first local verification operation on one or more of a plurality of groups in the first memory block, the first memory block being divided into the plurality of groups, using a first reference number and a second verification voltage having a second verification level different from the first verification level after the erase cycle is successfully completed; after the first partial verification operation is successfully completed, determining whether a second partial verification operation is required for a group of the one or more groups using a second reference number that is less than or equal to the first reference number; as well as performing the second local verification operation on all or some of a plurality of sub-groups in a group requiring the second local verification operation among the plurality of groups using a third verification voltage having a third verification level different from the first verification level and a third reference number different from the first reference number and the second reference number, Wherein, when at least one of the first partial verification operation and the second partial verification operation has failed, the first memory block is indicated as a bad block.

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