Methods for semiconductor die edge protection and semiconductor die separation

Abstract

This application relates to a method for edge protection and separation of semiconductor dies. Furthermore, the disclosed method provides a method for separating semiconductor dies without using dicing techniques. In one embodiment, a plurality of trenches may be formed on the front side of a substrate containing a plurality of semiconductor dies. Individual trenches may correspond to scribe lines on the substrate, wherein each trench contains a depth greater than the final thickness of the semiconductor die. Before filling the trenches with an adhesive material, a dielectric layer may be formed on the sidewalls of the trenches, thereby protecting the edges of the semiconductor dies. Subsequently, the substrate may be thinned from the rear side such that the adhesive material in the trenches can be exposed from the rear side. The adhesive material may be removed to separate individual semiconductor dies from the plurality of semiconductor dies from the substrate.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor die assemblies, and more specifically, to semiconductor die edge protection and semiconductor die separation. Background Technology

[0002] Semiconductor packages typically comprise one or more semiconductor dies (e.g., memory chips, microprocessor chips, imager chips) mounted on a substrate and enclosed in a protective cover. The semiconductor die may contain functional features, such as memory cells, processor circuitry, or imager devices, and bonding pads electrically connected to said functional features. The bonding pads may be electrically connected to corresponding conductive structures on the substrate, which may be coupled to terminals outside the protective cover to allow the semiconductor die to be connected to higher-level circuitry.

[0003] In some semiconductor packages, two or more semiconductor dies can be stacked on top of each other to reduce the footprint of the semiconductor package (which may be called a multi-chip package). The stacked semiconductor dies may include three-dimensional interconnects (such as through-silicon vias (TSVs)) to route electrical signals between the dies. The semiconductor dies can be thinned to reduce the overall thickness of such semiconductor packages and to reduce problems associated with forming three-dimensional interconnects through the stacked semiconductor dies. Typically, a carrier wafer is attached to the front side of a substrate (e.g., a wafer) on which the semiconductor dies are fabricated, allowing the substrate to be thinned from the rear side. Furthermore, the substrate can be diced to separate individual semiconductor dies when attached to an adhesive layer of a mounting tape. However, dicing often introduces particles, leading to yield losses. Additionally, dicing using blades may be incompatible with new, advanced materials incorporated into the semiconductor dies. Summary of the Invention

[0004] One aspect of this application relates to a method comprising: forming a plurality of trenches on a front side of a substrate comprising a plurality of semiconductor dies, wherein an individual trench of the plurality of trenches corresponds to a scribe line on the substrate; filling each of the plurality of trenches with an adhesive material; thinning the substrate from a rear side of the substrate; and removing the adhesive material to separate an individual semiconductor die of the plurality of semiconductor dies.

[0005] Another aspect of this application relates to a method comprising: forming a plurality of trenches on the front side of a semiconductor substrate comprising a plurality of semiconductor dies, each of the plurality of trenches having a depth greater than the final thickness of an individual semiconductor die; forming a first dielectric layer on the sidewalls of the plurality of trenches; filling each of the plurality of trenches with an adhesive material coated on the front side of the semiconductor substrate; thinning the semiconductor substrate from the back side of the semiconductor substrate to the final thickness; and removing the adhesive material to separate the individual semiconductor dies.

[0006] Another aspect of this application relates to a semiconductor device comprising: an integrated circuit formed on a front side of a semiconductor substrate; a first dielectric layer on a sidewall of the semiconductor substrate; and a second dielectric layer on a rear side of the semiconductor substrate opposite to the front side, the second dielectric layer being discontinuous with the first dielectric layer. Attached Figure Description

[0007] Many aspects of the invention can be better understood by referring to the accompanying drawings. The components in the drawings are not necessarily to scale. Instead, the focus is on clearly illustrating the principles and overall features of the invention.

[0008] Figures 1A to 1L This invention describes an example process for protecting the edge of a semiconductor die and separating the semiconductor die according to an embodiment of the present invention.

[0009] Figure 2 and 3 A flowchart illustrating a method for protecting the edge of a semiconductor die and separating a semiconductor die according to an embodiment of the present invention. Detailed Implementation

[0010] The following describes specific details and associated methods for several embodiments of protecting the edges (and / or back sides) of semiconductor dies in semiconductor device assemblies and for separating semiconductor dies. Schemes for protecting the edges of semiconductor dies as described herein can provide not only a passivation layer around the edges (and back sides) of the semiconductor die, but also alternative die separation techniques suitable for integrating new materials and / or deploying advanced packaging technologies compared to conventional dicing techniques. For example, a passivation layer around the edges of a semiconductor die can reduce cracks (or peeling) at the edges or reduce the propagation of such cracks inward toward the integrated circuits and / or various components of the semiconductor die. Additionally, the passivation layer may include a diffusion barrier (e.g., a nitride layer) to prevent contaminants (e.g., metal atoms such as copper) from diffusing through the silicon substrate of the semiconductor die, which can cause certain reliability issues.

[0011] Furthermore, the die separation technology according to the present invention eliminates conventional dicing steps (e.g., blade cutting, laser cutting), which produce particles attached to the surface of the die, resulting in yield loss. Conventional dicing also poses challenges to integrating new materials (e.g., low-k and / or ultra-low-k materials) that can be used to build state-of-the-art semiconductor devices. In some cases, conventional dicing can leave contaminants on the surface of the semiconductor die, which can subsequently hinder the deployment of advanced packaging technologies, such as bonding technology, which forms a direct bond between two semiconductor dies face-to-face.

[0012] Therefore, the methods for protecting the edges of semiconductor dies and separating semiconductor dies according to the present invention offer various benefits, such as reducing particle count to improve yield, protecting semiconductor dies to improve reliability, reducing contaminants for deployment of advanced packaging technologies, facilitating the integration of new materials that are incompatible with conventional dicing techniques, and so on. Furthermore, the present invention can reduce the width of dicing channels, allowing more semiconductor dies to be produced per wafer, for example, reducing production costs. As described in more detail below, the present invention can facilitate the reduction of wafer-level mechanical stress (e.g., reduced wafer warpage) during back-side wafer processing steps due to the adhesive material placed between the semiconductor dies, which absorbs the stress applied to the wafer.

[0013] The term "semiconductor device or die" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, microprocessors, diodes, and so on. Such semiconductor devices may include integrated circuits or components, data storage elements, processing components, and / or other features fabricated on a semiconductor substrate. Furthermore, the term "semiconductor device or die" may refer to a finished device or an assembly or other structure at various processing stages prior to becoming a finished device. Depending on its context, the term "substrate" may refer to a wafer-level substrate or a diced die-level substrate. Furthermore, a substrate may comprise a semiconductor wafer, a package support substrate, an internal component, a semiconductor device or die, or the like. Those skilled in the art will recognize that appropriate steps of the methods described herein can be performed at the wafer level or at the die level.

[0014] Furthermore, unless the context otherwise indicates, conventional semiconductor manufacturing techniques can be used to form the structures disclosed herein. Materials can be deposited, for example, using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, electroplating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization (CMP), or other suitable techniques. Some of these techniques can be combined with photolithography processes. Those skilled in the art will also understand that this technique may have additional embodiments, and that this technique may be implemented without reference herein. Figures 1A to 1L Practice in several cases as detailed in the embodiments described in 2 and 3.

[0015] As used herein, the terms “front,” “back,” “vertical,” “lateral,” “downward,” “upward,” “upper,” and “lower” can refer to the relative orientation or position of a feature in a semiconductor device assembly given the orientation shown in the figures. For example, “upper” or “topmost” can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices with other orientations. Those skilled in the art will also understand that the technology may have additional embodiments, and that the technology may be implemented without reference herein. Figures 1A to 1L Practice in several cases as detailed in the embodiments described in 2 and 3.

[0016] Figure 1A The illustration shows a cross-sectional view of a substrate 105, which includes semiconductor dies 115 (e.g., semiconductor dies 115a to 115c) fabricated on its front side 106. Each semiconductor die 115 may contain an integrated circuit formed on its front side. Furthermore, the semiconductor die 115 may include one or more vias coupled to the integrated circuit and extending from the front side to the rear side of the semiconductor die 115. Figure 1G , 1H (Depicted in 1I and 1L). One or more through-holes (which may also be referred to as through-silicon vias (TSVs)) are configured to provide one or more electrical connections to the integrated circuit on the back side—for example, to facilitate the stacking of multiple semiconductor dies 115 on top of each other. When in Figures 1A to 1L When depicting multiple semiconductor dies 115 at a relatively low magnification, the integrated circuits and vias of the semiconductor dies 115 are omitted in order to clearly illustrate certain aspects of the principles of the present invention.

[0017] Figure 1A A set of trenches 120 (e.g., trenches 120a to 120c) formed on the front side 106 are also depicted, along with a photoresist layer 110 for protecting the semiconductor die 115. Thus, individual trenches 120 may correspond to scribe lines (or cut channels) on the substrate 105. In some embodiments, the photoresist layer 110 may comprise a hard mask layer (e.g., a hard mask with carbon). In some embodiments, the trenches 120 may be formed by performing etching processes known to those skilled in the art of semiconductor manufacturing (e.g., plasma-based dry etching processes, wet etching processes). Although the trenches 120 are depicted as having vertical sidewalls, in some embodiments, the sidewalls of the trenches 120 may be sloped. For example, the opening of the trench 120 at the surface of the substrate 105 (e.g., sidewalls with a positive slope) may be larger than the opening at the bottom of the trench 120. In some cases, a positive slope of the sidewalls may facilitate the formation of a more uniform dielectric layer (e.g., a first dielectric layer 125) on the sidewalls.

[0018] The dimensions of groove 120 include the width (in Figure 1A The middle label is marked as "W") and the depth D (in Figure 1A (Illustrated as "D"). The width of trench 120 may be smaller than the typical width of a scribe line, and may be about 60 to 80 μm wide (e.g., within 10% of 60 μm, within 10% of 80 μm). In some embodiments, the width of trench 120 may be about 40 μm (e.g., within 10% of 40 μm), 30 μm (e.g., within 10% of 30 μm), or even smaller. Furthermore, the width may be based on the final thickness of the semiconductor die 115 (in... Figure 1G The depth of trench 120 is determined by the reference numeral "T". That is, the depth of trench 120 can be designed to be greater than the final thickness of semiconductor die 115, allowing individual semiconductor dies 115 to be segmented without a dicing process. For example, when the final thickness of semiconductor die 115 is approximately 50 μm (e.g., within 10% of 50 μm), the depth of trench 120 can be approximately 55 to 60 μm (e.g., within 10% of 55 μm, within 10% of 60 μm). Alternatively or additionally, taking into account process capabilities associated with downstream process steps, such as forming a dielectric layer on the sidewalls of trench 120 (e.g., chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process) and / or filling trench 120 with adhesive material, the width and depth of trench 120 can be based on an aspect ratio determined by the width and depth of trench 120.

[0019] Figure 1B This illustration shows a cross-sectional view of the substrate 105 after the photoresist layer 110 has been removed and the first dielectric layer 125 has subsequently been formed on the front side 106 of the substrate 105. For example, the first dielectric layer 125 can be formed by performing one or more process steps including a CVD process. The first dielectric layer 125 may comprise various dielectric materials, such as oxides, nitrides, oxide oxynitrides, or combinations thereof. In some embodiments, an oxide layer may be formed on a silicon surface, followed by the deposition of a nitride layer on the oxide layer formed on the silicon surface. This composite layer can reduce the formation of defects (e.g., crystal defects in the substrate 105) compared to a single layer of nitride formed directly on the silicon surface.

[0020] Figure 1C This illustration shows a cross-sectional view of the substrate 105 after the first dielectric layer 125 has been removed from the front side 106 of the substrate 105 and from the bottom of the individual trenches 120. Thus, the first dielectric layer 125 remains on the sidewalls of the trenches 120. In some embodiments, an etching process (e.g., a plasma-based dry etching process) may be performed to remove the first dielectric layer 125 from a relatively flat region (e.g., the front side 106, the bottom of the trench 120) relative to the incoming flux of the etchant, while retaining the first dielectric layer 125 on the sidewalls.

[0021] Figure 1D The illustration shows a cross-sectional view of a substrate 105 after the trench 120 (having a first dielectric layer 125 formed on its sidewalls) has been filled with an adhesive material 130—for example, a Nissan Chemical thermosetting adhesive. The adhesive material 130 (which may be referred to as a carrier adhesive) also covers (e.g., coats) the front side 106 of the substrate 105. The sidewalls of the trench 120 are protected by the first dielectric layer 125 to prevent the adhesive material 130 from directly contacting the sidewalls. In some embodiments, the adhesive material 130 may exhibit fluid-like material properties, allowing it to fill trenches 120 with high aspect ratios (e.g., relatively narrow openings with relatively deep trench bottoms). Furthermore, Figure 1D The substrate 105 has been flipped to depict the rear side 107 above the front side 106.

[0022] Figure 1E This illustration shows a cross-sectional view of the substrate 105 after the adhesive material 130 on the front side 106 has been used to bond the carrier substrate 135 (or support substrate). The carrier substrate 135 may be used in subsequent process steps to be performed on the rear side 107—for example, referring to… Figures 1F to 1J The described process steps involve mechanically supporting the substrate 105 (and the semiconductor die 115). Additionally, the adhesive material 130 may be densified (e.g., solidified, cured) to make it suitable for subsequent processing steps. In some embodiments, a thermal process may be applied to the adhesive material 130 (e.g., thermosetting the adhesive material 130). Alternatively, a chemical process may be applied to the adhesive material 130 (e.g., chemically curing the adhesive material 130).

[0023] Figure 1F This illustration shows a cross-sectional view of substrate 105 after a first portion of substrate 105 (as indicated by the arrow) has been removed from the back side 107 of substrate 105. In some embodiments, back grinding and / or chemical mechanical polishing (CMP) processes (e.g., the first process) may be performed to remove bulk material from substrate 105, for example, thinning substrate 105 from about 700 μm (e.g., within 10% of 700 μm) to about 100 μm (e.g., within 10% of 100 μm) or smaller. In other embodiments, different processes (e.g., etching processes) may be performed to remove bulk material from substrate 105, as is well known to those skilled in the art of semiconductor manufacturing.

[0024] Figure 1G This illustrates a cross-sectional view of the substrate 105 after the second portion of the substrate 105 has been removed from the rear side 107 of the substrate 105. In some embodiments, this can be achieved by (e.g., using a reference) Figure 1FAfter the CMP process described removes the bulk of substrate 105, an etching process (e.g., a second process) is performed on the back side 107. The etching process may be configured to expose the adhesive material 130 in the trench 120 from the back side 107 due to the removal of a second portion of substrate 105. Furthermore, the etching process may be designed to expose one or more through-silicon vias (TSVs) 140 of semiconductor die 115 from the back side 107. The TSVs are coupled to an integrated circuit 141 formed on the front side 106 of substrate 105 and are configured to provide one or more electrical connections to the integrated circuit 141 on the back side 107. In some embodiments, after removing the second portion of substrate 105, the back side 107 of substrate 105 may be recessed relative to the exposed adhesive material 130. Thus, the second process (e.g., the etching process) may be configured to remove semiconductor substrate 105 at a first removal rate and remove adhesive material 130 (and / or first dielectric layer 125) at a second removal rate less than the first removal rate.

[0025] It should be understood that after the second process is completed to expose the adhesive material 130 in the trench 120 from the back side 107 (e.g., when the etching front advances from the back side 107 through the bottom of the trench 120), the semiconductor die 115 separates from the substrate 105 because the depth of the trench 120 is determined to be greater than the final thickness of the semiconductor die 115 (e.g., the thickness of the semiconductor die 115 at the completion of the etching process). In other words, the individual semiconductor dies 115 separate from the substrate 105 because the portion of the substrate 105 common to all semiconductor dies 115 no longer exists due to the completion of the second process (e.g., the etching process). Subsequently, the individual semiconductor dies 115 are held together by the adhesive material 130 and held to the carrier substrate 135. In this way, the combination of forming a trench 120 on the front side 106 of the substrate 105 and thinning the substrate 105 from the rear side 107 through the bottom of the trench 120 achieves the separation of the semiconductor die 115 from the substrate 105, thereby eliminating the cutting step of physically cutting the semiconductor die 115 from the substrate 105.

[0026] Still referencing Figure 1G Because the substrate 105 shared by the semiconductor dies 115 no longer exists and the semiconductor dies 115 are coupled to each other by the adhesive material 130, warping of the substrate 105 can be avoided during subsequent process steps performed on the back side 107 of the semiconductor dies 115. In other words, the pressure (or force) applied to the semiconductor dies 115 by the back-side wafer processing steps can be at least partially absorbed by the adhesive material 130, rather than subjecting the substrate 105 to pressure (or force) that could, for example, create defects (e.g., slippage, crystal dislocation) in the substrate 105 during the debonding step.

[0027] As described herein, the various process steps associated with forming the trench 120 filled with adhesive material 130 (and the first dielectric layer 125) and thinning the substrate 105 from the back side 107 of the substrate 105 include conventional semiconductor process steps that can be performed in a semiconductor manufacturing environment (e.g., a cleanroom environment). Cleanroom process steps are inherently cleaner than conventional dicing processes involving mechanical cutting of the substrate 105. Therefore, the semiconductor die 115 separated from the substrate 105 according to the technology of the present invention can benefit from cleanroom process steps, such as reducing particles, debris, contaminants, damage, cracks, or the like, to improve the yield and reliability of the semiconductor die 115. Furthermore, the final thickness of the semiconductor die 115 can be thinner than the final thickness of a semiconductor die 115 separated by a conventional dicing process—for example, the semiconductor die 115 does not need to maintain a certain thickness during the dicing process to withstand various forces. A thinner semiconductor die 115 can reduce package height and / or facilitate the use of advanced packaging technologies (e.g., combination bonding) for the semiconductor die 115.

[0028] Furthermore, compared to dicing techniques, cleanroom process steps are more compatible with new materials (e.g., low-k dielectric materials, ultra-low-k dielectric materials) that may be necessary for integrating advanced semiconductor devices. Additionally, the present invention reduces the production cost of semiconductor dies 115 by separating all semiconductor dies 115 from the substrate 105 simultaneously at the wafer level, rather than by sawing a row (or column) of semiconductor dies 115 (one row (or column) at a time). Other benefits of the present invention may include the ability to flexibly place semiconductor dies 115 on the substrate 105 (which may be referred to as a wafer pattern of semiconductor dies) to increase the total number of semiconductor dies, since trenches 120 do not need to be formed in a straight line (as in dicing channels). For example, one or more rows (or columns) of semiconductor dies 115 may be shifted relative to adjacent rows (or columns) of semiconductor dies 115 to reduce the number of dies in the periphery of the wafer. Furthermore, the present invention facilitates variations in the shape and size of semiconductor dies 115 within a semiconductor wafer. For example, individual semiconductor dies 115 may be hexagonal (or different shapes other than conventional rectangular shapes). For example, hexagonal shapes can increase the total number of memory dies that can be placed in a semiconductor wafer, or provide an efficient layout of various components within the semiconductor die.

[0029] Figure 1H This is a cross-sectional view of the semiconductor die 115 attached to the carrier substrate 135 after the second dielectric layer 145 has been formed on the back side 107. (This can be achieved by performing a reference...) Figure 1BThe second dielectric layer 145 is formed using one or more process steps, such as deposition processes (e.g., CVD and / or PVD processes). The second dielectric layer 145 may comprise various dielectric materials, such as oxides, nitrides, oxynitrides, or combinations thereof. In some exemplary embodiments, the second dielectric layer 145 may comprise a composite layer having nitrides and oxides formed at relatively low temperatures (which may be referred to as low-temperature nitrides and oxides (LTNO)). In other exemplary embodiments, the second dielectric layer 145 may comprise a silicon nitride (SiN) layer and / or a tetraethyl orthosilicate (TEOS) layer. The second dielectric layer 145 may protect the backside 107 of the individual semiconductor die 115 from contaminants (e.g., copper) and / or protect the backside during subsequent processing steps (e.g., one or more cleaning steps to remove the adhesive material 130) to form a conductive component (e.g., the under-bump metallization (UBM) structure of the TSV 140). After the second dielectric layer 145 is formed, the TSV 140 can be embedded within the second dielectric layer 145. In addition, an interface 150 can be formed between the second dielectric layer 145 and the first dielectric layer 125 (and / or adhesive material 130).

[0030] Figure 1I This illustration shows a cross-sectional view of the semiconductor die 115 attached to the carrier substrate 135 after a portion of the second dielectric layer 145 has been removed to expose the TSV 140 of the semiconductor die 115 from the back side 107. In some embodiments, a CMP process may be performed to remove a portion of the second dielectric layer 145 to expose the TSV 140 of the semiconductor die 115. In other embodiments, an etching process may be performed to remove a portion of the second dielectric layer 145 to expose the TSV 140 of the semiconductor die 115. The interface 150 between the first dielectric layer 125 and the second dielectric layer 145 may be retained after the CMP process step (or etching process step).

[0031] In some embodiments, after the TSV 140 on the surface of the second dielectric layer 145 is exposed, one or more process steps may be performed on the backside 107 to form a conductive component—for example, a UBM structure corresponding to the TSV 140 to facilitate the stacking of semiconductor dies 115. Such process steps may include additional deposition process steps (e.g., forming one or more metal / conductive layers), photolithography process steps (e.g., defining the UBM structure corresponding to the TSV 140), etching process steps (e.g., removing excess metal / conductive material if unnecessary), cleaning process steps (e.g., removing photoresist, removing various byproducts generated during the etching process), etc. The adhesive material 130, once cured (e.g., as referenced...), Figure 1EAs described, (after thermal solidification), it can exhibit material properties (e.g., hardness modulus) sufficient to maintain its structural and / or compositional integrity (e.g., remain within the groove 120) during process steps. However, specific solvents that selectively dissolve the adhesive material 130 can be used to remove the adhesive material 130.

[0032] Figure 1J This illustration shows a cross-sectional view of a semiconductor die 115 attached to a carrier substrate 135 after the adhesive material 130 within the trench 120 has been partially removed from the back side 107 using a cleaning process (e.g., using a specific solvent to dissolve the adhesive material 130). Partial removal of the adhesive material 130 at this stage facilitates removal from the substrate as shown in the reference diagram. Figure 1L The described groove 120 completely removes the adhesive material 130. In some embodiments, this cleaning step may be omitted.

[0033] Figure 1K This illustration shows a cross-sectional view of the semiconductor die 115 attached to the thin-film frame sheet 155 after it has been detached (debonded) from the carrier substrate 135 (e.g., by removing the adhesive material 130 between the carrier substrate 135 and the semiconductor die 115). Furthermore, Figure 1K The semiconductor die 115 has been flipped to depict the front side 106 above the rear side 107. Figure 1K It also describes holding the adhesive material 130 within the groove 120.

[0034] Figure 1L This diagram illustrates a cross-sectional view of a semiconductor die 115 attached to a thin-film frame sheet 155 after the adhesive material 130 in the trench 120 has been removed. Subsequently, the functionality of individual dies 115 can be tested, and individual dies can be picked up from the thin-film frame sheet 155 for further processing, such as stacking multiple semiconductor dies 115 to form a semiconductor die assembly.

[0035] Each semiconductor die 115 may include an integrated circuit (e.g., integrated circuit 141) formed on a front side (e.g., front side 106) of a semiconductor substrate, a first dielectric layer (e.g., first dielectric layer 125) on a sidewall of the semiconductor substrate, and a second dielectric layer (e.g., second dielectric layer 145) on a rear side (e.g., rear side 107) of the semiconductor substrate opposite to the front side, wherein the second dielectric layer and the first dielectric layer may be discontinuous (e.g., due to the interface 150 between the first dielectric layer 125 and the second dielectric layer 145). In some embodiments, the first dielectric layer comprises at least two dielectric materials—for example, an oxide layer in contact with the sidewall of the semiconductor substrate, and a nitride layer in contact with the oxide layer. In some embodiments, the first dielectric layer comprises a first dielectric material (e.g., oxide), and the second dielectric layer comprises a second dielectric material (e.g., nitride) different from the first dielectric material. In some embodiments, the first and second dielectric materials comprise oxides, nitrides, oxide oxynitrides, or combinations thereof. In some embodiments, the semiconductor die 115 may include one or more vias (e.g., TSV 140) extending from the front side of the semiconductor substrate through a second dielectric material on the rear side, wherein the one or more vias are coupled to an integrated circuit and configured to provide one or more electrical connections to the integrated circuit on the surface of the second dielectric material (e.g., the second dielectric layer 145).

[0036] Figure 2 This is a flowchart 200 illustrating a method for protecting the edges of a semiconductor die according to an embodiment of the present invention. Flowchart 200 may include, as referenced... Figures 1A to 1L Aspects of the described method.

[0037] The method includes forming a plurality of trenches on the front side of a substrate comprising a plurality of semiconductor dies, wherein individual trenches of the plurality of trenches correspond to scribe lines on the substrate (box 210). The method further includes filling each of the plurality of trenches with an adhesive material (box 215). The method further includes thinning the substrate from the back side of the substrate (box 220). The method further includes removing the adhesive material to separate individual semiconductor dies of the plurality of semiconductor dies (box 225).

[0038] In some embodiments, forming a plurality of trenches includes performing an etching process on the front side of the substrate. In some embodiments, each of the plurality of trenches includes a depth greater than the thickness of an individual diced semiconductor die. In some embodiments, the method may further include forming a first dielectric layer on the sidewalls of the plurality of trenches before filling each of the plurality of trenches with an adhesive material. In some embodiments, the method may further include attaching a carrier substrate to the substrate using an adhesive material on the front side of the substrate before thinning the substrate on the back side.

[0039] In some embodiments, thinning the substrate from the back side includes exposing adhesive material in each of a plurality of trenches from the back side of the substrate. In some embodiments, the method may further include forming a second dielectric layer on the back side of the substrate after thinning the substrate from the back side, and removing at least a portion of the second dielectric layer to expose adhesive material in each of the plurality of trenches. In some embodiments, removing at least a portion of the second dielectric layer also exposes one or more through-silicon vias (TSVs) of a plurality of semiconductor dies. In some embodiments, the method may further include attaching a thin-film frame sheet to the second dielectric layer held on the back side of the substrate before removing the adhesive material.

[0040] Figure 3 This is a flowchart 300 illustrating a method for protecting the edges of a semiconductor die according to an embodiment of the present invention. Flowchart 300 may include, as referenced... Figures 1A to 1L Aspects of the described method.

[0041] The method includes forming a plurality of trenches on the front side of a semiconductor substrate comprising a plurality of semiconductor dies, each of the plurality of trenches having a depth greater than the final thickness of an individual semiconductor die (box 310). The method further includes forming a first dielectric layer on the sidewalls of the plurality of trenches (box 315). The method further includes filling each of the plurality of trenches with an adhesive material coated on the front side of the semiconductor substrate (box 320). The method further includes thinning the semiconductor substrate from the back side of the semiconductor substrate to its final thickness (box 325). The method further includes removing the adhesive material to separate the individual semiconductor dies (box 330).

[0042] In some embodiments, forming a first dielectric layer on the sidewalls further includes forming the first dielectric layer on the front side of the semiconductor substrate, which includes a plurality of trenches, and performing an etching process on the front side of the semiconductor substrate to remove the first dielectric layer from the front side of the semiconductor substrate and from the bottom of an individual trench among the plurality of trenches. In some embodiments, the method may further include attaching a carrier substrate to the semiconductor substrate using an adhesive material on the front side of the semiconductor substrate before thinning the semiconductor substrate.

[0043] In some embodiments, thinning the semiconductor substrate from the back side further includes removing a first portion of the semiconductor substrate from the back side using a first process without exposing the adhesive material in the trench, and then removing a second portion of the semiconductor substrate from the back side using a second process after removing the first portion, so as to expose the adhesive material in the trench due to the removal of the second portion of the semiconductor substrate. In some embodiments, the second process is configured to remove the semiconductor substrate at a first removal rate and remove the adhesive material at a second removal rate less than the first removal rate. In some embodiments, after removing the second portion, the back side of the semiconductor substrate is recessed relative to the exposed adhesive material.

[0044] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more embodiments from the methods may be combined.

[0045] In summary, it should be understood that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications can be made without departing from this disclosure. For example, although the above example process sequence will achieve... Figure 1F The first process (e.g., CMP process) and implementation of the results described herein Figure 1G The second process (e.g., etching process) described herein is illustrated as two separate process steps utilizing two different process modules (e.g., a CMP module and an etching module), but the invention is not limited thereto. That is, the process steps for thinning the substrate 105 to expose the adhesive material 130 (and TSV 140) from the back side 107 can be performed without using two different process modules.

[0046] For example, in order to achieve... Figure 1F Following the results described herein (e.g., using previously established substrate removal rates based on total CMP process time), various process parameters of the CMP process can be modified (e.g., using different pastes, changing the pressure associated with the stage of the wafer chuck and / or CMP tool, fine-tuning the rotational speed / or orientation of the wafer chuck and / or stage, etc.) to reduce the substrate removal rate, allowing the CMP process to continue removing the substrate 105 at a finely tuned removal rate to expose the adhesive material 130, thereby achieving Figure 1G The results described herein do not require switching to an etching process. Alternatively, the CMP process may utilize an endpoint mechanism based on the detection of changes in frictional force monitored by the motor of the CMP tool when the first dielectric layer 125 and the adhesive material 130 are exposed. This endpoint mechanism may indicate that, at least in certain areas of the substrate 105, the CMP process has reached the bottom of the trench 120 from the back side 107, allowing the CMP process to be subsequently fine-tuned to precisely control the removal rate. Furthermore, certain aspects of the inventive techniques described in the context of the specific embodiments may be combined or removed in other embodiments.

[0047] The devices containing semiconductor devices discussed herein can be formed on semiconductor substrates or dies such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0048] As used herein, the word "or" included in the claims, as in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of"), indicates a list of items such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0049] As will be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details have been set forth in the foregoing description to provide a thorough and illustrative description of embodiments of the invention. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the art. Generally, it should be understood that various other devices, systems, and methods besides those specific embodiments disclosed herein are within the scope of the invention.

Claims

1. A method for edge protection and separation of semiconductor dies, comprising: Multiple trenches are formed on the front side of a substrate containing multiple semiconductor dies, wherein an individual trench of the multiple trenches corresponds to a scribing line on the substrate; Fill each of the plurality of trenches with adhesive material; The substrate is thinned from the rear side; After thinning the substrate from the rear side, a second dielectric layer is formed on the rear side of the substrate; At least a portion of the second dielectric layer is removed to expose the adhesive material in each of the plurality of trenches; and Remove the adhesive material to separate individual semiconductor dies from the plurality of semiconductor dies.

2. The method of claim 1, wherein forming the plurality of trenches comprises performing an etching process on the front side of the substrate.

3. The method of claim 1, wherein each of the plurality of trenches comprises a depth greater than the thickness of the individual diced semiconductor wafers.

4. The method of claim 1, further comprising: Before filling each of the plurality of trenches with the adhesive material, a first dielectric layer is formed on the sidewalls of the plurality of trenches.

5. The method of claim 1, further comprising: The carrier substrate is attached to the substrate using the adhesive material on the front side of the substrate before the substrate is thinned from the rear side.

6. The method of claim 1, wherein thinning the substrate from the rear side comprises exposing the adhesive material in each of the plurality of trenches from the rear side of the substrate.

7. The method of claim 1, wherein removing at least a portion of the second dielectric layer further exposes one or more through-silicon vias (TSVs) of the plurality of semiconductor dies.

8. The method of claim 1, further comprising: Before removing the adhesive material, a thin film frame sheet is attached to the second dielectric layer held on the rear side of the substrate.

9. A method for edge protection and separation of semiconductor dies, comprising: Multiple trenches are formed on the front side of a semiconductor substrate containing multiple semiconductor dies, each of the multiple trenches having a depth greater than the final thickness of the individual semiconductor dies; A first dielectric layer is formed on the sidewalls of the plurality of trenches; Each of the plurality of trenches is filled with an adhesive material coated on the front side of the semiconductor substrate; The semiconductor substrate is thinned from the back side of the semiconductor substrate to the final thickness; After the semiconductor substrate is thinned from the rear side to the final thickness, a second dielectric layer is formed on the rear side of the semiconductor substrate; At least a portion of the second dielectric layer is removed to expose the adhesive material in each of the plurality of trenches; and Remove the adhesive material to separate the individual semiconductor dies.

10. The method of claim 9, wherein forming the first dielectric layer on the sidewall further comprises: The first dielectric layer is formed on the front side of the semiconductor substrate, which includes the plurality of trenches; and An etching process is performed on the front side of the semiconductor substrate to remove the first dielectric layer from the front side of the semiconductor substrate and from the bottom of an individual trench among the plurality of trenches.

11. The method of claim 9, further comprising: Before thinning the semiconductor substrate, the carrier substrate is attached to the semiconductor substrate using the adhesive material on the front side of the semiconductor substrate.

12. The method of claim 9, wherein thinning the semiconductor substrate from the rear side further comprises: Without exposing the adhesive material in the trench, a first portion of the semiconductor substrate is removed from the rear side using a first process; and After removing the first portion, a second portion of the semiconductor substrate is removed from the rear side using a second process to expose the adhesive material in the trench due to the removal of the second portion of the semiconductor substrate.

13. The method of claim 12, wherein the second process is configured to remove the semiconductor substrate at a first removal rate and to remove the adhesive material at a second removal rate less than the first removal rate.

14. The method of claim 12, wherein after the second portion is removed, the rear side of the semiconductor substrate is recessed relative to the exposed adhesive material.

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