Three-dimensional memory and methods of making the same
By employing a two-stage annealing process, the doped ions in the GIDL region are partially and fully activated, thus resolving the issue of initial threshold voltage offset in the storage cells of the three-dimensional memory and improving the read, write, and erase performance of the three-dimensional memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2021-09-18
- Publication Date
- 2026-06-09
Smart Images
Figure CN113921532B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory and its fabrication method. Background Technology
[0002] Currently, flash memory, also known as flash storage, has become the mainstream non-volatile memory. The main characteristics of flash memory are its ability to retain stored information for extended periods without power, and it boasts advantages such as high integration density, fast access speed, and ease of erasing and rewriting. Therefore, it has been widely used in microcomputers, automation control, and many other fields.
[0003] In novel three-dimensional memories such as flash memory, a semiconductor substrate is used to form the peripheral circuit area, and a stacked structure is used to form the memory cell array area. Then, the circuits of the peripheral circuit area and the memory cell array area are bonded together face to face. The wafer containing the memory cell array area is then thinned from the back to expose the circuits.
[0004] Compared to planar transistor structures, the vertical structure of the aforementioned three-dimensional memory requires more critical and complex manufacturing processes. As three-dimensional memories shift towards configurations with more memory cell layers to achieve higher densities at lower per-bit costs, improving the structure and manufacturing methods of memory devices becomes increasingly challenging. For example, controlling the initial threshold voltage (Uvvt) of the memory cells in a three-dimensional memory becomes challenging with the introduction of more memory cell layers. Summary of the Invention
[0005] In view of this, embodiments of the present invention aim to provide a three-dimensional memory and a method for fabricating the same, the method comprising:
[0006] A first semiconductor structure and a second semiconductor structure are provided, which are bonded together; wherein the first semiconductor structure includes: a sacrificial semiconductor layer, a stacked structure located on the sacrificial semiconductor layer, and a channel structure extending through the stacked structure and into the sacrificial semiconductor layer; the channel structure includes a stacked storage material layer and a channel layer;
[0007] Remove the sacrificial semiconductor layer and part of the memory material layer to expose part of the channel layer;
[0008] At least the exposed channel layer should undergo a first doping treatment;
[0009] The first semiconductor structure after the first doping treatment is subjected to a first annealing treatment;
[0010] A semiconductor layer is formed on the exposed channel layer after the first annealing process;
[0011] The first semiconductor structure with the semiconductor layer formed is subjected to a second annealing process.
[0012] In the above scheme, the first annealing process performed on the first semiconductor structure after the first doping treatment includes:
[0013] In the furnace tube, the first semiconductor structure after the first doping treatment is subjected to a first annealing treatment;
[0014] The second annealing process for the first semiconductor structure on which the semiconductor layer is formed includes:
[0015] The first semiconductor structure with the semiconductor layer formed is subjected to laser annealing.
[0016] In the above scheme, forming a semiconductor layer on the channel layer exposed after the first annealing process includes:
[0017] In a furnace tube, a semiconductor layer is formed on the exposed channel layer after the first annealing process; wherein the formation of the semiconductor layer on the exposed channel layer after the first annealing process and the first annealing process of the first semiconductor structure after the first doping process are performed in the same furnace tube.
[0018] In the above scheme, the annealing temperature range used during the first annealing process is 400℃~470℃.
[0019] In the above scheme, forming a semiconductor layer on the exposed channel layer after the first annealing process includes:
[0020] Semiconductor material is deposited on the exposed channel layer after a first annealing process at a first temperature and a first pressure.
[0021] The deposited semiconductor material is subjected to a second doping treatment to form the semiconductor layer.
[0022] In the above scheme, the first temperature is not higher than 420℃ and the first pressure is not higher than 3 Torr.
[0023] In the above scheme, the doping gas used in the second doping process includes PH3, and the flow rate of PH3 is between 0.3 slm and 0.8 slm.
[0024] In the above scheme, the materials of the semiconductor layer and the channel layer include polycrystalline silicon.
[0025] In the above scheme, the first semiconductor structure further includes a first substrate; the sacrificial semiconductor layer is located on the front side of the first substrate;
[0026] The second semiconductor structure includes a second substrate and peripheral devices located on the front side of the second substrate;
[0027] The first semiconductor structure and the second semiconductor structure are bonded with the front side of the first substrate facing the front side of the second substrate.
[0028] This invention also provides a three-dimensional memory, comprising: a three-dimensional memory manufactured by the method for preparing a three-dimensional memory according to this invention.
[0029] This invention provides a three-dimensional memory and its fabrication method. The fabrication method includes: providing a first semiconductor structure and a second semiconductor structure bonded together; wherein the first semiconductor structure includes: a sacrificial semiconductor layer, a stacked structure on the sacrificial semiconductor layer, and a channel structure extending through the stacked structure and into the sacrificial semiconductor layer; the channel structure includes a stacked storage material layer and a channel layer; removing the sacrificial semiconductor layer and a portion of the storage material layer to expose a portion of the channel layer; performing a first doping treatment on at least the exposed channel layer; performing a first annealing treatment on the first semiconductor structure after the first doping treatment; forming a semiconductor layer on the exposed channel layer after the first annealing treatment; and performing a second annealing treatment on the first semiconductor structure with the semiconductor layer formed. In the fabrication of the three-dimensional memory in this invention, to avoid the first and second semiconductor structures peeling off at high temperatures, the annealing time must be strictly controlled during the annealing treatment, which may result in insufficient activation of the dopant ions in the GIDL region. In this embodiment, without stripping the first and second semiconductor structures, a first annealing process is performed on the exposed channel layer before forming the semiconductor layer to at least partially activate the dopant ions in the GIDL region. After forming the semiconductor layer, a second annealing process is performed to fully activate the dopant ions in the GIDL region. Therefore, even with strict control of the annealing time during the second annealing process, the dopant ions implanted in the GIDL region can be fully activated, thereby increasing the second annealing process window and improving the initial threshold voltage offset (U) of the memory cell. VVT Addressing the issue of Tail, this improves the performance of reading, writing, and erasing in 3D memory. Attached Figure Description
[0030] Figure 1 A schematic diagram of the initial threshold voltage distribution in different regions of a three-dimensional memory after a single annealing process in a related technology.
[0031] Figure 2 A schematic diagram of the initial threshold voltage distribution in different regions of a three-dimensional memory after undergoing two annealing processes, provided in an embodiment of the present invention.
[0032] Figure 3 A schematic diagram illustrating the implementation process of a method for fabricating a three-dimensional memory according to an embodiment of the present invention;
[0033] Figures 4a-4i A cross-sectional schematic diagram illustrating the fabrication process of a three-dimensional memory provided in an embodiment of the present invention;
[0034] Figure 5 A resistivity test condition diagram of the doped region after the first annealing treatment of a three-dimensional memory provided in an embodiment of the present invention;
[0035] Figure 6 The equivalent resistivity distribution of the doped region of a three-dimensional memory provided in this embodiment of the invention after undergoing a first annealing process at 420°C and 450°C. Detailed Implementation
[0036] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0037] In the description of this invention, it should be understood that the terms "length", "width", "depth", "upper", "lower", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.
[0038] In embodiments of the invention, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
[0039] In embodiments of the invention, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.
[0040] In this embodiment of the invention, the terms "first," "second," etc., are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
[0041] It should be noted that the technical solutions described in the embodiments of the present invention can be combined arbitrarily without conflict.
[0042] A method for fabricating a three-dimensional memory mainly includes: forming a stacked structure covering the front side of a first wafer and a channel structure penetrating the stacked structure and extending into the wafer on the front side of a first wafer; the channel structure includes a stacked storage material layer and a channel layer; forming a peripheral circuit on the front side of a second wafer; forming a first metal interconnect layer on the stacked structure and a second metal interconnect layer on the peripheral circuit; and bonding the front side of the first wafer to the front side of the second wafer.
[0043] The back side of the first wafer is thinned to expose a portion of the channel layer; the channel layer is ion-doped to reduce its resistivity; a semiconductor layer is formed on the exposed channel layer; and the semiconductor structure with the semiconductor layer formed is annealed.
[0044] In practical applications, a semiconductor layer is formed on the exposed channel layer, the semiconductor layer is doped, and the doped semiconductor layer is annealed to form the common source (ACS) of the memory cell.
[0045] In practical applications, since the formation of the semiconductor layer on the exposed channel layer and the annealing of the semiconductor structure with the semiconductor layer are performed after the first wafer and the second wafer are bonded, the processing temperature in the aforementioned two steps must be controlled to avoid debonding of the first wafer and the second wafer at high temperatures. It is understood that when forming the semiconductor layer on the exposed channel layer, the temperature at which the semiconductor layer is deposited in the furnace tube cannot exceed the debonding temperature of the first wafer and the second wafer; similarly, when annealing the semiconductor structure with the semiconductor layer, the annealing temperature cannot exceed the debonding temperature of the first wafer and the second wafer.
[0046] In practical applications, the annealing process is laser annealing. During laser annealing, infrared radiation from the laser source transfers heat to the semiconductor layer and the stacked structure on it via thermal radiation. On one hand, due to the limited penetration depth of the laser beam and the difference in heat absorption efficiency between the semiconductor layer and the stacked structure, the semiconductor layer and the stacked structure absorb different amounts of heat. Therefore, the semiconductor layer closer to the outer edge of the semiconductor structure absorbs more heat during laser annealing than the stacked structure, making it easier for the semiconductor layer closer to the outer edge to reach the predetermined temperature. On the other hand, since the annealing temperature cannot exceed the separation temperature between the first and second wafers, the laser annealing duration must be controlled. However, the difficulty in reaching the predetermined temperature of the stacked structure and the shorter laser annealing duration can lead to insufficient activation of the doped ions implanted in the gate-induced drain leakage (GIDL) region, resulting in a shift in the initial threshold voltage of the memory cell. Specifically, as shown... Figure 1 As shown. Figure 1 This is a schematic diagram of the initial threshold voltage distribution curves in three different regions of a three-dimensional memory. Figure 1 The horizontal axis represents the initial threshold voltage, and the vertical axis represents the number of measurement points. From... Figure 1 It can be seen that the initial threshold voltage distribution curves in different regions of the 3D memory show a significant shift after one annealing process. Here, the GIDL region refers to the region where GIDL current is generated during the erase operation.
[0047] In practical applications, the aforementioned 3D memory abandons the traditional single-crystal silicon substrate and utilizes polycrystalline silicon as the substrate for the memory cell array region to achieve the read, write, and erase functions of the 3D memory. On the one hand, as mentioned earlier, to avoid the first wafer and the second wafer peeling off at high temperatures, the processing temperature during the process must be controlled; on the other hand, laser annealing requires the simultaneous activation of doped ions in both the polycrystalline silicon substrate of the memory cell array region and the GIDL region. Therefore, this poses a significant challenge to short-time (nanosecond-level) laser annealing.
[0048] In practical applications, the fabrication process of 3D memory exhibits the following specific drawbacks: Firstly, since the polysilicon deposition process is performed after the bonding process between the first and second wafers, the laser annealing process cannot be too long to avoid delamination between the first and second wafers. Therefore, the duration of the laser annealing process must be controlled. Secondly, because the duration of the laser annealing process must be controlled, the dopant ions implanted in the GIDL region cannot be fully activated, thereby affecting the conductivity of the GIDL region and leading to a shift in the initial threshold voltage of the memory cells.
[0049] The inventors discovered that performing a first annealing process at a certain temperature before polysilicon deposition in a furnace tube, followed by forming a semiconductor layer on the exposed channel layer, and finally performing a second annealing process on the semiconductor structure with the semiconductor layer formed, can avoid the problem of initial threshold voltage shift in memory cells. The initial threshold voltage distribution in different regions of the semiconductor structure after the two annealing processes is shown below. Figure 2 As shown. (Through) Figure 1 and Figure 2 It can be seen that, compared with the semiconductor structure that has undergone one annealing process, the initial threshold offset problem in different regions of the semiconductor structure that has undergone two annealing processes is significantly improved.
[0050] Based on this, in various embodiments of the present invention, the method for fabricating a three-dimensional memory includes: providing a first semiconductor structure and a second semiconductor structure bonded together; wherein the first semiconductor structure includes: a first substrate, a stacked structure located on the first substrate, and a channel structure extending through the stacked structure and into the substrate; the channel structure includes a stacked storage material layer and a channel layer; removing the first substrate and a portion of the storage material layer to expose a portion of the channel layer; performing a first doping treatment on at least the exposed channel layer; performing a first annealing treatment on the first semiconductor structure after the first doping treatment; forming a semiconductor layer on the exposed channel layer after the first annealing treatment; and performing a second annealing treatment on the first semiconductor structure with the semiconductor layer formed. In the fabrication of the three-dimensional memory in the embodiments of the present invention, to avoid the first semiconductor structure and the second semiconductor structure peeling off at high temperatures, the annealing time must be strictly controlled during the annealing treatment, thereby preventing the dopant ions in the GIDL region from being fully activated. In this embodiment, while avoiding the stripping of the first and second semiconductor structures, compared to a process that simultaneously activates the dopant ions in the GIDL region and the semiconductor layer through a single annealing process, the dopant ions in the GIDL region are at least partially activated by a first annealing process before forming the semiconductor layer on the exposed channel layer, and the dopant ions in the GIDL region are fully activated by a second annealing process after forming the semiconductor layer. Therefore, even if the annealing time is strictly controlled during the second annealing process, the dopant ions injected into the GIDL region can be fully activated, thereby increasing the process window of the second annealing process, improving the problem of initial threshold voltage offset of the memory cell, and improving the read, write, and erase performance of the three-dimensional memory.
[0051] This invention provides a method for fabricating a three-dimensional memory. Figure 3 This is a schematic flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of this application. Figure 3 As shown, the method includes the following steps:
[0052] Step 301: Provide a first semiconductor structure and a second semiconductor structure bonded together; wherein the first semiconductor structure includes: a sacrificial semiconductor layer, a stacked structure located on the sacrificial semiconductor layer, and a channel structure extending through the stacked structure and into the sacrificial semiconductor layer; the channel structure includes a stacked storage material layer and a channel layer;
[0053] Step 302: Remove the sacrificial semiconductor layer and part of the storage material layer to expose part of the channel layer;
[0054] Step 303: Perform a first doping treatment on at least the exposed channel layer;
[0055] Step 304: Perform a first annealing treatment on the first semiconductor structure after the first doping treatment;
[0056] Step 305: Form a semiconductor layer on the exposed channel layer after the first annealing process;
[0057] Step 306: Perform a second annealing process on the first semiconductor structure with the semiconductor layer formed.
[0058] Figures 4a-4i This is a cross-sectional schematic diagram of the fabrication process of a three-dimensional memory according to an embodiment of the present invention. The following is in conjunction with... Figure 3 and Figures 4a-4i This embodiment describes a method for forming a three-dimensional memory. It should be noted that... Figure 3 and Figures 4a-4i The operations shown are not exhaustive, and other operations may be performed before, after, or between any of the operations shown.
[0059] In step 301, such as Figure 4a It mainly provides a first semiconductor structure 401 and a second semiconductor structure 402 that are bonded together; wherein, as Figure 4b As shown, the first semiconductor structure 401 includes: a sacrificial semiconductor layer 4011, a stacked structure 4012 located on the sacrificial semiconductor layer 4011, and a channel structure extending through the stacked structure 4012 and into the sacrificial semiconductor layer 4011; the channel structure includes a storage material layer 4014 and a channel layer 4013 stacked together.
[0060] In some embodiments, the first semiconductor structure 401 further includes a first substrate ( Figure 4b (Not shown in the image); the sacrificial semiconductor layer 4011 is located on the front side of the first substrate;
[0061] The second semiconductor structure 402 includes a second substrate 4021 and peripheral devices 4022 located on the front side of the second substrate 4021;
[0062] The first semiconductor structure 401 and the second semiconductor structure 402 are bonded such that the front side of the first substrate faces the front side of the second substrate 4021.
[0063] Here, the first semiconductor structure 401 can be understood as the aforementioned memory cell array region; the second semiconductor structure 402 can be understood as the aforementioned peripheral circuit region. In practical applications, the first substrate may include the aforementioned first wafer; the second substrate 4021 may include the aforementioned second wafer. Here, the front side can be understood as the surface on the semiconductor substrate where components, stacks, interconnects, and pads are formed.
[0064] In practical applications, the first substrate or the second substrate 4021 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
[0065] In practical applications, the stacked structure 4012 includes several spaced-apart first and second material layers. The first material layer can be a sacrificial layer, for example, formed from one of oxide layers, nitride layers, silicon carbide layers, silicon layers, and silicon-germanium layers; the second material layer can be a dielectric layer, the material of which includes, but is not limited to, silicon oxide, silicon nitride, silicon nitride, and other high-k dielectric layers. In subsequent processes, the sacrificial layer can be removed, and the removed location can be filled with gate metal material to form a gate layer, the material of which includes, for example, tungsten (W). In a specific embodiment, the first material layer can be formed from silicon nitride (SiN); the second material layer can be formed from silicon oxide (SiO2), thereby forming a nitride-oxide (NO) stacked structure. In practical applications, both the first and second material layers can be formed using processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD); wherein the first and second material layers can have the same thickness or different thicknesses.
[0066] In practical applications, the storage channel structure includes a channel aperture and a storage material layer 4014 and a channel layer 4013 sequentially stacked along the radial direction of the storage channel aperture. The storage material layer 4014 may include a barrier dielectric layer 4014-1, a charge trapping layer 4014-2, and a tunneling dielectric layer 4014-3. In practical applications, the barrier dielectric layer 4014-1, the charge trapping layer 4014-2, the tunneling dielectric layer 4014-3, and the channel layer 4013 are formed sequentially along the sidewall and bottom surface of the storage channel aperture. The barrier dielectric layer 4014-1 is used to block the outflow of charge from the storage layer, and its material can be silicon oxide; the charge trapping layer 4014-2 is used to trap and store charge, and its material can be silicon nitride; the tunneling dielectric layer 4014-3 is used to generate charge, and its material can be silicon oxide; the channel layer 4013 can be made of polycrystalline silicon. In some specific embodiments, the barrier dielectric layer 4014-1, the charge trapping layer 4014-2, the tunneling dielectric layer 4014-3, and the channel layer 4013 are referred to as ONOP films.
[0067] In practical applications, in some embodiments, the process of forming the first semiconductor structure 401 may include: forming a stacked structure 4012 on the front side of the first substrate; and forming a channel structure in the stacked structure 4012.
[0068] In one embodiment, the process of forming the second semiconductor structure 402 may include:
[0069] A second substrate 4021 is provided, on which peripheral devices 4022 are formed.
[0070] In practical applications, the second substrate 4021 may include the aforementioned second wafer. In some embodiments, peripheral devices 4022 may be formed on the front side of the second substrate 4021. The peripheral device 4022 is the peripheral circuitry of a three-dimensional memory. The peripheral circuitry may include multiple transistors and logic control circuits thereof, wherein the transistors may be CMOS transistors, used to control the on / off state of the peripheral device 4022. In practical applications, the peripheral device 4022 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or active or passive components in any circuit (e.g., transistors, diodes, resistors, or capacitors).
[0071] In one embodiment, the process of forming the peripheral device 4022 may include forming a plurality of transistors and the logic control circuits thereof.
[0072] In step 302, the first substrate and a portion of the storage material layer 4014 are removed to expose a portion of the channel layer 4013.
[0073] In some embodiments, the first semiconductor structure 401 further includes: covering the first substrate ( Figure 4b Insulating layer on the second surface (not shown) Figure 4b (Not shown), a dielectric layer covering the first surface of the first substrate ( Figure 4b (Not shown) A sacrificial semiconductor layer 4011 covering the dielectric layer; wherein, the stacked structure 4012 covers the sacrificial semiconductor layer 4011; the first surface and the second surface are opposite to each other. Here, the first surface can be understood as the aforementioned front side, and the second surface can be understood as the aforementioned back side.
[0074] In practical applications, the insulating layer, the first substrate, the dielectric layer, the sacrificial semiconductor layer 4011, and part of the storage material layer 4014 on the second surface of the first substrate are removed in sequence.
[0075] It should be noted that, Figure 4b Only the sacrificial semiconductor layer 4011 is shown; the insulating layer, dielectric layer, and first substrate are not shown. When removing the insulating layer, first substrate, dielectric layer, and sacrificial semiconductor layer 4011 from the second surface of the first substrate, films without extended channel structures can be removed by etching or grinding, while films containing channel structures can be removed by wet etching.
[0076] In one embodiment, a wet etching process is used to remove the insulating layer on the second surface of the first substrate, and CMP is used to treat the first substrate until the dielectric layer is exposed; the dielectric layer is then removed; as... Figure 4c The sacrificial semiconductor layer 4011 and a portion of the storage material layer 4014 are removed using a wet etching solution, thereby exposing the channel structure extending from the stacked structure. In some specific embodiments, the wet etching solution may include hydrofluoric acid (HF) or a mixture of hydrofluoric acid and one or more other acidic solutions selected from nitric acid (HNO3), phosphoric acid (H3PO4), and hydrogen peroxide (H2O2).
[0077] Next, refer to Figure 4dAfter removing the insulating layer, the first substrate, the dielectric layer, and the sacrificial semiconductor layer 4011 from the second surface of the first substrate, a portion of the storage material layer 4014 in the channel structure is removed, specifically the barrier dielectric layer 4014-1, the charge trapping layer 4014-2, and the tunneling dielectric layer 4014-3 extending from the stacked structure, to expose the channel layer 4013 extending from the stacked structure. In some embodiments, multiple wet etching processes are performed sequentially to achieve the purpose of sequentially removing the barrier dielectric layer 4014-1, the charge trapping layer 4014-2, and the tunneling dielectric layer 4014-3. In practical applications, a suitable etchant such as phosphoric acid can be used to selectively remove the charge trapping layer 4014-2, which includes silicon nitride, and then a suitable etchant such as hydrofluoric acid can be used to selectively remove the barrier dielectric layer 4014-1 and the tunneling dielectric layer 4014-3, which includes silicon oxide. Meanwhile, the etching of the barrier dielectric layer 4014-1, charge trapping layer 4014-2, and tunneling dielectric layer 4014-3 can be controlled by controlling the etching time and / or etching rate, so that the etching does not affect the barrier dielectric layer 4014-1, charge trapping layer 4014-2, and tunneling dielectric layer 4014-3 corresponding to the remaining parts of the channel hole portion.
[0078] In step 303, refer to Figure 4e At least the exposed channel layer 4013 undergoes a first doping treatment.
[0079] In one embodiment, the conductivity of the exposed channel layer 4013 is enhanced by forming a doped region in the channel layer 4013 through ion implantation. Here, doping can be understood as incorporating desired impurities into the semiconductor material at a desired concentration and distribution.
[0080] In one embodiment, the channel layer 4013 is made of polycrystalline silicon. The polycrystalline silicon undergoes a first doping process to reduce resistance.
[0081] In step 304, refer to Figure 4f The first semiconductor structure after the first doping treatment is subjected to a first annealing treatment.
[0082] In one embodiment, a first annealing treatment at a certain temperature is performed in a furnace tube to activate the doped ions in the GIDL region. In practical applications, during ion implantation, the atoms or molecules to be doped collide with the atomic nuclei after ionization, causing some nuclei to leave their lattice positions and form numerous vacancies and interstitial atoms in the crystal. This defect can reduce the carrier mobility in the semiconductor, affecting the performance of the three-dimensional memory. Therefore, after ion implantation, annealing is often used to restore the material to a crystalline state and activate the implanted ions. Here, activation can be understood as moving ions that are no longer at their lattice positions to the lattice points, thereby improving electrical performance.
[0083] In one embodiment, the annealing temperature range used in the first annealing process is 400°C to 470°C, preferably 450°C. It is understood that the annealing temperature used in the first annealing process is not higher than the temperature at which the first substrate and the second substrate 4021 are separated. In practical applications, since the separation temperature between the first semiconductor structure and the second semiconductor structure is greater than 470°C, the first annealing temperature must be controlled at 470°C or below to avoid separation of the first semiconductor structure and the second semiconductor structure at high temperatures.
[0084] Figure 5 The annealing conditions for three different wafers (numbered #01, #02, and #03) are listed; where the letter "v" indicates that the corresponding wafer was treated under the corresponding conditions, and the symbol "--" indicates that the corresponding wafer was not treated under the corresponding conditions. Figure 6 The equivalent resistivity and normalized resistivity uniformity values of different regions measured on three different wafers (numbered #01, #02, and #03) are listed; where the symbol "--" indicates that the corresponding wafer has no corresponding value under the corresponding conditions.
[0085] from Figure 6 It can be seen that: (1) After the first annealing process at 420℃ and 450℃, the doped region is activated; (2) As the first annealing temperature increases from 420℃ to 450℃, the resistivity of the doped region decreases significantly; however, the uniformity of resistivity decreases slightly. In other words, as the first annealing temperature increases, the conductivity of the doped region increases. It is understandable that a first annealing process temperature of 450℃ can activate the doped ions in the GIDL region as much as possible, thereby enhancing the conductivity of the GIDL region; (3) Since the wafer numbered #03 was not annealed, no effective resistivity equivalent average value and resistivity uniformity normalized value were recorded.
[0086] In one embodiment, the first annealing process is performed in a hydrogen atmosphere. During the fabrication of the 3D memory, the channel layer 4013 is damaged, resulting in surface dangling bonds, internal grain boundaries, and intragranular defects in the channel layer 4013. Generally, a hydrogen atmosphere annealing process is used for the 3D memory. During gas annealing, free hydrogen is generated. The hydrogen diffuses into the channel layer 4013 and combines with defects or grain boundaries in the semiconductor layer and surface dangling bonds, saturating the dangling bonds and thereby reducing defects in the semiconductor layer in the channel.
[0087] In the fabrication of the three-dimensional memory in this embodiment of the invention, to prevent the first semiconductor structure 401 and the second semiconductor structure 402 from peeling off at high temperatures, the annealing time must be strictly controlled during the annealing process, which may result in insufficient activation of the doped ions in the GIDL region. In this embodiment, while avoiding the peeling off of the first semiconductor structure 401 and the second semiconductor structure 402, compared to a process that simultaneously activates the doped ions in the GIDL region and the semiconductor layer 4015 through a single annealing process, the first annealing process before forming the semiconductor layer 4015 on the exposed channel layer 4013 at least partially activates the doped ions in the GIDL region. After forming the semiconductor layer 4015, a second annealing process ensures full activation of the doped ions in the GIDL region. Therefore, even with strict control of the annealing time during the second annealing process, the doped ions implanted in the GIDL region can be fully activated, thereby increasing the second annealing process window and improving the initial threshold voltage offset (U0) of the memory cell. VVT Addressing the issue of Tail, this improves the performance of reading, writing, and erasing in 3D memory.
[0088] In step 305, refer to Figure 4g A semiconductor layer 4015 is formed on the exposed channel layer 4013 after the first annealing process;
[0089] In one embodiment, a semiconductor layer 4015 is formed in the furnace tube on the exposed channel layer 4013 after the first annealing process.
[0090] In one embodiment, semiconductor material is deposited on the exposed channel layer 4013 after a first annealing process at a first temperature and a first pressure.
[0091] In one embodiment, the first temperature is not higher than 420°C and the first pressure is not higher than 3 Torr.
[0092] In one embodiment, the semiconductor layer 4015 and the channel layer 4013 are made of polycrystalline silicon. In one embodiment, the polycrystalline silicon layer is formed by CVD on the exposed channel layer 4013 after a first annealing treatment. In practical applications, temperatures above 420°C are unacceptable for the silane (Si₂H₆) feedstock gas used in the polycrystalline silicon deposition process; therefore, the process temperature for polycrystalline silicon deposition must be below 420°C. In practical applications, the pressure during the polycrystalline silicon deposition process cannot be too high, otherwise it will affect the uniformity of the wafer; therefore, the pressure during the polycrystalline silicon deposition process is required to be less than 3 Torr.
[0093] In one embodiment, the deposited semiconductor material is subjected to a second doping process to form the semiconductor layer 4015. In another embodiment, a doped region (not shown) is formed on the semiconductor layer 4015 by ion implantation.
[0094] In one embodiment, the semiconductor layer 4015 is P-type doped to form the source of the memory cell array region.
[0095] In one embodiment, the doping gas used in the P-type doping process includes PH3. A higher flow rate of PH3 results in a poorer doping effect. In practical applications, the flow rate of PH3 is between 0.3 slm and 0.8 slm.
[0096] In one embodiment, an electrical lead-out structure is formed on the semiconductor layer 4015 to lead out the electrical components of the memory array region and peripheral circuit region that need to be connected to external devices.
[0097] In one embodiment, the formation of the semiconductor layer 4015 on the exposed channel layer 4013 after the first annealing treatment and the first annealing treatment of the first semiconductor structure after the first doping treatment are performed in the same furnace tube. In practical applications, when the semiconductor layer 4015 is polycrystalline silicon, the process temperature for polycrystalline silicon deposition is less than 420°C. That is, after the first annealing treatment, the furnace tube temperature can be adjusted to 420°C or below to perform the polycrystalline silicon deposition process. Therefore, there is no need to reheat and raise the furnace tube before performing the polycrystalline silicon deposition process, thus simplifying the process and reducing production costs.
[0098] In step 306, refer to Figure 4h The first semiconductor structure with semiconductor layer 4015 formed is subjected to a second annealing process.
[0099] In one embodiment, the first semiconductor structure on which the semiconductor layer 4015 is formed is laser annealed to simultaneously activate the dopant ions in the channel layer 4013 and the semiconductor layer 4015. It is understood that the annealing temperature used in the second annealing process is not higher than the temperature at which the first substrate and the second substrate 4021 are separated.
[0100] In one embodiment, the semiconductor layer 4015 is amorphous silicon (A-Si). In practical applications, firstly, an amorphous silicon layer is formed on the exposed channel layer 4013 using chemical vapor deposition, and then a polycrystalline silicon layer is formed by irradiating the amorphous silicon layer using excimer laser crystallization; secondly, the polycrystalline silicon layer is doped using ion implantation; finally, the doped polycrystalline silicon layer is activated using laser annealing to obtain the semiconductor layer 4015.
[0101] In this embodiment of the application, before forming the semiconductor layer 4015 on the exposed channel layer 4013 after the first annealing process, a first annealing process at a certain temperature is performed to activate the doped ions in the GIDL region. Therefore, even if the duration of the second annealing process is strictly controlled, the doped ions injected in the GIDL region can be fully activated, thereby increasing the process window of the second annealing process.
[0102] In one embodiment, reference Figure 4i After performing a second annealing process on the first semiconductor structure with the semiconductor layer 4015 formed, the semiconductor layer 4015 is planarized. In practical applications, such as... Figure 4h The semiconductor layer 4015 can be planarized using CMP.
[0103] The method for fabricating a three-dimensional memory provided in this embodiment of the invention includes: providing a first semiconductor structure and a second semiconductor structure bonded together; wherein the first semiconductor structure includes: a sacrificial semiconductor layer, a stacked structure located on the sacrificial semiconductor layer, and a channel structure extending through the stacked structure and into the sacrificial semiconductor layer; the channel structure includes a stacked storage material layer and a channel layer; removing the sacrificial semiconductor layer and a portion of the storage material layer to expose a portion of the channel layer; performing a first doping treatment on at least the exposed channel layer; performing a first annealing treatment on the first semiconductor structure after the first doping treatment; forming a semiconductor layer on the exposed channel layer after the first annealing treatment; and performing a second annealing treatment on the first semiconductor structure with the semiconductor layer formed. In the fabrication of the three-dimensional memory in this embodiment of the invention, to avoid the first semiconductor structure and the second semiconductor structure peeling off at high temperatures, the annealing time must be strictly controlled during the annealing treatment, thereby preventing the dopant ions in the GIDL region from being fully activated. In this embodiment, while avoiding the stripping of the first and second semiconductor structures, compared to a process that simultaneously activates the dopant ions in the GIDL region and the semiconductor layer through a single annealing process, the first annealing process before forming the semiconductor layer on the exposed channel layer at least partially activates the dopant ions in the GIDL region, and the second annealing process after forming the semiconductor layer fully activates the dopant ions in the GIDL region. Therefore, even with strict control of the annealing time during the second annealing process, the dopant ions implanted in the GIDL region can be fully activated, thereby increasing the process window of the second annealing process and improving the initial threshold voltage offset (U) of the memory cell. VVT Addressing the issue of Tail, this improves the performance of reading, writing, and erasing in 3D memory.
[0104] Based on the above-described method for fabricating a three-dimensional memory, this embodiment of the invention also provides a three-dimensional memory; the three-dimensional memory is manufactured using the method provided in this embodiment of the invention. The three-dimensional memory undergoes the first annealing treatment and the second annealing treatment, which fully activates the doped ions in the GIDL region, improving the initial threshold voltage offset of the memory cells and enhancing the read, write, and erase performance of the three-dimensional memory.
[0105] It should be noted that the three-dimensional memory mentioned in the embodiments of the present invention may include a three-dimensional NAND type memory.
[0106] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for fabricating a three-dimensional memory, characterized in that, include: A first semiconductor structure and a second semiconductor structure are provided, which are bonded together; wherein the first semiconductor structure includes: a sacrificial semiconductor layer, a stacked structure located on the sacrificial semiconductor layer, and a channel structure extending through the stacked structure and into the sacrificial semiconductor layer; the channel structure includes a stacked storage material layer and a channel layer; Remove the sacrificial semiconductor layer and part of the memory material layer to expose part of the channel layer; At least the exposed channel layer should undergo a first doping treatment; The first semiconductor structure after the first doping treatment is subjected to a first annealing treatment, wherein the annealing temperature used in the first annealing treatment is not higher than the temperature at which the first semiconductor structure is separated from the second semiconductor structure. A semiconductor layer is formed on the exposed channel layer after the first annealing process; The first semiconductor structure with the semiconductor layer formed is subjected to a second annealing process.
2. The method according to claim 1, characterized in that, The first annealing process performed on the first semiconductor structure after the first doping treatment includes: In the furnace tube, the first semiconductor structure after the first doping treatment is subjected to a first annealing treatment; The second annealing process for the first semiconductor structure on which the semiconductor layer is formed includes: The first semiconductor structure with the semiconductor layer formed is subjected to laser annealing.
3. The method according to claim 2, characterized in that, The process of forming a semiconductor layer on the exposed channel layer after the first annealing includes: In a furnace tube, a semiconductor layer is formed on the exposed channel layer after the first annealing process; wherein the formation of the semiconductor layer on the exposed channel layer after the first annealing process and the first annealing process of the first semiconductor structure after the first doping process are performed in the same furnace tube.
4. The method according to claim 2, characterized in that, The annealing temperature range used in the first annealing process is 400℃~470℃.
5. The method according to claim 1, characterized in that, The process of forming a semiconductor layer on the exposed channel layer after the first annealing includes: Semiconductor material is deposited on the exposed channel layer after a first annealing process at a first temperature and a first pressure. The deposited semiconductor material is subjected to a second doping treatment to form the semiconductor layer.
6. The method according to claim 5, characterized in that, The first temperature is not higher than 420°C, and the first pressure is not higher than 3 Torr.
7. The method according to claim 5, characterized in that, During the second doping process, the doping gas used includes PH3, and the flow rate of PH3 is between 0.3 slm and 0.8 slm.
8. The method according to claim 1, characterized in that, The semiconductor layer and the channel layer are made of polycrystalline silicon.
9. The method according to claim 1, characterized in that, The first semiconductor structure further includes a first substrate; the sacrificial semiconductor layer is located on the front side of the first substrate; The second semiconductor structure includes a second substrate and peripheral devices located on the front side of the second substrate; The first semiconductor structure and the second semiconductor structure are bonded with the front side of the first substrate facing the front side of the second substrate.
10. A three-dimensional memory, characterized in that, include: The three-dimensional memory is manufactured by the method according to any one of claims 1 to 9.