Heterojunction structure with perpendicular magnetic anisotropy at room temperature and applications thereof

Abstract

The application provides a heterojunction structure with perpendicular magnetic anisotropy at room temperature and an application thereof. The heterojunction structure comprises a van der Waals topological material layer and a two-dimensional magnetic material layer, wherein the thickness of the van der Waals topological material layer is 5-20 nm, and the thickness of the two-dimensional magnetic material layer is 1-10 nm. The application further provides a room-temperature full van der Waals spin-orbit torque magnetic memory comprising the above heterojunction structure, a room-temperature full van der Waals magnetoresistance device based on a topological insulator, and a device for implementing exclusive OR logic operation, a device for implementing bit counting operation, a device for implementing matrix-vector multiplication operation, and corresponding methods. The technical scheme of the application realizes the construction of a heterojunction structure with perpendicular magnetic anisotropy at room temperature and a spin electronic prototype device, and the prepared heterojunction structure and spin prototype device are simple, and the preparation method is simple to operate.

Description

Technical Field

[0001] This invention relates to the field of spin prototype device technology, specifically to heterojunction structures with perpendicular magnetic anisotropy at room temperature and their applications. Background Technology

[0002] With the continuous development of the electronics and information industry, electronic devices largely determine the performance of computers. From vacuum tubes to transistors, from discrete components to today's very large-scale integrated circuits, each technological iteration has triggered a major revolution in the computer field. Memory devices are one of the important components of the current computer architecture and one of the main application directions of magnetic materials. Currently, data storage devices based on magnetic materials are mainly divided into two categories: hard disk drives and magnetic random access memory (MRAM). At the same time, due to the rapid development of data-intensive applications such as artificial intelligence, the Internet of Things, and 5G communication, the efficient storage and processing of massive amounts of data poses a severe challenge to the traditional von Neumann computing architecture. Frequent data migration between discrete memory and processors causes a lot of energy consumption and latency, and the limited bandwidth of the bus also restricts the further improvement of computing power and energy efficiency of computer systems. Therefore, the new computing architecture of in-memory computing, which aims to perform calculations within memory, has gained widespread attention. Currently, MRAM has made remarkable progress as a non-volatile memory. Its basic storage unit is called a magnetic tunnel junction (MTJ). This core consists of a three-layer structure formed by two ferromagnetic metal layers sandwiching a tunneling barrier layer. One ferromagnetic layer is called the reference layer, with its magnetization direction fixed along the easy magnetization direction. The other ferromagnetic layer is called the free layer, and its magnetization direction has two stable directions, parallel or antiparallel to the reference layer, allowing the MTJ to exhibit either a low-resistance or high-resistance state. Furthermore, MRAM's ultra-low power consumption and good compatibility with CMOS back-end processes make it an excellent platform for building in-memory computing architectures. In many spin-based in-memory computing applications, binary neural networks (BNNs) can be naturally integrated with the binary storage characteristics of MRAM. Because they require learning and storing a large number of parameters, the currently widely used full-precision convolutional neural networks place high demands on computing power and storage resources. By binarizing the input and weights and replacing computationally intensive multiplication and addition operations with simple bitwise operations, BNN can significantly save power consumption in computer systems and greatly improve computation speed. Although BNN introduces some noise and reduces computational accuracy compared to its original full-precision convolutional neural network model, its extremely high compression ratio and acceleration effect make it a very promising technology for promoting the application of artificial intelligence models on resource- and power-constrained mobile and embedded devices.

[0003] Currently, spin orbital moment technology offers a novel writing method for magnetic memories. Spin orbital moment involves adding a non-ferromagnetic layer beneath a ferromagnetic layer and using a current source to input a charge flow into the non-ferromagnetic layer, generating a spin current. The resulting torque causes the magnetic moments in the ferromagnetic layer to reverse their magnetization direction. This technology offers significant advantages in reducing write power consumption and improving memory performance.

[0004] Two-dimensional materials are those in which electrons move only in a two-dimensional nanoscale, ranging from 1 to 100 nm. Since the first isolation of graphene, a single-atom-layer graphite material, two-dimensional materials have attracted widespread attention. To date, hundreds of two-dimensional materials have been theoretically and experimentally proven to be stable, some of which have already been applied in semiconductors, photovoltaics, and biomonitoring, while also holding the potential to trigger revolutionary breakthroughs in aerospace, integrated circuits, biomedicine, and the energy and environment sectors.

[0005] Ferromagnetic materials have wide applications in information processing, magnetic storage, and other technologies. When a stable ferromagnetic state is maintained at a single-atom-layer thickness, devices fabricated using this thin film can achieve advantages such as high efficiency and high integration. Therefore, two-dimensional magnetic materials have attracted widespread attention. Currently, Cr2Ge2Te6, CrI3, and Fe3GeTe2 are the main representatives and have received considerable attention. These materials can be cleaved to a single-layer thickness while still maintaining good physical and chemical stability and are easy to modulate. Unlike traditional magnetic thin films, two-dimensional magnetic materials may serve as the successor to silicon-based electronic devices. Utilizing spintronics, an important scientific and technological means in the post-Moore's Law era, it is hoped that novel spin prototype devices can be realized that are highly compatible with integrated circuit technology and integrate various functional devices. However, the Curie temperature (T0) is a significant factor. c The Curie temperature is a primary consideration in current research on magnetic two-dimensional materials. It refers to the temperature at which the spontaneous magnetization in a magnetic material drops to zero; it is the critical temperature at which ferromagnetic or ferrimagnetic materials transform into paramagnetic materials. Although bulk Fe3GeTe2 has a Curie temperature far higher than Cr2Ge2Te6 and CrI3, and is currently the highest... c While two-dimensional magnetic anisotropic thin films can be produced, the temperature remains below room temperature. This presents significant limitations and challenges to the application of two-dimensional magnetic materials in electronic devices, making it difficult to meet practical needs.

[0006] Currently, the best reported method for controlling the Curie temperature of two-dimensional magnetic materials is through topological coupling with them, utilizing interface engineering effects to significantly increase the Curie temperature of few-layer two-dimensional magnetic materials. Therefore, it is particularly important to construct a novel, high-efficiency room-temperature all-van der Waals spin-orbit moment magnetic memory cell based on two-dimensional materials and other materials. Furthermore, utilizing this memory cell to implement a binary neural network architecture is expected to further reduce write power consumption and improve the energy efficiency of neural network computation. Summary of the Invention

[0007] To address the aforementioned technical problems, the present invention aims to provide a fully van der Waals heterostructure with perpendicular magnetic anisotropy at room temperature and a fully van der Waals spintronic prototype device. This is achieved by growing a two-dimensional magnetic material on a van der Waals topological material, resulting in perpendicular magnetic anisotropy at room temperature, and by using the topological material to realize the magnetization reversal of the two-dimensional magnetic material.

[0008] The present invention also aims to provide a method for constructing a binary neural network based on a full van der Waals spin orbital moment magnetic memory unit.

[0009] To achieve the above objectives, the present invention provides a heterojunction structure with perpendicular magnetic anisotropy at room temperature, comprising a van der Waals topological material layer and a two-dimensional magnetic material layer grown on the van der Waals topological material layer, wherein the thickness of the van der Waals topological material layer is 5-20 nm and the thickness of the two-dimensional magnetic material layer is 1-10 nm.

[0010] According to a specific embodiment of the present invention, preferably, in the above heterojunction structure, the total thickness of the van der Waals topological material layer and the two-dimensional magnetic material layer does not exceed 20 nm.

[0011] According to a specific embodiment of the present invention, preferably, in the above-described heterojunction structure, the van der Waals topological material is selected from strongly spin-orbit coupled materials. The van der Waals topological material may be selected from Bi₂Se₃, Bi₂Te₃, Bi x Sb 1-x ,Sb2Te3 and (Bi x Sb 1-x One or more combinations of Bi₂Te₃, preferably Bi₂Te₃; wherein, the Bi x Sb 1-x The value of x in the equation can be approximately 0.9; the (Bi) x Sb 1-x In 2Te3, the value of x can range from approximately 0 to 1.

[0012] According to a specific embodiment of the present invention, preferably, in the above heterojunction structure, the two-dimensional magnetic material is a two-dimensional van der Waals material that is magnetic at room temperature, such as one or more combinations of Fe3GeTe2, Fe4GeTe2, Fe5GeTe2, Gr2Ge2Te6, and CrTe2; more preferably, it is Fe3GeTe2.

[0013] According to a specific embodiment of the present invention, preferably, the heterojunction structure further includes a substrate, and the van der Waals topological material layer is disposed on the substrate. The material of the substrate may be selected from sapphire and high Miller index gallium arsenide; preferably sapphire, more preferably (0001) oriented sapphire.

[0014] According to a specific embodiment of the present invention, the heterojunction structure with perpendicular magnetic anisotropy at room temperature can be prepared using molecular beam epitaxy, for example, by sequentially growing a van der Waals topological insulator Bi2Te3 and a two-dimensional magnetic material Fe3GeTe2 thin film on a sapphire substrate. In the Bi2Te3 / Fe3GeTe2 heterojunction grown by this method, both materials are in a single-crystal state, with a total thickness of less than 20 nm, and the prepared spintronic device has a micrometer-scale size.

[0015] The present invention also provides a room temperature full van der Waals spin-orbit moment magnetic memory, wherein the room temperature full van der Waals spin-orbit moment magnetic memory includes a bottom electrode layer, a van der Waals topology material layer, a first two-dimensional material layer, a barrier layer, a second two-dimensional material layer, and a top electrode arranged sequentially.

[0016] The van der Waals topological material layer and the first two-dimensional material layer constitute the heterojunction structure with perpendicular magnetic anisotropy at room temperature described above.

[0017] According to a specific embodiment of the present invention, preferably, in the above-mentioned room temperature full van der Waals spin-orbit magnetic memory, the van der Waals topological material layer is made of Bi2Te3 and has a thickness of 8 nm;

[0018] The first two-dimensional magnetic material layer is made of Fe3GeTe2 and has a thickness of 3-5 nm.

[0019] The material of the barrier layer is selected from one or more combinations of h-BN, graphite, MoS2, WS2, and doped graphene, and the thickness is 1-7 nm.

[0020] The material of the second two-dimensional magnetic material layer is Fe. 5-x GeTe2, with a thickness of 1-8nm.

[0021] The present invention also provides a room temperature full van der Waals spin-orbit magnetoresistive memory, which is a room temperature full van der Waals magnetoresistive device based on a topological insulator. The room temperature full van der Waals magnetoresistive device includes a bottom electrode layer, a van der Waals topological material layer, a first two-dimensional material layer, a topological insulator layer, a second two-dimensional material layer, and a top electrode arranged sequentially.

[0022] The van der Waals topological material layer and the first two-dimensional material layer constitute the heterojunction structure with perpendicular magnetic anisotropy at room temperature described above.

[0023] According to a specific embodiment of the present invention, preferably, in the above-mentioned room temperature full van der Waals magnetoresistive device, the van der Waals topological material layer is made of Bi2Te3 and has a thickness of 8 nm;

[0024] The first two-dimensional magnetic material layer is made of Fe3GeTe2 and has a thickness of 3-5 nm.

[0025] The material of the topological insulator layer is Bi2Te3, and the thickness is 1-5 nm.

[0026] The material of the second two-dimensional magnetic material layer is Fe3GeTe2, and the thickness is 3-5 nm.

[0027] The spin orbital moment magnetic storage device constructed using van der Waals materials in this invention can improve the interface spin transparency to prevent spin backflow and spin memory loss, and has many advantages such as improving spin orbital moment reversal efficiency.

[0028] According to a specific embodiment of the present invention, a charge flow is input into the van der Waals topological material layer of the above-mentioned room temperature full van der Waals spin orbital moment magnetic memory using a current source, so as to generate a spin current in the van der Waals topological material layer, and use the torque generated by it to achieve the purpose of magnetizing and reversing the magnetic moment in the two-dimensional magnetic material layer. The spin orbital moment generated by the spin current is based on the topological surface state effect, the Lashba effect, or the spin Hall effect.

[0029] This invention provides a method for constructing a full van der Waals spintronic prototype device at room temperature. The resulting room temperature full van der Waals spintronic prototype device has a simple structure and is easy to operate. Using mature molecular beam epitaxy technology, heterojunctions with controllable size and thickness can be rapidly prepared on sapphire substrates, which is suitable for the fabrication of large-scale nanodevices.

[0030] The present invention also provides an apparatus for implementing the XNOR logic operation, comprising a pair of room-temperature full van der Waals spin-orbit moment magnetic memories, word line pairs, and shared bit lines; the pair of room-temperature full van der Waals spin-orbit moment magnetic memories are used to store binary weights;

[0031] A pair of room temperature full van der Waals spin-orbit moment magnetoresistive memories are each connected to one of the word line pairs and are also connected to a shared bit line. That is, the two room temperature full van der Waals spin-orbit moment magnetoresistive memories are each connected to one of the word line pairs and are also connected to the same shared bit line.

[0032] The room-temperature full van der Waals spin-orbit moment magnetic memory is the room-temperature full van der Waals spin-orbit moment magnetic memory provided by the present invention.

[0033] According to a specific embodiment of the present invention, preferably, the apparatus for implementing the XOR logic operation further includes a voltage comparator or a sensing amplifier connected to the shared bit line.

[0034] According to a specific embodiment of the present invention, preferably, in the above-described device for implementing the XOR logic operation, the top electrode of the room temperature full van der Waals spin orbital magnetic memory is connected to the corresponding word line, and the bottom electrode is connected to the bit line.

[0035] This invention also provides a method for implementing the XNOR logic operation, which utilizes the aforementioned apparatus for implementing the XNOR logic operation, using a pair of room-temperature full van der Waals spin-orbit magnetic memories to store binary weights, and using the differential voltage on the word line pair as the binary input value to implement the XNOR logic operation; wherein:

[0036] One of a pair of room-temperature full van der Waals spin-orbit moment magnetoresistors is programmed to be in a high-resistance state and the other is programmed to be in a low-resistance state. The weights stored in the room-temperature full van der Waals spin-orbit moment magnetoresistors will correspond to logic values ​​1 or 0 respectively, depending on which magnetoresistor is programmed to be in a high-resistance state and which magnetoresistor is programmed to be in a low-resistance state.

[0037] The binary input value is applied as a differential voltage to the word line pairs connected to the room-temperature full van der Waals spin-orbit moment magnetoresistive memory (MEM). The MEM acts as a voltage divider, with one word line pair at a high level and the other at a low level (e.g., ground potential). For the relative positions of the high and low word lines, the binary input value corresponds to either a logic value 1 or a logic value 0 (depending on which word line in the word line pair is at a high level and which is at a low level, the binary input corresponds to a logic value 1 or a logic value 0).

[0038] By applying a differential voltage to the word line pair connected to the room temperature full van der Waals spin-orbit moment magnetic memory, a voltage divider is obtained on the shared bit line; depending on the voltage divider value obtained by different input values ​​and weighted pairings, the shared bit line is at a high voltage level or a low voltage level. The voltage of the shared bit line is compared with a reference voltage value to obtain the result of an XOR logic operation.

[0039] According to a specific embodiment of the present invention, preferably, the bit line is at a high voltage level or a low voltage level, depending on the voltage division value obtained by the pairing of different inputs and weights. The bit line voltage is compared with a reference voltage value to obtain the XOR logic operation result. The XOR logic operation result is obtained by a voltage comparator or a sense amplifier.

[0040] The present invention also provides an apparatus for implementing bit counting operations, comprising multiple pairs of room temperature full van der Waals spin-orbit moment magnetic memories connected to different word line pairs, and the room temperature full van der Waals spin-orbit moment magnetic memories connected to different word line pairs are connected to the same shared bit line.

[0041] The multiple pairs of room temperature full van der Waals spin-orbit moment magnetic memories are used to store binary weights; each pair of room temperature full van der Waals spin-orbit moment magnetic memories is connected to one of the word line pairs and is also connected to a shared bit line.

[0042] The room-temperature full van der Waals spin-orbit moment magnetic memory is the room-temperature full van der Waals spin-orbit moment magnetic memory provided by the present invention.

[0043] According to a specific embodiment of the present invention, preferably, the apparatus for implementing bit counting operations further includes a voltage comparator, a sensing amplifier, or an analog-to-digital converter (ADC) connected to the shared bit line.

[0044] According to a specific embodiment of the present invention, preferably, in the above-described device for implementing bit counting operations, the top electrode of the room temperature full van der Waals spin-orbit magnetic memory is connected to the corresponding word line, and the bottom electrode is connected to the bit line.

[0045] The present invention also provides a method for implementing bitcount operations, which is implemented using the aforementioned apparatus for implementing bitcount operations, comprising:

[0046] The device for implementing bit counting operations uses n pairs of room temperature full van der Waals spin-orbit magnetic memories and n pairs of word lines;

[0047] Based on different weights and input value pairings, the circuit is equivalent to: in n pairs of room temperature full van der Waals spin-orbit moment magnetoresistive memories, m pairs of low-resistivity room temperature full van der Waals spin-orbit moment magnetoresistive memories are connected to word lines at high level (correspondingly, the m pairs of high-resistivity room temperature full van der Waals spin-orbit moment magnetoresistive memories are connected to word lines at low level), and the remaining nm pairs of low-resistivity room temperature full van der Waals spin-orbit moment magnetoresistive memories are connected to word lines at low level (correspondingly, the nm pairs of high-resistivity room temperature full van der Waals spin-orbit moment magnetoresistive memories are connected to word lines at high level). These room temperature full van der Waals spin-orbit moment magnetoresistive memories are all connected to the same shared bit line BL.

[0048] The voltage on the shared bit line is:

[0049]

[0050] Where R AP For a room-temperature all-van der Waals spin-orbit magnetic memory with high resistance in the high-resistivity state, R P For the low-resistivity state resistance of a room-temperature all-van der Waals spin-orbit magnetic memory, V Bitcount For the voltage on the shared bit line;

[0051] According to V Bitcount The value of m is obtained, which is the accumulated result of the n-bit XOR operation, i.e., the result of the bit counting operation.

[0052] According to a specific embodiment of the present invention, preferably, according to V Bitcount The value of m is obtained through a voltage comparator, a sensing amplifier, or an analog-to-digital converter.

[0053] According to a specific embodiment of the present invention, the XOR operation and bit counting operation implemented based on the room temperature full van der Waals spin orbital moment magnetic memory can obtain the results of basic matrix-vector multiplication operations in binary neural networks.

[0054] The present invention also provides an apparatus for implementing matrix-vector multiplication operations in a binary neural network, wherein the binary neural network includes an input layer and an output layer, and there is at least one hidden layer between the input layer and the output layer;

[0055] The input layer, hidden layer, and output layer each include a word line decoder, as well as several voltage comparators, sense amplifiers, or analog-to-digital converters.

[0056] Each layer of the binary neural network has a cross-point array, which consists of several word line pairs, several shared bit lines, and several unit synapses. The intersection of each word line pair and each shared bit line is a unit synapse. The unit synapse stores the weights corresponding to each intersection of the respective layer. Each unit synapse is composed of a pair of room-temperature full van der Waals spin-orbit moment magnetic memories (MOMs). Each pair of MOMs is connected to one of the word line pairs and also to the shared bit line. The room-temperature full van der Waals spin-orbit moment magnetic memories are those described above in this invention.

[0057] The voltage comparator, sense amplifier, or analog-to-digital converter in the upper layer is connected to the word line decoder in the lower layer to input the calculation result of the upper layer into the lower layer, while the calculation result of the output layer is directly output.

[0058] According to a specific embodiment of the present invention, preferably, in the above-described apparatus for implementing matrix-vector multiplication in a binary neural network, the length of the input vector of the input layer is the same as the number of word line pairs of the input layer of the binary neural network.

[0059] According to a specific embodiment of the present invention, preferably, in the above-described apparatus for implementing matrix-vector multiplication in a binary neural network, the number of shared bit lines in each layer of the binary neural network is the same as the number of word line pairs in the next layer.

[0060] According to a specific embodiment of the present invention, preferably, in the above-described apparatus for implementing matrix-vector multiplication in a binary neural network, the top electrode of the room-temperature full van der Waals spin-orbit magnetic memory is connected to the corresponding word line, and the bottom electrode is connected to the bit line.

[0061] The present invention also provides a method for implementing matrix-vector multiplication, which is implemented using the aforementioned apparatus for implementing matrix-vector multiplication, comprising:

[0062] In a binary neural network, the weights and inputs are binarized into +1 and -1, which correspond to the logic values ​​1 and 0 respectively in the hardware.

[0063] The weight matrix is ​​stored in transpose on a cross-point array and consists of multiple columns of weight vectors; the dot product of the input vector Input and the weight vector W can be obtained by the following formula:

[0064] Input·W=Bitcount(Input XNORW)

[0065] Based on the received binary input values, the word line decoder selects the corresponding word line pairs and applies differential voltages to the selected word line pairs. The differential voltage on each word line pair is applied to all unit synapses connected to that word line pair. The output of the dot product operation of n input values ​​and n weights connected to the same bit line corresponds to different voltage levels on the bit line. The operation result is read out using a voltage comparator, sense amplifier, or analog-to-digital converter connected to the bit line. This operation result is one element of the output vector. The output vector is formed by the dot product operation of the input vector and all column weight vectors, which is the matrix-vector multiplication result of the input vector and the weight matrix.

[0066] The output vector of one layer is input to the next layer and the above process of selecting the corresponding word line pairs, applying differential voltage, outputting the calculation result, and reading the calculation result is repeated. For example, the calculation result of the input layer is input to the first hidden layer, the calculation result of the first hidden layer is input to the second hidden layer, and so on, until the calculation result of the penultimate layer is input to the output layer. Finally, the output layer completes the calculation and outputs the final calculation result.

[0067] The technical solution of this invention realizes the construction of heterostructures and spintronic prototype devices with perpendicular magnetic anisotropy at room temperature. The fabricated heterojunction structures and spintronic prototype devices are simple, and the fabrication method is easy to operate. Using mature molecular beam epitaxy technology, heterojunctions with controllable size and thickness can be rapidly fabricated on sapphire substrates, making it suitable for the fabrication of large-scale nanodevices. Furthermore, this invention also provides a binary neural network implementation scheme based on a room-temperature full van der Waals spin-orbit magnetic memory. This in-memory binary neural network model has a simple structure and can achieve high-energy-efficiency computation. Attached Figure Description

[0068] Figure 1 This is a schematic diagram of the heterojunction structure provided in Example 1.

[0069] Figure 2 A schematic diagram of the core structure of the room temperature full van der Waals spin orbital moment magnetic memory provided in Example 2.

[0070] Figure 3 This is a schematic diagram of the core structure of the room temperature full van der Waals magnetoresistive device based on topological insulator provided in Example 3.

[0071] Figures 4a-4d This is a schematic diagram of Example 4, which uses a pair of room-temperature full van der Waals spin-orbit magnetic memory cells as unit synapses and a pair of word line pairs with differential voltages as inputs to implement an XOR operation.

[0072] Figure 5 This is a schematic diagram of bit counting operations implemented using multiple pairs of room temperature full van der Waals spin-orbit moment magnetic memory cells and word line pairs, as provided in Example 5.

[0073] Figure 6a This is a schematic diagram of the apparatus for implementing matrix-vector multiplication in a binary neural network, as provided in Example 6.

[0074] Figure 6b This is a schematic diagram of Example 6, which uses room temperature full van der Waals spin-orbit magnetic memory cells to construct a weight matrix and performs matrix-vector multiplication operations in the matrix. Detailed Implementation

[0075] In order to provide a clearer understanding of the technical features, objectives and beneficial effects of the present invention, the technical solution of the present invention will now be described in detail below, but it should not be construed as limiting the scope of implementation of the present invention.

[0076] Example 1

[0077] This embodiment provides a heterojunction structure with perpendicular magnetic anisotropy at room temperature, which is a fully van der Waals heterostructure, as shown in the specific structure below. Figure 1 As shown, the heterojunction structure comprises a substrate, a topological insulating thin film (van der Waals topological material layer), and a two-dimensional magnetic material layer arranged sequentially.

[0078] The material of the topological insulator film is Bi2Te3, and the thickness is 8nm;

[0079] The material of the two-dimensional magnetic material layer is Fe3GeTe2, and the thickness is 3-5 nm.

[0080] The heterojunction structure with perpendicular magnetic anisotropy at room temperature in this embodiment was prepared using molecular beam epitaxy combined with material characterization techniques. The specific steps are as follows:

[0081] (1) Cleaning the substrate:

[0082] Taking (0001) sapphire as a substrate as an example, since sapphire is chemically stable and not easily corroded by acids and alkalis, a cleaning process is required before growing a thin film on the substrate. The cleaning procedure is as follows:

[0083] The sapphire substrate was ultrasonically treated in acetone and isopropanol for 5-6 minutes each, followed by ultrasonic treatment in deionized water for 5-6 minutes to remove organic matter from the surface of the substrate. It was then dried with nitrogen gas.

[0084] (2) Temperature verification:

[0085] The substrate temperature during growth is monitored using thermocouples, and the thermocouple temperatures are calibrated using a pyrometer. To ensure maximum temperature accuracy, the temperature is increased slowly to maintain thermal balance during each heating process.

[0086] (3) Growth of topological insulators:

[0087] The vacuum level inside the growth chamber is maintained at 10. -10 Around Torr, an ultra-high vacuum chamber houses bismuth (Bi) and tellurium (Te) evaporation source furnaces, employing thermal evaporation technology. The evaporation rate of both elements is determined using a film thickness monitoring instrument (FDC) to control the flux ratio during the growth process. The cleaned sapphire substrate is rapidly transferred into the ultra-high vacuum molecular beam epitaxy system and subjected to high-temperature annealing for approximately 30 minutes at a temperature of approximately 600℃-650℃. Subsequently, the substrate temperature is lowered to the growth temperature, and the film thickness is controlled by precisely controlling the deposition time.

[0088] (4) Growth of two-dimensional magnetic material iron-germanium-tellurium

[0089] The ultra-high vacuum chamber is equipped with evaporation source furnaces for iron (Fe), germanium (Ge), and tellurium (Te), employing thermal evaporation technology. Topological insulators (Bi) are grown on sapphire substrates. x Sb 1-x After depositing 2Te3, do not remove it. Confirm the vacuum level in the vacuum chamber, raise the temperature to the film growth temperature, and determine the evaporation rate of the three elements using a film thickness monitoring instrument (FDC). During the growth process, control the film thickness by precisely controlling the deposition time on the substrate. After growth, rapidly cool the substrate to room temperature and then remove it.

[0090] By growing a topological insulator thin film on a substrate using Bi2Te3, and then growing a two-dimensional magnetic material Fe3GeTe2 thin film on the topological insulator thin film, perpendicular magnetic anisotropy of the thin film can be achieved at room temperature.

[0091] By employing photolithography, dry etching, electron beam evaporation, and lift-off techniques to pattern thin films, micron-sized Hall rods can be fabricated.

[0092] Two-dimensional magnetic material Fe3GeTe2 exhibits strong perpendicular magnetic anisotropy. When coupled with a topological insulator, interface engineering effects can be used to maintain this perpendicular magnetic anisotropy at room temperature. Furthermore, a topological insulator is a special type of insulator; its internal structure is insulating, while charge can move on its surface. This is due to a band gap at the Fermi energy in the bulk insulator, resulting in bulk insulation. Therefore, when the topological insulator is thick enough, current cannot pass through it. The surface of a topological insulator exhibits a spin-momentum locking effect, a unique property that gives it a stronger spin-orbit coupling effect than commonly used heavy metals such as P, W, and Ta. Therefore, topological insulators can be used to achieve efficient magnetization reversal in two-dimensional magnetic materials.

[0093] Furthermore, molecular beam epitaxy can be used to fabricate this heterojunction over a large area. When the film thickness is reduced to the thickness of a single atomic layer, the device size can be reduced and the magnetic storage density can be increased.

[0094] Example 2

[0095] This embodiment provides a room-temperature all-van der Waals spin-orbit magnetic memory, the core structure of which is as follows: Figure 2 As shown.

[0096] The core structure of this room-temperature full van der Waals spin-orbit magnetic memory includes, from bottom to top, a van der Waals topology material layer, a first two-dimensional material layer, a barrier layer, and a second two-dimensional material layer. Furthermore, a bottom electrode is provided on the lower surface of the van der Waals topology material layer, and a top electrode is provided on the upper surface of the second two-dimensional material layer.

[0097] The van der Waals topology material is Bi2Te3, and its thickness is 8 nm.

[0098] The first two-dimensional magnetic material layer is made of Fe3GeTe2 and has a thickness of 3-5 nm.

[0099] The barrier layer is made of one of the following materials: h-BN, graphite, MoS2, WS2, or doped graphene, with a thickness of 1-7 nm.

[0100] The material of the second two-dimensional magnetic material layer is Fe. 5-x GeTe2, with a thickness of 1-8nm.

[0101] The room-temperature full van der Waals spin-orbit magnetic memory of this embodiment is prepared using molecular beam epitaxy combined with material characterization techniques. The growth sequence from bottom to top is as follows: van der Waals topological material layer, first two-dimensional magnetic material layer, barrier layer, and second two-dimensional magnetic material layer. Then, a bottom electrode is formed on the lower surface of the van der Waals topological material layer (the side surface where the first two-dimensional magnetic material is not grown), and a top electrode is formed on the upper surface of the second two-dimensional magnetic material layer (the side surface where it does not contact the barrier layer). Finally, photolithography, etching, and other processing are performed. The cross-sectional area of ​​this room-temperature full van der Waals spin-orbit magnetic memory is circular.

[0102] Example 3

[0103] This embodiment provides a room-temperature full van der Waals magnetoresistive device based on a topological insulator, which is also a room-temperature full van der Waals spin-orbit magnetoresistive memory. Its core structure is as follows: Figure 3 As shown.

[0104] The core structure of this room temperature full van der Waals magnetoresistive device based on topological insulator includes, from bottom to top, a van der Waals topological material layer, a first two-dimensional material layer, a topological insulator layer, and a second two-dimensional material layer. Furthermore, a bottom electrode is provided on the lower surface of the van der Waals topological material layer, and a top electrode is provided on the upper surface of the second two-dimensional material layer.

[0105] The van der Waals topology material is Bi2Te3, and its thickness is 8 nm.

[0106] The first two-dimensional magnetic material layer is made of Fe3GeTe2 and has a thickness of 3-5 nm.

[0107] The topological insulator layer is made of Bi2Te3 and has a thickness of 1-7 nm.

[0108] The second two-dimensional magnetic material layer is made of Fe3GeTe2 and has a thickness of 3-5 nm.

[0109] The room-temperature full van der Waals magnetoresistive device in this embodiment is prepared using molecular beam epitaxy combined with material characterization techniques and optimized growth conditions. The growth sequence from bottom to top is as follows: a van der Waals topological material layer, a first two-dimensional magnetic material layer, a topological insulator layer, and a second two-dimensional magnetic material layer. Then, a bottom electrode is formed on the lower surface of the van der Waals topological material layer (the side surface where the first two-dimensional magnetic material is not grown), and a top electrode is formed on the upper surface of the second two-dimensional magnetic material layer (the side surface where it is not in contact with the barrier layer). Finally, photolithography, etching, and other processing are performed. The cross-sectional area of ​​this room-temperature full van der Waals spin-orbit magnetoresistive memory is circular.

[0110] Example 4

[0111] This embodiment provides a device that uses a pair of room-temperature full van der Waals spin-orbit magnetic memories and employs word line pair differential voltages as inputs to implement an XOR operation, the structure of which is as follows: Figures 4a-4d As shown.

[0112] The device includes a pair of room-temperature full van der Waals spin-orbit moment magnetic memories for storing binary weights;

[0113] The top electrode of each room-temperature full van der Waals spin-orbit moment magnetic memory is connected to the corresponding word line, and the bottom electrode is connected to the bit line.

[0114] The room temperature full van der Waals spin-orbit moment magnetic storage device can be the room temperature full van der Waals spin-orbit moment magnetic storage device provided in Embodiment 2 or 3.

[0115] The device also includes a voltage comparator or sensing amplifier connected to a shared bit line.

[0116] The apparatus for implementing the XOR logic operation in this embodiment can store the binary weights of a binary neural network using a pair of room-temperature full van der Waals spin-orbit magnetic memories, and utilize the differential voltage on the word line pair as binary input to perform the XOR logic operation; wherein:

[0117] One of a pair of room-temperature full van der Waals spin-orbit moment magnetic memories is programmed to a high-resistivity state and the other is programmed to a low-resistivity state; wherein, for the relative positions of the room-temperature full van der Waals spin-orbit moment magnetic memories programmed to the high-resistivity and low-resistivity states, the weight stored in a unit synapse will correspond to a logic value of 1 or a logic value of 0, respectively.

[0118] When a binary input value is applied in differential voltage mode to a word line pair connected to a room-temperature full van der Waals spin-orbit moment magnetoresistive memory (MOM), the MOM pair acts as a voltage divider, with one word line pair being high and the other low. For the relative positions of the word lines at high and low levels, the binary input corresponds to logic 1 or logic 0, respectively.

[0119] By applying a differential voltage to a pair of word lines connected to a pair of room-temperature full van der Waals spin-orbit magnetic memories, a voltage divider is obtained on the shared bit line. Depending on the voltage divider value obtained from different inputs and weighted pairings, the bit line is at a high voltage level or a low voltage level. The bit line voltage is compared with a reference voltage value, and the result of an XOR logic operation is obtained through a voltage comparator or a sense amplifier.

[0120] In this embodiment, when the binary weight value W = 0, the corresponding memory cell R1 is in a high-resistance state (HRS) and the memory cell R2 is in a low-resistance state (LRS), such as Figure 4a As shown;

[0121] When the binary weight value W = 1, the corresponding memory cell R1 is in a low-resistance state (LRS) and the memory cell R1 is in a high-resistance state (HRS), such as Figure 4b As shown;

[0122] When the binary input value Input = 1, the corresponding word line WL is at a high level (Vdd) and the word line... When at a low level (GND), such as Figure 4c As shown;

[0123] When the binary input value Input = 0, the corresponding word line WL is at a low level (GND) and the word line... When at a high level (Vdd), such as Figure 4d As shown.

[0124] If the voltage on the shared bit line (BL) is high (e.g., greater than Vdd / 2), the output logic value Output = 1; if the voltage on BL is low (e.g., less than Vdd / 2), the output logic value Output = 0.

[0125] Example 5

[0126] This embodiment provides a device for implementing bit counting operations, the structure of which is as follows: Figure 5 As shown. The device includes multiple pairs of room-temperature full van der Waals spin-orbit moment magnetic memories connected to different word line pairs, and each pair of room-temperature full van der Waals spin-orbit moment magnetic memories is connected to one of the word line pairs, while both are connected to the same shared bit line;

[0127] Multiple pairs of room-temperature full van der Waals spin-orbit moment magnetoresistive memories are used for binary weighting; the top electrode of each room-temperature full van der Waals spin-orbit moment magnetoresistive memory is connected to the corresponding word line, and the bottom electrode is connected to the bit line;

[0128] The room temperature full van der Waals spin-orbit moment magnetic memory is the room temperature full van der Waals spin-orbit moment magnetic memory of Example 2 or 3.

[0129] The device for implementing bit counting operations also includes an analog-to-digital converter connected to a shared bit line.

[0130] The apparatus for implementing bit counting operations in this embodiment is a specific example of using n pairs of room-temperature full van der Waals spin-orbit moment magnetic memories and n pairs of word lines to implement bit counting operations. Based on different weights and the pairing of input values, bit counting operations can be performed... Figure 5 The circuit equivalent is as follows: In n pairs of room-temperature full van der Waals spin-orbit moment magnetic memories (MOMs), m pairs of low-resistivity MOMs are connected to the word lines at high levels (correspondingly, the high-resistivity MOMs of these m pairs are connected to the word lines at low levels), and the remaining nm pairs of low-resistivity MOMs are connected to the word lines at low levels (correspondingly, the high-resistivity MOMs of these nm pairs are connected to the word lines at high levels). These MOMs are all connected to the same bit line, i.e., the shared bit line BL. The voltage on the shared bit line BL is:

[0131]

[0132] Where R AP For a room-temperature all-van der Waals spin-orbit magnetic memory with high resistance in the high-resistivity state, R P This represents the low-resistivity state resistance of a room-temperature full van der Waals spin-orbit moment magnetic memory. From the above equation, we can see that V... BitcountIt is positively linearly correlated with m, and can be obtained from V using an analog-to-digital converter. Bitcount The value of m is obtained, which is the accumulated result of the n-bit XNOR operation.

[0133] Example 6

[0134] This embodiment provides a device for implementing matrix-vector multiplication operations in a binary neural network. The binary neural network includes an input layer and an output layer, and there are two hidden layers between the input and output layers, such as... Figure 6a and Figure 6b As shown, where, Figure 6b This is a schematic diagram of the structure of a certain layer of a binary neural network;

[0135] The input layer, hidden layer, and output layer each include a word line decoder and several analog-to-digital converters.

[0136] The length of the input vector of the input layer is the same as the number of word line pairs in the input layer of the binary neural network;

[0137] Each layer of the binary neural network has a cross-point array, which consists of several word line pairs, several shared bit lines, and several unit synapses. A unit synapse is located at the intersection of each word line pair and each shared bit line. The unit synapses store the weights corresponding to each intersection of the respective layer. Each unit synapse is composed of a pair of room-temperature full van der Waals spin-orbit moment magnetorem (MOMs). Each pair of MOMs is connected to one of the word line pairs and also to the shared bit line. The room-temperature full van der Waals MOM is the same as that in Embodiment 2 or 3. The top electrode of the room-temperature full van der Waals MOM is connected to the corresponding word line, and the bottom electrode is connected to the bit line.

[0138] The analog-to-digital converters in the upper layer are connected to the word line decoders in the lower layer;

[0139] The number of shared bit lines in each layer of a binary neural network is the same as the number of word line pairs in the next layer.

[0140] This embodiment demonstrates a specific example of a device for implementing matrix-vector multiplication using a room-temperature full van der Waals spin-orbit magnetic memory to construct a weight matrix and perform matrix-vector multiplication within that matrix. Figure 6aIn this structure, there are two hidden layers between the input and output layers. The length of the input vector is the same as the number of input nodes (i.e., the number of word pairs). Each weight corresponds to an arrow connecting the two layers. The weight matrix has the same number of rows as the length of the input vector and the same number of columns as the number of nodes required for the next layer's input. Each node in the output layer corresponds to one element of the matrix-vector multiplication result of the multiple weights and the corresponding input vector.

[0141] In a binary neural network, the weights and input are binarized into +1 and -1, respectively, which correspond to the logic values ​​1 and 0 in the hardware. The weight matrix is ​​stored in transpose form on a cross-point array and consists of multiple columns of weight vectors. The dot product of the input vector Input and the weight vector W can be obtained by the following formula:

[0142] Input·W=Bitcount(Input XNORW)

[0143] like Figure 6b As shown, in a cross-point array, each word line pair With bit line BL j The intersection point is where the storage weight W is located. i,j The unit synapse. Based on the received binary input, the wordline decoder selects the corresponding wordline pairs and applies a differential voltage to the selected wordline pairs. Each wordline pair The differential voltage on the line will be applied to all unit synapses connected to that word line pair (W). i,j On the n inputs (Input1, ..., Input...) n ) and n weights (W) connected to the same bit line (BL1) i,1 The result of the dot product operation (Output1) corresponds to different voltage levels on the bit line. The result can be read out using an analog-to-digital converter connected to the bit line (BL1), which corresponds to one element of the output vector. The output vector is formed by the dot product operation of the input vector and all column weight vectors, which is the matrix-vector multiplication result of the input vector and the weight matrix.

[0144] The output vector in one layer is input to the next layer and the above process of selecting the corresponding word line pairs, applying differential voltage, outputting the calculation result, and reading the calculation result is repeated. Finally, the output layer outputs the final calculation result.

[0145] In the training process of a binary neural network based on magnetic memory, the input data for training is first received, binarized, and converted into differential voltages. Then, the differential voltages are applied to the room-temperature full van der Waals spin-orbit moment magnetic memory array of the trained binary weights to obtain the matrix operation result of one layer. Then, the operation result of the previous layer is used as input to the weight array of the next layer, and the weighted operation result is passed layer by layer in this way. The final result is obtained at the output layer and compared with the correct result. If the output result of the neural network is inaccurate, the weights are readjusted and the training process is repeated until the accuracy of the calculation result meets the requirements.

[0146] After the weights are trained, inference can be performed using a binary neural network based on a room-temperature full van der Waals spin-orbit moment magnetic memory. During inference, the input data is first received, binarized, and converted into differential voltages. Then, the differential voltages are applied to the trained binary weight array to obtain the matrix operation result of one layer. Next, the result of the previous layer is used as input to the weight array of the next layer, and the weighted operation results are passed layer by layer in this manner, finally obtaining the final inference result at the output layer.

[0147] In this embodiment, the high level in the differential voltage can be tens of millivolts to tens of volts, and the low level can be ground potential. The number of weights and inputs in the crosspoint array can be much greater than... Figure 6b The number displayed.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A room-temperature all-van der Waals spin-orbit magnetic memory, wherein: This room-temperature all-van der Waals spin-orbit magnetic memory comprises, sequentially arranged, a bottom electrode layer, a van der Waals topological material layer, a first two-dimensional material layer, a barrier layer, a second two-dimensional material layer, and a top electrode. The van der Waals topological material layer and the first two-dimensional material layer form a heterojunction structure, with the first two-dimensional material layer grown on top of the van der Waals topological material layer. The van der Waals topological material layer is made of Bi₂Te₃ and has a thickness of 8 nm. The first two-dimensional material layer is made of Fe₃GeTe₂ and has a thickness of 3-5 nm. The barrier layer is made of one or more of h-BN, graphite, MoS₂, WS₂, and doped graphene, with a thickness of 1-7 nm. The second two-dimensional material layer is made of Fe₃GeTe₂. 5-x GeTe2, with a thickness of 1-8nm; Alternatively, the room-temperature all-van der Waals spin-orbit magnetic memory includes a bottom electrode layer, a van der Waals topological material layer, a first two-dimensional material layer, a topological insulator layer, a second two-dimensional material layer, and a top electrode arranged sequentially; wherein the van der Waals topological material layer and the first two-dimensional material layer form a heterojunction structure, and the first two-dimensional material layer is grown on the van der Waals topological material layer; the van der Waals topological material layer is made of Bi2Te3 and has a thickness of 8 nm; the first two-dimensional material layer is made of Fe3GeTe2 and has a thickness of 3-5 nm; the topological insulator layer is made of Bi2Te3 and has a thickness of 1-5 nm; and the second two-dimensional material layer is made of Fe3GeTe2 and has a thickness of 3-5 nm.

2. An apparatus for implementing an XOR logic operation, comprising a pair of room-temperature full van der Waals spin-orbit moment magnetic memories, a word line pair, and a shared bit line; the pair of room-temperature full van der Waals spin-orbit moment magnetic memories are used to store binary weights; Each room temperature full van der Waals spin-orbit moment magnetoresistive memory is connected to one of the word line pairs and simultaneously connected to a shared bit line. in, The room-temperature full van der Waals spin-orbit magnetic memory is the room-temperature full van der Waals spin-orbit magnetic memory as described in claim 1.

3. The apparatus for implementing the XOR logic operation according to claim 2, wherein, The device for implementing the XOR logic operation also includes a voltage comparator or a sensing amplifier connected to the shared bit line.

4. The apparatus for implementing the XOR logic operation according to claim 2, wherein, The top electrode of the room-temperature full van der Waals spin-orbit magnetic memory is connected to the corresponding word line, and the bottom electrode is connected to the bit line.

5. A method for implementing an XOR logic operation, comprising using the apparatus for implementing an XOR logic operation as described in any one of claims 2-4, storing binary weights using a pair of room-temperature full van der Waals spin-orbit magnetic memories, and using the differential voltage on the word line pair as the binary input value to implement the XOR logic operation; wherein: One of a pair of room-temperature full van der Waals spin-orbit moment magnetic memories is programmed to a high-resistivity state and the other is programmed to a low-resistivity state; wherein, for the relative positions of the room-temperature full van der Waals spin-orbit moment magnetic memories programmed to the high-resistivity and low-resistivity states, the weights stored in the room-temperature full van der Waals spin-orbit moment magnetic memories will correspond to logic values ​​1 or 0, respectively. The binary input value is applied in differential voltage mode to the word line pair connected to the room temperature full van der Waals spin-orbit moment magneto-receptor (MOR). The MOR acts as a voltage divider, with one word line pair at a high level and the other at a low level. For the relative positions of the word lines at high and low levels, the binary input value corresponds to logic 1 or logic 0, respectively. By applying a differential voltage to the word line pairs connected to the room temperature full van der Waals spin-orbit moment magnetic memory, a voltage divider is obtained on the shared bit line; depending on the voltage divider value obtained from different input values ​​and weighted pairings, the shared bit line is at a high voltage level or a low voltage level. The voltage of the shared bit line is compared with a reference voltage value to obtain the result of an XOR logic operation.

6. The method for implementing the XOR logic operation according to claim 5, wherein, The voltage divider value obtained based on the pairing of different input values ​​and weights, the shared bit line is at a high voltage level or a low voltage level, the voltage of the shared bit line is compared with the reference voltage value, and the result of the XOR logic operation is obtained by a voltage comparator or a sense amplifier.

7. An apparatus for performing bit counting operations, comprising multiple pairs of room-temperature full van der Waals spin-orbit moment magnetic memories connected to different word line pairs, wherein the room-temperature full van der Waals spin-orbit moment magnetic memories are connected to the same shared bit line. Multiple pairs of room-temperature full van der Waals spin-orbit moment magnetic memories are used to store binary weights; each pair of room-temperature full van der Waals spin-orbit moment magnetic memories is connected to one of the word line pairs and is also connected to a shared bit line. in, The room-temperature full van der Waals spin-orbit magnetic memory is the room-temperature full van der Waals spin-orbit magnetic memory as described in claim 1.

8. The apparatus for implementing bit counting operations according to claim 7, wherein, The apparatus for implementing bit counting operations also includes a voltage comparator, a sense amplifier, or an analog-to-digital converter connected to the shared bit line.

9. The apparatus for implementing bit counting operations according to claim 7, wherein, The top electrode of the room-temperature full van der Waals spin-orbit magnetic memory is connected to the corresponding word line, and the bottom electrode is connected to the bit line.

10. A method for implementing bit counting operations, which is implemented using the apparatus for implementing bit counting operations according to any one of claims 7-9, comprising: The device for implementing bit counting operations uses n pairs of room temperature full van der Waals spin-orbit magnetic memories and n pairs of word lines; Based on the pairing of different weights and input values, the circuit is equivalent to: in n pairs of room temperature full van der Waals spin-orbit moment magnetoresistors, m pairs of low-resistivity room temperature full van der Waals spin-orbit moment magnetoresistors are connected to the word line at a high level, and the remaining nm pairs of low-resistivity room temperature full van der Waals spin-orbit moment magnetoresistors are connected to the word line at a low level. These room temperature full van der Waals spin-orbit moment magnetoresistors are all connected to the same shared bit line. The voltage on the shared bit line is: in The high-resistivity state of the room-temperature all-van der Waals spin orbital moment magnetic memory. For the low-resistivity state resistance of a room-temperature all-van der Waals spin-orbit magnetic memory, V Bitcount For the voltage on the shared bit line; According to V Bitcount The value of m is obtained, which is the accumulated result of the n-bit XOR operation, i.e., the result of the bit counting operation.

11. The method for implementing bit counting operations according to claim 10, wherein, According to V Bitcount The value of m is obtained through a voltage comparator, a sensing amplifier, or an analog-to-digital converter.

12. An apparatus for implementing matrix-vector multiplication operations in a binary neural network, wherein, The binary neural network includes an input layer and an output layer, and there is at least one hidden layer between the input layer and the output layer; The input layer, hidden layer, and output layer each include a word line decoder, as well as several voltage comparators, sense amplifiers, or analog-to-digital converters. Each layer of the binary neural network has a cross-point array, which consists of several word line pairs, several shared bit lines, and several unit synapses. The intersection of each word line pair and each shared bit line is a unit synapse. The unit synapse is used to store the weights corresponding to each intersection of the corresponding layer. Each unit synapse is composed of a pair of room-temperature full van der Waals spin-orbit moment magnetorem (MOMs). Each MOM is connected to one of the word line pairs and also to the shared bit line. The MOM is the MOM described in claim 1. The top electrode of the MOM is connected to the corresponding word line, and the bottom electrode is connected to the bit line. The voltage comparator, sense amplifier, or analog-to-digital converter in the upper layer is connected to the word line decoder in the lower layer.

13. The apparatus for implementing matrix-vector multiplication in a binary neural network according to claim 12, wherein, The length of the input vector of the input layer is the same as the number of word pairs in the input layer of the binary neural network.

14. The apparatus for implementing matrix-vector multiplication in a binary neural network according to claim 12, wherein, The number of shared bit lines in each layer of a binary neural network is the same as the number of word line pairs in the next layer.

15. A method for implementing matrix-vector multiplication in a binary neural network, which is implemented using the apparatus for implementing matrix-vector multiplication in a binary neural network as described in any one of claims 12-14, comprising: In a binary neural network, the weights and inputs are binarized into +1 and -1, which correspond to the logic values ​​1 and 0 respectively in the hardware. The weight matrix is ​​stored in transpose on a cross-point array and consists of multiple columns of weight vectors; the dot product of the input vector Input and the weight vector W can be obtained by the following formula: Input W=Bitcount(Input XNOR W) Based on the binary input value received by the input layer, the word line decoder selects the corresponding word line pairs and applies a differential voltage to the selected word line pairs. The differential voltage on each word line pair is applied to all unit synapses connected to that word line pair; the output of the dot product of n input values ​​and n weights connected to the same shared bit line corresponds to different voltage levels on that shared bit line. The result is read out using a voltage comparator, sense amplifier, or analog-to-digital converter connected to that shared bit line. This result is one element of the output vector. The output vector is formed by the dot product of the input vector and all column weight vectors, which is the matrix-vector multiplication result of the input vector and the weight matrix. In a neural network, the output vector of one layer is input into the next layer and the process of selecting the corresponding word pairs, applying differential voltage, outputting the matrix-vector multiplication result, and reading out the result is repeated. Finally, the output layer outputs the final result.

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