Stage and display device comprising stage

Abstract

A stage and a display device including the stage are provided. The stage includes a node control unit, a node maintenance unit, and an output unit, the node control unit controlling a voltage of a first control node and a voltage of a second control node in correspondence with a first input signal supplied to a first input terminal, a second input signal supplied to a second input terminal, and a third input signal supplied to a third input terminal. The node control unit includes a first transistor, a second transistor, and a short prevention transistor connected between the first transistor and the second transistor and including a first electrode connected to a second electrode of the second transistor and a second electrode connected to a second electrode of the first transistor.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0079406, filed on June 29, 2020, which is incorporated by reference herein in its entirety for all purposes as if fully set forth herein. TECHNICAL FIELD

[0003] Exemplary embodiments of the present application relate generally to a stage and a display apparatus having the same, and more particularly, to a stage for supplying a light emission control signal to a pixel and a display apparatus having the same. BACKGROUND

[0004] A display apparatus displays an image using pixels arranged in a display unit. The pixels are connected to scan lines and data lines, and are driven by scan signals and data signals supplied from the scan lines and the data lines.

[0005] The pixels can also be connected to a light emission control line, and a light emission period of the pixels can be controlled using a light emission control signal supplied to the light emission control line. In this case, the display apparatus includes a light emission control driver for generating the light emission control signal.

[0006] The light emission control driver includes stages for respectively supplying the light emission control signal to the light emission control line. During a light emission period of the pixels positioned on each horizontal line, the stages output the light emission control signal of the second gate voltage to the light emission control line connected to the corresponding pixels, and in other periods, the stages output the light emission control signal of the first gate voltage to the light emission control line to block light emission.

[0007] The display apparatus can have a timing in which the power is turned on again after the apparatus is forcibly reset when the apparatus needs to be protected, such as in the case of an unexpected impact applied from the outside.

[0008] When the display apparatus is forcibly reset, the light emission control signal outputting the second gate voltage (gate-on voltage) can instantaneously change to a ground voltage. When the apparatus is powered on before a sufficient time elapses after the forced reset, the first gate voltage (gate-off voltage) is relatively slowly applied to the low buffer gate of the output unit in lower stages among the stages of the light emission control driver compared to higher stages. Thus, a short circuit can occur between the second gate voltage and the first gate voltage.

[0009] When a short circuit occurs between the first gate voltage and the second gate voltage, a short circuit can occur between the first pixel power (VDD) and a data voltage (Vdata), i.e., a data signal, in a pixel circuit. Thus, an initial abnormal light emission phenomenon (flickering phenomenon) such as screen flickering can occur.

[0010] The above information disclosed in this Background section is only for understanding of the background of the present inventive concept, and therefore it can contain information that does not constitute prior art. SUMMARY

[0011] An exemplary embodiment of the present application provides a stage that outputs a normal light emission control signal during a power-on process after a forced reset.

[0012] An exemplary embodiment of the present application further provides a display device that outputs a normal light emission control signal during a power-on process after a forced reset.

[0013] Additional features of the inventive concept will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the inventive concept.

[0014] An exemplary embodiment of the present application provides a stage including a node control unit, a node maintenance unit, and an output unit, the node control unit controlling a voltage of a first control node and a voltage of a second control node in correspondence with a first input signal supplied to a first input terminal, a second input signal supplied to a second input terminal, and a third input signal supplied to a third input terminal, the node maintenance unit maintaining the voltage of the first control node to be constant in correspondence with the voltage of the second control node, and the output unit supplying a first gate voltage supplied to a first power terminal or a second gate voltage supplied to a second power terminal to an output terminal in correspondence with the voltage of the first control node and the voltage of the second control node.

[0015] The node control unit includes a first transistor connected between the first input terminal and the second control node and including a first electrode connected to the first input terminal, a second transistor connected between the first power terminal and the third input terminal and including a first electrode connected to the first power terminal, and a short prevention transistor connected between the first transistor and the second transistor and including a first electrode connected to a second electrode of the second transistor and a second electrode connected to a second electrode of the first transistor.

[0016] A gate electrode of the short prevention transistor can be connected to the third input terminal, and the short prevention transistor can be turned on in correspondence with the third input signal.

[0017] A gate electrode of the first transistor can be connected to the second input terminal, and the first transistor can be turned on in correspondence with the second input signal.

[0018] The node control unit can include a third transistor including a first electrode connected with the second electrode of the second transistor, a second electrode connected to the third input terminal, and a gate electrode connected to the second control node, a fourth transistor including a first electrode connected with the gate electrode of the second transistor, a second electrode connected to the second input terminal, and a gate electrode connected with the second electrode of the first transistor, a fifth transistor including a first electrode connected with the first electrode of the fourth transistor, a second electrode connected to the second power terminal, and a gate electrode connected to the second input terminal, a first coupling transistor including a first electrode connected with the first electrode of the fifth transistor, including a second electrode, and including a gate electrode connected to the second power terminal, a first coupling capacitor including a first electrode connected with the second electrode of the first coupling transistor, and including a second electrode, a sixth transistor including a first electrode connected to the first control node, a second electrode connected with the second electrode of the first coupling capacitor, and a gate electrode connected to the third input terminal, and a seventh transistor including a first electrode connected with the second electrode of the first coupling capacitor, a second electrode connected to the third input terminal, and a gate electrode connected with the first electrode of the first coupling capacitor.

[0019] The node control unit can further include a second coupling capacitor including a first electrode connected to the second electrode of the second transistor, and a second electrode connected to the gate electrode of the third transistor, and a second coupling transistor connected between the second electrode of the first transistor and the second control node and turned on in correspondence with the second gate voltage.

[0020] The node maintenance unit can include an eighth transistor including a first electrode connected to the first power terminal, a second electrode connected to the first control node, and a gate electrode connected to the second electrode of the first transistor, and a first capacitor including a first electrode connected to the first power terminal, and a second electrode connected to the first control node.

[0021] The output unit can include a pull-up transistor including a first electrode connected to the first power terminal, a second electrode connected to the output terminal, and a gate electrode connected to the first control node, and a pull-down transistor including a first electrode connected to the output terminal, a second electrode connected to the second power terminal, and a gate electrode connected to the second control node.

[0022] The first gate voltage can be set as a gate-off voltage, and the second gate voltage can be set as a gate-on voltage.

[0023] The first input signal can be a start pulse or an output signal of a previous stage, and the second and third input signals can be first and second clock signals, respectively.

[0024] The first and second clock signals can alternately have a gate-on voltage portion, and the start pulse or the output signal of the previous stage can be supplied to overlap at least one gate-on voltage portion of the first clock signal.

[0025] Another exemplary embodiment of the present application provides a display apparatus including a pixel connected to a scan line, a data line, and a light emission control line, a scan driver supplying a scan signal to the scan line, a data driver supplying a data signal to the data line, and a light emission control driver including a plurality of stages to supply a light emission control signal to the light emission control line.

[0026] Each of the stages includes a node control unit, a node maintenance unit, and an output unit, the node control unit corresponding to a first input signal supplied to a first input terminal, a second input signal supplied to a second input terminal, and a third input signal supplied to a third input terminal, controlling a voltage of a first control node and a voltage of a second control node, and including a first transistor connected between the first input terminal and the second control node and including a first electrode connected to the first input terminal, a second transistor connected between a first power terminal and the third input terminal and including a first electrode connected to the first power terminal, and a short prevention transistor connected between the first transistor and the second transistor and including a first electrode connected to a second electrode of the second transistor and a second electrode connected to a second electrode of the first transistor, the node maintenance unit maintaining the voltage of the first control node constant corresponding to the voltage of the second control node, and the output unit supplying a first gate voltage supplied to the first power terminal or a second gate voltage supplied to a second power terminal to an output terminal corresponding to the voltage of the first control node and the voltage of the second control node.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the application as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the application and together with the description serve to explain the principles of the application.

[0029] Figure 1 A display apparatus according to an exemplary embodiment of the present application is illustrated.

[0030] Figure 2A and Figure 2B Pixels are shown according to an exemplary embodiment of the present invention.

[0031] Figure 3 An optical emission control driver according to an exemplary embodiment of the present invention is shown.

[0032] Figure 4 It shows Figure 3 An exemplary implementation of the level shown.

[0033] Figure 5 It is shown in Figure 4 Waveform diagram of an example of a signal measured in the first stage.

[0034] Figure 6A and Figure 6B This is a waveform diagram showing a sequence of display devices illustrating the effects of the thirteenth transistor of the present invention.

[0035] Figure 7 It is used to describe Figure 4 The signal flow diagram for the first stage of operation is shown below. Detailed Implementation

[0036] In the following description, numerous specific details are set forth for purposes of explanation to provide a thorough understanding of various exemplary embodiments of the invention. As used herein, “implementation” is a non-limiting example employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without specific details or in one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, the specific shapes, configurations, and characteristics of the exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0037] Unless otherwise specified, the exemplary embodiments shown are to be understood as exemplary features providing details of variations in how the inventive concept can be implemented in practice. Therefore, unless otherwise specified, features, components, modules, layers, films, panels, areas, and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged, and / or rearranged in other ways without departing from the inventive concept.

[0038] Crosshairs and / or shading are typically provided in the accompanying drawings to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, properties, performance, etc., of the elements. Additionally, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, similar reference numerals denote similar elements.

[0039] When a component (such as a layer) is referred to as being "on," "connected to," or "attached to" another component or layer, it may be directly on, directly connected to, or attached to the other component or layer, or there may be intermediate components or layers present. However, when a component or layer is referred to as being "directly" on, directly connected to, or directly attached to another component or layer, there are no intermediate components or layers present. Therefore, the term "connection" can refer to a physical, electrical, and / or fluid connection, with or without intermediate components. Furthermore, the D1-axis, D2-axis, and D3-axis are not limited to the three axes of a Cartesian coordinate system (such as the x-axis, y-axis, and z-axis) and can be interpreted in a broader sense. For example, the D1-axis, D2-axis, and D3-axis may be perpendicular to each other, or they may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the cluster of X, Y, and Z" can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] While the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0041] Spatial relative terms such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes and, therefore, to describe the relationship between one element and another as shown in the accompanying drawings. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features would subsequently be oriented “above” other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thereby the spatial relative descriptive terms used herein are interpreted accordingly.

[0042] The technical terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the,” as used herein, are intended to include the plural forms as well. Furthermore, the terms “comprises,” “comprising,” “includes,” and / or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and / or clusters thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or clusters thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and similar terms are used as approximations rather than terms of degree, and are thus utilized to account for inherent biases in measurements, calculations, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0043] Various exemplary embodiments are described herein with reference to cross-sectional and / or exploded views as schematic illustrations of idealized exemplary embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Consequently, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the shape of a particular shown area, but will include deviations in shape due to, for example, manufacturing processes. In this way, the areas shown in the figures may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and are therefore not intended to be limiting.

[0044] As is customary in the art, exemplary embodiments of functional blocks, units, and / or modules are shown and described in the accompanying drawings. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented via electronic (or optical) circuitry, such as logic circuits, discrete components, microprocessors, hardwired circuitry, memory elements, and wiring connectors, which may be formed using semiconductor-based or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may be optionally driven by firmware and / or software. It is also contemplated that each block, unit, and / or module may be implemented by dedicated hardware, or may be implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module of some exemplary embodiments may be physically separated into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the present invention, some exemplary embodiments of blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules.

[0045] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms (such as those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense.

[0046] Figure 1 A display device 1 according to an exemplary embodiment of the present invention is shown. Figure 1 A light-emitting display device including a light-emitting element is shown as an example of display device 1, but the display device 1 according to the concept of the present invention is not limited thereto.

[0047] Reference Figure 1 According to an exemplary embodiment of the present invention, the display device 1 may include a display unit 10, a scan driver 20 for driving the display unit 10, a light emission control driver 30, a data driver 40, and a timing controller 50.

[0048] The display unit 10 may include a plurality of scan lines S1 to Sn, a plurality of light emission control lines E1 to En, and a plurality of pixels PXL connected to a plurality of data lines D1 to Dm. In describing exemplary embodiments of the invention, "connection" may broadly mean electrical and / or physical connection. For example, the plurality of pixels PXL may be electrically connected to the plurality of scan lines S1 to Sn, the plurality of light emission control lines E1 to En, and the plurality of data lines D1 to Dm.

[0049] Multiple pixels PXL can receive scan signals, light emission control signals, and data signals from multiple scan lines S1 to Sn, multiple light emission control lines E1 to En, and multiple data lines D1 to Dm, respectively. In addition, pixels PXL can also receive driving power supplies, such as a first pixel power supply VDD and a second pixel power supply VSS.

[0050] When scanning signals are supplied from multiple scan lines S1 to Sn, pixel PXL can receive its respective data signals from multiple data lines D1 to Dm and emit light with a brightness corresponding to the data signals. Therefore, an image corresponding to the data signals of each frame can be displayed on display unit 10.

[0051] Each pixel PXL may include a light-emitting element and pixel circuitry for driving the light-emitting element. The pixel circuitry controls, in accordance with the data signal, the drive current flowing from the first pixel power supply VDD to the second pixel power supply VSS via the light-emitting element.

[0052] The scan driver 20 can receive a scan drive control signal SCS from the timing controller 50 and supply scan signals to multiple scan lines S1 to Sn in accordance with the scan drive control signal SCS. For example, the scan driver 20 can sequentially supply scan signals to multiple scan lines S1 to Sn. When scan signals are sequentially supplied to multiple scan lines S1 to Sn, pixels PXL are selected in units of horizontal lines corresponding to each scan signal.

[0053] A scan signal can be used to select pixels PXL on a horizontal line basis. For example, the scan signal may have a second gate voltage (e.g., logic low) that enables the transistors of each pixel PXL connected to multiple data lines D1 to Dm to conduct, and each horizontal time may be supplied to the pixel PXL arranged on the corresponding horizontal line.

[0054] The pixel PXL, which receives the scan signal, can be connected to multiple data lines D1 to Dm during the period when the scan signal is supplied, and thus receive each data signal. That is, a scan signal can be supplied to transmit data signals to the pixel PXL.

[0055] The optical emission control driver 30 can receive an optical emission drive control signal ECS from the timing controller 50, and supply optical emission control signals to multiple optical emission control lines E1 to En in accordance with the optical emission drive control signal ECS. For example, the optical emission control driver 30 can sequentially supply optical emission control signals to multiple optical emission control lines E1 to En.

[0056] The light emission control signal can be used to control the light emission period (e.g., light emission time point and / or light emission duration) of a pixel PXL on a horizontal line basis. For example, the light emission control signal may have a first gate voltage (gate turn-off voltage, e.g., logic high level), at which at least one transistor arranged in the current path of each of the plurality of pixels PXLs can be turned off. In this case, the pixel PXL receiving the light emission control signal can be set to a non-light emission state during the period when the light emission control signal is supplied, and can be set to a light emission state during other periods. At the same time, when a data signal corresponding to black grayscale is supplied to a specific pixel PXL, the pixel PXL can remain in a non-light emission state corresponding to the data signal even if no light emission control signal is supplied.

[0057] The data driver 40 receives a data drive control signal DCS and image data RGB from the timing controller 50, and supplies data signals to multiple data lines D1 to Dm corresponding to the data drive control signal DCS and the image data RGB. The data signals supplied to the multiple data lines D1 to Dm are then supplied to the pixel PXL selected by the scan signal. For this purpose, the data driver 40 can supply data signals to the multiple data lines D1 to Dm synchronously with each scan signal. For example, for each horizontal time interval, the data driver 40 can output the data signal corresponding to the pixel PXL of the corresponding horizontal line to the multiple data lines D1 to Dm synchronously with the scan signal.

[0058] The timing controller 50 receives various control signals (e.g., vertical synchronization signals) from an external source (e.g., a host processor). Figure 6A The system generates scan drive control signal SCS, optical emission drive control signal ECS, and data drive control signal DCS in accordance with the control signals. The scan drive control signal SCS, optical emission drive control signal ECS, and data drive control signal DCS can be supplied to scan driver 20, optical emission control driver 30, and data driver 40, respectively.

[0059] The scan drive control signal SCS may include a start pulse and a clock signal. The start pulse controls the output timing of the first scan signal (e.g., the scan signal supplied to the first scan line S1), and the clock signal is used to shift the start pulse.

[0060] The optical emission drive control signal ECS includes a start pulse and a clock signal. The start pulse controls the output timing of the first optical emission control signal (e.g., the optical emission control signal supplied to the first optical emission control line E1), and the clock signal is used to shift the start pulse.

[0061] The data-driven control signal (DCS) includes a source start pulse and a clock signal. The source start pulse controls the start time of data sampling, and the clock signal is used to control the sampling operation.

[0062] Additionally, the timing controller 50 receives input image data from an external source, rearranges the input image data, and generates RGB image data. The timing controller 50 can then supply the RGB image data to the data driver 40.

[0063] Figure 2A and Figure 2B Pixels according to an exemplary embodiment of the present invention are shown respectively. For example, Figure 2A and Figure 2B It shows that it can be arranged in Figure 1 Different implementations of pixel PXL on display unit 10. Pixel PXL or pixel PXL' can be arranged on the i-th (i is a natural number) horizontal line and the j-th (j is a natural number) vertical line of display unit 10, and can be connected to the i-th scan line Si, the i-th light emission control line Ei, and the j-th data line Dj. According to an exemplary embodiment, arranged on... Figure 1 The pixels PXL on the display unit 10 may have substantially the same structure. In the following text, "the i-th scan line Si", "the i-th light emission control line Ei" and "the j-th data line Dj" are referred to as "scan line Si", "light emission control line Ei" and "data line Dj", respectively.

[0064] Reference Figure 2A According to an exemplary embodiment of the present invention, a pixel PXL includes a light-emitting element LD and a pixel circuit PXC for driving the light-emitting element LD. According to an exemplary embodiment, the light-emitting element LD may be connected between the pixel circuit PXC and a second pixel power supply VSS, but the location of the light-emitting element LD is not limited thereto. For example, in another embodiment, the light-emitting element LD may be connected between a first pixel power supply VDD and the pixel circuit PXC.

[0065] The light-emitting element (LD) is connected in the forward direction between a first pixel power supply VDD and a second pixel power supply VSS. For example, the anode of the LD can be connected to the first pixel power supply VDD via a pixel circuit PXC, and the cathode of the LD can be connected to the second pixel power supply VSS. The first pixel power supply VDD and the second pixel power supply VSS can have a potential difference that allows the LD to emit light. For example, the first pixel power supply VDD can be a high-potential pixel power supply, and the second pixel power supply VSS can be a low-potential pixel power supply with a potential lower than or greater than the threshold voltage of the LD than the potential of the first pixel power supply VDD.

[0066] Light-emitting elements (LDs) can be configured using organic light-emitting diodes (OLEDs). Alternatively, LDs can be configured using micro-LEDs (LEDs) or inorganic LEDs (such as quantum dot LEDs). Furthermore, LDs can be configured using a combination of organic and inorganic materials. Figure 2A and Figure 2B In this embodiment, pixels PXL and PXL' each include a single light-emitting element LD. However, in another embodiment, pixels PXL and PXL' may each include multiple light-emitting elements LD, and the multiple light-emitting elements LD may be connected in series, in parallel, or in a combination of series and parallel. The pixel circuit PXC includes a first transistor T1 (driving transistor), a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0067] A first transistor T1 is connected between the first pixel power supply VDD and the light-emitting element LD. For example, the first electrode (e.g., the source electrode) of the first transistor T1 can be connected to the first pixel power supply VDD, and the second electrode (e.g., the drain electrode) of the first transistor T1 can be connected to the anode of the light-emitting element LD via a third transistor T3. Additionally, the gate electrode of the first transistor T1 is connected to the tenth node N10. Corresponding to the voltage of the tenth node N10, the first transistor T1 controls the drive current flowing from the first pixel power supply VDD to the second pixel power supply VSS via the third transistor T3 and the light-emitting element LD.

[0068] A second transistor T2 is connected between data line Dj and the tenth node N10. For example, the first electrode (e.g., the source electrode) of the second transistor T2 may be connected to data line Dj, and the second electrode (e.g., the drain electrode) of the second transistor T2 may be connected to the tenth node N10. Additionally, the gate electrode of the second transistor T2 is connected to scan line Si. The second transistor T2 is turned on when a scan signal (e.g., a logic low scan signal) is supplied to scan line Si to transmit the data signal from data line Dj to the tenth node N10.

[0069] A third transistor T3 is connected between the first transistor T1 and the light-emitting element LD. For example, the first electrode (e.g., the source electrode) of the third transistor T3 can be connected to the second electrode of the first transistor T1, and the second electrode (e.g., the drain electrode) of the third transistor T3 can be connected to the anode of the light-emitting element LD. Additionally, the gate electrode of the third transistor T3 is connected to the light emission control line Ei. The third transistor T3 is turned off when a light emission control signal (e.g., a logic high-level light emission control signal) is supplied to the light emission control line Ei, and turned on under other conditions (e.g., when the supply of the light emission control signal stops and the voltage of the light emission control line Ei remains at the second gate voltage).

[0070] When the third transistor T3 is turned off, the connection between the first transistor T1 and the light-emitting element LD is broken. Therefore, a current path is blocked inside pixel PXL, and thus pixel PXL does not emit light. When the third transistor T3 is turned on, the first transistor T1 and the light-emitting element LD are electrically connected to each other. Therefore, a current path through which the driving current can flow is formed in pixel PXL, and thus pixel PXL can emit light.

[0071] The storage capacitor Cst is connected between the first pixel power supply VDD and the tenth node N10. The storage capacitor Cst is charged to a voltage corresponding to the voltage of the tenth node N10.

[0072] Furthermore, the structure of pixel PXL can be modified in various ways according to the concept of this invention. For example, the structure of pixel circuit PXC can be as follows: Figure 2B The implementation shown is modified as described.

[0073] Reference Figure 2B Pixel PXL' includes a light-emitting element LD and a pixel circuit PXC' for driving the light-emitting element LD. Pixel circuit PXC' includes a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0074] The anode of the light-emitting element LD is connected to the first transistor T1 via the third transistor T3, and the cathode of the light-emitting element LD is connected to the second pixel power supply VSS. When a driving current is supplied from the first transistor T1, the light-emitting element LD generates light with a brightness corresponding to the amount of driving current.

[0075] The first electrode of the first transistor T1 is connected to the first pixel power supply VDD via the fourth transistor T4, and the second electrode of the first transistor T1 is connected to the anode of the light-emitting element LD via the third transistor T3. Additionally, the gate electrode of the first transistor T1 can be connected to the tenth node N10. Corresponding to the voltage of the tenth node N10, the first transistor T1 controls the drive current flowing from the first pixel power supply VDD to the second pixel power supply VSS via the light-emitting element LD.

[0076] The second transistor T2 is connected between the data line Dj and the first electrode of the first transistor T1. Furthermore, the gate electrode of the second transistor T2 is connected to the scan line Si. The second transistor T2 is turned on when a scan signal is supplied to the scan line Si to connect the data line Dj and the first electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal from the data line Dj can be transmitted to the first electrode of the first transistor T1. Simultaneously, during the period when the second transistor T2 is turned on by the scan signal, the first transistor T1 is turned on via the fifth transistor T5 in a diode-connected configuration. Therefore, the data signal from the data line Dj can be transmitted to the tenth node N10 via the second transistor T2, the first transistor T1, and the fifth transistor T5. Then, the storage capacitor Cst is charged with a voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0077] The third transistor T3 is connected between the first transistor T1 and the light-emitting element LD, and the gate electrode of the third transistor T3 is connected to the light emission control line Ei. The third transistor T3 is turned off when the light emission control signal is supplied to the light emission control line Ei, and turned on under other conditions.

[0078] The fourth transistor T4 is connected between the first pixel power supply VDD and the first transistor T1. Furthermore, the gate electrode of the fourth transistor T4 is connected to the light emission control line Ei. The fourth transistor T4 is turned off when the light emission control signal is supplied to the light emission control line Ei, and turned on under other conditions.

[0079] That is, the third transistor T3 and the fourth transistor T4 can be simultaneously turned on or off by a light emission control signal. When the third transistor T3 and the fourth transistor T4 are turned on, a current path for the driving current is formed in pixel PXL'. Conversely, when the third transistor T3 and the fourth transistor T4 are turned off, the current path is blocked, and therefore pixel PXL' does not emit light.

[0080] The fifth transistor T5 is connected between the first transistor T1 and the tenth node N10. Furthermore, the gate electrode of the fifth transistor T5 is connected to the scan line Si. The fifth transistor T5 conducts when a scan signal is supplied to the scan line Si, connecting the second electrode of the first transistor T1 and the tenth node N10. Therefore, when the fifth transistor T5 is on, the first transistor T1 is connected in the form of a diode.

[0081] The sixth transistor T6 is connected between the tenth node N10 and the initialization power supply Vint. Additionally, the gate electrode of the sixth transistor T6 is connected to the previous scan line, for example, the (i-1)th scan line Si-1. The sixth transistor T6 is turned on when the scan signal is supplied to the (i-1)th scan line Si-1 to initialize the voltage of the tenth node N10 to the voltage of the initialization power supply Vint.

[0082] In this embodiment, the (i-1)th scan line Si-1 is used as an initialization control line for initializing the gate electrode (i.e., the tenth node N10) of the first transistor T1, but the concept of the invention is not limited thereto. For example, in another embodiment, another control line including the (i-2)th scan line can be used as an initialization control line for initializing the gate electrode of the first transistor T1.

[0083] The voltage of the initial power supply Vint can be set lower than the voltage of the data signal. That is, the voltage of the initial power supply Vint can be set equal to or less than the minimum voltage of the data signal. Therefore, before sending the data signal of the current frame to each pixel PXL', when the voltage of the tenth node N10, charged by the data signal of the previous frame, is initialized to be equal to or less than the minimum voltage of the data signal, the first transistor T1 is connected in the forward direction as a diode, independent of the data signal of the previous frame, when the scan signal is supplied to the scan line Si. Therefore, the data signal of the current frame can be stably transmitted to the tenth node N10.

[0084] The seventh transistor T7 is connected between the initialization power supply Vint and the anode of the light-emitting element LD. Furthermore, the gate electrode of the seventh transistor T7 is connected to the (i+1)th scan line Si+1. The seventh transistor T7 is turned on when the scan signal is supplied to the (i+1)th scan line Si+1 to initialize the anode voltage of the light-emitting element LD to the voltage of the initialization power supply Vint. Therefore, pixel PXL' can exhibit uniform brightness characteristics.

[0085] In this embodiment, the case where the anode initialization control line connected to the gate electrode of the seventh transistor T7 is the (i+1)th scan line Si+1 is described as an example, but the concept of the present invention is not limited thereto. For example, in another embodiment, the gate electrode of the seventh transistor T7 may be connected to the current scan line, i.e., scan line Si (or another control line). In this case, when the scan signal is supplied to the scan line Si, the anode voltage of the light-emitting element LD can be initialized to the voltage of the initialization power supply Vint.

[0086] The storage capacitor Cst is connected between the first pixel power supply VDD and the tenth node N10. The storage capacitor Cst is charged with a voltage corresponding to the data signal and a voltage corresponding to the threshold voltage of the first transistor T1.

[0087] Meanwhile, the structures of pixels PXL and PXL' are not limited to Figure 2A and Figure 2B The implementation shown is illustrated. For example, pixel circuits PXC and PXC' can have various structures currently known.

[0088] Figure 3 A light emission control driver 30 according to an exemplary embodiment of the present invention is shown. For convenience, in Figure 3 Only four stages ST are shown, for example, stage 1 to stage 4 ST4. According to an embodiment, the optical emission control driver 30 may include multiple stages ST, such as stage 1 to stage 4 ST4, that are independently connected to the input terminal of the start pulse SP (e.g., the first input terminal 101 of stage 1 ST1).

[0089] Reference Figure 3 According to an exemplary embodiment of the present invention, the optical emission control driver 30 may include multiple stages ST to supply multiple optical emission control signals to multiple optical emission control lines E, respectively. Each stage ST may be connected to any one of the first optical emission control lines E1 to the fourth optical emission control line E4, and may be driven corresponding to at least one clock signal CLK (e.g., a first clock signal CLK1 and a second clock signal CLK2). For example, the first stages ST1 to the fourth stages ST4 may be connected to the first optical emission control lines E1 to the fourth optical emission control lines E4, respectively, and may use the first clock signal CLK1 and the second clock signal CLK2 to generate their respective optical emission control signals. The first stages ST1 to the fourth stages ST4 may sequentially output the optical emission control signals to the first optical emission control lines E1 to the fourth optical emission control lines E4. According to the exemplary embodiment, the multiple stages ST may have substantially the same circuit structure.

[0090] Each of the multiple ST stages may include a first input terminal 101, a second input terminal 102, a third input terminal 103, and an output terminal 104.

[0091] The first input terminal 101 can receive a first input signal. According to an exemplary embodiment, the first input signal may be a start pulse SP or the output signal of the previous stage (i.e., the optical emission control signal of the previous stage). For example, the first stage (hereinafter referred to as "first stage ST1") can receive the start pulse SP through the first input terminal 101, and the remaining stages ST can receive the output signal of the previous stage through their respective first input terminals 101.

[0092] The second input terminal 102 and the third input terminal 103 can receive the second input signal and the third input signal, respectively. According to an exemplary embodiment, the second input signal and the third input signal of the k-th (k is an odd or even number) stage STk can be the first clock signal CLK1 and the second clock signal CLK2, respectively. Furthermore, the second input signal and the third input signal of the (k+1)-th stage STk+1 can be the second clock signal CLK2 and the first clock signal CLK1, respectively. For example, the k-th stage STk can receive the first clock signal CLK1 and the second clock signal CLK2 through the second input terminal 102 and the third input terminal 103, respectively, and the (k+1)-th stage STk+1 can receive the second clock signal CLK2 and the first clock signal CLK1 through the second input terminal 102 and the third input terminal 103, respectively.

[0093] The first clock signal CLK1 and the second clock signal CLK2 may alternately have a second gate voltage. For example, the first clock signal CLK1 and the second clock signal CLK2 may be signals with the same period and phases that do not overlap. For example, the second clock signal CLK2 may be a clock signal in the form of the first clock signal CLK1 shifted by half a period.

[0094] Additionally, stage ST can be operated by receiving a first gate voltage VGH and a second gate voltage VGL. The first gate voltage VGH can be set to a gate turn-off voltage, for example, a logic high level, and the second gate voltage VGL can be set to a gate turn-on voltage, for example, a logic low level (when the pixel is formed by a P-type transistor). In this case, the first gate voltage VGH transmitted to output terminal 104 can be used as a light emission control signal to prevent light emission from pixel PXL.

[0095] Figure 4 It shows Figure 3 The implementation of the stage ST shown is illustrated. According to the implementation, multiple stage STs configuring the optical emission control driver 30 can have substantially the same circuit structure. Therefore, in Figure 4 In the text, only the first level ST1 and the second level ST2 are shown, representing multiple levels of ST.

[0096] Reference Figure 3 and Figure 4 The ST level may include a node control unit SST1, an output unit SST2 (or a buffer unit), and a node maintenance unit SST3.

[0097] The stage ST can generate an optical emission control signal using the first input signal to the third input signal supplied through the first input terminal 101 to the third input terminal 103, and supply the generated optical emission control signal to the output terminal 104. For example, the stage ST can output the optical emission control signal using the start pulse SP or the output signal of the previous stage supplied through the first input terminal 101 to the third input terminal 103, as well as the first clock signal CLK1 and the second clock signal CLK2.

[0098] Furthermore, stage ST can receive a first gate voltage VGH and a second gate voltage VGL through a first power supply terminal 105 and a second power supply terminal 106, respectively. Stage ST can use the voltages of the first gate voltage VGH and the second gate voltage VGL supplied to the first power supply terminal 105 and the second power supply terminal 106, respectively, to control the voltage of the output terminal 104. For convenience, the circuit structure of each stage ST is described below based on the first stage ST1.

[0099] First, the output unit SST2 can be connected to the first power supply terminal 105 and the second power supply terminal 106, and the output unit SST2 can output the first gate voltage VGH to the output terminal 104 as a light emission control signal based on the voltage of the second control node Q and the voltage of the first control node QB.

[0100] The output unit SST2 may include a ninth transistor M9 (or a pull-up transistor) and a tenth transistor M10 (or a pull-down transistor).

[0101] The ninth transistor M9 may include a first electrode connected to the first power supply terminal 105, a second electrode connected to the output terminal 104, and a gate electrode connected to the first control node QB.

[0102] The tenth transistor M10 may include a first electrode connected to the output terminal 104, a second electrode connected to the second power supply terminal 106, and a gate electrode connected to the second control node Q.

[0103] The node control unit SST1 can be connected to the first input terminal 101, the second input terminal 102, the third input terminal 103, the first power supply terminal 105, and the second power supply terminal 106. The node control unit SST1 can use the start pulse SP (or the optical emission control signal from the previous stage) provided through the first input terminal 101 to control the voltage of the first control node QB and the voltage of the second control node Q.

[0104] The node control unit SST1 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13, a second capacitor C2 (or a first coupling capacitor) and a third capacitor C3 (or a second coupling capacitor).

[0105] The first transistor M1 may include a first electrode connected to the first input terminal 101, a second electrode connected to the first electrode of the twelfth transistor M12, and a gate electrode connected to the second input terminal 102.

[0106] The second transistor M2 may include a first electrode connected to the first power supply terminal 105, a second electrode connected to the first electrode of the third transistor M3, and a gate electrode connected to the first electrode of the eleventh transistor M11.

[0107] The third transistor M3 may include a first electrode connected to the second electrode of the second transistor M2, a second electrode connected to the third input terminal 103, and a gate electrode connected to the second control node Q.

[0108] A third capacitor C3 may be formed between the second electrode of the second transistor M2 and the second control node Q, and may include a first electrode connected to the second electrode of the second transistor M2 and a second electrode connected to the second control node Q. According to an embodiment, the second electrode of the third capacitor C3 may be connected to the gate electrode of the third transistor M3.

[0109] The fourth transistor M4 may include a first electrode connected to the gate electrode of the second transistor M2, a second electrode connected to the second input terminal 102, and a gate electrode connected to the second electrode of the first transistor M1. The fourth transistor M4 may be configured by connecting transistors M41 and M42 in series.

[0110] The fifth transistor M5 may include a first electrode connected to the gate electrode of the second transistor M2, a second electrode connected to the second power supply terminal 106, and a gate electrode connected to the second input terminal 102.

[0111] The sixth transistor M6 may include a first electrode connected to the first control node QB, a second electrode connected to the first electrode of the seventh transistor M7, and a gate electrode connected to the third input terminal 103.

[0112] The seventh transistor M7 may include a first electrode connected to the second electrode of the sixth transistor M6, a second electrode connected to the third input terminal 103, and a gate electrode connected to the second electrode of the eleventh transistor M11.

[0113] The second capacitor C2 (or the first coupling capacitor) may be formed between the second electrode of the eleventh transistor M11 and the second electrode of the sixth transistor M6, and may include a first electrode connected to the second electrode of the eleventh transistor M11 and a second electrode connected to the second electrode of the sixth transistor M6.

[0114] The eleventh transistor M11 (or the first coupled transistor) may include a first electrode connected to the gate electrode of the second transistor M2, a second electrode connected to the first electrode of the second capacitor C2, and a gate electrode connected to the second power supply terminal 106.

[0115] The twelfth transistor M12 (or the second coupled transistor) may include a first electrode connected to the second electrode of the first transistor M1, a second electrode connected to the second control node Q, and a gate electrode connected to the second power supply terminal 106.

[0116] The thirteenth transistor M13 (or short-circuit protection transistor) may include a first electrode connected to the second electrode of the second transistor M2, a second electrode connected to the second electrode of the first transistor M1, and a gate electrode connected to the third input terminal 103. When the display device 1 is powered on after being forcibly reset, a logic low-level second clock signal CLK2 can be applied to the third input terminal 103, and therefore, the thirteenth transistor M13 can be turned on in response to the logic low-level second clock signal CLK2. Therefore, the voltage at the second electrode of the first transistor M1 (i.e., the second control node Q) can immediately have a first gate voltage VGH, and therefore, the turn-off operation of the tenth transistor M10 can be performed quickly.

[0117] The node maintenance unit SST3 can maintain the voltage of the first control node QB at a constant level in response to the voltage of the second control node Q. The node maintenance unit SST3 may include a first capacitor C1 and an eighth transistor M8.

[0118] A first capacitor C1 is formed between a first power supply terminal 105 and a first control node QB, and may include a first electrode connected to the first power supply terminal 105 and a second electrode connected to the first control node QB.

[0119] The eighth transistor M8 may include a first electrode connected to the first power supply terminal 105, a second electrode connected to the first control node QB, and a gate electrode connected to the second electrode of the first transistor M1. The eighth transistor M8 may maintain the voltage of the first control node QB at a constant level in response to the voltage at the second electrode of the first transistor M1 (i.e., the voltage of the second control node Q). For example, when the voltage of the second control node Q is at a logic low level, the eighth transistor M8 may use a first gate voltage VGH to maintain the voltage of the first control node QB at a logic high level.

[0120] Each of the first transistor M1 to the thirteenth transistor M13 can be a P-type transistor. Figure 4 In this embodiment, the first transistor M1 to the third transistor M3 and the fifth transistor M5 to the thirteenth transistor M13 are single-gate transistors, and the fourth transistor M4 is a dual-gate transistor (i.e., a dual-gate transistor configured by two transistors connected in series and having gate electrodes connected to each other), but the concept of the invention is not limited thereto. For example, to improve reliability, at least one of the first transistor M1 to the third transistor M3 and the fifth transistor M5 to the thirteenth transistor M13 may be additionally implemented as a dual-gate transistor.

[0121] The first input signals to the first input terminals 101 to the third input terminals 103 of the second stage ST2 are different from those of the first stage ST1, and the circuit structure and operation of the second stage ST2 can be substantially the same as those of the first stage ST1. For example, the second stage ST2 can receive the output signal of the first stage ST1 (the first optical emission control signal supplied to the first optical emission control line E1), the second clock signal CLK2, and the first clock signal CLK1 through the first input terminals 101 to the third input terminals 103, and use the output signal of the first stage ST1, the second clock signal CLK2, and the first clock signal CLK1 to generate the optical emission control signal. The optical emission control signal generated by the second stage ST2 is supplied to the second optical emission control line E2.

[0122] The ST stage can sequentially output optical emission control signals to each optical emission control line E using the method described above. The circuit structure and operation of each of the second ST stage (ST2) and subsequent ST stages are essentially the same as those of the first ST stage (ST1). Therefore, a detailed description thereof is omitted.

[0123] To describe the operations of the first-level ST1 and the second-level ST2, please refer to... Figure 4 .

[0124] Figure 5 It is shown in Figure 4 The waveform diagram shows an example of the signal measured in the first stage ST1. Since the operations of the first stage ST1 and the second stage ST2 are essentially the same or similar to each other, the operation of the first stage ST1 is described by covering the first stage ST1 and the second stage ST2.

[0125] Reference Figure 4 and Figure 5The first clock signal CLK1 applied to the second input terminal 102 can have a logic low level and a logic high level during two horizontal time periods of 2H. Here, the logic low level can be the same as the voltage level of the second gate voltage VGL that turns on the P-type transistor. The logic high level can be the same as the level of the first gate voltage VGH that turns off the P-type transistor.

[0126] The second clock signal CLK2 applied to the third input terminal 103 may have a waveform in which the first clock signal CLK1 is delayed by half a cycle (i.e., a horizontal time 1H).

[0127] At the first time point t1, the input voltage V_IN at the first input terminal 101 (e.g., the start pulse SP) can change from a logic low level to a logic high level. For example, the input voltage V_IN can remain at a logic high level for four horizontal times 4H.

[0128] At the first time point t1, the second node voltage V_Q at the second control node Q can have a logic low level, the first node voltage V_QB at the first control node QB can have a logic high level, and the output voltage V_OUT (i.e., the optical emission control signal) at the output terminal 104 can have a logic low level.

[0129] At the second time point t2, the first clock signal CLK1 can be changed from logic high level to logic low level.

[0130] The first transistor M1 can be turned on in response to a first clock signal CLK1 with a logic low level, and a logic high level input voltage V_IN can be applied to the first electrode of the twelfth transistor M12. Because the twelfth transistor M12 is turned on by the second gate voltage VGL, the logic high level input voltage V_IN can be applied to the second control node Q through the twelfth transistor M12. That is, the second node voltage V_Q can be changed to have a logic high level.

[0131] Additionally, the fifth transistor M5 can be turned on in response to a first clock signal CLK1 at a logic low level, and a second gate voltage VGL can be applied to the first electrode of the eleventh transistor M11. Because the eleventh transistor M11 is turned on by the second gate voltage VGL, the second gate voltage VGL can be applied to the first electrode of the second capacitor C2. The seventh transistor M7 can be turned on in response to the second gate voltage VGL (i.e., the second gate voltage VGL applied to the first electrode of the second capacitor C2), and a second clock signal CLK2 at a logic high level can be applied to the second electrode of the second capacitor C2. Therefore, the voltage corresponding to the difference between the logic high level and the logic low level can charge the second capacitor C2.

[0132] The second transistor M2 can be turned on in response to the second gate voltage VGL, and the first gate voltage VGH can be applied to the first electrode of the third capacitor C3. Because the second electrode of the third capacitor C3 is connected to the second control node Q, and the second node voltage V_Q has a logic high level, the third capacitor C3 can be discharged.

[0133] At the third time point t3, the second clock signal CLK2 can change from logic high level to logic low level.

[0134] In this configuration, the sixth transistor M6 can be turned on in response to a logic-low second clock signal CLK2, and the logic-low second clock signal CLK2 can be applied to the first control node QB through the seventh transistor M7, which is turned on by the second capacitor C2, and the turned-on sixth transistor M6. That is, the first node voltage V_QB can be changed to have a logic-low level.

[0135] The ninth transistor M9 can be turned on in response to a first node voltage V_QB with a logic low level, and a first gate voltage VGH can be applied to the output terminal 104 through the first power supply terminal 105 and the ninth transistor M9. That is, the output voltage V_OUT can be changed to have a logic high level.

[0136] Simultaneously, the thirteenth transistor M13 can be turned on in response to the second clock signal CLK2 at a logic low level, and the first gate voltage VGH, which is applied to the second electrode of the third capacitor C3 through the turned-on thirteenth transistor M13 and the twelfth transistor M12 turned on by the second gate voltage VGL, can be applied to the second control node Q.

[0137] like Figure 4 As shown, when the ninth transistor M9 is turned on, the first gate voltage VGH, which serves as the output voltage V_OUT (i.e., the light emission control signal) of the first stage ST1, is supplied to the output terminal 104. The first gate voltage VGH supplied to the output terminal 104 can be supplied to the first light emission control line E1 as a light emission control signal.

[0138] Subsequently, even if the first control node QB is in a floating state due to the changes in the first clock signal CLK1 and the second clock signal CLK2, the first node voltage V_QB can be kept at a logic low level through the first capacitor C1, and the output voltage V_OUT can be kept at a logic high level.

[0139] At the fourth time point t4, the input voltage V_IN can change from logic high level to logic low level.

[0140] At the fifth time point t5, the first clock signal CLK1 can change from logic high level to logic low level.

[0141] In this configuration, the first transistor M1 can be turned on in response to a first clock signal CLK1 at a logic low level, and a logic low input voltage V_IN can be applied to the first electrode of the twelfth transistor M12. Because the twelfth transistor M12 is turned on by a second gate voltage VGL, the logic low input voltage V_IN can be applied to the second control node Q through the twelfth transistor M12.

[0142] The tenth transistor M10 can be turned on in response to a logic low level second node voltage V_Q, and a second gate voltage VGL can be applied to the output terminal 104.

[0143] Simultaneously, the fourth transistor M4 can be turned on by an input voltage V_IN that is logic low provided by the first transistor M1. In addition, the fifth transistor M5 can be turned on in response to a first clock signal CLK1 that is logic low, and a second gate voltage VGL (and the first clock signal CLK1) can be applied to the gate electrode of the second transistor M2.

[0144] The second transistor M2 can be turned on in response to the second gate voltage VGL, and the first gate voltage VGH can be applied to the first electrode of the third capacitor C3. Because the second electrode of the third capacitor C3 is connected to the second control node Q, the logic low level second node voltage V_Q can be applied to the second electrode of the third capacitor C3.

[0145] Simultaneously, the eighth transistor M8 can be turned on by a logic low input voltage V_IN, and the first gate voltage VGH can be applied to the first control node QB. That is, the first node voltage V_QB can be changed to have a logic high level.

[0146] At the sixth time point t6, the second clock signal CLK2 can change from logic high level to logic low level.

[0147] Because the third transistor M3 is turned on by the second node voltage V_Q, the second clock signal CLK2, which is at a logic low level, can be applied to the first electrode of the third capacitor C3. The second node voltage V_Q can be boosted by the third capacitor C3, and the second node voltage V_Q can be changed to have a second logic low level. Furthermore, the output voltage V_OUT can have a logic low level corresponding to the second node voltage V_Q, which is at a second logic low level. Here, the second logic low level can have a voltage level lower than a logic low level, for example, lower than the second gate voltage VGL (i.e., 2VGL).

[0148] Figure 6A and Figure 6BThis is a waveform diagram showing a schematic display of the sequence of display devices used to describe the effect of the thirteenth transistor M13 of this disclosure. Figure 7 It is used to describe Figure 4 The signal flow diagram for the operation of the first stage ST1 is shown below. At this time, Figure 6A The waveform diagram assumes Figure 4 The first stage ST1 shown does not include the thirteenth transistor M13, and Figure 6B The waveform diagram assumes Figure 4 The first stage ST1 shown includes the thirteenth transistor M13.

[0149] refer to Figure 1 , Figure 4 and Figure 6A To protect the various drivers, the display device 1 in an abnormal state (such as being subjected to an external impact) can be forcibly reset. In this case, an initial abnormal light emission phenomenon (flickering phenomenon) may occur, in which a logic high-level input voltage V_IN is slowly applied to the second control node Q and the screen of the display device 1 flickers.

[0150] Specifically, when the display device 1 is forcibly reset, the light emission control driver 30 can immediately change most of the light emission control signal, which is output at a logic low level, to the ground level (GND).

[0151] When the display device 1 is forcibly reset and then powered on, a logic high-level start pulse SP and a logic low-level first clock signal CLK1 and second clock signal CLK2 can be applied to the light emission control driver 30. After a certain period of time, such as Figure 5 As shown, a start pulse SP that remains at a logic high level for each frame during the four horizontal times 4H, and a first clock signal CLK1 and a second clock signal CLK2 that have logic low and logic high levels during the two horizontal times 2H can be applied to the optical emission control driver 30 (i.e., EM on).

[0152] In this scenario, during the application of a logic-high start pulse SP and logic-low first clock signals CLK1 and CLK2 to the optical emission control driver 30, the black grayscale source (Source) can be applied to the data driver 40 (i.e., source enabled). Furthermore, a start pulse FLM for generating the scan signal, along with third clock signals CLK3 and fourth clock signals CLK4, can be applied to begin image display within a time period (i.e., scan enabled), during which a logic-high start pulse SP for each frame during four horizontal times 4H, and first clock signals CLK1 and CLK2 during two horizontal times 2H, are applied to the optical emission control driver 30. (In Figure 6A and Figure 6B Although the third clock signal CLK3 and the fourth clock signal CLK4 are indicated as being supplied, corresponding to the structure of the scan driver 20, three or more clock signals may be supplied.

[0153] When the display device 1 is forcibly reset and then powered on, since the logic high-level start pulse SP and the logic low-level first clock signal CLK1 and second clock signal CLK2 are applied to the light emission control driver 30 for a certain period of time, ideally, a light emission control signal with a first gate voltage VGH (i.e., logic high level) needs to be output.

[0154] However, in the first stage ST1 to the fourth stage ST4 of the optical emission control driver 30 (see...) Figure 3 In a lower level (e.g., ST4), compared to a higher level (e.g., ST1), the first gate voltage VGH can be applied relatively slowly to the low-buffered gate (second control node Q) of the output terminal 104. In this case, a short circuit can occur between the second gate voltage VGL and the first gate voltage VGH because the tenth transistor M10, which is turned off corresponding to the first gate voltage VGH, is not completely turned off.

[0155] Therefore, the light emission control signal is applied because the voltage level drops. Figure 2A The third transistor T3 of the pixel circuit PXC or Figure 2B The third transistor T3 and the fourth transistor T4 of the pixel circuit PXC' are therefore not completely turned off. Figure 2A The third transistor T3 or Figure 2B The fourth transistor T4 can be short-circuited between the first pixel power supply VDD and the data voltage Vdata, thus causing initial abnormal light emission (flickering). Figure 6AIn the diagram, the quadrilateral frame indicated by the dashed line indicates that the first pixel power supply VDD is leaking, and therefore a short circuit occurs between the first pixel power supply VDD and the data voltage Vdata.

[0156] Reference Figure 6B and Figure 7 According to the embodiments of this disclosure, the first stage ST1 may additionally include a path for applying the first gate voltage VGH via a thirteenth transistor M13 disposed between the second electrode of the second transistor M2 and the second electrode of the first transistor M1. Therefore, the tenth transistor M10, which is turned off corresponding to the first gate voltage VGH, can be completely turned off. That is, because the second gate voltage VGL is not applied to the output terminal 104, no short circuit is generated between the first gate voltage VGH and the second gate voltage VGL, and a logic high-level light emission control signal can be output.

[0157] Therefore, because the voltage level did not drop, the light emission control signal was applied to Figure 2A The third transistor T3 of the pixel circuit PXC or Figure 2B The third transistor T3 and the fourth transistor T4 of the pixel circuit PXC', therefore Figure 2A The third transistor T3 or Figure 2B The fourth transistor T4 can be completely turned off. Because no short circuit is generated between the first pixel power supply VDD and the data voltage Vdata, initial abnormal light emission (flickering) will not occur. Figure 6B The leakage of the first pixel power supply VDD, indicated by the dashed line in the quadrilateral frame, is prevented.

[0158] By adding a transistor that provides a first gate voltage (gate turn-off voltage) to the low-buffered gate of the output unit, the stage output according to the concept of the present invention outputs a normal light emission control signal, thereby preventing the initial abnormal light emission phenomenon.

[0159] By adding a transistor that provides a first gate voltage (gate turn-off voltage) to the low-buffered gate of the output unit, the display device according to the present invention outputs a normal light emission control signal, thereby preventing the initial abnormal light emission phenomenon.

[0160] Although the concept of the invention has been described with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes may be made to the concept of the invention without departing from the spirit and scope of the concept of the invention as disclosed in the appended claims.

Claims

1. A stage for providing optical emission control signals, comprising: A node control unit controls the voltage of a first control node and the voltage of a second control node based on a first input signal supplied to a first input terminal, a second input signal supplied to a second input terminal, and a third input signal supplied to a third input terminal. A node maintenance unit, wherein the node maintenance unit maintains the voltage of the first control node at a constant value based on the voltage of the second control node; as well as An output unit, which supplies either a first gate voltage supplied to a first power supply terminal or a second gate voltage supplied to a second power supply terminal to an output terminal based on the voltage of the first control node and the voltage of the second control node. The node control unit includes: A first transistor, the first transistor being connected between the first input terminal and the second control node and including a first electrode connected to the first input terminal; A second transistor is connected between the first power terminal and the third input terminal and includes a first electrode connected to the first power terminal; A short-circuit prevention transistor, the short-circuit prevention transistor being connected between a first transistor and a second transistor and including a first electrode connected to a second electrode of the second transistor and a second electrode connected to a second electrode of the first transistor; A third transistor, the third transistor comprising a first electrode connected to the second electrode of the second transistor, a second electrode connected to the third input terminal, and a gate electrode connected to the second control node; and The second coupling capacitor includes a first electrode connected to the second electrode of the second transistor and a second electrode connected to the gate electrode of the third transistor. The stage is configured such that, during the power-on process after a forced reset, when the first input signal with a gate turn-off voltage and the second and third input signals with gate turn-on voltages are applied to the stage, a path is provided through the second transistor and the short-circuit prevention transistor to apply the first gate voltage applied to the first power supply terminal to the second control node, so as to prevent a short circuit between the first gate voltage and the second gate voltage.

2. The stage according to claim 1, wherein, The gate electrode of the short-circuit prevention transistor is connected to the third input terminal, and the short-circuit prevention transistor is turned on according to the third input signal.

3. The stage according to claim 1, wherein, The gate electrode of the first transistor is connected to the second input terminal, and the first transistor is turned on according to the second input signal.

4. The stage according to claim 3, wherein, The node control unit includes: A fourth transistor, the fourth transistor comprising a first electrode connected to the gate electrode of the second transistor, a second electrode connected to the second input terminal, and a gate electrode connected to the second electrode of the first transistor; The fifth transistor includes a first electrode connected to the first electrode of the fourth transistor, a second electrode connected to the second power supply terminal, and a gate electrode connected to the second input terminal; A first coupling transistor, the first coupling transistor including a first electrode connected to the first electrode of the fifth transistor, including a second electrode, and including a gate electrode connected to the second power supply terminal; A first coupling capacitor, the first coupling capacitor including a first electrode connected to the second electrode of the first coupling transistor, and including a second electrode; A sixth transistor, the sixth transistor comprising a first electrode connected to the first control node, a second electrode connected to the second electrode of the first coupling capacitor, and a gate electrode connected to the third input terminal; and A seventh transistor, the seventh transistor comprising a first electrode connected to the second electrode of the first coupling capacitor, a second electrode connected to the third input terminal, and a gate electrode connected to the first electrode of the first coupling capacitor.

5. The stage according to claim 4, wherein, The node control unit also includes: The second coupling transistor is connected between the second electrode of the first transistor and the second control node and is turned on according to the second gate voltage.

6. The stage according to claim 5, wherein, The node maintenance unit includes: An eighth transistor, the eighth transistor including a first electrode connected to the first power supply terminal, a second electrode connected to the first control node, and a gate electrode connected to the second electrode of the first transistor; and A first capacitor includes a first electrode connected to the first power supply terminal and a second electrode connected to the first control node.

7. The stage according to claim 1, wherein, The output unit includes: A pull-up transistor, the pull-up transistor including a first electrode connected to the first power supply terminal, a second electrode connected to the output terminal, and a gate electrode connected to the first control node; and A pull-down transistor, the pull-down transistor including a first electrode connected to the output terminal, a second electrode connected to the second power supply terminal, and a gate electrode connected to the second control node.

8. The stage according to claim 1, wherein, The first gate voltage is set as the gate turn-off voltage, and the second gate voltage is set as the gate turn-on voltage.

9. The level according to claim 1, wherein: The first input signal is a start pulse or the output signal of the previous stage; and The second input signal and the third input signal are the first clock signal and the second clock signal, respectively.

10. The level according to claim 9, wherein: The first clock signal and the second clock signal alternately have gate on-voltage portions; and The start pulse or the output signal of the preceding stage is supplied to overlap with at least one of the gate on-voltage portions of the first clock signal.

11. A display device, comprising: Pixels, which are connected to scan lines, data lines and light emission control lines; A scan driver that supplies scan signals to the scan lines; A data driver that supplies data signals to the data line; as well as An optical emission control driver, comprising multiple stages for supplying optical emission control signals to multiple optical emission control lines. Each of the plurality of levels includes: A node control unit controls the voltage of a first control node and a second control node based on a first input signal supplied to a first input terminal, a second input signal supplied to a second input terminal, and a third input signal supplied to a third input terminal. The node control unit includes a first transistor, a second transistor, and a short-circuit prevention transistor. The first transistor is connected between the first input terminal and the second control node and includes a first electrode connected to the first input terminal. The second transistor is connected between a first power supply terminal and the third input terminal and includes a first electrode connected to the first power supply terminal. The short-circuit prevention transistor is connected between the first transistor and the second transistor and includes a first electrode connected to the second electrode of the second transistor and a second electrode connected to the second electrode of the first transistor. A node maintenance unit, wherein the node maintenance unit maintains the voltage of the first control node constant based on the voltage of the second control node; and An output unit, which supplies either a first gate voltage supplied to the first power supply terminal or a second gate voltage supplied to the second power supply terminal to the output terminal based on the voltage of the first control node and the voltage of the second control node. The node control unit further includes: A third transistor, the third transistor comprising a first electrode connected to the second electrode of the second transistor, a second electrode connected to the third input terminal, and a gate electrode connected to the second control node; and The second coupling capacitor includes a first electrode connected to the second electrode of the second transistor and a second electrode connected to the gate electrode of the third transistor. Each of the plurality of stages is configured such that, during power-on after a forced reset, when the first input signal having a gate turn-off voltage and the second and third input signals having a gate turn-on voltage are applied to the stage, a path is provided through the second transistor and the short-circuit prevention transistor to the second control node to prevent a short circuit between the first gate voltage and the second gate voltage.

12. The display device according to claim 11, wherein, The gate electrode of the short-circuit prevention transistor is connected to the third input terminal, and the short-circuit prevention transistor is turned on according to the third input signal.

13. The display device according to claim 11, wherein, The gate electrode of the first transistor is connected to the second input terminal, and the first transistor is turned on according to the second input signal.

14. The display device according to claim 13, wherein, The node control unit includes: A fourth transistor, the fourth transistor comprising a first electrode connected to the gate electrode of the second transistor, a second electrode connected to the second input terminal, and a gate electrode connected to the second electrode of the first transistor; The fifth transistor includes a first electrode connected to the first electrode of the fourth transistor, a second electrode connected to the second power supply terminal, and a gate electrode connected to the second input terminal; A first coupling transistor, the first coupling transistor including a first electrode connected to the first electrode of the fifth transistor, including a second electrode, and including a gate electrode connected to the second power supply terminal; A first coupling capacitor, the first coupling capacitor including a first electrode connected to the second electrode of the first coupling transistor, and including a second electrode; A sixth transistor, the sixth transistor comprising a first electrode connected to the first control node, a second electrode connected to the second electrode of the first coupling capacitor, and a gate electrode connected to the third input terminal; and A seventh transistor, the seventh transistor comprising a first electrode connected to the second electrode of the first coupling capacitor, a second electrode connected to the third input terminal, and a gate electrode connected to the first electrode of the first coupling capacitor.

15. The display device according to claim 14, wherein, The node control unit also includes: The second coupling transistor is connected between the second electrode of the first transistor and the second control node and is turned on according to the second gate voltage.

16. The display device according to claim 15, wherein, The node maintenance unit includes: An eighth transistor, the eighth transistor including a first electrode connected to the first power supply terminal, a second electrode connected to the first control node, and a gate electrode connected to the second electrode of the first transistor; and A first capacitor includes a first electrode connected to the first power supply terminal and a second electrode connected to the first control node.

17. The display device according to claim 11, wherein, The output unit includes: A pull-up transistor, the pull-up transistor including a first electrode connected to the first power supply terminal, a second electrode connected to the output terminal, and a gate electrode connected to the first control node; and A pull-down transistor, the pull-down transistor including a first electrode connected to the output terminal, a second electrode connected to the second power supply terminal, and a gate electrode connected to the second control node.

18. The display device according to claim 11, wherein, The first gate voltage is set as the gate turn-off voltage, and the second gate voltage is set as the gate turn-on voltage.

19. The display device according to claim 11, wherein: The first input signal is a start pulse or the output signal of the previous stage; and The second input signal and the third input signal are the first clock signal and the second clock signal, respectively.

20. The display device according to claim 19, wherein: The first clock signal and the second clock signal alternately have gate on-voltage portions; and The start pulse or the output signal of the preceding stage is supplied to overlap with at least one of the gate on-voltage portions of the first clock signal.

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