Memory Controller

Abstract

The present invention provides a memory controller. The memory controller is applicable to a pseudo-static random access memory. The memory controller includes a mode register, a mode register write controller, and a delay controller. The mode register is used to generate a delay control signal according to a write indication signal. The mode register write controller is used to generate a write indication signal during a mode register write operation and generate a write mask signal according to a chip select signal. The delay controller generates a delay pattern control signal according to the delay control signal and the write mask signal.

Description

Technical Field

[0001] The present invention relates to a memory technology, and more particularly to a memory controller. Background Art

[0002] Pseudo Static Random Access Memory (hereinafter referred to as pSRAM) uses DRAM as a memory cell array to store data, and redesigns the access interface of DRAM to make it compatible with the access interface of SRAM, and the access timing characteristics are also similar to those of SRAM.

[0003] In the existing memory technology, a memory controller is usually used to determine whether a self - refresh collision occurs in the pSRAM, and the memory controller is used to control the states of the delay control signal LTCX2_t generated by the mode register and the delay type control signal LTNCY2_t generated by the delay controller, so as to set the delay type of the access latency of the pSRAM.

[0004] Figure 1A And Figure 1B Show the signal timing diagram of the existing pseudo static random access memory. Please refer to Figure 1A And Figure 1B , which are the signal timing diagrams respectively corresponding to the pSRAM when it executes the Mode Register Write (MRW) operation and operates in the write mode, and when the memory controller determines that no self - refresh collision occurs and adjusts the access latency of the pSRAM to different delay types.

[0005] In Figure 1A In the situation where the memory controller wants to adjust the access latency of the pSRAM from 2 - fold delay time to 1 - fold delay time (that is, convert the delay type from the fixed delay type to the variable delay type), the inverted chip select signal (Chip Select Signal) CS# of the pSRAM is set to a low voltage level, and at this time, the delay control signal LTCX2_t and the delay type control signal LTNCY2_t will be first set to a high voltage level.

[0006] However, in the prior art, due to the too short reaction time of the time interval (that is, tCSH and tCSHI) when the inverted chip select signal CS# transitions from a low voltage level to a high voltage level, the delay control signal LTCX2_t and the delay type control signal LTNCY2_t cannot immediately transition to a low voltage level during the time interval.

[0007] In this case, it may cause the read / write data strobe signal RWDS output by the read / write data strobe (RWDS) pin (hereinafter referred to as the RWDS pin) to malfunction during the write operation of the memory cell array.

[0008] In contrast, in Figure 1B the situation where the memory controller desires to adjust the access delay of the pSRAM from 1 times the delay time to 2 times the delay time (i.e., convert the delay type from the variable delay type to the fixed delay type), the inverted chip select signal (CS#) of the pSRAM is set to a low voltage level, and at this time, the delay control signal LTCX2_t and the delay type control signal LTNCY2_t are first set to a low voltage level.

[0009] However, due to the short response time of the time interval (i.e., tCSH and tCSHI) during which the inverted chip select signal CS# transitions from the low voltage level to the high voltage level, the delay control signal LTCX2_t and the delay type control signal LTNCY2_t cannot immediately transition to the high voltage level during this time interval.

[0010] In this case, it may also cause the read / write data strobe signal RWDS output by the RWDS pin to malfunction during the write operation of the memory cell array.

[0011] In other words, in the above Figure 1A and Figure 1B cases, the read / write data strobe signal RWDS output by the RWDS pin is affected by the short time interval (i.e., tCSH and tCSHI), causing the read / write data strobe signal RWDS to malfunction during the write operation of the memory cell array, thereby preventing the pSRAM from writing valid data under the correct timing control and resulting in the overall memory system being unable to operate normally. SUMMARY OF THE INVENTION

[0012] The present invention provides a memory controller that can effectively reduce the occurrence of malfunction when setting the delay type of the access delay of the pSRAM, thereby improving the operation quality of the memory system.

[0013] The memory controller of the present invention is applicable to a pseudo-static random access memory. The memory controller includes a mode register, a mode register write controller, and a delay controller. The mode register is used to generate a delay control signal according to a write indication signal. The mode register write controller is used to generate a write indication signal during a mode register write operation and generate a write mask signal according to a chip select signal. The delay controller is coupled to the mode register and the mode register write controller, and generates a delay pattern control signal according to the delay control signal and the write mask signal.

[0014] Based on the above, the memory controller described in the embodiments of the present invention can perform a write operation on a memory cell array, and when the inverted chip select signal is in a disabled state, the delay controller can control the delay pattern control signal to remain in an enabled state according to a write mask signal with a high voltage level, so that the read / write data acquisition signal output by the RWDS pin will not malfunction during the write operation of the memory cell array, thereby effectively improving the operation quality of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A and Figure 1B show a signal timing diagram of a conventional pseudo-static random access memory;

[0016] Figure 2 is a schematic diagram showing an overview of a pseudo-static random access memory according to an embodiment of the present invention;

[0017] Figure 3 is described according to an embodiment of the present invention Figure 2 a circuit schematic diagram of the memory controller shown;

[0018] Figure 4 is a signal timing diagram showing when the memory controller controls the access delay of the pseudo-static random access memory to be converted from a fixed delay pattern to a variable delay pattern according to an embodiment of the present invention;

[0019] Figure 5 is a signal timing diagram showing when the memory controller controls the access delay of the pseudo-static random access memory to be converted from a variable delay pattern to a fixed delay pattern according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0021] Figure 2 is a schematic diagram showing an overview of a pseudo-static random access memory according to an embodiment of the present invention. Please refer toFigure 2 , the pSRAM 200 includes a memory controller 300, an input / output interface, an X decoder circuit, a Y decoder circuit, a memory cell array, a data latch circuit, and a data transfer path. Among them, the pSRAM 200 in this embodiment can be, for example, an xSPI pSRAM or a HyperRAM pSRAM with an Expanded Serial Peripheral Interface (hereinafter referred to as xSPI) or a HyperBus TM interface as its access interface, but the present invention is not limited thereto.

[0022] In this embodiment, the input / output interface of the pSRAM 200 can provide a chip select signal CS_t to the memory controller 300 according to the inverted chip select signal CS#. Among them, when the chip select signal CS_t is enabled (for example, a high voltage level), the pSRAM 200 can perform data access operations. When the chip select signal CS_t is disabled (for example, a low voltage level), the pSRAM 200 cannot perform data access operations. Among them, in this embodiment, the states of the chip select signal CS_t and the inverted chip select signal CS# can be complementary.

[0023] It should be noted that Figure 2 the detailed functions and implementation manners of the memory controller 300, the input / output interface, the X decoder circuit, the Y decoder circuit, the memory cell array, the data latch circuit, and the data transfer path shown can obtain sufficient teachings, suggestions, and implementation descriptions from the general knowledge in the technical field.

[0024] Figure 3 is illustrated according to an embodiment of the present invention Figure 2 a circuit schematic diagram of the memory controller shown. Please refer to Figure 3 , the memory controller 300 can be applicable to Figure 2 the memory controller of the pSRAM 200 shown. In this embodiment, the memory controller 300 includes a mode register 310, a mode register write controller 320, a delay controller 330, and a self-refresh controller 340.

[0025] In this embodiment, the mode register 310 receives a write indication signal MRW_t and mode register write data DATA, and generates a delay control signal LTCX2_t according to the write indication signal MRW_t and the mode register write data DATA. Among them, when the delay control signal LTCX2_t is in an enabled state (for example, a high voltage level), the delay control signal LTCX2_t can instruct the delay controller 330 to generate a delay type control signal LTNCY2_t for controlling the access delay of the pSRAM 200 to be a first type. In contrast, when the delay control signal LTCX2_t is in a disabled state (for example, a low voltage level), the delay control signal LTCX2_t can instruct the delay controller 330 to generate a delay type control signal LTNCY2_t for controlling the access delay of the pSRAM 200 to be a second type.

[0026] The self-refresh controller 340 receives a self-refresh request RE and a chip select signal CS_t, and generates a self-refresh wait signal WAITSR_t according to the self-refresh request RE and the chip select signal CS_t.

[0027] In this embodiment, the mode register write controller 320 includes a first-stage circuit 321 and a second-stage circuit 322. The mode register write controller 320 can receive a command COM through the first-stage circuit 321, and generate a write indication signal MRW_t in a mode register write (MRW) operation according to the command COM. Thereby, the mode register write controller 320 can determine whether the pSRAM 200 performs an MRW operation through the write indication signal MRW_t.

[0028] On the other hand, the second-stage circuit 322 is coupled to the first-stage circuit 321. The second-stage circuit 322 can generate a write mask signal WAITMRW_t according to the write indication signal MRW_t, the chip select signal CS_t, and the initialization control signal CHRDY_t.

[0029] Specifically, the second-stage circuit 322 includes a latch 323, a pulse width adjustment circuit 325, a logic gate AND, and an inverter INV7. Among them, the logic gate AND in this embodiment can be, for example, an AND gate, but the present invention is not limited thereto.

[0030] In this embodiment, the pulse width adjustment circuit 325 can receive the chip select signal CS_t and adjust the pulse width of the chip select signal CS_t to generate a complementary control signal CSD_t and an inverted control signal CSD_c. In addition, the latch 323 is coupled to the pulse width adjustment circuit 325 and the first-stage circuit 321. The latch 323 can generate an output signal n01 based on the control signal CSD_t, the inverted control signal CSD_c, and the write indication signal MRW_t.

[0031] On the other hand, the first input terminal of the logic gate AND is coupled to the pulse width adjustment circuit 325 to receive the control signal CSD_t, and the second input terminal of the logic gate AND is coupled to the latch 323 to receive the output signal n01. Moreover, the logic gate AND can perform an AND operation on the control signal CSD_t and the output signal n01 to generate a write mask signal WAITMRW_t at the output terminal of the logic gate AND. In addition, the input terminal of the inverter INV7 receives the initialization control signal CHRDY_t, and the output terminal of the inverter INV7 is coupled to the latch 323.

[0032] Regarding the detailed circuit architecture of the pulse width adjustment circuit 325, the pulse width adjustment circuit 325 includes inverters INV1, INV4, a plurality of inverters connected in series (e.g., INV2 and INV3), and a NAND gate NAND. Specifically, the input terminal of the inverter INV1 receives the chip select signal CS_t. The input terminals of the plurality of inverters connected in series are coupled to the output terminal of the inverter INV1. The first input terminal of the NAND gate NAND is coupled to the output terminal of the inverter INV1, and the second input terminal of the NAND gate NAND is coupled to the output terminal of the plurality of inverters connected in series. Moreover, the NAND gate NAND can perform a NAND operation on the signal generated by the inverter INV1 and the signal generated by the plurality of inverters connected in series to generate a control signal CSD_t at the output terminal of the NAND gate NAND.

[0033] In addition, the input terminal of the inverter INV4 is coupled to the output terminal of the NAND gate NAND to receive the control signal CSD_t. And the inverter INV4 can perform an inversion operation on the control signal CSD_t to generate an inverted control signal CSD_c at the output terminal of the inverter INV4.

[0034] Regarding the detailed circuit architecture of the latch 323, the latch 323 includes a tri-state inverter 324, an inverter INV5, and a NOR gate NOR. Among them, the tri-state inverter 324 in this embodiment can be composed of an inverter INV6, a P-type transistor M1, and an N-type transistor M2.

[0035] Specifically, in the tri-state inverter 324, the input terminal of the inverter INV6 can receive the write indication signal MRW_t. The P-type transistor M1 can be controlled by the control signal CSD_t, and the N-type transistor M2 can be controlled by the inverted control signal CSD_c. Moreover, the latch 323 can enable the tri-state inverter 324 according to the states of the control signal CSD_t and the inverted control signal CSD_c, so that the P-type transistor M1 and the N-type transistor M2 can be turned on respectively according to the control signal CSD_t and the inverted control signal CSD_c, and then the inverter INV6 can generate an inverted write indication signal MRW_t at the output terminal.

[0036] In addition, the first input terminal of the NOR gate is coupled to the output terminal of the inverter INV7, and the second input terminal of the NOR gate is coupled to the output terminal of the inverter INV6. And the NOR gate can perform an inverted AND-OR operation on the signal generated by the inverter INV7 and the inverted write indication signal MRW_t to generate an output signal n01 at the output terminal of the NOR gate. Additionally, the inverter INV5 is coupled between the output terminal of the NOR gate and the second input terminal of the NOR gate. Therefore, the latch 323 can feedback the output signal n01 to the second input terminal of the NOR gate through the inverter INV5.

[0037] It should be noted that the latch 323, the tri-state inverter 324, and the pulse width adjustment circuit 325 in this embodiment can be implemented by latches, tri-state inverters, and pulse width adjustment circuits well-known to those skilled in the art. The present invention is not limited to the circuit architectures proposed above.

[0038] On the other hand, the delay controller 330 is coupled to the mode register 310, the mode register write controller 320, and the self-refresh controller 340. In this embodiment, the delay controller 330 can generate a delay mode control signal LTNCY2_t according to the self-refresh wait signal WAITSR_t, the delay control signal LTCX2_t, and the write mask signal WAITMRW_t.

[0039] It is worth mentioning that the delay controller 330 in this embodiment can control the access delay of the pSRAM 200 to be the first mode or the second mode through the delay mode control signal LTNCY2_t. For example, when the delay mode control signal LTNCY2_t is in the enabled state (such as a high voltage level), the delay mode of the access delay can be defined as a fixed delay mode (corresponding to the first mode). And when the delay mode control signal LTNCY2_t is in the disabled state (such as a low voltage level), the delay mode of the access delay can be defined as a variable delay mode (corresponding to the second mode).

[0040] Furthermore, in the present embodiment, the first pattern may correspond to a first delay time, and the second pattern may correspond to a second delay time, and the first delay time is an integer multiple of the second delay time (for example, 2 times, but the present invention is not limited thereto).

[0041] Regarding the detailed circuit architecture of the delay controller 330, the delay controller 330 includes a logic gate OR1 and a logic gate OR2. These logic gates OR1 and OR2 may be, for example, OR gates, but the present invention is not limited thereto. Specifically, the first input terminal of the logic gate OR1 is coupled to the mode register 310 to receive the delay control signal LTCX2_t, and the second input terminal of the logic gate OR1 is coupled to the mode register write controller 320 to receive the write mask signal WAITMRW_t.

[0042] In addition, the first input terminal of the logic gate OR2 is coupled to the self-refresh controller 340 to receive the self-refresh wait signal WAITSR_t, and the second input terminal of the logic gate OR2 is coupled to the output terminal of the logic gate OR1. Moreover, the logic gate OR2 can perform an OR operation on the self-refresh wait signal WAITSR_t and the signal output by the logic gate OR1 to generate a delay pattern control signal LTNCY2_t at the output terminal.

[0043] That is to say, in the present embodiment, when any one of the self-refresh wait signal WAITSR_t, the delay control signal LTCX2_t, and the write mask signal WAITMRW_t is set to be enabled (for example, a high voltage level), the delay controller 330 can control the access delay of the pSRAM 200 to be the first pattern (i.e., a fixed delay pattern) through the delay pattern control signal LTNCY2_t.

[0044] Figure 4 FIG. is a signal timing diagram when the memory controller controls the access delay of the pseudo-static random access memory to be converted from a fixed delay pattern to a variable delay pattern according to an embodiment of the present invention. Among them, Figure 4 The embodiment assumes that the pSRAM 200 operates in the write mode and no self-refresh collision occurs.

[0045] Please refer to Figures 2 to 4, in this embodiment, when the pSRAM 200 operates at the initial time before startup (e.g., power-on), the memory controller 300 does not perform the MRW operation, and the initialization control signal CHRDY_t can be set to the disabled state (e.g., low voltage level). In this case, the latch 323 of the mode register write controller 320 can initialize the output signal n01 according to the disabled initialization control signal CHRDY_t, so that the output signal n01 is set to the low voltage level state at the initial time.

[0046] Then, after the pSRAM 200 completes the power-on operation, the initialization control signal CHRDY_t can be set to the enabled state (e.g., high voltage level) again, and the state of the initialization output signal n01 is completed.

[0047] Then, when the pSRAM 200 operates in the time interval T11, the inverted chip select signal CS# and the write indication signal MRW_t are both set to the disabled state (e.g., low voltage level). At this time, the pulse width adjustment circuit 325 can generate a control signal CSD_t with a high voltage level and an inverted control signal CSD_c with a low voltage level according to the enabled chip select signal CS_t (e.g., high voltage level).

[0048] In this case, the transistors M1 and M2 of the tri-state inverter 324 are disconnected according to the control signal CSD_t and the inverted control signal CSD_c respectively, so that the latch 323 can latch the state of the output signal n01 (i.e., the state of the output signal n01 is maintained at the low voltage level). At the same time, the mode register write controller 320 can generate a write mask signal WAITMRW_t with a disabled state (e.g., low voltage level) according to the control signal CSD_t with a high voltage level and the output signal n01 with a low voltage level.

[0049] It is worth mentioning that when the pSRAM 200 operates at the initial time of the time interval T11, the mode register write controller 320 can determine that the memory controller 300 does not perform the MRW operation according to the write indication signal MRW_t.

[0050] Then, when the pSRAM 200 operates in the time interval T21 after the time interval T11, the inverted chip select signal CS# and the write indication signal MRW_t are both set to the enabled state (e.g., high voltage level). At this time, the pulse width adjustment circuit 325 can generate a control signal CSD_t with a low voltage level and an inverted control signal CSD_c with a high voltage level according to the disabled chip select signal CS_t (e.g., low voltage level).

[0051] In this case, the transistors M1 and M2 of the tri-state inverter 324 are turned on respectively according to the control signal CSD_t and the inverted control signal CSD_c, so that the latch 323 can generate an output signal n01 with a high voltage level according to the write indication signal MRW_t with a high voltage level and the initialization control signal CHRDY_t with a high voltage level. And, the mode register write controller 320 can generate a write mask signal WAITMRW_t that is disabled (for example, at a low voltage level) according to the output signal n01 and the control signal CSD_t.

[0052] On the other hand, when the pSRAM 200 operates in the time interval T31 after the time interval T21, it means that the memory cell array of the pSRAM 200 can start a write operation. At this time, the inverted chip select signal CS# is set to the disabled (for example, at a low voltage level) state, and the write indication signal MRW_t can be maintained at the enabled (for example, at a high voltage level) state at the initial time of the time interval T31. Therefore, the pulse width adjustment circuit 325 can generate a control signal CSD_t with a high voltage level and an inverted control signal CSD_c with a low voltage level according to the enabled (for example, at a high voltage level) chip select signal CS_t.

[0053] In this case, the transistors M1 and M2 of the tri-state inverter 324 are turned off respectively according to the control signal CSD_t and the inverted control signal CSD_c, so that the latch 323 can latch the state of the output signal n01 (that is, the state of the output signal n01 is maintained at a high voltage level).

[0054] At the same time, the mode register write controller 320 can generate a write mask signal WAITMRW_t that is enabled (for example, at a high voltage level) according to the control signal CSD_t with a high voltage level and the output signal n01 with a high voltage level.

[0055] In other words, during the write operation of the memory cell array of the pSRAM 200 (that is, the time interval T31), the delay controller 330 can generate an enabled delay type control signal LTNCY2_t according to the write mask signal WAITMRW_t with a high voltage level, so that the read / write data acquisition signal RWDS output by the RWDS pin does not malfunction during the write operation of the memory cell array.

[0056] In addition, in this embodiment, the mode register write controller 320 can determine that the pSRAM 200 is executing an MRW operation at the initial time when a write operation is performed on the memory cell array of the pSRAM 200. And, since the mode register 310 generates a disabled delay control signal LTCX2_t according to the write indication signal MRW_t at this time, the memory controller 300 can set the access delay of the pSRAM 200 to a variable delay type when a write operation is performed on the memory cell array of the pSRAM 200, and the delay type control signal LTNCY2_t can still be maintained at a high voltage level.

[0057] Next, when the pSRAM 200 operates in the time interval T41 after the time interval T31, it indicates that the write operation on the memory cell array of the pSRAM 200 has been completed. At this time, the inverted chip select signal CS# is set to an enabled state (for example, a high voltage level), and the write indication signal MRW_t is set to a disabled state (for example, a low voltage level). Therefore, the pulse width adjustment circuit 325 can generate a control signal CSD_t with a low voltage level and an inverted control signal CSD_c with a high voltage level according to the disabled (for example, low voltage level) chip select signal CS_t.

[0058] In this case, the transistors M1 and M2 of the tri-state inverter 324 are turned on respectively according to the control signal CSD_t and the inverted control signal CSD_c, so that the latch 323 can generate an output signal n01 with a low voltage level according to the write indication signal MRW_t with a low voltage level and the initialization control signal CHRDY_t with a high voltage level. And the mode register write controller 320 can generate a disabled (for example, low voltage level) write mask signal WAITMRW_t according to the output signal n01 and the control signal CSD_t.

[0059] Figure 5 It is a signal timing diagram showing that a memory controller controls the access delay of a pseudo-static random access memory to be converted from a variable delay type to a fixed delay type according to an embodiment of the present invention. Among them, Figure 5 The embodiment assumes that the pSRAM 200 operates in the write mode and no self-refresh collision occurs.

[0060] It should be noted that in Figure 5 the shown embodiment, the operation details of the pSRAM 200 operating in the time interval T12 - T22 can be analogized with reference to the relevant description of the time interval T11 - T21 in the Figure 4 shown embodiment, so it will not be elaborated here.

[0061] Please refer to it simultaneously hereFigure 2 , Figure 3 and Figure 5 , when the pSRAM 200 operates in the time interval T32 after the time interval T22, it indicates that the memory cell array of the pSRAM 200 can start a write operation. At this time, the inverted chip select signal CS# is set to the disabled (e.g., low voltage level) state, and the write indication signal MRW_t can be maintained at the enabled (e.g., high voltage level) state at the initial time of the time interval T32. Therefore, the pulse width adjustment circuit 325 can generate a control signal CSD_t with a high voltage level and an inverted control signal CSD_c with a low voltage level according to the chip select signal CS_t that is enabled (e.g., high voltage level).

[0062] In this case, the transistors M1 and M2 of the tri-state inverter 324 are respectively turned off according to the control signal CSD_t and the inverted control signal CSD_c, so that the latch 323 can latch the state of the output signal n01 (i.e., the state of the output signal n01 is maintained at a high voltage level).

[0063] At the same time, the mode register write controller 320 can generate a write mask signal WAITMRW_t that is enabled (e.g., high voltage level) according to the control signal CSD_t with a high voltage level and the output signal n01 with a high voltage level.

[0064] In other words, during the write operation of the memory cell array of the pSRAM 200 (i.e., the time interval T32), the delay controller 330 can generate an enabled delay mode control signal LTNCY2_t according to the write mask signal WAITMRW_t with a high voltage level, so that the read / write data acquisition signal RWDS output by the RWDS pin does not malfunction during the write operation of the memory cell array.

[0065] In addition, in this embodiment, the mode register write controller 320 can determine that the pSRAM 200 executes the MRW operation at the initial time of the write operation of the memory cell array of the pSRAM 200. And since the mode register 310 generates an enabled delay control signal LTCX2_t according to the write indication signal MRW_t at this time, the memory controller 300 can set the access delay of the pSRAM 200 to a fixed delay mode during the write operation of the memory cell array of the pSRAM 200, and the delay mode control signal LTNCY2_t can still be maintained at a high voltage level.

[0066] Next, when the pSRAM 200 operates in the time interval T42 after the time interval T32, it indicates that the write operation of the memory cell array of the pSRAM 200 has been completed. At this time, the inverted chip select signal CS# is set to the enabled state (e.g., high voltage level), and the write indication signal MRW_t is set to the disabled state (e.g., low voltage level). Therefore, the pulse width adjustment circuit 325 can generate a control signal CSD_t with a low voltage level and an inverted control signal CSD_c with a high voltage level according to the chip select signal CS_t that is disabled (e.g., low voltage level).

[0067] In this case, the transistors M1 and M2 of the tri-state inverter 324 are turned on respectively according to the control signal CSD_t and the inverted control signal CSD_c, so that the latch 323 can generate an output signal n01 with a low voltage level according to the write indication signal MRW_t with a low voltage level and the initialization control signal CHRDY_t with a high voltage level. And the mode register write controller 320 can generate a write mask signal WAITMRW_t that is disabled (e.g., low voltage level) according to the output signal n01 and the control signal CSD_t.

[0068] According to the above Figure 4 and Figure 5 description of the embodiments, whether the memory controller 300 wants to convert the access delay of the pSRAM 200 from the variable delay type to the fixed delay type, or convert the access delay of the pSRAM 200 from the fixed delay type to the variable delay type, and even if the pSRAM 200 operates in the time intervals tCSH and tCSHI with shorter response times, the read / write data acquisition signal RWDS output by the RWDS pin of this embodiment will not malfunction due to misinterpretation of the delay type during the write operation of the memory cell array.

[0069] In summary, the memory controller described in the present invention can perform a write operation on the memory cell array, and when the inverted chip select signal is in the disabled state, the delay controller can control the delay type control signal to remain in the enabled state according to the write mask signal with a high voltage level, so that the read / write data acquisition signal output by the RWDS pin will not malfunction during the write operation of the memory cell array, thereby effectively improving the operation quality of the memory system.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory controller, applicable to a pseudo-static random access memory, comprising: a mode register for generating a delay control signal according to a write indication signal; a mode register write controller for generating the write indication signal during a mode register write operation and generating a write mask signal according to a chip select signal; and a delay controller coupled to the mode register and the mode register write controller and generating a delay pattern control signal according to the delay control signal and the write mask signal.

2. The memory controller according to claim 1, wherein when the chip select signal is enabled, the mode register write controller determines whether the mode register write operation is executed according to the write indication signal, and the mode register write controller generates the write mask signal according to the determination result, so that the delay controller controls the access delay of the pseudo-static random access memory to be a first pattern or a second pattern through the delay pattern control signal.

3. The memory controller according to claim 2, wherein when the write indication signal indicates that the mode register write operation is executed, the mode register write controller generates the write mask signal that is enabled, and enables the delay controller to control the access delay of the pseudo-static random access memory to be the first pattern through the delay pattern control signal.

4. The memory controller according to claim 3, wherein the first pattern corresponds to a first delay time, and the second pattern corresponds to a second delay time, and the first delay time is an integer multiple of the second delay time.

5. The memory controller according to claim 1, further comprising: a self-refresh controller for generating a self-refresh wait signal according to a self-refresh request and the chip select signal, wherein the delay controller is further coupled to the self-refresh controller, and the delay controller further generates the delay pattern control signal according to the self-refresh wait signal.

6. The memory controller according to claim 5, wherein the delay controller comprises: a first logic gate, whose first input terminal receives the delay control signal and whose second input terminal receives the write mask signal; and a second logic gate, whose first input terminal receives the self-refresh wait signal, whose second input terminal is coupled to the output terminal of the first logic gate, and whose output terminal generates the delay pattern control signal.

7. The memory controller according to claim 5, wherein when any one of the self-refresh wait signal, the delay control signal, and the write mask signal is enabled, the delay controller controls the access delay of the pseudo-static random access memory to be the first pattern through the delay pattern control signal.

8. The memory controller according to claim 1, wherein the mode register write controller comprises: a first-stage circuit for generating the write indication signal according to a command; and A second-stage circuit, coupled to the first-stage circuit, and generating the write mask signal according to the write instruction signal, the chip select signal, and the initialization control signal.

9. The memory controller according to claim 8, wherein the second-stage circuit comprises: A pulse width adjustment circuit, receiving the chip select signal, and generating a control signal and an inverted control signal according to the chip select signal; A latch, coupled to the pulse width adjustment circuit and the first-stage circuit, and generating an output signal according to the control signal, the inverted control signal, and the write instruction signal; and A logic gate, having its first input terminal receiving the control signal, its second input terminal receiving the output signal, and its output terminal generating the write mask signal.

10. The memory controller according to claim 9, wherein the pulse width adjustment circuit adjusts the pulse width of the chip select signal to generate the complementary control signal and inverted control signal.

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