Memory array including a string of memory cells and method for forming a memory array

Abstract

This application relates to memory arrays including strings of memory cells and methods for forming memory arrays including strings of memory cells. A memory array including strings of memory cells includes an upper stack above a lower stack. The lower stack includes vertically alternating lower conductive layers and lower insulative layers. The upper stack includes vertically alternating upper conductive layers and upper insulative layers. An intermediate layer is vertically between the upper stack and the lower stack. The intermediate layer is at least predominantly polysilicon and has a composition different from the compositions of the upper conductive layers and the upper insulative layers directly above the intermediate layer and a composition different from the compositions of the lower conductive layers and the lower insulative layers directly below the intermediate layer. Strings of channel material of memory cells extend through the upper stack, the intermediate layer, and the lower stack. Other structures and methods are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to memory arrays and methods for forming memory arrays. Background Technology

[0002] Memory is a type of integrated circuit system used to store data in computer systems. Memory can be fabricated in an array of one or more individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines conductively interconnect memory cells along the columns of the array, while access lines conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed through a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically specified as having a retention time of at least approximately 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. In any case, memory cells are configured to hold or store the memory in at least two distinct optional states. In binary systems, states are considered to be "0" or "1". In other systems, at least some individual memory cells can be configured to store information in more than two levels or states.

[0004] Field-effect transistors (FETs) are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying an appropriate voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely prevented. FETs may also include additional structures, such as a reversible programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory with a variety of uses in modern computers and devices. For example, modern personal computers can store the BIOS on flash memory chips. As another example, it is becoming increasingly common for computers and other devices to use flash memory in solid-state drives instead of conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it allows manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices to enhance features.

[0006] NAND can be a basic architecture for integrated flash memory. A NAND cell unit includes at least one selection device of a series combination (often referred to as a NAND string) of memory cells coupled in series to them. The NAND architecture can be configured in a three-dimensional arrangement comprising vertically stacked memory cells, each individually including a reversible programmable vertical transistor. Control or other circuitry can be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells, each individually including a transistor.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and portions of blocks (e.g., sub-blocks), as well as memory planes, for example, as shown and described in any of U.S. Patent Application Publications Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. Memory blocks can at least partially define the longitudinal profile of individual word lines in a single word line hierarchy of vertically stacked memory cells. Connections to these word lines can occur in a so-called “stair-step structure” at the ends or edges of the vertically stacked memory cell array. The stair-step structure comprises a single “step” (also called a “step portion” or “staircase”) that defines a contact area for the individual word line, on which vertically extending conductive vias contact to provide electrical access to the word line. Summary of the Invention

[0008] One embodiment of this disclosure provides a method for forming a memory array including a string of memory cells, comprising: forming an upper stack above a lower stack, the lower stack including vertically alternating lower first and lower second layers, the upper stack including vertically alternating upper first and upper second layers, an intermediate layer vertically located between the upper stack and the lower stack, a lower channel opening extending through the intermediate layer and the lower first and lower second layers, the lower channel opening having sacrificial material in the intermediate layer and in the lower first and lower second layers, the intermediate layer being at least one of (a), (b), and (c), wherein: (a) the thickness is greater than the thickness of the upper first layer and the upper second layer directly above the intermediate layer, and greater than the thickness of the lower first layer and the lower second layer directly below the intermediate layer; (b) at least a primary layer... If it is polycrystalline silicon and has a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; and (c): at least primarily conductive and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; forming an upper channel opening through the upper first layer and the upper second layer to the intermediate layer, a single upper channel opening in the upper channel opening extending into a sacrificial material in a single lower channel opening in the lower channel opening; and removing the sacrificial material from the single lower channel opening through the upper channel opening, subsequently forming a channel material string in the upper channel opening and the lower channel opening.

[0009] Another embodiment of this disclosure provides a memory array including strings of memory cells, comprising: an upper stack above a lower stack, the lower stack including vertically alternating lower conductive layers and lower insulating layers, the upper stack including vertically alternating upper conductive layers and upper insulating layers; an intermediate layer vertically located between the upper stack and the lower stack, the intermediate layer being at least primarily polysilicon and having a composition different from that of the upper conductive layers and the upper insulating layers directly above the intermediate layer, and having a composition different from that of the lower conductive layers and the lower insulating layers directly below the intermediate layer; and a string of channel material for memory cells extending through the upper stack, the intermediate layer, and the lower stack.

[0010] Another embodiment of this disclosure provides a memory array including strings of memory cells, comprising: an upper stack above a lower stack, the lower stack including vertically alternating lower conductive layers and lower insulating layers, the upper stack including vertically alternating upper conductive layers and upper insulating layers; an intermediate layer vertically located between the upper stack and the lower stack, the intermediate layer being at least primarily conductive and having a composition different from that of the upper conductive layer directly above the intermediate layer and having a composition different from that of the lower conductive layer directly below the intermediate layer; and a string of channel material for memory cells extending through the upper stack, the intermediate layer, and the lower stack.

[0011] Another embodiment of this disclosure provides a memory array including strings of memory cells, comprising: an upper stack above a lower stack, the lower stack including vertically alternating lower conductive layers and lower insulating layers, the upper stack including vertically alternating upper conductive layers and upper insulating layers; an intermediate layer vertically located between the upper stack and the lower stack; and a string of channel material for memory cells extending through the upper stack, the intermediate layer, and the lower stack; portions of individual channel material strings in the upper stack having an average longitudinal axis angled to the average longitudinal axis of said portion of said individual channel material string in the lower stack.

[0012] Another embodiment of this disclosure provides a memory array including a string of memory cells, comprising: an upper stack above a lower stack, the lower stack including vertically alternating lower conductive layers and lower insulating layers, the upper stack including vertically alternating upper conductive layers and upper insulating layers; an intermediate layer vertically located between the upper stack and the lower stack, the intermediate layer being at least one of (a), (b), and (c), wherein: (a) the thickness is greater than the thickness of the upper conductive layer directly above the intermediate layer and the thickness of the upper insulating layer, and greater than the thickness of the lower conductive layer directly below the intermediate layer and the thickness of the lower insulating layer; (b) the layer is at least primarily polysilicon and has a layer adjacent to the upper conductive layer directly above the intermediate layer and the lower insulating layer. The composition of the upper insulating layer is different from that of the lower conductive layer directly below the intermediate layer and the lower insulating layer; and (c) is at least primarily conductive and has a composition different from that of the upper conductive layer directly above the intermediate layer and has a composition different from that of the lower conductive layer directly below the intermediate layer; and a channel material string of memory cells extending through the upper stack, the intermediate layer and the lower stack; a portion of a single channel material string in the upper stack has an average longitudinal axis that is angled to the average longitudinal axis of the portion of the single channel material string in the lower stack. Attached Figure Description

[0013] Figure 1 This is a schematic cross-sectional view of a portion of the substrate in the process according to an embodiment of the present invention, and along... Figure 2 Cut off line 1-1 in the middle.

[0014] Figure 2 It is along Figure 1 A schematic cross-sectional view taken from line 2-2 in the diagram.

[0015] Figure 3 yes Figure 1 and 2 A magnified view of a portion of it.

[0016] Figures 4 to 20 It is a process according to some embodiments of the present invention. Figures 1 to 3 Schematic sequential cross-sectional views, unfolded views, enlarged views and / or partial views of the structure or its parts.

[0017] Figure 21 Alternative exemplary methods and / or structural embodiments of the present invention are shown. Detailed Implementation

[0018] Embodiments of the present invention cover methods for forming memory arrays, such as NAND or other memory cells that may have at least some peripheral control circuitry beneath the array (e.g., CMOS-under-array). Embodiments of the present invention cover so-called "back gate" or "replacement gate" processes, so-called "front gate" processes, and other existing or future-developed processes independent of when the transistor gate is formed. Embodiments of the present invention also cover memory arrays (e.g., NAND architectures) independent of the manufacturing process. Reference Figures 1 to 20 Describing a first exemplary method embodiment, the method may be considered a "post-gate" or "replacement gate" process and from Figures 1 to 3 start.

[0019] Figures 1 to 3 A configuration 10 with an array or array region 12 is shown, in which vertically extending strings of transistors and / or memory cells will be formed. Configuration 10 includes a substrate 11 having any one or more of the following materials: conductive / conductive / conductively conductive, semiconductive / semiconductor / semi-conductive, or insulating / insulating (i.e., electrical in this context). Various materials have been vertically formed over the substrate 11. The materials can be... Figures 1 to 3 The material depicted may be located beside, vertically inside, or vertically outside the substrate 11. For example, other parts or all finished components of an integrated circuit system may be disposed above, around, or inside the substrate 11. Control and / or other peripheral circuitry systems for operating components within an array (e.g., array 12) of vertically extending strings of memory cells may also be fabricated, and these control and / or other peripheral circuitry systems may or may not be wholly or partially within the array or subarray. Furthermore, multiple subarrays may be fabricated and operated independently, in series, or otherwise relative to each other. In this document, "subarray" may also be considered as an array.

[0020] Including conductor material 17 (e.g., WSi) x A conductive layer 16 of top-conductive doped polysilicon has been formed over the substrate 11. The conductive layer 16 may include a portion of a control circuitry system (e.g., peripheral array under-circuit and / or common source line or board) for controlling read and write access to transistors and / or memory cells to be formed within the array 12.

[0021] A lower stack 18L, comprising vertically alternating lower insulating layers 20L and lower conductive layers 22L, has been formed above the conductor layer 16. Each of the lower layers 20L and 22L has an exemplary thickness of 22 to 60 nanometers. Only a small number of lower layers 20L and 22L are shown; more likely, the lower stack 18L comprises tens, hundreds, or more lower layers 20L and 22L. Other circuitry, which may or may not be part of a peripheral device and / or control circuitry system, may exist between the conductor layer 16 and the lower stack 18L. For example, multiple vertically alternating layers of conductive and insulating material in this circuitry may be below the lowest layer in the lower conductive layer 22L and / or above the highest layer in the lower conductive layer 22L. For example, one or more select gate layers (not shown) or dummy layers (not shown) may exist between the conductor layer 16 and the lowermost conductive layer 22L, and one or more select gate layers (not shown) or dummy layers (not shown) may exist above the uppermost layer in the lower conductive layer 22L. Alternatively or additionally, at least one of the depicted lowest conductive layers 22L may be a selected gate layer. In any case, the lower conductive layer 22L (alternately referred to as the lower first layer) may not include conductive material, and the lower insulating layer 20L (alternately referred to as the lower second layer) may not include insulating material, or may be insulating at the moment of processing in conjunction with the exemplary method embodiments described herein, a method known as "post-gate" or "replacement gate". The exemplary lower conductive layer 22L comprises a first material 26 (e.g., silicon nitride), which may be wholly or partially sacrificed. The exemplary lower insulating layer 20L comprises a second material 24 (e.g., silicon dioxide), which has a different composition from the first material 26 and may be wholly or partially sacrificed.

[0022] The intermediate layer 21 is above the lower stack 18L, and its characteristics are further described below.

[0023] A lower channel opening 25 is formed (e.g., by etching) through the intermediate layer 21, the lower insulating layer 20L, and the lower conductive layer 22L to reach the conductor layer 16. The lower channel opening 25 may taper radially inward (not shown) to extend deeper into the lower stack 18L. In some embodiments, the lower channel opening 25 may extend into the conductor material 17 of the conductor layer 16 as shown, or it may stop at its top (not shown). Alternatively, as an example, the lower channel opening 25 may stop at the top or inside of the lowest lower insulating layer 20L. The reason for extending the lower channel opening 25 at least into the conductor material 17 of the conductor layer 16 is to provide an anchoring effect of material within the lower channel opening 25. An etch-stop material (not shown) may be present within or on top of the conductor material 17 of the conductor layer 16 to facilitate this when it is necessary to stop etching the lower channel opening 25 relative to the conductor layer 16. This etch-stop material may be sacrificial or non-sacrificial. In any case, the lower channel opening 25 can be considered to have a vertical average longitudinal axis 75 in one embodiment (e.g., if axis 75 is not perfectly straight, it is average).

[0024] A horizontally elongated lower trench 40L has been formed (e.g., by anisotropic etching) into the intermediate layer 21 and the lower stack 18L to form laterally spaced memory block regions 58. By way of example only and for simplicity, the lower channel openings 25 are shown as groups or columns arranged in staggered rows of four and five lower channel openings 25 per row, and arranged within the laterally spaced memory block regions 58, which will comprise laterally spaced memory blocks 58 of the finished circuit system construction. In this document, "block" generally includes "sub-block". The lower trench 40L will typically be wider than the lower channel openings 25 (e.g., 10 to 20 times wider, but this wider extent is not shown for simplicity). The memory block regions 58 and the resulting memory blocks 58 (not shown) can be considered as longitudinally elongated and oriented, for example, along direction 55. Any alternative existing or future-developed arrangements and constructions can be used.

[0025] Sacrificial material 59 is formed in the lower channel opening 25 of the intermediate layer 21, the lower first layer 22L, and the lower second layer 20L. In one embodiment, and as shown, sacrificial material 59 is formed in the lower trench 40L. In one embodiment, the sacrificial material 59 in the lower channel opening 25 includes radially outer silicon dioxide 70, radially inner silicon dioxide 72, and alumina 71 between the radially outer silicon dioxide 70 and the radially inner silicon dioxide 72. The lower trench 40L may include corresponding alumina 71 and silicon dioxide 70, 72. In other figures, for simplicity, materials 70, 71, and 72 are only shown in the lower trench. Figure 3As specified herein. In one embodiment, the radially outer silicon dioxide 70 and the radially inner silicon dioxide 72 have different compositions from each other, and in one such embodiment, the different compositions are characterized by the concentration of at least one of boron and phosphorus. By way of specific example only, the radially inner silicon dioxide 72 is BPSG, while the radially outer silicon dioxide 70 is undoped silicon dioxide.

[0026] refer to Figure 4 An upper stack 18U, comprising vertically alternating upper insulating layer 20U (alternately referred to as the upper second layer) and upper conductive layer 22U (alternately referred to as the upper first layer), is formed above the intermediate layer 21 and the lower stack 18L. The upper insulating layer 20U and the upper conductive layer 22U may have any of the properties described above regarding the lower insulating layer 20L and the lower conductive layer 22L. An exemplary upper conductive layer 22U comprises a first material 26 (e.g., silicon nitride), which may be entirely or partially sacrificed. An exemplary upper insulating layer 20U is shown comprising a second material 24, while the upper conductive layer 22U is shown comprising the first material 26; however, other compositions may of course be used, and it need not have the same composition as in the lower stack 18L.

[0027] In some embodiments, the intermediate layer 21 is at least one of (a), (b), and (c), wherein:

[0028] (a): The thickness is greater than the thickness of the upper first layer 22U directly above the intermediate layer 21 and the thickness of the upper second layer 20U, and is greater than the thickness of the lower first layer 22L and the lower second layer 20L directly below the intermediate layer 21 (for example, at least two or three times as shown in the figure).

[0029] (b): At least primarily polycrystalline silicon and having a composition different from that of the upper first layer 22U and upper second layer 20U directly above the intermediate layer 21 and a composition different from that of the lower first layer 22L and lower second layer 20L directly below the intermediate layer 21; and

[0030] (c): It is at least primarily conductive and has a composition different from that of the upper first layer 22U and upper second layer 20U directly above the intermediate layer 21 and a composition different from that of the lower first layer 22L and lower second layer 20L directly below the intermediate layer 21.

[0031] In one embodiment, the intermediate layer 21 is (a); in another embodiment it is (b); in another embodiment it is (c); in another embodiment it is at least two of (a), (b) and (c); and in yet another embodiment it is (a), (b) and (c).

[0032] If (b) or includes (b), then in one embodiment, the intermediate layer 21 is at least primarily undoped polysilicon (i.e., "undoped" in the context of polysilicon refers to impurities that increase conductivity, and means from 0 atoms / cm²). 3 Up to 1×10 12 atoms / cm 3 If (b) or includes (b), then in one embodiment, the intermediate layer 21 is at least primarily doped polysilicon (i.e., "doped" in the context of polysilicon is an impurity with increased reference conductivity, and means from 1x10⁻⁶ to 10⁻⁶). 12 atoms / cm 3 Up to 1x10 30 atoms / cm 3 In one such embodiment, at least primarily semiconductive doped polycrystalline silicon (e.g., from 1x10⁻¹⁰) is used. 14 atoms / cm 3 Less than 1x10 21 atoms / cm 3 In another such embodiment, at least primarily conductive-doped polysilicon (e.g., from 1x10⁻¹⁰) is used. 21 atoms / cm 3 Up to 1x10 30 atoms / cm 3 ).

[0033] In one embodiment, if (c) or includes (c), then the intermediate layer 21 is at least primarily at least one selected from elemental metals, metal alloys, metal nitrides, and metal silicides. In another embodiment, if (c) or includes (c), then the intermediate layer 21 is at least primarily a conductive-doped semiconductive material.

[0034] refer to Figures 5 to 7 An upper channel opening 39 has been formed (e.g., by etching) through the upper first layer 22U and the upper second layer 20U to reach the intermediate layer 21. A single upper channel opening 39 extends into a single lower channel opening 25 containing sacrificial material 59. In one embodiment, as shown in the figure and referenced... Figure 6 and 7As can be best understood, a single upper channel opening 39 is formed having an average longitudinal axis 85, which forms an angle A with the average longitudinal axis 75 of the corresponding single lower channel opening 25 to which the upper channel opening is to extend. In one embodiment, this angle is at least 0.5° with respect to the average longitudinal axis 75, in another such embodiment it is no more than 5.0°, and in yet another such embodiment it is at least 1.0° to no more than 5.0° (4° is shown in the figure) with respect to the average longitudinal axis 75. In any case, if the upper channel opening 39 is formed by etching, some etching (not shown) may occur in the lower sacrificial material 59, the intermediate material, and / or the uppermost layer.

[0035] refer to Figure 8 and 9 The sacrificial material 59 (i.e., at least some) has been removed from the single lower channel opening 25 through the upper channel opening 39 (e.g., by etching). For example, in the presence of materials 70, 71, and 72, some of 70 and / or 71 may be retained to facilitate the formation of transistor material (described below).

[0036] Transistor channel material can be formed along the insulating and conductive layers in a single channel opening, thus comprising a single string of channel material that is directly electrically coupled to the conductive material in the conductor layer. A single memory cell of the formed exemplary memory array may include a gate region (e.g., a control-gate region) and a memory structure laterally located between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge-blocking region, a storage material (e.g., a charge storage material), and an insulating charge channel material. The storage material of the single memory cell (e.g., a floating gate material such as doped or undoped silicon or a charge-trapping material such as silicon nitride, a metal point, etc.) is perpendicular to the single charge-blocking region within the charge-blocking region. The insulating charge channel material (e.g., a bandgap engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulating oxides (e.g., silicon dioxide) is laterally located between the channel material and the storage material.

[0037] Figures 10 to 13 One embodiment is shown in which charge blocking material 30, storage material 32, and charge channel material 34 are formed perpendicularly along insulating layer 20 and conductive layer 22 in a single upper channel opening 39 and lower channel opening 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed, for example, by depositing corresponding thin layers of the transistor material over the upper stack 18U and within the single openings 39 and 25, and subsequently planarizing such thin layers at least back to the top surface of the upper stack 18U.

[0038] Channel material 36 is also formed perpendicularly to the insulating layers 20U / 20L and the conductive layers 22U / 22L in the channel openings 39 / 25, thus including a single effective channel material string 53 in the channel openings 39 / 25. In one embodiment, the channel material string 53 has memory cell materials (e.g., 30, 32, and 34) along it, wherein a second layer of material (e.g., 24) is horizontally located between adjacent channel material strings 53. Due to proportions, materials 30, 32, 34, and 36 are... Figure 10 and 11 The material is shown and designated as material 37 only. An exemplary channel material 36 comprises a suitably doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called group III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). Each of materials 30, 32, 34, and 36 has an exemplary thickness of 25 to 100 angstroms. A stamping etching may be performed to remove materials 30, 32, and 34 from the bottom (not shown) of the lower channel opening 25 to expose the conductor layer 16, such that the channel material 36 directly abuts the conductor material 17 of the conductor layer 16. This stamping etching may occur individually with respect to each of materials 30, 32, and 34 (as shown), or it may occur only with respect to some materials (not shown). Alternatively, and only by way of example, stamping etching may not be performed, and the channel material 36 may be directly electrically coupled to the conductor material 17 of the conductor layer 16 only through individual conductive interconnects (not shown). The channel opening 39 / 25 is shown as comprising a radially centered solid dielectric material 38 (e.g., spin-coated dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and by way of example only, the radially centered portion within the channel opening 39 / 25 may contain void spaces (not shown) and / or have no solid material (not shown).

[0039] See Figure 14 and 15 The horizontally elongated upper trench 40U has been formed into the lower trench 40L, and the sacrificial material 59 (not shown) has been removed from the lower trench (e.g., by selective etching).

[0040] refer to Figures 16 to 20Material 26 (not shown) of the conductive layer 22U / 22L has been removed, for example by theoretically selectively etching it away isotropically through trench 40U / 40L relative to other exposed materials (e.g., using liquid or vapor H3PO4 as the primary etchant, where material 26 is silicon nitride and other materials include one or more oxides or polysilicon). In the exemplary embodiment, material 26 (not shown) in the conductive layer 22U / 22L is sacrificial and has been replaced with conductive material 48, subsequently removed from trench 40U / 40L, thus forming a single conductive line 29 (e.g., word line) and a vertically extending string 49 for a single transistor and / or memory cell 56.

[0041] A thin insulating pad (e.g., Al2O3, not shown) may be formed prior to the formation of the conductive material 48. The approximate location of the transistor and / or memory cell 56 is... Figure 19 Parentheses are used to indicate this, while some are in Figures 16 to 18 In Figures 20 and 20, the transistors and / or memory cells 56 are indicated by dashed outlines, where they are substantially annular or ring-shaped in the depicted examples. Alternatively, the transistors and / or memory cells 56 may not completely surround a single channel opening 39 / 25, such that each channel opening 39 / 25 may have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells surrounding a single channel opening in a single conductive layer, where each channel opening in the single conductive layer may have multiple word lines, and not shown). The conductive material 48 can be considered to have a terminal 50 corresponding to the control-gate region 52 of the single transistor and / or memory cell 56. Figure 19 The control-gate region 52 in the depicted embodiment includes a single portion of a single conductor 29. Materials 30, 32, and 34 can be considered as memory structure 65 laterally located between the control-gate region 52 and the channel material 36. In one embodiment, and as shown with respect to the exemplary “back gate” process, conductive material 48 of the conductive layer 22U / 22L is formed after the formation of the channel openings 39 / 25 and / or the trenches 40U / 40L. Alternatively, for example with respect to the “front gate” process, the conductive material of the conductive layer may be formed before the formation of the channel openings 39 / 25 and / or the trenches 40U / 40L (not shown).

[0042] A charge-blocking region (e.g., charge-blocking material 30) lies between the storage material 32 and the individual control-gate region 52. The charge block can function in the memory cell to prevent charge carriers from escaping from the storage material (e.g., a floating gate material, a charge-trapping material, etc.) toward the control gate in programming mode, and to prevent charge carriers from flowing from the control gate into the storage material in erase mode. Therefore, the charge block can be used to block charge migration between the control gate region and the storage material of the individual memory cell. The exemplary charge-blocking region shown includes an insulating material 30. By other examples, the charge-blocking region may include the lateral (e.g., radial) exterior of the storage material (e.g., material 32), where this storage material is insulating (e.g., there is no material of different composition between the insulating storage material 32 and the conductive material 48). However, as an additional example, in the absence of any separately composed insulating material 30, the interface between the storage material and the conductive material of the control gate may be sufficient to serve as a charge-blocking region. Furthermore, the interface between the conductive material 48 and the insulating material 30 (when present) can together serve as a charge-blocking region, and alternatively or additionally, can serve as a lateral outer region of an insulating storage material (e.g., silicon nitride material 32). Example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

[0043] Intermediate material 57 is formed in trenches 40U / 40L, thereby laterally forming between directly laterally adjacent memory blocks 58 and longitudinally forming along these directly laterally adjacent memory blocks. Intermediate material 57 can provide lateral electrical isolation (insulation) between directly laterally adjacent memory blocks. This can comprise one or more of insulating, semiconductive, and conductive materials, and in any case, can facilitate short-circuiting of conductive layers 22 to each other in the finished circuit system configuration. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Intermediate material 57 can contain an array of through-holes (not shown).

[0044] In the embodiments shown and described with reference to the above embodiments, any other properties or aspects shown and / or described herein with reference to other embodiments may be used.

[0045] Figure 21 It shows the relationship with Figure 17 The exemplary alternative embodiment 10a is compared to configuration 10. The same reference numerals as those used in the above embodiment have been used where appropriate, with some construction differences indicated by the suffix "a" or different reference numerals. In configuration 10a, the intermediate layer 21a has the same thickness as the layers 22U / 22L and 20U / 20L directly above and below it. This can be achieved, for example, by modification... Figure 2Construction 10 is produced by having an intermediate layer 21a and otherwise continuing the methods described herein. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0046] While not limited thereto, some aspects of the invention are motivated by overcoming problems associated with the formation of the charge-blocking material 30 in oxide form. In some methods, the residual presence of the radially outer silicon dioxide 70 of the sacrificial material 59 in the lower channel opening 25L promotes the formation of the charge-blocking oxide material 30. Etching the sacrificial material 59 into the lower channel opening 25L previously tended to etch away much of the radially outer silicon dioxide 70, creating gaps in which the charge-blocking oxide material 30 would not form. Forming an intermediate layer 21 or 21a as described herein can reduce or eliminate such problems.

[0047] Alternative embodiments may be constructed using the method embodiments described above or other methods. In any case, embodiments of the present invention cover memory arrays independent of the manufacturing method. However, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may be combined, formed, and / or have any of the properties described with respect to the device embodiments.

[0048] In one embodiment, a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56) includes an upper stack (e.g., 18U) situated above a lower stack (e.g., 18L). The lower stack comprises vertically alternating lower conductive layers (e.g., 22L) and lower insulating layers (e.g., 20L). The upper stack comprises vertically alternating upper conductive layers (e.g., 22U) and upper insulating layers (e.g., 20U). An intermediate layer (e.g., 21 or 21a) is vertically positioned between the upper and lower stacks. This intermediate layer is at least predominantly polysilicon and has a composition different from that of the upper conductive and upper insulating layers directly above and below the intermediate layer. A string of channel material (e.g., 53) of the memory cells (e.g., 56) extends through the upper stack, the intermediate layer, and the lower stack. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0049] In one embodiment, a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56) includes an upper stack (e.g., 18U) situated above a lower stack (e.g., 18L). The lower stack comprises vertically alternating lower conductive layers (e.g., 22L) and lower insulating layers (e.g., 20L). The upper stack comprises vertically alternating upper conductive layers (e.g., 22U) and upper insulating layers (e.g., 20U). An intermediate layer (e.g., 21 or 21a) is vertically positioned between the upper and lower stacks. This intermediate layer is at least primarily conductive and has a composition different from that of the upper conductive layer directly above it, and a composition different from that of the lower conductive layer directly below it. A string (e.g., 53) of channel material for the memory cells (e.g., 56) extends through the upper stack, the intermediate layer, and the lower stack. In one embodiment, the intermediate layer is at least primarily at least one of an elemental metal, a metal alloy, a metal nitride, and a metal silicide. In another embodiment, the intermediate layer is at least primarily a conductive-doped semiconducting material.

[0050] In one embodiment, the conductive material of the intermediate layer directly abuts against the conductive material of the upper conductive layer directly above the intermediate layer, and directly abuts against the lower conductive layer directly below the intermediate layer. In such an embodiment, each of the conductive material, conductive material, and conductor material is a metallic material. And in such a subsequent embodiment, the metallic material is at least primarily at least one selected from elemental metals, metal alloys, metal nitrides, and metal silicides.

[0051] Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0052] In one embodiment, a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56) includes an upper stack (e.g., 18U) situated above a lower stack (e.g., 18L). The lower stack comprises vertically alternating lower conductive layers (e.g., 22L) and lower insulating layers (e.g., 20L). The upper stack comprises vertically alternating upper conductive layers (e.g., 22U) and upper insulating layers (e.g., 20U). An intermediate layer [e.g., 21 or 21a, regardless of whether it has any of the properties (a), (b), and / or (c)] is vertically positioned between the upper and lower stacks. A channel material string (e.g., 53) of the memory cells (e.g., 56) extends through the upper stack, the intermediate layer, and the lower stack. A portion of a single channel material string in the upper stack has an average longitudinal axis (e.g., 85°) that is angled to the average longitudinal axis (e.g., 75°) of a portion of a single channel material string in the lower stack. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0053] The aforementioned processing or construction can be considered relative to an array of components formed as two stacks or layers of such components, or formed therein or as part of an underlying substrate (although each of the two stacks / layers may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array can also be formed anywhere as part of the finished construction, and in some embodiments may be below the array (e.g., below a CMOS array). In any case, one or more additional such stacks / layers may be positioned or fabricated above and / or below what is shown in the figures or described above. Furthermore, the component arrays may be identical or different from each other in different stacks / layers, and the different stacks / layers may have the same thickness or different thicknesses. Intermediate structures may be positioned between directly vertically adjacent stacks / layers (e.g., additional circuitry and / or dielectric layers). Moreover, the different stacks / layers may be electrically coupled to each other. Multiple stacks / layers may be fabricated individually and sequentially (e.g., on top of each other), or two or more stacks / layers may be fabricated substantially simultaneously.

[0054] The components and structures discussed above can be used in integrated circuit / circuit systems and can be integrated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of a variety of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting fixtures, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0055] In this document, unless otherwise indicated, “vertical,” “higher,” “upper,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “below,” “upward,” and “downward” generally refer to a vertical direction. “Horizontal” refers to a direction approximately along the surface of the main substrate (i.e., within 10 degrees) and may be relative to which substrate is processed during manufacturing, and vertical is a direction approximately orthogonal to the horizontal. A reference to “fully horizontal” is a direction along the surface of the main substrate (i.e., without an angle to it) and may be relative to which substrate is processed during manufacturing. Furthermore, as used herein, “vertical” and “horizontal” generally refer to directions perpendicular to each other and are independent of the substrate orientation in three-dimensional space. Additionally, “vertically extending” and “vertically extending” refer to a direction at an angle of at least 45° to fully horizontal. Furthermore, regarding field-effect transistors, “vertically extending,” “vertically extending,” “horizontally extending,” “horizontally extending,” etc., refer to the orientation of the transistor's channel length along which current flows between the source / drain regions during operation. For bipolar junction transistors, "vertically extended," "vertically extended," "horizontally extended," etc., refer to the orientation of the base length along which current flows between the emitter and collector during operation. In some embodiments, any vertically extended component, feature, and / or region extends vertically or within 10° of vertical.

[0056] Furthermore, the phrases "directly above," "directly below," and "directly under" require that the two stated regions / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. Moreover, the absence of "directly" before "above" only requires that a portion of the region / material / component above another region / material / component is vertically outside the other region / material / component (i.e., regardless of whether there is any lateral overlap between the two stated regions / materials / components). Similarly, the absence of "directly" before "below" and "beneath" only requires that a portion of the region / material / component below / beneath another region / material / component is vertically inside the other region / material / component (i.e., regardless of whether there is any lateral overlap between the two stated regions / materials / components).

[0057] Any of the materials, regions, and structures described herein can be homogeneous or heterogeneous, and can be continuous or discontinuous over any material thus covered. When one or more exemplary compositions are provided for any material, the material may include, substantially consist of, or consist of such compositions. Furthermore, unless otherwise stated, each material can be formed using any suitable existing or future-developed techniques, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0058] Additionally, “thickness” itself (without a directional adjective) is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions with different compositions, passing through a given material or region. Furthermore, the various materials or regions described herein may have substantially constant or variable thicknesses. If the thickness is variable, unless otherwise indicated, the thickness refers to the average thickness, and because the thickness is variable, this material or region will have a certain minimum thickness and a certain maximum thickness. As used herein, “different compositions” only requires that the portions of two said materials or regions that can directly contact each other are chemically and / or physically different, for example, provided that such materials or regions are not homogeneous. If two said materials or regions do not directly contact each other, then “different compositions” only requires that the portions of two said materials or regions that are closest to each other are chemically and / or physically different, provided that such materials or regions are not homogeneous. In this document, a material, region, or structure is “directly contacting” another material, region, or structure when there is at least some physical contact between them. Conversely, the words “above,” “on top,” “adjacent,” “along,” and “against” are not preceded by “directly” to encompass “directly against” and constructions in which intermediate materials, areas, or structures result in no physical contact between said materials, areas, or structures.

[0059] In this paper, a region-material-component is considered "electrically coupled" relative to each other if, during normal operation, current can flow continuously from one region-material-component to another, and when sufficient subatomic positive and / or negative charges are generated, the flow is primarily through the movement of subatomic positive and / or negative charges. Another electronic component can be electrically coupled between and to that region-material-component. Conversely, when a region-material-component is referred to as "directly electrically coupled," there are no intermediate electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled regions-material-components.

[0060] Any use of the terms "row" and "column" in this document is for the convenience of distinguishing one series or orientation of features from another series or orientation of features, and along which parts have been or may be formed. "Row" and "column" are used synonymously with any series of areas, parts, and / or features unrelated to function. In any case, rows can be straight and / or curved and / or parallel and / or non-parallel to each other, just as columns are. Furthermore, rows and columns can intersect each other at 90° or at one or more other angles (i.e., other than right angles).

[0061] The composition of any of the conductive materials / conducting materials / conductive materials described herein may be metallic materials and / or conductive doped semiconducting / semiconductor / semiconductive materials. "Metallic material" means elemental metal, any mixture or alloy of two or more elemental metals, and any one or a combination of any one or more conductive metallic compounds.

[0062] In this document, any use of "selective" in relation to etch, etching, removing, removal, deposition, forming, and / or formation is an action in which said material is acted relative to another said material at a rate of at least 2:1 by volume. Furthermore, any use of selective deposition, selective growth, or selective formation is the deposition, growth, or formation of one said material relative to another said material at a rate of at least 2:1 by volume for at least the first 75 angstroms.

[0063] Unless otherwise indicated, the use of "or" in this document covers either one or both.

[0064] in conclusion

[0065] In some embodiments, a method for forming a memory array including strings of memory cells includes forming an upper stack above a lower stack. The lower stack includes vertically alternating lower first and lower second layers. The upper stack includes vertically alternating upper first and upper second layers. An intermediate layer is vertically located between the upper stack and the lower stack. A lower channel opening extends through the intermediate layer and the lower first and lower second layers. The lower channel opening contains sacrificial material in the intermediate layer and the lower first and lower second layers. The intermediate layer is at least one of (a), (b), and (c), wherein: (a) its thickness is greater than the thickness of the upper first layer and the upper second layer directly above the intermediate layer, and greater than the thickness of the lower first layer and the lower second layer directly below the intermediate layer; (b) it is at least primarily polycrystalline silicon and has a composition different from the composition of the upper first layer and the upper second layer directly above the intermediate layer, and a composition different from the composition of the lower first layer and the lower second layer directly below the intermediate layer; and (c) it is at least primarily conductive and has a composition different from the composition of the upper first layer and the upper second layer directly above the intermediate layer, and a composition different from the composition of the lower first layer and the lower second layer directly below the intermediate layer. An upper channel opening is formed through the upper first layer and the upper second layer to the intermediate layer. A single upper channel opening in the upper channel opening extends into a sacrificial material in a single lower channel opening in the lower channel opening. The sacrificial material is removed from the single lower channel opening through the upper channel opening, and then a channel material string is formed in the upper channel opening and the lower channel opening.

[0066] In some embodiments, a memory array including strings of memory cells includes an upper stack located above a lower stack. The lower stack includes vertically alternating lower conductive layers and lower insulating layers. The upper stack includes vertically alternating upper conductive layers and upper insulating layers. An intermediate layer is vertically located between the upper stack and the lower stack. The intermediate layer is at least primarily polysilicon and has a composition different from that of the upper conductive layers and upper insulating layers directly above the intermediate layer, and a composition different from that of the lower conductive layers and lower insulating layers directly below the intermediate layer. Channel material strings of memory cells extend through the upper stack, the intermediate layer, and the lower stack.

[0067] In some embodiments, a memory array including strings of memory cells includes an upper stack located above a lower stack. The lower stack includes vertically alternating lower conductive layers and lower insulating layers. The upper stack includes vertically alternating upper conductive layers and upper insulating layers. An intermediate layer is vertically located between the upper stack and the lower stack. The intermediate layer is at least primarily conductive and has a composition different from that of the upper conductive layer directly above it, and a composition different from that of the lower conductive layer directly below it. Channel material strings of memory cells extend through the upper stack, the intermediate layer, and the lower stack.

[0068] In some embodiments, a memory array including strings of memory cells includes an upper stack located above a lower stack. The lower stack includes vertically alternating lower conductive layers and lower insulating layers. The upper stack includes vertically alternating upper conductive layers and upper insulating layers. An intermediate layer is vertically located between the upper stack and the lower stack. Channel material strings of memory cells extend through the upper stack, the intermediate layer, and the lower stack. A portion of a single channel material string in the upper stack has an average longitudinal axis that is angled to the average longitudinal axis of the portion of the single channel material string in the lower stack.

[0069] In some embodiments, a memory array including strings of memory cells includes an upper stack located above a lower stack. The lower stack includes vertically alternating lower conductive layers and lower insulating layers. The upper stack includes vertically alternating upper conductive layers and upper insulating layers. An intermediate layer is vertically located between the upper stack and the lower stack. The intermediate layer is at least one of (a), (b), and (c), wherein: (a) its thickness is greater than the thickness of the upper conductive layer directly above the intermediate layer and the thickness of the upper insulating layer, and greater than the thickness of the lower conductive layer directly below the intermediate layer and the thickness of the lower insulating layer; (b) it is at least primarily polysilicon and has a composition different from the composition of the upper conductive layer and the upper insulating layer directly above the intermediate layer and a composition different from the composition of the lower conductive layer and the lower insulating layer directly below the intermediate layer; and (c) it is at least primarily conductive and has a composition different from the composition of the upper conductive layer directly above the intermediate layer and a composition different from the composition of the lower conductive layer directly below the intermediate layer; a channel material string of a memory cell extends through the upper stack, the intermediate layer, and the lower stack. A portion of a single channel material string in the upper stack has an average longitudinal axis that is angled to the average longitudinal axis of the portion of the single channel material string in the lower stack.

[0070] In accordance with regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the elements disclosed herein include exemplary embodiments. Therefore, the claims should be provided for in their full literal sense and should be properly interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array comprising strings of memory cells, comprising: An upper stack is formed above a lower stack, the lower stack comprising vertically alternating lower first and lower second layers, the upper stack comprising vertically alternating upper first and upper second layers, an intermediate layer vertically situated between the upper stack and the lower stack, a lower channel opening extending through the intermediate layer and the lower first and lower second layers, the lower channel opening containing sacrificial material in the intermediate layer and in the lower first and lower second layers, the intermediate layer being at least one of (a), (b), and (c), wherein: (a): The thickness is greater than the thickness of the upper first layer and the upper second layer directly above the intermediate layer, and greater than the thickness of the lower first layer and the lower second layer directly below the intermediate layer; (b): At least primarily polycrystalline silicon and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; and (c): At least primarily conductive, and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; An upper channel opening is formed, extending through the upper first layer and the upper second layer to the intermediate layer; a single upper channel opening in the upper channel opening extends into sacrificial material in a single lower channel opening in the lower channel opening; and The sacrificial material is removed from the single lower channel opening through the upper channel opening, and then a channel material string is formed in the upper channel opening and the lower channel opening, wherein the sacrificial material comprises radially outer silica, radially inner silica, and radial alumina between the radially outer silica and the radially inner silica.

2. The method according to claim 1, wherein the radially outer silica and the radially inner silica have different compositions from each other.

3. The method according to claim 2, wherein the different composition is characterized by the concentration of at least one of boron and phosphorus.

4. A method for forming a memory array comprising strings of memory cells, comprising: An upper stack is formed above a lower stack, the lower stack comprising vertically alternating lower first and lower second layers, the upper stack comprising vertically alternating upper first and upper second layers, an intermediate layer vertically situated between the upper stack and the lower stack, a lower channel opening extending through the intermediate layer and the lower first and lower second layers, the lower channel opening containing sacrificial material in the intermediate layer and in the lower first and lower second layers, the intermediate layer being at least one of (a), (b), and (c), wherein: (a): The thickness is greater than the thickness of the upper first layer and the upper second layer directly above the intermediate layer, and greater than the thickness of the lower first layer and the lower second layer directly below the intermediate layer; (b): At least primarily polycrystalline silicon and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; and (c): At least primarily conductive, and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; An upper channel opening is formed, extending through the upper first layer and the upper second layer to the intermediate layer; a single upper channel opening in the upper channel opening extends into sacrificial material in a single lower channel opening in the lower channel opening; and The sacrificial material is removed from the single lower channel opening through the upper channel opening, and then a channel material string is formed in the upper channel opening and the lower channel opening, wherein at least one of (a), (b) and (c) is (b).

5. A method for forming a memory array comprising strings of memory cells, comprising: An upper stack is formed above a lower stack, the lower stack comprising vertically alternating lower first and lower second layers, the upper stack comprising vertically alternating upper first and upper second layers, an intermediate layer vertically situated between the upper stack and the lower stack, a lower channel opening extending through the intermediate layer and the lower first and lower second layers, the lower channel opening containing sacrificial material in the intermediate layer and in the lower first and lower second layers, the intermediate layer being at least one of (a), (b), and (c), wherein: (a): The thickness is greater than the thickness of the upper first layer and the upper second layer directly above the intermediate layer, and greater than the thickness of the lower first layer and the lower second layer directly below the intermediate layer; (b): At least primarily polycrystalline silicon and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; and (c): At least primarily conductive, and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; An upper channel opening is formed, extending through the upper first layer and the upper second layer to the intermediate layer; a single upper channel opening in the upper channel opening extends into sacrificial material in a single lower channel opening in the lower channel opening; and The sacrificial material is removed from the single lower channel opening through the upper channel opening, and then a channel material string is formed in the upper channel opening and the lower channel opening, wherein at least one of (a), (b) and (c) is (c).

6. A method for forming a memory array comprising strings of memory cells, comprising: An upper stack is formed above a lower stack, the lower stack comprising vertically alternating lower first and lower second layers, the upper stack comprising vertically alternating upper first and upper second layers, an intermediate layer vertically situated between the upper stack and the lower stack, a lower channel opening extending through the intermediate layer and the lower first and lower second layers, the lower channel opening containing sacrificial material in the intermediate layer and in the lower first and lower second layers, the intermediate layer being at least one of (a), (b), and (c), wherein: (a): The thickness is greater than the thickness of the upper first layer and the upper second layer directly above the intermediate layer, and greater than the thickness of the lower first layer and the lower second layer directly below the intermediate layer; (b): At least primarily polycrystalline silicon and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; and (c): At least primarily conductive, and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; An upper channel opening is formed, extending through the upper first layer and the upper second layer to the intermediate layer; a single upper channel opening in the upper channel opening extends into sacrificial material in a single lower channel opening in the lower channel opening; and The sacrificial material is removed from the single lower channel opening through the upper channel opening, and then a channel material string is formed in the upper channel opening and the lower channel opening, wherein at least one of (a), (b) and (c) is at least two of (a), (b) and (c).

7. A method for forming a memory array comprising strings of memory cells, comprising: An upper stack is formed above a lower stack, the lower stack comprising vertically alternating lower first and lower second layers, the upper stack comprising vertically alternating upper first and upper second layers, an intermediate layer vertically situated between the upper stack and the lower stack, a lower channel opening extending through the intermediate layer and the lower first and lower second layers, the lower channel opening containing sacrificial material in the intermediate layer and in the lower first and lower second layers, the intermediate layer being at least one of (a), (b), and (c), wherein: (a): The thickness is greater than the thickness of the upper first layer and the upper second layer directly above the intermediate layer, and greater than the thickness of the lower first layer and the lower second layer directly below the intermediate layer; (b): At least primarily polycrystalline silicon and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; and (c): At least primarily conductive, and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; An upper channel opening is formed, extending through the upper first layer and the upper second layer to the intermediate layer; a single upper channel opening in the upper channel opening extends into sacrificial material in a single lower channel opening in the lower channel opening; and The sacrificial material is removed from the single lower channel opening through the upper channel opening, and then a channel material string is formed in the upper channel opening and the lower channel opening, wherein at least one of (a), (b) and (c) is (a), (b) and (c).

8. A method for forming a memory array comprising strings of memory cells, comprising: An upper stack is formed above a lower stack, the lower stack comprising vertically alternating lower first and lower second layers, the upper stack comprising vertically alternating upper first and upper second layers, an intermediate layer vertically situated between the upper stack and the lower stack, a lower channel opening extending through the intermediate layer and the lower first and lower second layers, the lower channel opening containing sacrificial material in the intermediate layer and in the lower first and lower second layers, the intermediate layer being at least one of (a), (b), and (c), wherein: (a): The thickness is greater than the thickness of the upper first layer and the upper second layer directly above the intermediate layer, and greater than the thickness of the lower first layer and the lower second layer directly below the intermediate layer; (b): At least primarily polycrystalline silicon and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; and (c): At least primarily conductive, and having a composition different from that of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from that of the lower first layer and the lower second layer directly below the intermediate layer; An upper channel opening is formed, extending through the upper first layer and the upper second layer to the intermediate layer; a single upper channel opening in the upper channel opening extends into sacrificial material in a single lower channel opening in the lower channel opening; and The sacrificial material is removed from the single lower channel opening through the upper channel opening, and then a channel material string is formed in the upper channel opening and the lower channel opening. The single upper channel opening is formed with an average longitudinal axis that is angled to the average longitudinal axis of the corresponding single lower channel opening to which the single upper channel opening is to be extended.

9. The method of claim 8, wherein the angle is an angle of at least 0.5° to the average longitudinal axis of its corresponding single lower channel opening.

10. The method of claim 8, wherein the angle is an angle of no more than 5.0° with respect to the average longitudinal axis of the corresponding individual lower channel opening.

11. The method of claim 8, wherein the angle is an angle of at least 1.0° to no more than 5.0° with respect to the average longitudinal axis of the corresponding single lower channel opening.

12. A memory array comprising a string of memory cells, comprising: An upper stack above a lower stack, the lower stack comprising vertically alternating lower conductive layers and lower insulating layers, the upper stack comprising vertically alternating upper conductive layers and upper insulating layers; An intermediate layer is vertically located between the upper stack and the lower stack. The intermediate layer is at least primarily polysilicon and has a composition different from that of the upper conductive layer and the upper insulating layer directly above the intermediate layer, and has a composition different from that of the lower conductive layer and the lower insulating layer directly below the intermediate layer. as well as A channel material string of a memory cell, the channel material string of the memory cell extending through the upper stack, the intermediate layer and the lower stack; A portion of a single channel material string in the upper stack has an average longitudinal axis that is at an angle to the average longitudinal axis of the portion of the single channel material string in the lower stack.

13. The memory array of claim 12, wherein the intermediate layer is at least primarily undoped polysilicon.

14. The memory array of claim 12, wherein the intermediate layer is at least primarily doped polysilicon.

15. The memory array of claim 14, wherein the intermediate layer is at least primarily semiconductively doped polysilicon.

16. The memory array of claim 14, wherein the intermediate layer is at least primarily conductive-doped polysilicon.

17. A memory array comprising a string of memory cells, comprising: An upper stack above a lower stack, the lower stack comprising vertically alternating lower conductive layers and lower insulating layers, the upper stack comprising vertically alternating upper conductive layers and upper insulating layers; An intermediate layer is vertically located between the upper stack and the lower stack, the intermediate layer being at least primarily conductive and having a composition different from that of the upper conductive layer directly above the intermediate layer, and having a composition different from that of the lower conductive layer directly below the intermediate layer; as well as A channel material string of a memory cell, the channel material string of the memory cell extending through the upper stack, the intermediate layer and the lower stack; A portion of a single channel material string in the upper stack has an average longitudinal axis that is at an angle to the average longitudinal axis of the portion of the single channel material string in the lower stack.

18. The memory array of claim 17, wherein the intermediate layer is at least primarily selected from elemental metals, metal alloys, metal nitrides, and metal silicides.

19. The memory array of claim 17, wherein the intermediate layer is at least primarily a conductive-doped semiconducting material.

20. The memory array of claim 17, wherein the conductive material of the intermediate layer directly abuts against the conductive material of the upper conductive layer directly above the intermediate layer, and directly abuts against the lower conductive layer directly below the intermediate layer.

21. The memory array of claim 20, wherein each of the conductive material, the conductive material, and the lower conductor layer is a metallic material.

22. The memory array of claim 21, wherein the metallic material is at least one of elemental metals, metal alloys, metal nitrides and metal silicides.

23. The memory array of claim 20, wherein each of the conductive material and the lower conductor layer is a metallic material, and the conductive material is a conductive-doped semiconducting material.

24. A memory array comprising a string of memory cells, comprising: An upper stack above a lower stack, the lower stack comprising vertically alternating lower conductive layers and lower insulating layers, the upper stack comprising vertically alternating upper conductive layers and upper insulating layers; An intermediate layer, which is vertically located between the upper stack and the lower stack; as well as A channel material string of a memory cell, the channel material string of the memory cell extending through the upper stack, the intermediate layer and the lower stack; A portion of a single channel material string in the upper stack has an average longitudinal axis that is at an angle to the average longitudinal axis of the portion of the single channel material string in the lower stack.

25. The memory array of claim 24, wherein the angle is an angle of at least 0.5° with respect to the average longitudinal axis of the portion of the single channel material string in the lower stack.

26. The memory array of claim 24, wherein the angle is an angle of no more than 5.0° with respect to the average longitudinal axis of the portion of the individual channel material string in the lower stack.

27. The memory array of claim 24, wherein the angle is an angle of at least 1.0° to no more than 5.0° with respect to the average longitudinal axis of the portion of the individual channel material string in the lower stack.

28. A memory array comprising a string of memory cells, comprising: An upper stack above a lower stack, the lower stack comprising vertically alternating lower conductive layers and lower insulating layers, the upper stack comprising vertically alternating upper conductive layers and upper insulating layers; A vertical intermediate layer located between the upper stack and the lower stack, wherein the intermediate layer is at least one of (a), (b), and (c), wherein: (a): The thickness is greater than the thickness of the upper conductive layer directly above the intermediate layer and the thickness of the upper insulating layer, and is also greater than the thickness of the lower conductive layer directly below the intermediate layer and the thickness of the lower insulating layer; (b): At least primarily polycrystalline silicon and having a composition different from that of the upper conductive layer and the upper insulating layer directly above the intermediate layer, and a composition different from that of the lower conductive layer and the lower insulating layer directly below the intermediate layer; and (c): At least primarily conductive, and having a composition different from that of the upper conductive layer directly above the intermediate layer, and having a composition different from that of the lower conductive layer directly below the intermediate layer; and A channel material string of memory cells extending through the upper stack, the intermediate layer, and the lower stack; a portion of a single channel material string in the upper stack has an average longitudinal axis that is angled to the average longitudinal axis of the portion of the single channel material string in the lower stack.

29. The memory array according to claim 28, wherein it is (a).

30. The memory array according to claim 28, wherein it is (b).

31. The memory array according to claim 28, wherein it is (c).

32. The memory array according to claim 28, wherein at least two of (a), (b) and (c) are included.

33. The memory array according to claim 28, wherein it is (a), (b) and (c).

34. The memory array of claim 28, wherein the angle is an angle of at least 0.5° with respect to the average longitudinal axis of the portion of the individual channel material string in the lower stack.

35. The memory array of claim 28, wherein the angle is an angle of no more than 5.0° with respect to the average longitudinal axis of the portion of the individual channel material string in the lower stack.

36. The memory array of claim 28, wherein the angle is an angle of at least 1.0° to no more than 5.0° with respect to the average longitudinal axis of the portion of the single channel material string in the lower stack.

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