Display structure of double-gate driving device and display device

Abstract

The display structure of the double-gate driving device comprises a substrate, a thin film transistor, an insulating layer and a passivation layer, and a plurality of pixel areas formed in sequence; a gate line for transmitting a display signal, two gate lines penetrating each pixel area; two thin film transistors arranged in each pixel area are arranged on both sides of a first space formed by the two gate lines. The two thin film transistors in each pixel area are arranged on both sides of the first space formed by the two gate lines, so as to solve the problems that the display screen flickering risk and the crosstalk probability of the display device in the prior art are relatively high, that is, the storage capacitance of the display structure is increased, and the display screen flickering risk and the crosstalk probability are reduced.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display structure and display device for a dual-gate driving device. Background Technology

[0002] In the display field, the demand for high-definition and ultra-high-definition displays is increasing, meaning the need for small-sized, high-PPI electronic devices is growing daily. PPI (Pixels Per Inch) is a unit of image resolution, representing the number of pixels per inch. A higher PPI value means the display device can show images at a higher density; higher density results in higher image fidelity and a more realistic display.

[0003] However, high PPI means that the pixels of small-sized products are also getting smaller and smaller, and the design space is often very limited. Current technology cannot reduce the thickness of the passivation layer in terms of process, which makes the display screen of the display device more prone to flicker and crosstalk. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is to provide a display structure and display device for a dual-gate driving device, which can solve the problems of high risk of screen flicker and high probability of crosstalk in conventional display devices.

[0005] In a first aspect, this disclosure provides a display structure for a dual-gate driving device, comprising:

[0006] Substrate, thin-film transistor, and gate line;

[0007] The grid lines are used to transmit display signals, and two grid lines pass through each pixel area included in the display structure.

[0008] The two thin-film transistors disposed within each pixel region are respectively located on both sides of the first space formed by the two gate lines.

[0009] In one possible implementation, the gate line is connected to the gate of the thin-film transistor.

[0010] In one possible implementation, the thin-film transistor is located in the corner region of the pixel region.

[0011] In one possible implementation, it also includes:

[0012] Insulating layer and passivation layer;

[0013] Pixel electrode disposed between the insulating layer and the passivation layer;

[0014] A common electrode is disposed on the passivation layer.

[0015] In one possible implementation, the pixel region includes a pixel electrode and a common electrode, wherein the projection of the center line of the common electrode onto the substrate coincides with the projection of the center line of the pixel electrode onto the substrate.

[0016] In one possible implementation, the width of the common electrode is 4.5 μm.

[0017] In one possible implementation, the spacing between two adjacent common electrodes is 5 μm.

[0018] In one possible implementation, the width of the pixel electrode is greater than the width of the common electrode, and the width difference between the pixel electrode and the common electrode is greater than or equal to 5.8 μm.

[0019] In one possible implementation, the width of the gate line is greater than or equal to 3.5 μm, and the vertical distance between two gate lines is greater than or equal to 5.2 μm.

[0020] Secondly, this disclosure also provides a display device for a dual-gate driving product, comprising:

[0021] The display structure described in any of the embodiments of the first aspect above.

[0022] This embodiment of the present disclosure solves the problem of high risk of screen flicker and high probability of crosstalk in conventional display devices by distributing two film transistors in each pixel region on both sides of the first space formed by two gate lines. In other words, it increases the storage capacitance of the display structure and reduces the risk of screen flicker and the probability of crosstalk.

[0023] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram of a display structure in the prior art is shown;

[0026] Figure 2A schematic diagram of a display structure of a dual-gate driving device provided in an embodiment of this disclosure is shown;

[0027] Figure 3 This diagram illustrates a pixel region in a display structure of a dual-gate driving device according to an embodiment of the present disclosure;

[0028] Figure 4 This illustration shows a schematic diagram of a pixel region in the display structure of another dual-gate driving device provided in an embodiment of the present disclosure;

[0029] Figure 5 A schematic diagram of another display structure of a dual-gate driving device provided in an embodiment of this disclosure is shown;

[0030] Figure 6 A cross-sectional view of a display structure of a dual-gate driving device provided in an embodiment of this disclosure is shown.

[0031] Figure label:

[0032] 1-Substrate; 2-Thin film transistor; 3-Gate line; 4-Pixel electrode; 5-Common electrode. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0035] To keep the following description of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0036] The first aspect of this disclosure provides a display structure for a dual-gate driving device, wherein, for a conventional 6-mask or 7-mask (6-mask+GI) high-PPI dual-gate device, the film structure from bottom to top comprises a gate line 3, an insulating layer, a semiconductor material layer, a source / drain layer, a pixel electrode 4, a passivation layer, and a common electrode 5, and, referring to... Figure 1 As shown in the schematic diagram of the prior art display structure, the thin-film transistor 2 in each pixel region is located between two gate lines 3. However, for high PPI (above 350) small-size dual-gate driving devices, the overlap area between the pixel electrode 4 and the common electrode 5 is relatively limited, and the thickness of the insulating layer between the pixel electrode 4 and the common electrode 5 cannot be reduced in the manufacturing process. This makes the storage capacitance of the display structure insufficient to meet display requirements, thus affecting the voltage of the dual-gate driving device and the stability of the display. In other words, it leads to a higher risk of screen flicker and a higher probability of crosstalk. The storage capacitance is the capacitance formed by the pixel electrode 4 and the common electrode 5. Therefore, in this embodiment, the two thin-film transistors in each pixel region are respectively disposed on both sides of the first space formed by the two gate lines 3 to solve the problem of high screen flicker risk and crosstalk probability in conventional technologies. This increases the storage capacitance of the display structure and reduces the risk of screen flicker and the probability of crosstalk.

[0037] Reference Figure 2 The schematic diagram of the display structure shown includes a substrate 1, thin-film transistors 2, and gate lines 3. The gate lines 3 are used to transmit display signals. Preferably, both ends of the two gate lines 3 are connected to opposite ends of the display structure, thus the two gate lines 3 penetrate each pixel area included in the display structure. It is worth noting that the two gate lines 3 refer to a row or column of pixel areas. If the display structure includes multiple rows or columns of pixel areas, each row or column of pixel areas corresponds to two gate lines 3, and the two gate lines 3 penetrate each pixel area in their corresponding row or column. Furthermore, the gate lines 3 are connected to the gate of the thin-film transistors 2 so that the gate lines 3 can transmit display signals to the thin-film transistors 2, enabling each thin-film transistor 2 to display according to display requirements.

[0038] Furthermore, referring to Figure 3 As shown in the schematic diagram of the display structure, the two thin-film transistors 2 disposed within each pixel region are respectively positioned on either side of the first space formed by the two gate lines 3. Furthermore, the width of the gate line 3 is greater than or equal to 3.5 μm, and the distance between the two gate lines 3 is greater than or equal to 5.2 μm. Figure 3In this context, b and d represent the dimensions of the thin-film transistor 2-gate line 3 pedestal, and X is the pixel size. Of course, those skilled in the art should understand that the width of the gate line 3 and the distance between two gate lines 3 are just one embodiment, and specific parameters can be adjusted according to actual needs.

[0039] Here, the distributed design of the thin-film transistor 2 described in this disclosure can increase the design area b(Xd)um2 compared to existing designs in the prior art.

[0040] In practical product applications, considering factors such as overlapping capacitance, CD, and the relative positional relationship between the pixel electrode 4 and the common electrode 5, reference can also be made to... Figure 4 The schematic diagram of the display structure shows the arrangement of the thin-film transistors 2, that is, the thin-film transistors 2 are located in the corner areas of the pixel region. For example, in the case of a rectangular pixel region, the thin-film transistors 2 can be placed at any of the upper left, lower left, upper right, and lower right corners of the pixel region, as long as the gate of the thin-film transistor 2 can be connected to the gate line 3. At this time, the two thin-film transistors 2 are 180° rotationally symmetrical along the metal line, which greatly increases the pixel design space. Sufficient space is reserved next to the drain of the thin-film transistors 2 to increase the area of ​​the pixel electrode 4. Compared with the conventional design, the display structure provided by this disclosure increases the storage capacitance by 9.6%, which can effectively ensure that the voltage of the pixel region remains stable, thereby reducing the risk of display flicker and the probability of crosstalk.

[0041] Furthermore, the display structure of the dual-gate driving device also includes an insulating layer (GI) and a passivation layer (PVX), a pixel electrode 4 (1TO) disposed between the insulating layer and the passivation layer, and a common electrode 5 (2TO) disposed on the passivation layer. Since the embodiments of this disclosure are designed for small-size, high-PPI dual-gate devices, meaning that the pixel area size of its display structure is relatively small, specifically less than or equal to 24.5µm, a large number of common electrodes 5 cannot be placed within the pixel area. Therefore, referring to… Figure 5 The schematic diagram of the structure within the pixel region shown in this embodiment of the present disclosure is provided with a pixel electrode 4 and a common electrode 5 within the pixel region. The projection of the center line of the common electrode 5 onto the substrate 1 coincides with the projection of the center line of the pixel electrode 4 onto the substrate 1, and the width of the common electrode 5 is increased.

[0042] and, Figure 6 It shows the basis Figure 2The cross-sectional view of the display structure obtained in the AA' direction, as shown in the cross-sectional view of the display structure shown in Figure 6, shows that in this embodiment, the width of the common electrode 5 is 4.5 μm, and the interval between two adjacent common electrodes 5 is 5 μm. Therefore, the width of the common electrode 5 and the interval between two adjacent common electrodes 5 are 4.5 / 5.0. Under the premise of satisfying the light efficiency and pixel transmittance, the storage capacitance is maximized. Compared with the storage capacitance corresponding to the width of the conventional common electrode 5 of 2.7 μm, its capacity is increased by 38%, thereby effectively reducing the risk of display screen flicker and the probability of crosstalk.

[0043] Continue to refer to Figure 6 In the pixel area design, to reduce the probability of crosstalk, it is necessary to minimize the pulling effect of the display signal on the pixel area. Therefore, the minimum distance between the pixel electrode 4 and the signal line is 4.5µm. Furthermore, considering the risk of connection line breakage during the manufacturing process if the width of the connection lines in the display structure is small, the width of the signal line is set to be greater than or equal to 2.8µm to avoid connection line breakage, and it is connected to the source of the thin-film transistor 2. Simultaneously, in this embodiment, the width of the common voltage line is set to be greater than or equal to 2.6µm. Under this scheme, the pixel size in the display structure is 23.6µm, the pixel area of ​​the dual-gate driving device is small, and the PPI is high.

[0044] An electric field is formed between the pixel electrode 4 and the common electrode 5. When the distance between the pixel electrode 4 and the common electrode 5 is small, not only does the light efficiency decrease, but local stains are also generated on the display device to which the display structure belongs. Therefore, when setting the positional relationship between the pixel electrode 4 and the common electrode 5, it is not only necessary that the projection of the center line of the common electrode 5 on the substrate 1 coincides with the projection of the center line of the pixel electrode 4 on the substrate 1, but also that the projection width of the pixel electrode 4 on the substrate 1 is greater than the projection width of the common electrode 5 on the substrate 1, and the minimum width difference is 5.8 μm. That is to say, the minimum width of the pixel electrode 4 and the width of the common electrode 5 are 5.8 μm. (Refer to...) Figure 6 In this scheme, the width difference between the pixel electrode 4 and the common electrode 5 is 7.90um, that is, the side of the projection of the pixel electrode 4 on the substrate 1 extends 3.95um beyond the side of the projection of the common electrode 5 on the substrate 1.

[0045] This embodiment of the present disclosure solves the problem of high risk of screen flicker and high probability of crosstalk in conventional display devices by distributing two film transistors in each pixel region on both sides of the first space formed by two gate lines. In other words, it increases the storage capacitance of the display structure and reduces the risk of screen flicker and the probability of crosstalk.

[0046] Secondly, embodiments of this disclosure provide a display device for a dual-gate driving product, which includes the display structure provided in the first aspect.

[0047] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0048] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0049] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0050] The foregoing has provided a detailed description of several embodiments of this disclosure. However, this disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications based on the concept of this disclosure, and all such variations and modifications should fall within the scope of protection claimed by this disclosure.

Claims

1. A display structure for a dual-grid driving device, characterized in that, include: A substrate, a thin-film transistor, and a gate line; the thin-film transistor includes a gate, a source, and a drain, and the gate is connected to the gate line. The grid lines are used to transmit display signals, and two grid lines pass through each pixel area included in the display structure. Data line and Vcom line, the Data line and Vcom line are designed on the same layer, the Data line is connected to the source, and a pixel electrode is disposed between the drain and the Vcom line; The pixel electrode and the data line are disposed on the same layer; Two thin-film transistors are disposed in each pixel region and are respectively disposed on both sides of the first space formed by the two gate lines. The two thin-film transistors are 180° rotationally symmetrical along the metal line, and the two gate lines are arranged parallel to each other on the same horizontal plane. Insulating layer and passivation layer; The pixel electrode is disposed between the insulating layer and the passivation layer; A common electrode is disposed on the passivation layer; Wherein, the projection of the center line of the common electrode onto the substrate coincides with the projection of the center line of the pixel electrode onto the substrate; The Vcom line and the Data line are arranged adjacent to each other. The Vcom line includes a widened portion, and the Vcom lines connected to both ends of the widened portion are arranged alternately. In the direction perpendicular to the substrate, the widened portion overlaps with the two gate lines between two adjacent rows of pixel electrodes.

2. The display structure according to claim 1, characterized in that, The gate line is connected to the gate of the thin-film transistor.

3. The display structure according to claim 1, characterized in that, The thin-film transistor is located in the corner area of ​​the pixel region.

4. The display structure according to claim 1, characterized in that, The pixel region includes a pixel electrode and a common electrode, and the projection of the center line of the common electrode onto the substrate coincides with the projection of the center line of the pixel electrode onto the substrate.

5. The display structure according to claim 1, characterized in that, The width of the common electrode is 4.5 μm.

6. The display structure according to claim 1, characterized in that, The interval between two adjacent common electrodes is 5 μm.

7. The display structure according to claim 1, characterized in that, The width of the pixel electrode is greater than the width of the common electrode, and the width difference between the pixel electrode and the common electrode is greater than or equal to 5.8 μm.

8. The display structure according to claim 1, characterized in that, The width of the gate line is greater than or equal to 3.5 μm, and the vertical distance between two gate lines is greater than or equal to 5.2 μm.

9. A display device for a dual-gate driving product, characterized in that, Includes the display structure as described in any one of claims 1 to 8.

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