Analog FIR filter

Abstract

Analog FIR filter. An FIR filter (15) includes an input terminal for receiving an input signal, a first filter circuit including: a first transconductance device (30a) configured to generate a first current signal (i1) proportional to the input signal; a first analog switch (41a) commutated in n by a first digital gate signal (φ1) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor (45a) when the first digital gate signal has a second value; characterized in that the first digital gate signal (φ1) includes a periodic series of pulses, wherein the pulses have a width proportional to the filter coefficients.

Description

Technical Field

[0001] In embodiments, the present invention relates to programmable analog FIR filters that can be applied to many signal processing tasks. An important, but not limited, use case of the filters of the present invention is a low-pass filter for channel selection in a wireless receiver. Background Technology

[0002] Analog filters with various topologies are known in the art. Typically, operational amplifiers or gm-C transconductance amplifiers are used to design analog filters. However, these topologies require multiple gain stages to create higher-order filters.

[0003] Electronic filters are used in many signal processing applications. Modern RF receivers and transmitters rely heavily on electronic filters, which include, but are not limited to, low-pass filters for channel selection. RF devices targeting IoT applications must provide a sufficient signal-to-noise ratio for minimal power consumption, and channel filters are a crucial component in this optimization. Conventional filters based on multiple gain stages struggle to meet this goal.

[0004] IEEE Solid-State Circuits Letters The paper "A 0.06–3.4-MHz 92-μW Analog FIR Channel Selection Filter With Very Sharp Transition Band for IoT Receivers" by BJ Thijssen, EAM Klumperink, P. Quinlan, and B. Nauta, published in vol. 2, no. 9, pp. 171–174, September 2019, doi:10.1109 / LSSC.2019.2935569, proposes an architecture that combines strong filtering and low power consumption with a single variable gain stage whose transconductance can be digitally set. While limiting the number of gain stages, this architecture increases the complexity of the receiver.

[0005] JPH04284714A discloses an FIR filter with variable coefficients for audio processing, and US2010 / 17151548A1 discloses an analog FIR filter. Summary of the Invention

[0006] The purpose of this invention is to provide a filter that overcomes the shortcomings and limitations of the prior art.

[0007] According to the invention, these objectives are achieved by the subject matter of the appended claims, and in particular by an FIR filter comprising an input terminal for receiving an input signal, a first filter circuit comprising: a first integrating capacitor; a first transconductance device configured to generate a first current signal proportional to the input signal; a first analog switch commutated by a first digital gate signal and configured to block the current signal when the first digital gate signal has a first value and to transmit the first current signal to the first integrating capacitor when the first digital gate signal has a second value; wherein the first digital gate signal comprises a periodic series of pulses, wherein the pulses have a width proportional to the set of coefficients of the FIR filter.

[0008] The dependent claims relate to important and advantageous but not essential variations of the invention, such as a gate generator comprising a memory storing filter coefficients and a digital time converter, wherein the filter coefficients are read from the memory and provided sequentially and synchronously with a clock signal to the digital time converter, and the digital time converter generates pulses with a width proportional to each received filter coefficient; a reset switch for a first integrating capacitor such that the charge stored therein is periodically transferred to an output unit and reset; a second transconductance device configured to generate a second current signal proportional to an inverted-phase copy of the input signal; a second analog switch controlled by a second digital gate signal and configured to block the second current signal when the second digital gate signal has a first value and to transmit the second current signal to the first integrating capacitor when the second digital gate signal has a second value; wherein the second gate signal comprises a series of pulses of constant width; and a second digital time converter whose input is static to generate the second gate signal.

[0009] In an advantageous variant, the FIR filter of the present invention has a plurality of integrating capacitors and a plurality of analog switches, the plurality of analog switches being controlled by digital signals and configured to cyclically select integrating capacitors from the plurality of integrating capacitors, blocking a current signal when a first digital gate signal has a first value and transmitting a first current signal to the selected integrating capacitor when the first digital gate signal has a second value, blocking a second current signal when a second digital gate signal has a first value and transmitting a second current signal to the selected integrating capacitor when the second digital gate signal has a second value.

[0010] This disposition of many integrating capacitors simplifies the periodic resetting of the integrating capacitors, which can be conveniently short-circuited during their inactive periods. The number of integrating capacitors can be more than two to increase the sampling rate of the output signal. For example, in a filter with four interleaved integrating capacitors, the sampling rate of the output signal can be doubled. If the number of integrators equals the number of coefficients in the FIR filter, the output rate can be made equal to the clock rate.

[0011] Within the framework of this disclosure, the term "digital" is used in electronics to specify systems that operate on discrete, quantized values, in contrast to "analog" systems that operate on continuously variable values. The device of the present invention falls into this definition of analog circuitry because it filters continuously variable voltages and produces unquantized, continuously filtered outputs, although the filter coefficients can be quantized and stored in digital memory, and the circuit operates in discrete steps of time. Attached Figure Description

[0012] Exemplary embodiments of the present invention are disclosed in the specification and illustrated in the accompanying drawings, in which:

[0013] Figure 1 A filter according to the present invention is illustrated schematically.

[0014] Figure 1a A variant of the invention with two filter chains is shown, one receiving a positive signal and the other receiving a complementary negative signal.

[0015] Figure 2a and 2b A variant of the invention with two multiplexed filters is shown.

[0016] Figure 3 It is drawing Figure 2a and 2b The chronogram of signals in the filter, including the time sequence signal ϕ 11 ϕ 21 ϕ 12 ϕ 22 ϕ 2r ϕ 2s ϕ 1r ϕ 1s ,drive Figure 2a The corresponding switch name.

[0017] Figure 4 The transfer functions of two filters according to the present invention are plotted and compared with those of similar digital filters. Detailed Implementation

[0018] refer to Figure 1 The filter 15 of the present invention includes an input terminal 12a, which receives the signal V to be filtered. in This is then provided to the input of transconductance node 30a to generate a circuit I1 (I1 = G) that is sensibly proportional to the input signal level. m ⋅V in The transconductance node 30a can be implemented using any of the many circuits used in the art to provide a fixed gain G. m Transconductance.

[0019] An N-tap FIR filter consists of N real coefficients α1, ..., α2. n Defined and can be mathematically represented in the z-domain by the following formula:

[0020] .

[0021] FIR coefficients α0, ..., α n-1 The clock signals are stored in memory 23 and are cyclically read from memory 23 at each cycle of the clock signal clk. In the presented example, the clock signal has a frequency of 50 MHz, but this value can be changed depending on the application. The coefficient α... n The digital value is provided as input to the digital time converter 25a, which generates a gate signal ϕ1 consisting of a series of pulses, one for each cycle of the clock clk, with a width equal to the coefficient α. n The value of one is proportional. Since memory 23 is read cyclically, the gate signal ϕ1 is periodic and in T s,out = N⋅T s It repeats itself after a period of time, where T s N is the period of the clock signal and N is the number of taps.

[0022] In the example shown, the data fed from the memory to the DTC has a depth of 10 bits, but the invention can be applied to coefficients represented by digital words of any size.

[0023] Switch 41a uses gate signal ϕ1 to switch current I1, and gate signal ϕ1 sets the coefficient α. n The encoding is pulse width, which makes the integrating capacitor C int Receive with V at each pulse in ⋅G m ⋅α n ⋅T s Proportional charge. During period T s,out At the end, C intThe accumulated charge will be proportional to the desired filtered output and can be transferred to the output terminal V by temporarily closing switch 43a. out Then, use switch 47a to reset the integrating capacitor 45a to zero and repeat the cycle.

[0024] Therefore, the existing signal V out It is the frequency f s / N of the sampled output, where f s Let f represent the clock frequency, and N represent the number of taps in the filter. In other words, the output signal is relative to the clock frequency f. s Decimated to 1 / N. For example, to implement a channel filter in a digital receiver, the circuitry of this invention can be used to synthesize a low-pass filter with a corner frequency of several MHz or lower. This can be achieved with a 25-tap FIR filter, by which, if f s = 50 MHz, then the output will be sampled at 2 MHz.

[0025] The digital time converter 25a can be implemented in various ways using a counter, a variable slope integrator, a constant slope integrator, or other suitable devices. Due to the non-zero rise and fall times of the DTC output, the DTC output for α... n The low value may not be accurate enough (for short pulses, the duty cycle becomes comparable to the rise and fall times of the DTC). This can lead to deviations from the desired transfer function and reduced attenuation in the stop band.

[0026] To mitigate this problem, use, for example Figure 1a The two filter chains shown are advantageous, one receiving the positive signal +V. in / 2, and another receives a complementary negative signal -V in / 2. The first and second filter chains have two ideally identical transconductance nodes 30a or (respectively) 30b, whose outputs are switched by S. 11 and S 22 The wave is chopped and integrated in capacitor 45a.

[0027] In the diagram, one of the switches S connected to the positive input in the upper chain is... 11 The gate signal ϕ is the coefficient of the coding filter. 11 Drivers, such as Figure 1 As shown, but with an intentionally inserted offset D min1 ,like Figure 2b As can be seen in the image. Another switch S in this case... 12 From the gate signal ϕ 12 Driver, gate signal ϕ12 From width D min2 The same pulse composition. The second gate signal can be generated via the second DTC 25b or by any other means. This process completely avoids very short pulses and errors caused by finite rise and fall times. By tuning D... min1 and D min2 The value of can avoid any additional adverse effects that may occur due to mismatches between paths.

[0028] Figure 2a and 2b A variation of the invention is shown, wherein the outputs of transconductance amplifiers 30a and 30b are presented to two integrators arranged in parallel. In the first filter, the currents I1 and I2 generated by the transconductance amplifiers are integrated in capacitor 45a after being chopped by switches 14a (S11) and 42a (S12). In the second filter, the same currents I1 and I2 are integrated through switch 41b (S12). 22 ) and 42b (S 21 The integral is made in capacitor 45b. Each filter has an independent reset switch 47a (S). 1s ) or (respectively) 47b (S 2s ) and transfer switch 43a (S 1r ) or (respectively) 43b (S 2r It should be understood that the two filters are electrically related. Figure 1a The filters are the same.

[0029] The two filters operate in a time-interleaved mode, in each cycle T s,out Then the roles are reversed. In the first cycle, if the length is T... s,out The voltage is integrated, for example, in capacitor 45a, and in a continuous period of the same length, the voltage will be integrated in capacitor 45b, while each integration of capacitor 45a is reset by the integrated voltage on switch 47a and capacitor Cint1 (2). The capacitor needs to be reset to avoid peaking in the filter response due to the IIR (infinite impulse response) effect. Figure 3 The timing diagram shows the corresponding signals that may be implemented.

[0030] The transfer function of the proposed filter with Gm1=Gm2, Dmin1=Dmin2, and Cint1=Cint2 can be expressed as given by the following equation:

[0031] .

[0032] Bandwidth is inversely proportional to the number of taps N and to the clock rate f s Proportional. Time interleaving offers a further advantage: decoupling the relationship between the output sampling rate and bandwidth. By increasing the number of parallel filters to four, for example, the output signal can have a decimation factor of N / 2 instead of N. Other decimation ratios can be obtained by increasing the number of interleaved parallel filters. N interleaved filters can be used to suppress decimation and have a decimation ratio proportional to the clock rate f. s The output signal is sampled at the same frequency.

[0033] To improve aliasing performance, a low-pass filter can be placed before the proposed filter, such as an RC filter in the continuous time domain or a discrete-time filter such as a windowed integral (integration time of Ts) sampler.

[0034] Figure 4 The analog transfer functions (solid lines) of the filter of the present invention in 25-tap and 50-tap implementations are shown. The dashed lines plot the ideal transfer function obtained from the above equations, and the dotted lines show the ideal output of the digital FIR filter with the same coefficients for comparison.

Claims

1. An FIR filter, comprising: - Input terminals used to receive input signals. - The first filter circuit includes: - First integrating capacitor - A first transconductance device is configured to generate a first current signal proportional to the input signal; - Gate generator; - A first analog switch is commutated by a first digital gate signal from a gate generator and configured to block a current signal when the first digital gate signal has a first value and to transmit the first current signal to a first integrating capacitor when the first digital gate signal has a second value. in The first digital gate signal consists of a periodic series of pulses, wherein the pulses have a width proportional to the set of coefficients of the FIR filter. The gate generator includes: - Memory for storing filter coefficients, and - Digital time converter The filter coefficients are read from memory and provided sequentially and synchronously with the clock signal to the digital time converter, which generates a pulse with a width proportional to the received filter coefficient.

2. The FIR filter according to claim 1, wherein, The first integrating capacitor is periodically reset.

3. The FIR filter according to claim 1, wherein the charge stored in the first integrating capacitor is periodically transferred to the output unit.

4. The FIR filter according to claim 1, comprising a second filtering circuit, including: The second transconducting device is configured to generate a second current signal that is proportional to an inverted copy of the input signal; The second analog switch is controlled by a second digital gate signal and configured to block the second current signal when the second digital gate signal has a first value and to transmit the second current signal to the first integrating capacitor when the second digital gate signal has a second value; wherein the second gate signal comprises a series of pulses of constant width.

5. The FIR filter according to claim 3, wherein, The second digital gate signal is generated by the second digital time converter, and the input of the second digital time converter is static.

6. The FIR filter according to claim 3, comprising a second integrating capacitor, a third analog switch and a fourth analog switch, controlled by digital signals and configured to transfer the first current signal and the second current signal to the first and second integrating capacitors in an interleaved manner.

7. The FIR filter of claim 3, comprising a plurality of integrating capacitors and a plurality of analog switches, the plurality of analog switches being controlled by digital signals and configured to cyclically select integrating capacitors from the plurality of integrating capacitors, blocking a current signal when a first digital gate signal has a first value and transmitting a first current signal to the selected integrating capacitor when the first digital gate signal has a second value, blocking a second current signal when a second digital gate signal has a first value and transmitting a second current signal to the selected integrating capacitor when the second digital gate signal has a second value.

8. The FIR filter according to claim 7, having two alternatingly charged integrating capacitors.

9. The FIR filter of claim 7, wherein the charge stored in the integrating capacitor is cyclically transferred to the output circuit and the sampled output signal is determined.

10. The FIR filter of claim 9, having a gate generator, including a memory storing filter coefficients and a digital time converter, wherein the filter coefficients are read from the memory and provided to the digital time converter sequentially and synchronously with a clock signal, and the digital time converter generates a pulse having a width proportional to the received filter coefficient, wherein the sampled output signal is decimated relative to the clock signal.

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