Apparatus and method for controlling skimming rate

Abstract

An apparatus can include a refresh control circuit having a plurality of timing circuits. The timing circuits can be used to control a steal rate, e.g., a rate of refresh slots dedicated to fixing victim word lines that are hammered by a row hammer. The timing circuits can be controlled to allow the steal rate to be independently adjusted for different victim word lines. Thus, different victim word lines can be refreshed at different rates, and the different rates can be independent of one another.

Description

Background Technology

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor memory devices. More specifically, this disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Information may be stored as physical signals (e.g., charge on a capacitive element) in individual memory cells. The memory may be volatile, and the physical signals may decay over time (which may degrade or destroy the information stored in the memory cells). It may be necessary to periodically refresh the information in the memory cells by, for example, rewriting the information to restore the physical signals to their initial values.

[0002] As the size of memory devices decreases, the density of memory cells increases significantly. Typically, memory cells are arranged in arrays containing a series of rows called word lines and columns called bit lines. Automatic refresh operations are performed, where memory cells with one or more word lines are periodically refreshed to retain the data stored in the memory cells. Repeated access to a specific memory cell or group of memory cells, such as a word line, can increase the rate of data degradation in nearby memory cells (e.g., adjacent word lines). This repeated access is often referred to as 'row hammer'. To retain data in nearby memory cells, the word lines of nearby memory cells may need to be refreshed at a rate higher than that of the automatic refresh operation. However, additional refresh operations increase power consumption and may interfere with other memory operations. Therefore, it is necessary to reduce additional refresh operations. Summary of the Invention

[0003] The apparatus and methods described herein allow for independent control of the theft rate for different victim word lines, such as victim word lines located at different physical distances from the attacker word line. In some embodiments, the refresh control circuitry may include two or more timing circuits to allow for independent control of the theft rate for different victim word lines. This allows for optimization of the target refresh rate for each type of victim word line, which can reduce over-refreshing of the word line.

[0004] According to at least one embodiment of the present disclosure, the device may include refresh control circuitry comprising: a first victim theft rate timing circuitry configured to provide a first signal at a first frequency, wherein the first frequency indicates the rate at which a first victim word line is refreshed; and a second victim theft rate timing circuitry configured to provide a second signal at a second frequency, wherein the second frequency indicates the rate at which a second victim word line is refreshed, wherein the first frequency and the second frequency are independent of each other.

[0005] According to at least one embodiment of this disclosure, the device may include a memory array; row control circuitry coupled to the memory array; a first timing circuitry configured to provide a first signal at a first frequency; a second timing circuitry configured to provide a second signal at a second frequency, wherein the second frequency is independent of the first frequency; and a target refresh address controller circuitry configured to provide a first type of victim row address at the first frequency and a second type of victim row address at the second frequency, wherein the first type and the second type of victim row addresses are provided to the row control circuitry for performing a refresh operation on victim word lines in the memory array corresponding to the first type and the second type of victim row addresses.

[0006] According to at least one embodiment of this disclosure, a method may include: providing a first signal having a first frequency; providing a second signal having a second frequency, wherein the second frequency is independent of the first frequency; refreshing a first victim word line at least partially based on the first frequency; and refreshing a second victim word line at least partially based on the second frequency. Attached Figure Description

[0007] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 This is a block diagram of a refresh control circuit according to an embodiment of the present disclosure.

[0009] Figure 3 This is a circuit diagram of an example target refresh address controller circuit according to an embodiment of the present disclosure.

[0010] Figure 4 This is an example timing diagram of a refresh signal, a first timing signal, and a second timing signal according to an embodiment of the present disclosure.

[0011] Figure 5 This is an example of an infringer detection circuit according to an embodiment of the present disclosure.

[0012] Figure 6 This is a flowchart of a method according to an embodiment of the present disclosure. Detailed Implementation

[0013] The following description of certain embodiments is exemplary in nature and is not intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the systems and methods of the invention, reference is made to the accompanying drawings, which form a part of this document, and specific embodiments in which the described systems and methods can be practiced are illustrated by means of the figures. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized, and changes in structure and logic may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, detailed descriptions of certain features will not be elaborated where they would be obvious to those skilled in the art, so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of this disclosure is limited only by the appended claims.

[0014] A memory device may include multiple memory cells. Each memory cell may store information (e.g., as one or more bits) and may be organized at the intersections of word lines (rows) and bit lines (columns). Several word lines and bit lines may be organized into a memory bank. A memory device may include several different memory banks. The memory device may receive one or more command signals that instruct operations on one or more of the memory banks encapsulated in the memory. For example, the memory device may enter a refresh mode, in which word lines in one or more of the memory banks are refreshed.

[0015] Information in a memory cell can decay over time. Memory cells can be refreshed row-by-row (e.g., word-by-word) to preserve the information in the memory cell. During a refresh operation, information in one or more rows can be rewritten back to the corresponding word line to restore the initial value of the information. Repeated access to a given word line (e.g., the aggressor word line) can increase the rate of information decay in one or more adjacent word lines (e.g., the victim word line). In some applications, a victim word line can be considered a word line physically adjacent to the aggressor word line. For example, a victim word line can be physically adjacent to the aggressor word line, meaning that the victim word line can be physically located on either side of the aggressor word line (e.g., R+1 and R-1). In some embodiments, word lines physically adjacent to neighboring word lines (e.g., R+2 and R-2) can also be considered victim word lines. In some applications, such as in memories where word lines are densely spaced, more distant word lines can also be considered victim word lines (e.g., R+3, R-3, R+4, R-4, etc.). In other example implementations, other relationships between the victim word line and the aggressor word line may be used.

[0016] Access to different word lines in memory can be tracked to determine whether a word line is an attacker word line. For example, the row address of the accessed word line and / or attacker word line may be stored in a register (e.g., a file) or other storage device in memory. If a word line is identified as an attacker word line, the victim address associated with the victim word line can be determined at least in part based on the row address of the attacker word line. In some embodiments, the victim word lines (e.g., R+1, R-1, R+2, and R-2) may be refreshed as part of a targeted (or 'row hammer') refresh operation, and therefore there may be, for example, four victim addresses refreshed for each identified attacker row address. The row address of the victim word line refreshed during the targeted refresh operation may be referred to as the target refresh address.

[0017] In some embodiments, some time slots used for refresh operations may be reserved for automatic refresh operations, and some time slots may be reserved for target refresh operations. In some embodiments, the target refresh address may be published in (e.g., “stolen”) time slots when hammer management is not required; otherwise, these time slots would be allocated to the automatic refresh address. In some embodiments, certain refresh time slots may be reserved for the target refresh address. These time slots may be referred to as target refresh time slots. The time period between reserving time slots for the target refresh address may be referred to as the target refresh rate or the stolen rate.

[0018] Different victim word lines of an aggressor word line may be affected by line hammering to varying degrees. For example, a victim word line closer to the aggressor word line (e.g., a neighboring victim word line, R+ / -1) may suffer a higher rate of data degradation compared to a more distant victim word line (e.g., R+ / -2). Therefore, it may be necessary to perform targeted refresh operations on different victim word lines at different rates. For example, the refresh rate of a victim word line R+ / -1 may be four times the refresh rate of a victim word line R+ / -2. In another instance, the refresh rate of a victim word line R+ / -1 may be eight times the refresh rate of a victim word line R+ / -2. In some applications, it may be necessary to be able to adjust the target refresh rate of different victim word lines independently of each other. That is, the target refresh rate of R+ / -2 may not depend on the target refresh rate of R+ / -1. This allows for optimization of the target refresh rate for each type of victim word line, which can reduce over-refreshing of word lines.

[0019] This disclosure depicts apparatus and methods for controlling a target refresh rate (e.g., theft rate). More specifically, this disclosure depicts apparatus and methods for independently controlling the theft rate for different victim word lines, such as victim word lines located at different physical distances from the attacker word line. In some embodiments, the refresh control circuitry may include two or more timing circuits to allow independent control of the theft rate for different victim word lines.

[0020] Figure 1 This is a block diagram illustrating the overall configuration of a semiconductor device according to at least one embodiment of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0021] Semiconductor device 100 includes memory array 112. In some embodiments, memory array 112 may include multiple memory banks. Each memory bank includes multiple word lines WL, multiple bit lines BL and / BL, and multiple memory cells MC disposed at the intersections of the multiple word lines WL and the multiple bit lines BL and / BL. The selection of word lines WL is performed by row control circuitry 108, and the selection of bit lines BL and / BL is performed by column control circuitry 110. In some embodiments, row control circuitry 108 and column control circuitry 110 may be present for each of the memory banks.

[0022] Bit lines BL and / BL are coupled to the corresponding sense amplifier (SAMP) 117. Read data from bit line BL or / BL is amplified by sense amplifier SAMP 117 and transmitted to read / write amplifier 120 via complementary local data line (LIOT / B), transmission gate (TG) 118, and complementary master data line (MIO). Conversely, write data output from read / write amplifier 120 is transmitted to sense amplifier 117 via complementary master data line MIO, transmission gate 118, and complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL or / BL.

[0023] The semiconductor device 100 may employ a plurality of external terminals, the plurality of external terminals including: a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses; a clock terminal receiving clock CK and / or CK; a data terminal DQ providing data; and a power supply terminal receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0024] An external clock CK and / CK are supplied to the clock input circuit 122 via a clock terminal. The external clocks may be complementary. The clock input circuit 122 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is supplied to the command control circuit 106 and to the internal clock generator circuit 124. The internal clock generator circuit 124 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is supplied to the input / output circuit 126 to time the operation of circuits contained within the input / output circuit 126, for example, to a data receiver to time the reception of written data.

[0025] The C / A terminal may supply a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder circuit 104 via the command / address input circuit 102. The address decoder circuit 104 receives the address and supplies the decoded row address XADD to the row control circuit 108 and the decoded column address YADD to the column control circuit 110. The row address XADD can be used to specify one or more word lines WL of the memory array 112, and the column address YADD can specify one or more bit lines BL of the memory array 112. The address decoder circuit 104 may also provide a bank address BADD, which specifies a particular bank of memory. The bank address BADD can be provided to the row control circuit 108 and / or the column control circuit 110 to direct access operations to one or more of the banks of memory. The C / A terminal may supply commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, as well as other commands and operations. Access commands can be associated with one or more row addresses XADD, column addresses YADD, and / or bank addresses BADD to indicate the memory cell to be accessed.

[0026] Commands can be provided as internal command signals to command control circuitry 106 via command / address input circuitry 102. Command control circuitry 106 includes circuitry for decoding internal command signals to generate various internal signals and commands for performing operations. For example, command control circuitry 106 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0027] Device 100 can receive access commands as row activation commands ACT. When the row activation command ACT is received, the row address XADD is supplied along with the row activation command ACT.

[0028] Device 100 can receive access commands as read commands. When a read command is received, the bank address BADD and column address YADD are supplied along with the read command, and read data is read from the memory cells in memory array 112 corresponding to row address XADD and column address YADD. The read command is received via command control circuit 106, which provides an internal command to provide the read data from memory array 112 to read / write amplifier 120. The read data is output to the outside via input / output circuit 126 from data terminal DQ.

[0029] Device 100 can receive access commands as write commands. When a write command is received, the bank address and column address are supplied along with the write command, and the write data supplied to the data terminal DQ is written to the memory cells in memory array 112 corresponding to the row address and column address. The write command is received via command control circuit 106, which provides internal commands to cause the write data to be received by the data receiver in input / output circuit 126. A write clock can also be provided to an external clock terminal to time the data receiver in input / output circuit 126 to receive the write data. The write data is supplied to read / write amplifier 120 via input / output circuit 126, and then to memory array 112 via read / write amplifier 120 to be written into memory cell MC.

[0030] The device 100 can also receive commands to perform a refresh operation. The refresh signal AREF can be a pulse signal that is activated when the command control circuit 106 receives a signal indicating a refresh command. In some embodiments, the refresh command can be issued to the memory device 100 from an external source. In some embodiments, the refresh command can be generated periodically by components of the device. In some embodiments, the refresh signal AREF can also be activated when an external signal indicates a self-refresh entry command. The refresh signal AREF can be activated immediately after the command input and can subsequently be activated cyclically according to desired internal timing. Therefore, the refresh operation can continue automatically. A self-refresh exit command can stop the automatic activation of the refresh signal AREF and return it to an idle state.

[0031] Refresh control circuit 116 supplies a refresh row address RXADD to row control circuit 108, which can refresh one or more word lines WL indicated by the refresh row address RXADD. Refresh control circuit 116 can control the timing of refresh operations based on refresh signal AREF. In some embodiments, in response to AREF activation, refresh control circuit 116 can generate one or more activations of pump signals, and can generate and provide a refresh address RXADD for each activation of the pump signal (e.g., each pump).

[0032] One type of refresh operation can be an auto-refresh operation. In response to an auto-refresh operation, the memory bank can refresh a word line or group of word lines, and then refresh the next word line or group of word lines in response to the next auto-refresh operation. Refresh control circuitry 116 can provide an auto-refresh address as a refresh address RXADD indicating a word line or group of word lines in the memory bank. Refresh control circuitry 116 can generate a refresh address RXADD sequence such that, over time, the auto-refresh operation can cycle through all word lines WL of the memory bank. The timing of the refresh operation allows each word line to be refreshed at a frequency at least partially based on the normal rate of data degradation in the memory cells (e.g., the auto-refresh rate).

[0033] Another type of refresh operation can be a targeted refresh operation. As previously mentioned, repeated access to a specific word line of memory (e.g., an aggressor word line) can increase the decay rate in adjacent word lines (e.g., victim word lines) due to, for example, electromagnetic coupling between word lines. In some embodiments, a victim word line may include word lines physically adjacent to the aggressor word line. In some embodiments, a victim word line may include word lines further away from the aggressor word line. Information in a victim word line can decay at a rate such that data may be lost if the victim word line is not refreshed before the next automatic refresh operation of the word line. To prevent information loss, it may be necessary to identify the aggressor word line and then perform a targeted refresh operation, wherein the refresh address RXADD associated with one or more associated victim word lines is refreshed.

[0034] The refresh control circuit 116 can selectively output a target refresh address (e.g., the victim row address) or an automatic refresh address (or auto-refresh address) as the refresh address RXADD. The automatic refresh address can be derived from an address sequence provided based on the activation of the automatic refresh signal AREF. The refresh control circuit 116 can cycle through the automatic refresh address sequence at a rate determined by AREF. In some embodiments, the automatic refresh address sequence can be generated by updating (e.g., incrementing) one or more portions of a previous automatic refresh address.

[0035] The refresh control circuit 116 can also determine a target refresh address based on the access patterns of nearby addresses in the memory array 112 (e.g., the attacker row address corresponding to the attacker word line), the target refresh address being the address to be refreshed (e.g., the victim row address corresponding to the victim word line). The refresh control circuit 116 can selectively use one or more signals from the device 100 to calculate the refresh address RXADD. For example, the refresh address RXADD can be calculated based on the row address XADD provided by the address decoder circuit 104. The refresh control circuit 116 can receive the current value of the row address XADD provided by the address decoder circuit 104 and determine the target refresh address based on one or more of the received addresses XADD.

[0036] Timing can be provided for refresh addresses RXADD based on the timing of the refresh signal AREF. The refresh control circuit 116 may have time slots corresponding to the timing of AREF and may provide one or more refresh addresses RXADD during each time slot. Target refresh addresses may be published in (e.g., “stolen”) time slots, which would otherwise be allocated to auto-refresh addresses. In some embodiments, certain time slots may be reserved for target refresh addresses. These time slots may be referred to as target refresh intervals or target refresh time slots. The time period between reserved time slots for target refresh addresses may be referred to as target refresh rate or stolen rate.

[0037] In some embodiments, certain target refresh time slots may be reserved for refreshing one type of victim word line, while other target refresh time slots may be reserved for refreshing another type of victim word line. For example, certain target refresh time slots may be reserved for refreshing R+ / -1 victim word lines, and other target refresh time slots may be reserved for refreshing R+ / -2 victim word lines. In some embodiments, the theft rate of target refresh time slots for different types of victim word lines may be different. In some embodiments, the theft rate of target refresh time slots for different types of victim word lines may be independent of each other.

[0038] The refresh control circuit 116 may receive a row address XADD provided by the address decoder circuit 104 and may determine which word lines are being hammered based on the row address XADD. For example, the refresh control circuit 116 may count accesses to word lines and may determine which word lines are aggressors based on the access count (e.g., reaching a threshold). The row address XADD and the access count value may be stored by the refresh control circuit 116. When an aggressor word line is determined, the refresh control circuit 116 may calculate the victim word lines associated with the aggressor word line and perform the targeted refresh operation as previously described.

[0039] The power supply terminals provide power potentials VDD and VSS. These power potentials VDD and VSS are supplied to the internal voltage generator circuit 128. The internal voltage generator circuit 128 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is primarily used in the line decoder circuit 108, the internal potentials VOD and VARY are primarily used in the sense amplifier SAMP included in the memory array 112, and the internal potential VPERI is used in many peripheral circuit blocks.

[0040] The power supply terminals are also supplied with power potentials VDDQ and VSSQ. Power potentials VDDQ and VSSQ are supplied to input / output circuitry 126. In embodiments of this disclosure, the power potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power potentials VDD and VSS supplied to the power supply terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power potentials VDD and VSS supplied to the power supply terminals. The power potentials VDDQ and VSSQ supplied to the power supply terminals are used in input / output circuitry 122 to prevent power supply noise generated by input / output circuitry 126 from propagating to other circuit blocks.

[0041] Figure 2 This is a block diagram of a refresh control circuit 216 according to an embodiment of the present disclosure. In some embodiments, the refresh control circuit 216 may be included in a memory device, such as... Figure 1 The memory device 100 shown herein. For the context, Figure 2 The image also shows a DRAM interface 226 and a line decoder circuit 208. In some embodiments, a refresh control circuit 216 may be included in... Figure 1 The refresh control circuit 116 is shown in the diagram. In some embodiments, the row decoder circuit 208 may be included in the row control circuit 108. In some embodiments, some of the components (e.g., refresh control circuit 216 and row decoder circuit 208) may be provided for a specific memory bank, and these components may be repeated for each memory bank. Therefore, multiple refresh control circuits 216 and row decoder circuits 208 may exist in a memory device. For the sake of brevity, only the components for a single memory bank will be described.

[0042] DRAM interface 226 can provide one or more signals to address refresh control circuit 216 and row decoder circuit 208. Refresh control circuit 216 may include attacker row detector circuit 230, first victim address generator 232, second victim address generator 234, auto refresh (AREF) address generator 236, first victim theft rate timing circuit 238, second victim theft rate timing circuit 240, multiplexer 242, and target refresh address controller circuit 244. DRAM interface 226 can provide one or more control signals, such as auto refresh signal AREF, activation / precharge signal ACT / Pre, and row address XADD.

[0043] DRAM interface 226 may represent components that provide signals to a memory bank, such as one or more components of refresh control circuitry 216 and line decoder circuitry 208. In some embodiments, DRAM interface 226 may represent a connection to a semiconductor memory device (e.g., Figure 1The memory controller of the device 100). In some embodiments, the DRAM interface 226 may represent, for example, Figure 1 The DRAM interface 226 includes components such as command address input circuit 102, address decoder circuit 104, and / or command control circuit 106. The DRAM interface 226 can provide a row address XADD, an auto-refresh signal AREF, an activation signal ACT, and / or a precharge signal Pre. The auto-refresh signal AREF can be a periodic signal indicating when an auto-refresh operation occurs. The activation signal ACT can be provided to activate a given memory bank. The row address XADD can be a signal containing multiple bits (which can be emitted consecutively or simultaneously) and can correspond to a specific row of a memory bank (e.g., a memory bank activated by ACT / Pre).

[0044] During memory operation, the attacker row detector circuit 230 may receive the current row address XADD. In some embodiments, the attacker row detector circuit 230 may store the current value of the row address XADD. The attacker row detector circuit 230 may further store a count value associated with each stored row address. Whenever a row address stored in the attacker row detector circuit 230 is received as XADD, the count value of the row address may be adjusted (e.g., incremented).

[0045] For each row address XADD stored in the aggressor row detector circuit 230, the aggressor row detector circuit 230 may determine whether the current row address XADD is an aggressor row address based on one or more previously stored row addresses. For example, in some embodiments, the aggressor row detector circuit 230 may determine that a row address is an aggressor row address based on receiving row address XADD multiple times (e.g., the count value of the stored row address exceeds a threshold). The aggressor row detector circuit 230 may then reset the count value associated with the aggressor row address. Other aggressor row detection methods may be used in other embodiments. In some embodiments, when an aggressor row address is identified, the aggressor row detector circuit 230 may provide a matching address HitXADD to a first victim address generator 232 and a second victim address generator 234.

[0046] When DRAM interface 226 directs access operations (e.g., read and write operations) to the memory cell array (e.g., Figure 1The row address XADD can change when the memory cell array 118 is in a different row. In some embodiments, the aggressor row detector circuit 230 can store each received row address XADD. In other embodiments, the aggressor row detector circuit 230 can store the received row address in response to an active sample signal provided by a sample timing generator (not shown). In some embodiments, the sample signal can be a pulse signal. That is, it can transition to an active state and return to an inactive state after a certain time period (e.g., half a clock cycle, one clock cycle). The sample generator can vary the time interval regularly, randomly, or pseudo-randomly between pulses of the sample signal.

[0047] The first victim address generator 232 and the second victim address generator 234 calculate one or more row addresses to be refreshed based on the aggressor row address identified by the aggressor row detector circuit 230 (e.g., row address XADD associated with a count value above a threshold). The row address calculated by the first victim address generator 232 and the second victim address generator 234 may be the victim row address corresponding to the victim word line associated with the aggressor word line of HitXADD. The matching address HitXADD may be provided as input to the first victim address generator 232 and the second victim address generator 234. The first victim address generator 232 may provide a target refresh address V1ADD, and the second victim address generator 234 may provide a target refresh address V2ADD in response to these inputs. The target refresh address may be the address of a memory location (e.g., a word line), which may be affected by repeated activation of the memory location corresponding to the matching address HitXADD. In other words, the matching address HitXADD can be the 'aggressor' row address, and the target refresh addresses V1ADD and V2ADD can be the 'victim' addresses. Different calculations can be used to generate different victim addresses as target refresh addresses V1ADD and V2ADD.

[0048] The first victim address generator 232 and the second victim address generator 234 may employ different calculations to generate victim line addresses. In one instance, the first calculation may be used by the first victim address generator 232, and the second calculation may be used by the second victim address generator 234. The calculations may provide a target refresh address V1ADD or V2ADD corresponding to a word line that has a known physical relationship (e.g., spatial relationship) with the word line corresponding to the matching address HitXADD. In some embodiments, the different calculations may be based on different physical relationships between the victim word line and the aggressor word line. In some embodiments of this disclosure, the calculations may generate a single target refresh address for V1ADD and / or V2ADD. In other embodiments of this disclosure, the calculations may generate a sequence of target refresh addresses for V1ADD and / or V2ADD.

[0049] In one embodiment, a first calculation may cause a first victim address generator 232 to output a pair of addresses corresponding to word lines adjacent to the word line corresponding to the matching address HitXADD (e.g., V1ADD = HitXADD+ / -1). A second calculation may cause a second victim address generator 234 to output a pair of addresses corresponding to word lines adjacent to the word line corresponding to the address HitXADD+ / -1 (e.g., V2ADD = HitXADD+ / -2). In other words, the second calculation may output a pair of addresses corresponding to victim word lines adjacent to the victim word line corresponding to the address V1ADD. In other example embodiments, other calculations are possible. For example, the first calculation may be based on the physical relationship with the matching address HitXADD, while the second calculation may be based on the physical relationship with the address provided by the first calculation. In some embodiments, the target addresses V1ADD and V2ADD calculated by the first victim address generator 232 and the second victim address generator 234 may be provided to the multiplexer 242. In some embodiments, the first victim address generator 232 and the second victim address generator 234 may include a buffer (not shown) for storing the victim row address to be provided to the multiplexer 242 during a subsequent target refresh operation.

[0050] AREF address generator 236 generates an auto-refresh address Pre_RXADD in response to a refresh signal AREF. As part of the auto-refresh operation, the auto-refresh address Pre_RXADD may be part of a sequence of addresses to be refreshed. AREF address generator 236 may update the current auto-refresh address Pre_RXADD to the next address in the sequence in response to the active refresh signal AREF. AREF address generator 236 also provides a command signal RHR from target refresh address controller circuitry 244. In some embodiments, when the command signal is active, AREF address generator 236 may be controlled to stop updating the auto-refresh address Pre_RXADD, even when the auto-refresh signal AREF is active. As described herein, since the active command signal RHR indicates that a target refresh operation will be performed instead of an auto-refresh operation, this allows the auto-refresh operation to be paused during a target refresh and resumed when the command signal RHR is inactive.

[0051] Multiplexer 242 accepts the auto-refresh address Pre_RXADD provided by AREF address generator 236, V1ADD provided by first victim address generator 232, and V2ADD provided by second victim address generator 234, and outputs one of them as the refresh address RXADD. Multiplexer 242 can select among the refresh addresses based on the command signal RHR. Target refresh address controller circuit 244 provides the output RHR to multiplexer 242 to control the selection of the Pre_RXADD, V1ADD, or V2ADD address as the refresh address RXADD.

[0052] The first victim theft rate timing circuit 238 can provide a timing signal V1Time that determines the rate at which the victim row address V1ADD is provided as RXADD. The second victim theft rate timing circuit 240 can provide a timing signal V2Time that determines the rate at which the victim row address V2ADD is provided as RXADD. The timing signals V1Time and V2Time can be periodic signals that alternate between active and inactive states (e.g., between high and low logic levels). In some embodiments, the timing signals V1Time and V2Time can operate at different frequencies. For example, in some embodiments, V1Time can have a higher frequency than V2Time. In these embodiments, this allows the victim row address V1ADD to be provided as RXADD at a higher frequency compared to V2ADD. The first victim theft rate timing circuit 238 and the second victim theft rate timing circuit 240 can be independent. That is, neither timing circuit requires input from the other timing circuit to produce its output. In some embodiments, the timing circuits can each receive at least one input specific to the timing circuit, such that the timing circuits do not receive exactly the same input.

[0053] The first victim theft rate timing circuit 238 and / or the second victim theft rate timing circuit 240 may include square wave generation circuits for generating outputs V1Time and V2Time, respectively. For example, a Schmitt trigger waveform generator, a 555 timer (not shown), and / or a ring waveform generator may be included in the first victim theft rate timing circuit 238 and / or the second victim theft rate timing circuit 240. Figure 2 As indicated by sets (1) and (2) in the table, the frequencies of V1Time and / or V2Time can be set by means of fuses, antifuses, programming one or more mode registers, and / or other frequency setting methods. For example, in some embodiments, the frequencies can be set by providing a timing control voltage via / in response to a command signal from DRAM interface 226.

[0054] Optionally, in some embodiments, the first victim theft rate timing circuit 238 and / or the second victim theft rate timing circuit 240 may receive an AREF signal to synchronize the activation of V1Time and / or V2Time with the AREF signal. This helps ensure that the V1Time and / or V2Time signals are activated during refresh operations rather than between refresh operations where timing signals are negligible.

[0055] The target refresh address controller circuit 244 may receive V1Time, V2Time, and AREF as inputs and provide a control signal RHR based on these inputs. The target refresh address controller circuit 244 may include logic gates and / or other circuitry to generate the control signal RHR. In some embodiments, the control signal RHR may have multiple states. In some embodiments, the control signal RHR may be a multi-bit signal with multiple states (e.g., '00', '01', '10', '11'). For example, RHR may have a first state when AREF is inactive, regardless of the states of V1Time and V2Time; a second state when AREF is inactive and V1Time is active; a third state when AREF is active and V2Time is active; and a fourth state when AREF is active and both V1Time and V2Time are active. In some embodiments, V1Time and V2Time may be prevented from being active simultaneously. In some embodiments, the target refresh address controller circuit 244 may favor one timing signal over another. For example, if both V1Time and V2Time are active, the target refresh address control circuit 244 can favor V1Time and provide an RHR in the second state.

[0056] In some embodiments, when the RHR is in a state indicating AREF and V1Time activity, the multiplexer 242 may provide V1ADD as RXADD; when the RHR is in a state indicating AREF and V2Time activity, it may provide V2ADD as RXADD; and when the RHR is in a state indicating only AREF activity, it may provide Pre_RXADD. When AREF is inactive, the address may not be provided as RXADD, and / or when AREF is inactive, the line decoder circuitry 208 may ignore RXADD.

[0057] The row decoder circuit 208 can perform one or more operations on the memory array (not shown) based on the received signals and addresses. For example, in response to the activation signal ACT and the row address XADD (and AREF at a low logic level), the row decoder circuit 208 can guide one or more access operations (e.g., read operations) to the specified row address XADD. In response to the AREF signal being inactive, the row decoder circuit 208 can refresh the refresh address RXADD.

[0058] although Figure 2 The example illustrated shows two victim rate-stealing timing circuits and two victim address generators, but it should be understood that other embodiments may include additional victim rate-stealing timing circuits and victim address generators. For example, it may be necessary to have separate rate-stealing timings for additional victim word line types (e.g., R+ / -3, R+ / -4), and to perform target refresh operations on these additional victim word lines.

[0059] Figure 3 This is a circuit diagram of an example target refresh address controller circuit 300 according to an embodiment of the present disclosure. In some embodiments, the target refresh address controller circuit 300 may be included in... Figure 2 The target refresh address controller circuit 244 is shown in the diagram. For the context, Figure 3 The image also shows a multiplexer 302. In some embodiments, the multiplexer 302 may be included in... Figure 2 The multiplexer 242 shown in the image.

[0060] The target refresh address controller circuit 300 can receive a refresh signal AREF, a first timing signal V1Time, and a second timing signal V2Time. In some embodiments, the refresh signal AREF may be generated by, for example... Figure 1 The command control circuit of the command control circuit 106 shown is provided. In some embodiments, it can be provided via, for example... Figure 2 The DRAM interface 226 shown provides a refresh signal AREF. In some embodiments, the first timing signal V1Time and / or the second timing signal V2Time may be provided by a victim-stealing rate timing circuit, such as... Figure 2 The first victim theft rate timing circuit 238 and the second victim theft rate timing circuit 240 shown are provided. Based on the refresh signal AREF and the timing signals V1Time and V2Time, the target refresh address controller circuit 300 can provide the control signal RHR to the multiplexer 302. The state of the control signal RHR determines which row address is provided as the refresh address RXADD. Figure 3 In the example shown, the control signal RHR is a two-bit signal containing the least significant bit RHR_LSB and the most significant bit RHR_MSB.

[0061] Depending on the state of the RHR signal, multiplexer 302 can provide the first victim row address V1ADD, the second victim row address V2ADD, or the auto-refresh address Pre-RXADD as RXADD. In some embodiments, the first victim row address V1ADD and / or the second victim row address V2ADD can be generated by a victim row address generator, such as... Figure 2 The first victim row address generator 232 and the second victim row address generator 234 shown in the diagram are provided. In some embodiments, the auto-refresh address Pre_RXADD may be provided by the auto-refresh address generator, such as... Figure 2 The AREF address generator 236 shown in the figure provides this feature. In some embodiments, a first victim line address V1ADD may contain one or more victim line addresses corresponding to one or more victim word lines, which have a first physical relationship with the aggressor word line. In some embodiments, a second victim line address V2ADD may contain one or more victim line addresses corresponding to one or more victim word lines, which have a second physical relationship with the aggressor word line. For example, the first victim line address V1ADD may correspond to a victim word line that is physically adjacent to the aggressor word line, and the second victim line address V2ADD may correspond to a victim word line that is physically adjacent to the victim word line corresponding to V1ADD.

[0062] In some embodiments, the target refresh address controller circuit 300 may include a first AND gate 304 that receives an AREF signal at a first input and an inverted V2Time signal at a second input. The V2Time signal may be inverted by an inverter 306. A second AND gate 308 may receive the AREF signal and the V1Time signal at its input. The outputs of the first AND gate 304 and the second AND gate 308 may be provided to a first OR gate 310. Based on the inputs, the first OR gate 310 may output RHR_LSB. The target refresh address controller circuit 300 may include a third AND gate 312 that receives the AREF and V2Time signals as inputs. A fourth AND gate 314 may receive the AREF and V1Time signals as inputs. The outputs of the third AND gate 312 and the fourth AND gate 314 may be provided to a second OR gate 316. The OR gate 316 may provide RHR_MSB as its output.

[0063] exist Figure 3In the example shown, multiplexer 302 is configured to provide Pre_RXADD when RHR is in state '00' or '01', V2ADD when RHR is in state '10', and V1ADD when RHR is in state '11'. In operation, when AREF is inactive (e.g., logic low), the target refresh address controller circuitry 300 provides RHR in state '00', regardless of the states of V1Time and V2Time. Although multiplexer 302 may provide Pre_RXADD as RXADD in this state, as previously mentioned, it can be ignored by the line decoder circuitry because no refresh operation has occurred. When AREF is active (e.g., logic high) and V1Time and V2Time are inactive, RHR is in state '01'. In response, multiplexer 302 may provide Pre_RXADD as RXADD, which can be received by the line decoder circuitry for use during refresh operations. When AREF and V1Time are active and V2Time is inactive, RHR is in state '11', and multiplexer 302 provides the victim row address V1ADD as RXADD. When AREF and V2Time are active and V1Time is inactive, RHR is in state '10', and multiplexer 302 provides the victim row address V2ADD as RXADD.

[0064] exist Figure 3 In the example shown, when AREF, V1Time, and V2Time are all active, RHR is in state '11' and V1ADD is provided as RXADD. Therefore, in the event of a conflict between V1Time and V2Time, the victim word line associated with V1ADD is refreshed before the word line associated with V2ADD. This may be desirable if, as in the example described above, the word line associated with V1ADD is physically closer to the aggressor word line than the word line associated with V2ADD. However, in other embodiments, alternative logic gates may be provided to prioritize the word line associated with V2ADD over the word line associated with V1ADD in the event of a conflict between V1Time and V2Time. In other embodiments, additional circuitry and / or logic gates may be provided to prevent V1Time and V2Time from being active simultaneously.

[0065] although Figure 3 Not shown in the text, but in some embodiments, RHR_MSB can be provided to the auto-refresh address generator, for example... Figure 2 The AREF address generator 236 is shown in the image. The automatic refresh address generator can pause the generation of the automatic refresh address during the target refresh address operation using the RHR_MSB signal, as previously referenced. Figure 2 The discussion.

[0066] Figure 4 This is an example timing diagram of a refresh signal, a first timing signal, and a second timing signal according to embodiments of the present disclosure. Timing diagram 400 illustrates the refresh signal AREF, the first timing signal V1Time, and the second timing signal V2Time. In some embodiments, the refresh signal AREF may be, for example... Figure 1 The command control circuit of the command control circuit 106 shown is provided. In some embodiments, it can be provided via, for example... Figure 2 The DRAM interface 226 shown provides a refresh signal AREF. In some embodiments, the first timing signal V1Time and / or the second timing signal V2Time may be provided by a victim-stealing rate timing circuit, such as... Figure 2 The first victim theft rate timing circuit 238 and the second victim theft rate timing circuit 240 shown in the diagram are provided. AREF, V1Time, and V2Time can be used to control the target refresh address controller circuit, for example... Figure 2 The target refresh address controller circuit 244 shown in the image is... Figure 3 The target refresh address controller circuit 300 is shown in the figure. In some embodiments, for example Figure 1 The refresh control circuit 116 shown in the image or Figure 2 Other components of the refresh control circuit, such as the refresh control circuit 216 shown, can receive AREF, V1Time, and / or V2Time.

[0067] As shown in timing diagram 400, the refresh control circuit refreshes a first victim word line at a first rate based on the rate of timing signal V1Time, and a second victim word line at a second rate based on the rate of timing signal V2Time. In this example, the first victim word lines are a pair of word lines adjacent to the aggressor word lines. The first victim word lines may be associated with the victim row address V1ADD. The second victim word lines are a pair of word lines each adjacent to one of the first victim word lines. The second victim word lines may be associated with the victim row address V2ADD. Other circuitry may employ other operations, where, for example, neither pair of word lines is adjacent to the aggressor word line.

[0068] Figure 4The first line shows a portion of the refresh signal AREF. The refresh signal AREF can be a sequence of pulses (e.g., from low logic level to high logic level over a set duration). The refresh signal AREF can occur at regular time intervals in a set mode. The refresh signal AREF controls a refresh operation that refreshes one or more word lines of the memory. As discussed herein, the refresh signal AREF can be used to trigger a refresh operation in the memory. As shown, during the period of a particular AREF pulse activity, some of the individual pulses are marked with "T" or "A" to indicate that a target refresh operation or an automatic refresh operation is in progress, respectively.

[0069] Figure 4 The second line represents the first timing signal V1Time. As shown, the first command signal V1Time is a periodic pulse signal. In some embodiments, the duration of the first timing signal V1Time may be longer than the duration of each of the pulses of the refresh signal AREF. In this example, the first timing signal V1Time indicates that the word line adjacent to the attacker's word line (e.g., refreshed at address V1ADD) will be refreshed. When the first timing signal V1Time is active, the first activation of the refresh signal AREF will instead refresh the first adjacent victim word line (e.g., R+1), and the second activation of the refresh signal AREF will refresh the second adjacent victim word line (e.g., R-1).

[0070] Figure 4 The third line represents the second timing signal V2Time. As shown, the second timing signal V2Time can also be a periodic pulse signal. Figure 4 In the example shown, the frequency of the second timing signal V2Time is different from the frequency of the first timing signal V1Time. In some embodiments, the duration of the pulse of the second timing signal V2Time may be equal to the duration of the pulse of the first timing signal V1Time. In this example, the second timing signal V2Time indicates that a word line adjacent to the victim word line (e.g., refreshed at address V2ADD) will be refreshed, and the victim word line is adjacent to the aggressor word line. When the second timing signal V2Time is active, the first activation of the refresh signal AREF will refresh the first victim word line (e.g., R+2), and the second activation of the refresh signal AREF will refresh the second victim word line (e.g., R-2).

[0071] Figure 5 This is an example of an intruder detection circuit 500 according to an embodiment of the present disclosure. In some embodiments, the intruder detection circuit 500 may be included in... Figure 2The attacker line decoder circuit 230 is shown in the diagram. However, in other embodiments, other attacker line detector circuitry may be included in the attacker line decoder circuit 230. The attacker line detector circuit 500 may include a stack 501. In some embodiments, the stack 501 may be a content-addressable memory (CAM) stack. The stack 501 may include a plurality of registers (e.g., files) 502, each of which may have corresponding fields 504, 506. Figure 5 In the embodiment shown, each register includes a field 504 configured to store row addresses (RowADD0-7) and a field 506 configured to store corresponding count values ​​(ACntVal0-7). The field 506 storing the count values ​​may be coupled to a comparator 508, which may be coupled to a pointer 512 via a counter scrambler 510. In some embodiments, the field 504 storing the row addresses may be coupled to one or more victim address generators (…). Figure 5 (not shown in the text), for example Figure 2 The first victim address generator 232 and / or the second victim address generator 234 shown in the diagram provide the matching address HitXADD to the victim address generator. Although Figure 5 The example shown illustrates eight registers 502 within stack 501, but it should be understood that stacks can contain fewer or more registers. For example, stack 501 may have 128 registers. In another example, stack 501 may have 1,024 registers.

[0072] Whenever a row address XADD is provided to register 502, it can be compared with field 504. If the current row address XADD is already stored in one of the registers 502, the count value associated with the matching row address in field 504 can be adjusted (e.g., increased). If the current row address XADD is not yet stored in one of the registers 502, it can be added to register 502. If an open register exists (e.g., a register without a row address), the row address XADD can be stored in the open register. If no open register exists, the register 502 associated with the lowest count value (as indicated by pointer 512) can have its row address replaced with the current row address XADD and its count value reset.

[0073] Comparator 508 can compare the count value in field 506 with a threshold to determine whether the count value of a row address matches or exceeds the threshold (e.g., 2,000, 3,000, 5,000). In some embodiments, comparator 508 can further compare the count values ​​to determine which row address is associated with a minimum count value. Field 506 corresponding to one or more minimum count values ​​that meet or exceed the threshold can be provided to counter scrambler 510, which can match the threshold field and minimum count value field with their respective associated row address fields 504. Pointer 512 can point to the row address in field 504 associated with a count value at or above the threshold, and can point to field 504 associated with the minimum count value in field 506. The threshold pointer can be used to reset the count of the row addresses identified as aggressors. In some embodiments, the threshold pointer can be used to provide the corresponding row address as a HitXADD to a victim address generator. When a new row address XADD is received and there is no open register 502 to store the new row address therein, the minimum count value pointer can be used to overwrite register 502.

[0074] Figure 6 This is a flowchart 600 of a method according to an embodiment of the present disclosure. At block 602, the step of "providing a first signal having a first frequency" can be performed. In some embodiments, the first signal may be provided by a victim-stealing rate timing circuit, for example... Figure 2 The first victim theft rate timing circuit 238 shown in the diagram generates the signal. At block 604, the step of "providing a second signal having a second frequency" can be performed. In some embodiments, the second signal may be generated by the victim theft rate timing circuit, for example... Figure 2 The second victim theft rate timing circuit 240 shown in the figure generates the frequency. In some embodiments, the second frequency is independent of the first frequency. In some embodiments, the second frequency is different from the first frequency. At block 606, the step of "refreshing the first victim word line" can be performed. In some embodiments, the refresh can be at least partially based on the first frequency. At block 608, the step of "refreshing the second victim word line" can be performed. In some embodiments, the refresh can be at least partially based on the second frequency.

[0075] In some embodiments, the method shown in flowchart 600 may further include generating a control signal based at least in part on the first signal and the second signal. In some embodiments, the control signal may be generated by a target refresh address controller circuit, such as... Figure 2 The target refresh address controller circuit 244 shown in the image is... Figure 3The target refresh address controller circuit 300 shown in the flowchart generates the refresh address. In some embodiments, the method shown in flowchart 600 may further include providing a refresh address for a refresh word line based at least in part on a control signal, wherein the refresh address is a first victim word line or a second victim word line. In some embodiments, the refresh address may be generated by a multiplexer, such as... Figure 2 The multiplexer 242 shown in the image or Figure 3 The multiplexer 302 shown in the image is provided.

[0076] The apparatus and methods described herein allow for independent control of the theft rate for different victim word lines, such as victim word lines located at different physical distances from the attacker word line. In some embodiments, the refresh control circuitry may include two or more timing circuits to allow for independent control of the theft rate for different victim word lines. This allows for optimization of the target refresh rate for each type of victim word line, which can reduce over-refreshing of the word line.

[0077] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate device or device portion of a system, apparatus, or method according to the invention.

[0078] Finally, the foregoing discussion is intended to illustrate the system of the invention only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the system of the invention has been described in detail with reference to exemplary embodiments, it should be understood that many modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and established spirit and scope of the system of the invention as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device for controlling the rate of theft, comprising: The refresh control circuit includes: An attacker line detector circuit is configured to identify attacker word lines contained in a plurality of word lines of a memory array; A first victim theft rate timing circuit is configured to provide a first signal at a first frequency, wherein the first frequency indicates the rate at which a first victim word line contained in the plurality of word lines is refreshed. and A second victim theft rate timing circuit is configured to provide a second signal at a second frequency, wherein the second frequency indicates the rate at which a second victim word line included among the plurality of word lines is refreshed, wherein the first victim word line and the second victim word line are adjacent word lines of the aggressor word line, and the first victim word line is physically closer to the aggressor word line than the second victim word line. The first frequency and the second frequency are independent of each other, and the first frequency is greater than the second frequency.

2. The device according to claim 1, wherein at least one of the first frequency or the second frequency is set by a fuse.

3. The device of claim 1, wherein at least one of the first frequency or the second frequency is set by programming the mode register.

4. The apparatus of claim 1, further comprising a target refresh address controller circuit configured to receive the first signal and the second signal, wherein the target refresh address controller circuit is configured to provide a control signal at least in part based on the first signal and the second signal, wherein the control signal determines a row address provided as a refresh address.

5. The device of claim 4, further comprising a multiplexer configured to receive a first victim row address corresponding to the first victim word line and a second victim row address corresponding to the second victim word line, wherein, based on the control signal, the multiplexer is configured to provide the first victim row address or the second victim row address as the refresh address.

6. The device of claim 5, wherein when the first signal is active, the control signal causes the multiplexer to provide the first victim row address, and when the second signal is active, the control signal causes the multiplexer to provide the second victim row address as the refresh address.

7. The device of claim 5, wherein when both the first signal and the second signal are active, the control signal causes the multiplexer to provide the first victim row address as the refresh address.

8. The device of claim 5, wherein the target refresh address controller circuit further receives a refresh signal and the multiplexer further receives an automatic refresh address, wherein when the refresh signal is active and the first signal and the second signal are inactive, the control signal causes the multiplexer to provide the automatic refresh address as the refresh address.

9. The device of claim 8, wherein when the refresh signal is inactive, the control signal causes the multiplexer not to provide the refresh address.

10. The device of claim 8, wherein the refresh signal is provided by a command control circuit.

11. The device of claim 1, wherein at least one of the first victim theft rate timing circuit or the second victim theft rate timing circuit receives a refresh signal, wherein the refresh signal is configured to synchronously activate at least one of the first signal and the second signal.

12. A device for controlling the rate of theft, comprising: Memory array; A row control circuit, which is coupled to the memory array; An attacker line detector circuit is configured to identify attacker word lines among a plurality of word lines contained in the memory array; A first timing circuit is configured to provide a first signal at a first frequency, wherein the first frequency is associated with a first victim word line included in the plurality of word lines; A second timing circuit is configured to provide a second signal at a second frequency, wherein the second frequency is associated with a second victim word line included in the plurality of word lines, the first victim word line and the second victim word line being adjacent word lines to the aggressor word line, and the first victim word line being physically closer to the aggressor word line than the second victim word line, and wherein the second frequency is independent of the first frequency, and the first frequency is greater than the second frequency. and The target refresh address controller circuit is configured to provide a first type of victim row address at the first frequency and a second type of victim row address at the second frequency. The victim row addresses of the first type and the second type are provided to the row control circuit for performing refresh operations on the victim word lines in the memory array corresponding to the victim row addresses of the first type and the second type.

13. The device according to claim 12, wherein: The attacker line detector circuit is configured to provide the attacker line address corresponding to the attacker word line; and The device further includes: A first victim address generator is configured to provide a victim line address of the first type based at least in part on the perpetrator line address; and A second victim address generator is configured to provide the second type of victim line address based at least in part on the aggressor line address.

14. A method for controlling the rate of theft, comprising: Identify the intruder word line contained in multiple word lines of the memory array; Provide a first signal having a first frequency; Provide a second signal with a second frequency; The first victim word line contained in the plurality of word lines is refreshed at least in part based on the first frequency; and The second victim word line included in the plurality of word lines is refreshed at least in part based on the second frequency, wherein the first victim word line and the second victim word line are neighboring word lines of the aggressor word line, and the first victim word line is physically closer to the aggressor word line than the second victim word line, and wherein the second frequency is independent of the first frequency, and the first frequency is greater than the second frequency.

15. The method of claim 14, further comprising: Control signals are generated at least in part based on the first signal and the second signal; and A refresh address is provided for refreshing a word line at least in part based on the control signal, wherein the refresh address is the first victim word line or the second victim word line.

16. The method of claim 14, further comprising setting at least one of the first frequency or the second frequency by setting a fuse.

17. The method of claim 14, further comprising setting at least one of the first frequency or the second frequency by programming a mode register.

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