Imaging device

Abstract

The present invention is provided with: a first substrate including sensor pixels for performing photoelectric conversion; a second substrate including a pixel circuit for outputting a pixel signal based on charges output from the sensor pixels; and a third substrate including a processing circuit for performing signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in sequence. A semiconductor layer including the pixel circuit is divided by an insulating layer. In at least one direction on a plane perpendicular to the optical axis direction of the sensor pixels, the insulating layer divides the semiconductor layer such that the center position of a continuous region of the semiconductor layer or the center position of a region dividing the semiconductor layer corresponds to the position of the optical center of the sensor pixels.

Description

Technical Field

[0001] The present disclosure relates to an imaging device. Background Art

[0002] By introducing miniaturization processes and increasing packaging density, miniaturization of the area of each pixel of a two-dimensional structured imaging device has been achieved. In recent years, in order to achieve further size reduction and higher pixel density of the imaging device, a three-dimensional structured imaging device has been developed. The three-dimensional structured imaging device is configured by stacking, for example, a semiconductor substrate including a plurality of sensor pixels and a semiconductor substrate including a signal processing circuit that processes signals obtained in each sensor pixel (see Patent Document 1).

[0003] Citation List

[0004] Patent Document

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2010-245506 Summary of the Invention

[0006] A three-dimensional structured imaging device has a complex structure in the stacking direction, and thus increases reflection of incident light inside the imaging device. The reflected incident light leaks into adjacent pixels (so-called crosstalk), which can reduce the sensitivity of adjacent pixels. Therefore, it is desirable to study the structure of the imaging device in consideration of internal incident light reflection.

[0007] Therefore, it is desirable to provide an imaging device that can equalize internal incident light reflection.

[0008] An imaging device according to an embodiment of the present disclosure includes: a first substrate including sensor pixels that perform photoelectric conversion; a second substrate including pixel circuits that output pixel signals based on charges output from the sensor pixels; and a third substrate including processing circuits that perform signal processing on the pixel signals. The first substrate, the second substrate, and the third substrate are stacked in this order. A semiconductor layer including the pixel circuits is divided by an insulating layer. In at least one direction on a plane perpendicular to the optical axis direction of the sensor pixels, the insulating layer divides the semiconductor layer such that the center position of a continuous region of the semiconductor layer or the center position of a region that divides the semiconductor layer corresponds to the position of the optical center of the sensor pixels.

[0009] The imaging device according to an embodiment of the present disclosure includes: a first substrate including sensor pixels that perform photoelectric conversion; a second substrate including pixel circuits that output pixel signals based on charges output from the sensor pixels; and a third substrate including processing circuits that perform signal processing on the pixel signals. The first substrate, the second substrate, and the third substrate are stacked in this order. The semiconductor layer including the pixel circuits is divided by an insulating layer. In at least one direction on a plane perpendicular to the optical axis direction of the sensor pixels, the insulating layer divides the semiconductor layer in such a manner that the center position of the continuous region of the semiconductor layer or the center position of the region dividing the semiconductor layer corresponds to the position of the optical center of the sensor pixels. Thus, the imaging device according to an embodiment of the present disclosure can, for example, make the distribution of light that passes through the first substrate, is reflected at the semiconductor layer and the insulating layer of the second substrate, and enters the sensor pixels more uniform. Description of the Drawings

[0010] Figure 1 Figure 1 is a schematic diagram showing an example of the schematic configuration of the imaging device 1 according to an embodiment of the present disclosure.

[0011] Figure 2 Figure 2 is a circuit diagram showing an example of the sensor pixels 12 and the pixel circuits 22.

[0012] Figure 3 Figure 3 is a circuit diagram showing another example of the sensor pixels 12 and the pixel circuits 22.

[0013] Figure 4 Figure 4 is a circuit diagram showing another example of the sensor pixels 12 and the pixel circuits 22.

[0014] Figure 5 Figure 5 is a circuit diagram showing another example of the sensor pixels 12 and the pixel circuits 22.

[0015] Figure 6 Figure 6 is a circuit diagram showing an example of the connection between a plurality of pixel circuits 22 and a plurality of vertical signal lines 24.

[0016] Figure 7 Figure 7 is a longitudinal sectional view showing an example of the sectional configuration of the imaging device 1 in the stacking direction.

[0017] Figure 8 Figure 8 is a schematic diagram showing an example of the sectional configuration of the imaging device 1 in the horizontal direction. ​​​​​​​​​​​​​​​​

[0018] Figure 9 Figure 9 is a schematic diagram showing an example of a cross-sectional structure of the imaging device 1 in the horizontal direction.

[0019] Figure 10 Figure 10 is a schematic diagram showing an example of a wiring layout of the imaging device 1 in the horizontal plane.

[0020] Figure 11 Figure 11 is a schematic diagram showing an example of a wiring layout of the imaging device 1 in the horizontal plane.

[0021] Figure 12 Figure 12 is a schematic diagram showing an example of a wiring layout of the imaging device 1 in the horizontal plane.

[0022] Figure 13 Figure 13 is a schematic diagram showing an example of a wiring layout of the imaging device 1 in the horizontal plane.

[0023] Figure 14 Figure 14 is a longitudinal sectional view showing an example of a cross-sectional structure of the imaging device 1 in the stacking direction according to an embodiment of the present disclosure.

[0024] Figure 15 Figure 15 is a plan view showing a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0025] Figure 16 Figure 16 is a plan view showing a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0026] Figure 17 Figure 17 is a plan view showing a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0027] Figure 18 Figure 18 is a plan view showing a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0028] Figure 19 Figure 19 is a plan view showing a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0029] Figure 20 Figure 20 ​​​​​​​​​​​​​​​​​​​​​​​​It is a plan view of a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0030] Figure 21 Figure 21 It is a plan view of a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0031] Figure 22 Figure 22 It is a plan view of a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0032] Figure 23 Figure 23 It is a plan view of a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0033] Figure 24 Figure 24 It is a plan view of a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0034] Figure 25 Figure 25 It is a plan view of a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0035] Figure 26 Figure 26 It is a plan view of a variation of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21 in the same embodiment.

[0036] Figure 27A Figure 27A It is a schematic longitudinal sectional view of a partial sectional structure of the imaging device 1 according to the thirteenth variation.

[0037] Figure 27B Figure 27B It is a schematic longitudinal sectional view of a partial sectional structure of the imaging device 1 according to the thirteenth variation.

[0038] Figure 27C Figure 27C It is a schematic longitudinal sectional view of a partial sectional structure of the imaging device 1 according to the thirteenth variation.

[0039] Figure 27D Figure 27D It is a schematic longitudinal sectional view of a partial sectional structure of the imaging device 1 according to the thirteenth variation.

[0040] Figure 28A Figure 28A ​​​​​​​​​​​​​​​​​​​​​​It is a schematic longitudinal sectional view of a partial sectional structure of the imaging device 1 according to the fourteenth variant.

[0041] Figure 28B Figure 28B It is a schematic longitudinal sectional view of a partial sectional structure of the imaging device 1 according to the fourteenth variant.

[0042] Figure 28C Figure 28C It is a schematic longitudinal sectional view of a partial sectional structure of the imaging device 1 according to the fourteenth variant.

[0043] Figure 28D Figure 28D It is a schematic longitudinal sectional view of a partial sectional structure of the imaging device 1 according to the fourteenth variant.

[0044] Figure 29 Figure 29 Is Figure 7 A longitudinal sectional view of a modified example of the sectional structure shown.

[0045] Figure 30 Figure 30 Is Figure 7 A longitudinal sectional view of a modified example of the sectional structure shown.

[0046] Figure 31 Figure 31 It is a sectional view in the thickness direction of a structural example of the imaging device according to the third modification example.

[0047] Figure 32 Figure 32 It is a sectional view in the thickness direction of a structural example of the imaging device according to the third modification example.

[0048] Figure 33 Figure 33 It is a sectional view in the thickness direction of a structural example of the imaging device according to the third modification example.

[0049] Figure 34 Figure 34 It is a sectional view in the horizontal direction of a layout example of a plurality of pixel units according to the third modification example.

[0050] Figure 35 Figure 35 It is a sectional view in the horizontal direction of a layout example of a plurality of pixel units according to the third modification example.

[0051] Figure 36 Figure 36 It is a sectional view in the horizontal direction of a layout example of a plurality of pixel units according to the third modification example.

[0052] ​​​​​​​​​​​​​​​​​​​​​​​Figure 37 Figure 37 is a schematic diagram of a modified example of the cross-sectional structure along the cutting planes Sec1 and Sec2 in Figure 7 .

[0053] Figure 38 Figure 38 is a schematic diagram of a modified example of the cross-sectional structure along the cutting planes Sec1 and Sec2 in Figure 7 .

[0054] Figure 39 Figure 39 is a schematic diagram of a modified example of the cross-sectional structure along the cutting planes Sec1 and Sec2 in Figure 7 .

[0055] Figure 40 Figure 40 is a schematic diagram of a modified example of the cross-sectional structure along the cutting planes Sec1 and Sec2 in Figure 7 .

[0056] Figure 41 Figure 41 is a schematic diagram of a modified example of the cross-sectional structure along the cutting planes Sec1 and Sec2 in Figure 7 .

[0057] Figure 42 Figure 42 is a schematic diagram of another example of the cross-sectional structure along the cutting plane Sec2 of the imaging device 1 according to the seventh modified example.

[0058] Figure 43 Figure 43 is a schematic diagram of another example of the cross-sectional structure along the cutting plane Sec2 of the imaging device 1 according to the seventh modified example.

[0059] Figure 44 Figure 44 is a schematic diagram of the circuit structure of a CMOS image sensor mounted on a column-parallel ADC.

[0060] Figure 45 Figure 45 is Figure 44 a schematic diagram of an example of the structure of the imaging device 1 shown in which includes three stacked substrates.

[0061] Figure 46 Figure 46 is a schematic diagram of an example of the cross-sectional structure of the imaging device 1 according to the ninth modified example.

[0062] Figure 47 Figure 47 is a structure that includes, for example, CoSi 2 ​​​​​​​​​​​​​​​​​​​​​Schematic diagram of an example in which a low-resistance region 26 of a silicide such as NiSi is applied to an imaging device 1 including a stacked substrate.

[0063] Figure 48 Figure 48 Block diagram showing an example of the functional configuration of an imaging device according to an embodiment of the present disclosure.

[0064] Figure 49 Figure 49 Is Figure 48 Schematic plan view of the schematic configuration of the imaging device shown.

[0065] Figure 50 Figure 50 Is along Figure 49 Schematic diagram of the cross-sectional structure taken along the line III-III' shown.

[0066] Figure 51 Figure 51 Is Figure 48 Equivalent circuit diagram of the pixel sharing unit shown.

[0067] Figure 52 Figure 52 Shows an example of the connection pattern between a plurality of pixel sharing units and a plurality of vertical signal lines.

[0068] Figure 53 Figure 53 Is Figure 50 Schematic cross-sectional view of an example of the specific structure of the imaging device shown.

[0069] Figure 54A Figure 54A Is Figure 53 Schematic diagram of an example of the planar structure of the main part of the first substrate shown.

[0070] Figure 54B Figure 54B Is Figure 54A Schematic diagram of the planar structure of the main part and the pad portion of the first substrate shown.

[0071] Figure 55 Figure 55 Is Figure 53 Schematic diagram of an example of the planar structure of the second substrate (semiconductor layer) shown.

[0072] Figure 56 Figure 56 Is Figure 53 Schematic diagram of an example of the planar structure of the first wiring layer, the pixel circuit, and the main part of the first substrate shown.

[0073] Figure 57 ​​​​​​​​​​​​​​​​​​​​​​Figure 57 is Figure 53 A schematic diagram of an example of the planar structure of the first wiring layer and the second wiring layer shown.

[0074] Figure 58 Figure 58 is Figure 53 A schematic diagram of an example of the planar structure of the second wiring layer and the third wiring layer shown.

[0075] Figure 59 Figure 59 is Figure 53 A schematic diagram of an example of the planar structure of the third wiring layer and the fourth wiring layer shown.

[0076] Figure 60 Figure 60 is a schematic diagram for describing the path of an input signal input to Figure 50 the imaging device shown.

[0077] Figure 61 Figure 61 is a schematic diagram for describing Figure 50 the signal path of the pixel signal of the imaging device shown.

[0078] Figure 62 Figure 62 is Figure 55 a schematic diagram of a modified example of the planar structure of the second substrate (semiconductor layer) shown.

[0079] Figure 63 Figure 63 is Figure 62 a schematic diagram of the planar structure of the main parts of the pixel circuit, the first wiring layer, and the first substrate shown.

[0080] Figure 64 Figure 64 is Figure 63 a schematic diagram of an example of the planar structure of the first wiring layer and the second wiring layer shown.

[0081] Figure 65 Figure 65 is Figure 64 a schematic diagram of an example of the planar structure of the second wiring layer and the third wiring layer shown.

[0082] Figure 66 Figure 66 is Figure 65 a schematic diagram of an example of the planar structure of the third wiring layer and the fourth wiring layer shown.

[0083] Figure 67 Figure 67 is Figure 54A a schematic diagram of a modified example of the planar structure of the first substrate shown.​​​​​​​​​​​​​​​​​​​​

[0084] Figure 68 Figure 68 is a schematic diagram of an example of the planar structure of a second substrate (semiconductor layer) stacked on the first substrate shown in Figure 67 .

[0085] Figure 69 Figure 69 is Figure 68 a schematic diagram of an example of the planar structure of the pixel circuit and the first wiring layer shown in

[0086] Figure 70 Figure 70 is Figure 69 a schematic diagram of an example of the planar structure of the first wiring layer and the second wiring layer shown in

[0087] Figure 71 Figure 71 is Figure 70 a schematic diagram of an example of the planar structure of the second wiring layer and the third wiring layer shown in

[0088] Figure 72 Figure 72 is Figure 71 a schematic diagram of an example of the planar structure of the third wiring layer and the fourth wiring layer shown in

[0089] Figure 73 Figure 73 is Figure 67 a schematic diagram of another example of the planar structure of the first substrate shown in

[0090] Figure 74 Figure 74 is a schematic diagram of an example of the planar structure of a second substrate (semiconductor layer) stacked on the first substrate shown in Figure 73 .

[0091] Figure 75 Figure 75 is Figure 74 a schematic diagram of an example of the planar structure of the pixel circuit and the first wiring layer shown in

[0092] Figure 76 Figure 76 is Figure 75 a schematic diagram of an example of the planar structure of the first wiring layer and the second wiring layer shown in

[0093] Figure 77 Figure 77 is Figure 76 a schematic diagram of an example of the planar structure of the second wiring layer and the third wiring layer shown in

[0094] Figure 78 ​​​​​​​​​​​​​​​​​​​​​​Figure 78 is Figure 77 A schematic diagram of an example of the planar structure of the third wiring layer and the fourth wiring layer shown in

[0095] Figure 79 Figure 79 is Figure 50 A schematic cross-sectional view of another example of the imaging device shown in

[0096] Figure 80 Figure 80 is a schematic diagram for describing the path of an input signal input to Figure 79 the imaging device shown in

[0097] Figure 81 Figure 81 is for describing Figure 79 the signal path of the pixel signal of the imaging device shown in

[0098] Figure 82 Figure 82 is Figure 53 A schematic cross-sectional view of another example of the imaging device shown in

[0099] Figure 83 Figure 83 shows Figure 51 another example of the equivalent circuit shown in

[0100] Figure 84 Figure 84 is Figure 54A a schematic plan view of another example of the pixel separation section shown in

[0101] Figure 85 Figure 85 shows an example of the schematic configuration of an imaging system including an imaging device according to any one of the above embodiments and their modifications.

[0102] Figure 86 Figure 86 shows Figure 85 an example of the imaging process in the imaging system shown in

[0103] Figure 87 Figure 87 is a block diagram showing an example of the schematic configuration of a vehicle control system.

[0104] Figure 88 Figure 88 is a diagram helpful for explaining an example of the installation positions of the out-of-vehicle information detection section and the imaging section.

[0105] Figure 89 Figure 89 ​​​​​​​​​​​​​​​​​​​​​​It is a diagram showing an example of the schematic configuration of an endoscopic surgical system.

[0106] Figure 90 Figure 90 It is a block diagram showing an example of the functional configuration of a camera and a camera control unit (CCU). Detailed Implementation Modes

[0107] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments described below are merely specific examples of the present disclosure, and the technology according to the present disclosure is not limited to the modes described below. In addition, attributes such as the arrangement, dimensions, and dimensional ratios of the respective constituent elements of the present disclosure shown in the respective drawings of the present disclosure are not limited to those shown in the respective drawings.

[0108] It should be noted that the description will be made in the following order.

[0109] 1. Configuration of the imaging device

[0110] 2. Technology according to the present disclosure

[0111] 3. Variants

[0112] 4. Specific examples

[0113] 4.1. Embodiment (imaging device having a stacked structure of three substrates)

[0114] 4.2. Variant 1 (Example 1 of planar configuration)

[0115] 4.3. Variant 2 (Example 2 of planar configuration)

[0116] 4.4. Variant 3 (Example 3 of planar configuration)

[0117] 4.5. Variant 4 (Example having a contact portion between substrates in the central portion of the pixel array section)

[0118] 4.6. Variant 5 (Example having a planar transfer transistor)

[0119] 4.7. Variant 6 (Example where one pixel is connected to one pixel circuit)

[0120] 4.8. Variant 7 (Example of the configuration of the pixel separation section)

[0121] 4.9. Application example (imaging system)

[0122] 4.10. Application examples

[0123] <<1. Configuration of the imaging device>>

[0124] First, with reference to​​Figures 1 to 13 A description is given of an imaging device to which the technology according to the present disclosure is applied.

[0125] Figure 1 is a schematic diagram showing an example of the schematic configuration of the imaging device 1 according to an embodiment of the present disclosure. As Figure 1 shown, the imaging device 1 is an imaging device having a three-dimensional structure including a first substrate 10, a second substrate 20, and a third substrate 30, and having a structure in which these three substrates are attached together. It should be noted that the first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0126] The first substrate 10 includes a first semiconductor substrate 11, and the first semiconductor substrate 11 includes a plurality of sensor pixels 12 that perform photoelectric conversion. The plurality of sensor pixels 12 are arranged in a matrix within the pixel region 13 of the first substrate 10.

[0127] The second substrate 20 includes a second semiconductor substrate 21, and the second semiconductor substrate 21 includes a pixel circuit 22 that outputs a pixel signal based on the charge from the sensor pixel 12. For example, one pixel circuit 22 is provided for every four sensor pixels 12; the pixel circuit 22 is a readout circuit that sequentially reads out the charge that has been photoelectrically converted from the four sensor pixels 12. In addition, the second substrate 20 includes a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction.

[0128] The third substrate 30 includes a third semiconductor substrate 31, and the third semiconductor substrate 31 includes a processing circuit 32 that performs signal processing on the pixel signal. In addition, the processing circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The processing circuit 32 can output the output voltage Vout of each sensor pixel 12 from the horizontal drive circuit 35 to the outside.

[0129] For example, the vertical drive circuit 33 sequentially selects a plurality of sensor pixels 12 in units of rows. The column signal processing circuit 34, for example, performs correlated double sampling processing on the pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. For example, the column signal processing circuit 34 performs correlated double sampling processing to extract the signal level of the pixel signal, and thus can hold the pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. For example, the system control circuit 36 controls the driving of each structure inside the processing circuit 32. This enables the processing circuit 32 to output pixel data based on the amount of light received by each sensor pixel 12 to the outside.

[0130] Figure 2This is a circuit diagram showing an example of sensor pixel 12 and pixel circuit 22. In Figure 2 In the shown circuit diagram, four sensor pixels 12 share one pixel circuit 22. The term "share" used here means that the outputs from the four sensor pixels 12 are input to a common pixel circuit 22.

[0131] Each sensor pixel 12 has components that are common to each other. Hereinafter, when differentiating the respective components of the sensor pixel 12 from each other, identification numbers (1, 2, 3, and 4) are respectively given at the end of the symbols of the components. At the same time, when it is not necessary to differentiate the respective sensor pixels 12 from each other, the giving of the identification numbers at the end of the symbols of the components is omitted.

[0132] The sensor pixel 12 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion section FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD is a photoelectric conversion element that performs photoelectric conversion to generate charge corresponding to the amount of light received. The transfer transistor TR is, for example, a MOS (Metal-Oxide-Semiconductor) transistor.

[0133] The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to the reference potential line. The drain of the transfer transistor TR is electrically connected to the floating diffusion section FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 23.

[0134] The respective floating diffusion sections FD of the sensor pixels 12 sharing the pixel circuit 22 are electrically connected to each other and electrically connected to the input terminal of the common pixel circuit 22. The pixel circuit 22 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. In addition, the pixel circuit 22 optionally includes a selection transistor SEL.

[0135] The source of the reset transistor RST (i.e., the input terminal of the pixel circuit 22) is electrically connected to the floating diffusion section FD; the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP; the gate of the reset transistor RST is electrically connected to the pixel drive line 23. The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (i.e., the output terminal of the pixel circuit 22) is electrically connected to the vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23.

[0136] The transfer transistor TR that enters the conduction state transfers the charge that has been photoelectrically converted by the photodiode PD to the floating diffusion section FD. The reset transistor RST resets the potential of the floating diffusion section FD to a predetermined potential. The reset transistor RST that enters the conduction state resets the potential of the floating diffusion section FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 22.

[0137] The amplification transistor AMP generates a signal of a voltage corresponding to the level of the charge held in the floating diffusion section FD as a pixel signal. The amplification transistor AMP constitutes a so-called source follower type amplifier and outputs a pixel signal of a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL enters the conduction state, the amplification transistor AMP amplifies the potential of the floating diffusion section FD and outputs a voltage corresponding to the amplified potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, MOS transistors respectively.

[0138] Figures 3 to 5 They are circuit diagrams respectively showing another example of the sensor pixel 12 and the pixel circuit 22.

[0139] As Figure 3 shown, the selection transistor SEL can be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23. The source of the amplification transistor AMP (i.e., the output terminal of the pixel circuit 22) is electrically connected to the vertical signal line 24, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0140] In addition, as Figure 4 or Figure 5 shown, an FD conversion gain switching transistor FDG can also be provided between the source of the reset transistor RST and the gate of the amplification transistor AMP.

[0141] The charge Q is represented by the product of the capacitance C and the voltage V; thus, when the capacitance C of the floating diffusion section FD is large, the voltage V after conversion in the amplification transistor AMP becomes low. At the same time, when the charge Q of the pixel signal is large, the floating diffusion section FD cannot hold the charge Q from the photodiode PD unless the capacitance C of the floating diffusion section FD is large enough. In addition, it is also crucial that the magnitude of the capacitance C of the floating diffusion section FD is appropriate such that the voltage V after conversion in the amplification transistor AMP does not become too high. Therefore, the FD conversion gain switching transistor FDG is provided to switch the charge-voltage conversion efficiency in the pixel circuit 22.

[0142] The FD conversion gain switching transistor FDG enters the conducting state, so that the capacitance C of the floating diffusion section FD increases by the amount of the gate capacitance of the FD conversion gain switching transistor FDG compared to the cutoff state. Therefore, by switching the conducting or cutoff state of the FD conversion gain switching transistor FDG to make the capacitance C of the floating diffusion section FD variable, the charge-voltage conversion efficiency in the pixel circuit 22 can be switched.

[0143] Figure 6 is a circuit diagram showing an example of the connection between a plurality of pixel circuits 22 and a plurality of vertical signal lines 24.

[0144] As Figure 6 shown, when a plurality of pixel circuits 22 are arranged side by side along the extending direction of the vertical signal lines 24 (e.g., the column direction), the plurality of vertical signal lines 24 can be assigned to each pixel circuit 22 one by one. It should be noted that in Figure 6 , in order to distinguish each vertical signal line 24 from each other, identification numbers (1, 2, 3, and 4) are assigned to the end of each symbol of the vertical signal line 24.

[0145] Figure 7 is a longitudinal sectional view showing an example of the sectional structure of the imaging device 1 in the stacking direction.

[0146] As Figure 7 shown, the imaging device 1 has a structure in which a first substrate 10, a second substrate 20, and a third substrate 30 are stacked in sequence. For example, on the light incident surface side (also referred to as the back side) of the first substrate 10, a color filter 40 and an optical receiving lens 50 are provided for each sensor pixel 12. That is, the imaging device 1 is a so-called back-illuminated type imaging device.

[0147] The first substrate 10 has a structure in which a first insulating layer 46 is stacked on a first semiconductor substrate 11. The first semiconductor substrate 11 is a silicon substrate and includes, for example, a p-well layer 42 in a part of or near the front surface and a photodiode PD in other regions (i.e., regions deeper than the p-well layer 42). The p-well layer 42 is formed of a p-type semiconductor region, and the photodiode PD is formed of a semiconductor region having a conductivity type (specifically, n-type) different from that of the p-well layer 42. The first semiconductor substrate 11 includes a floating diffusion portion FD inside the p-well layer 42, and the floating diffusion portion FD is a semiconductor region having a conductivity type (specifically, n-type) different from that of the p-well layer 42.

[0148] For each sensor pixel 12, the first substrate 10 includes a photodiode PD, a transfer transistor TR, and a floating diffusion portion FD. The first substrate 10 includes the transfer transistor TR and the floating diffusion portion FD in a part on the opposite side (i.e., the front surface side or the second substrate 20 side) of the light incident surface side of the first semiconductor substrate 11.

[0149] The first substrate 10 includes an element isolation portion 43 that separates the respective sensor pixels 12 from each other. The element isolation portion 43 is formed to extend in the normal direction of the main surface of the first semiconductor substrate 11 (the direction perpendicular to the front surface of the first semiconductor substrate 11) and electrically separates the adjacent respective sensor pixels 12 from each other. The element isolation portion 43 includes, for example, silicon oxide that penetrates the first semiconductor substrate 11.

[0150] The first substrate 10 includes, for example, a p-well layer 44 that contacts the side surface of the photodiode PD side of the element isolation portion 43. The p-well layer 44 is formed of a semiconductor region having a conductivity type (specifically, p-type) different from that of the photodiode PD. The first substrate 10 includes, for example, a fixed charge film 45 that contacts the back surface of the first semiconductor substrate 11. In order to suppress dark current generated due to interface states on the light receiving surface side of the first semiconductor substrate 11, the fixed charge film 45 includes an insulating film having negative fixed charges. Examples of the material of the fixed charge film 45 may include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. The fixed charge film 45 induces an electric field, thereby forming a hole accumulation layer for suppressing the generation of electrons from the interface at the interface on the light receiving surface side of the first semiconductor substrate 11.

[0151] The color filter 40 is provided on the back surface side of the first semiconductor substrate 11. Specifically, with respect to the fixed charge film 45, the color filter 40 is provided to contact the fixed charge film 45, for example, at a position opposite to the sensor pixel 12. With respect to the color filter 40 and the fixed charge film 45, the light receiving lens 50 is provided to contact the color filter 40, for example, at a position opposite to the sensor pixel 12.

[0152] The second substrate 20 includes a second insulating layer 52 stacked on the second semiconductor substrate 21. The second semiconductor substrate 21 is a silicon substrate, and includes one pixel circuit 22 for every four sensor pixels 12. The second substrate 20 includes the pixel circuits 22 in a part on the third substrate 30 side (i.e., the front side) of the second semiconductor substrate 21. The second substrate 20 is attached to the first substrate 10 such that the back surface of the second semiconductor substrate 21 faces the front side of the first semiconductor substrate 11. That is, the second substrate 20 is attached to the first substrate 10 in a back-to-back manner.

[0153] The second semiconductor substrate 21 includes a separation insulating layer 53, and a through-wiring 54 is provided inside the separation insulating layer 53. By covering the side surface of the through-wiring 54 with the separation insulating layer 53, the through-wiring 54 is electrically insulated from the second semiconductor substrate 21. The through-wiring 54 extends in the normal direction of the main surface of the second semiconductor substrate 21, and electrically connects the elements of the first substrate 10 and the elements of the second substrate 20 to each other. Specifically, the through-wiring 54 electrically connects the floating diffusion portion FD and the connection wiring 55 to each other. For example, one through-wiring 54 is provided for each sensor pixel 12.

[0154] The second substrate 20 includes a plurality of connection portions 59 that are electrically connected to the pixel circuits 22 or the second semiconductor substrate 21, for example, in the second insulating layer 52. The wiring layer 56 includes, for example, an interlayer insulating layer 57 and a plurality of pixel driving lines 23 and a plurality of vertical signal lines 24 provided inside the interlayer insulating layer 57. The wiring layer 56 includes, for example, one connection wiring 55 for every four sensor pixels 12 inside the interlayer insulating layer 57. The connection wiring 55 electrically connects the through-wiring 54 of the four sensor pixels 12 of the common pixel circuit 22 together.

[0155] The wiring layer 56 further includes a plurality of pad electrodes 58 inside the interlayer insulating layer 57. For example, each pad electrode 58 contains a metal such as copper (Cu). Each pad electrode 58 is exposed on the front surface of the wiring layer 56, and is used to attach the second substrate 20 and the third substrate 30 together, and is used to electrically connect the second substrate 20 and the third substrate 30 together. The plurality of pad electrodes 58 are provided one by one for each pixel driving line 23 and each vertical signal line 24.

[0156] Here, the second substrate 20 can be provided in a stacked structure of a plurality of semiconductor substrates and a plurality of insulating layers.

[0157] Specifically, the second substrate 20 may include two semiconductor substrates stacked in the thickness direction. For example, the second substrate 20 may be arranged such that a semiconductor substrate is further stacked on a second insulating layer 52 stacked on the second semiconductor substrate 21. For example, a transistor is provided in the semiconductor substrate further provided on the second insulating layer 52, and the transistor is electrically connected to a transistor provided in the second semiconductor substrate 21 via a connection portion 59.

[0158] That is, the pixel circuit 22 provided in the second substrate 20 may be separately provided in the second semiconductor substrate 21 and in the semiconductor substrate further stacked on the second insulating layer 52. Specifically, at least one or more of the transistors included in the pixel circuit 22, such as an amplifying transistor AMP, a reset transistor RST, and a selection transistor SEL, may be provided in the second semiconductor substrate 21, and the remaining transistors may be provided in the semiconductor substrate further stacked on the second insulating layer 52. As an example, the amplifying transistor AMP may be provided in the second semiconductor substrate 21, and the reset transistor RST and the selection transistor SEL may be provided in the semiconductor substrate further stacked on the second insulating layer 52.

[0159] Alternatively, the second substrate 20 may include three semiconductor substrates stacked in the thickness direction. For example, the second substrate 20 may be arranged such that an upper first semiconductor substrate is further stacked on a second insulating layer 52 stacked on the second semiconductor substrate 21, and an upper second semiconductor substrate is further stacked on the upper first semiconductor substrate with an insulating layer therebetween. For example, a transistor is provided in the stacked upper first semiconductor substrate and upper second semiconductor substrate, and the transistor is electrically connected to a transistor provided in the second semiconductor substrate 21 via a connection portion 59 or the like.

[0160] That is, the pixel circuit 22 provided in the second substrate 20 may be separately provided in the second semiconductor substrate 21 and in the stacked upper first semiconductor substrate and upper second semiconductor substrate. Specifically, at least one or more of the transistors included in the pixel circuit 22, such as an amplifying transistor AMP, a reset transistor RST, and a selection transistor SEL, may be provided in each of the second semiconductor substrate 21, the upper first semiconductor substrate, and the upper second semiconductor substrate. As an example, the amplifying transistor AMP may be provided in the second semiconductor substrate 21; the reset transistor RST may be provided in the upper first semiconductor substrate further provided on the second semiconductor substrate 21; and the selection transistor SEL may be provided in the upper second semiconductor substrate further provided on the upper first semiconductor substrate.

[0161] In the second substrate 20 including a plurality of semiconductor substrates stacked in the thickness direction, by separately stacking the semiconductor substrates, the area of the semiconductor substrate occupied by one pixel circuit 22 can be further reduced. By using such a second substrate 20, the imaging device 1 can further reduce the chip area of the imaging device 1.

[0162] In addition, by using such a second substrate 20, the imaging device 1 can selectively enlarge the area of any one of the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL included in the pixel circuit 22. This enables the imaging device 1 to further reduce noise by enlarging the area of the amplification transistor AMP.

[0163] The third substrate 30 includes, for example, a third insulating film 61 stacked on a third semiconductor substrate 31. The third semiconductor substrate 31 is a silicon substrate and includes a processing circuit 32. It should be noted that the third substrate 30 is attached to the second substrate 20 in such a manner that the surfaces on the front side are attached together. For this reason, in the description of each structure of the third substrate 30, the up-down relationship to be described is opposite to the up-down direction in the drawings. The third substrate 30 is attached to the second substrate 20 in such a manner that the front surface of the third semiconductor substrate 31 faces the front side of the second semiconductor substrate 21. That is, the third substrate 30 is attached to the second substrate 20 in a face-to-face manner.

[0164] The third substrate 30 includes, for example, a wiring layer 62 on the third insulating film 61. The wiring layer 62 includes, for example, an interlayer insulating layer 63 and a plurality of pad electrodes 64 provided inside the interlayer insulating layer 63 and electrically connected to the processing circuit 32. For example, each pad electrode 64 contains a metal such as copper (Cu). The pad electrodes 64 are exposed on the front surface of the wiring layer 62 and are used to attach the second substrate 20 and the third substrate 30 together and to electrically connect the second substrate 20 and the third substrate 30 together. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding between the pad electrodes 58 and 64. That is, the gate (transfer gate TG) of the transfer transistor TR is electrically connected to the processing circuit 32 via the through-wiring 54 and the pad electrodes 58 and 64.

[0165] Figure 8 and Figure 9 are schematic diagrams of examples of the cross-sectional structure of the imaging device 1 in the horizontal direction. Figure 8 and Figure 9 The upper-side diagrams in are schematic diagrams of examples of the cross-sectional structure along the cut surface Sec1 in Figure 7 respectively, and Figure 8 and Figure 9 The lower-side diagrams in respectively are schematic diagrams of examples of the cross-sectional structure along the cut surface Sec2 in Figure 7 respectively.

[0166] Figure 8 illustrates a configuration in which four sensor pixels 12 of 2×2 are arranged in a first direction V1, and Figure 9 illustrates a configuration in which four sensor pixels 12 of 2×2 are arranged in a first direction V1 and a second direction V2.

[0167] The first direction V1 is parallel to one of two arrangement directions (e.g., row direction and column direction) in which a plurality of sensor pixels 12 are arranged in a matrix (e.g., row direction). Further, the second direction V2 is parallel to an arrangement direction orthogonal to the first direction (e.g., column direction).

[0168] For example, a through-wiring 54 is provided for each sensor pixel 12, and electrically connects the floating diffusion portion FD and a connection wiring 55 described later. For example, through-wirings 47 and 48 are provided for each sensor pixel 12. The through-wiring 47 electrically connects the p-well layer 42 of the first semiconductor substrate 11 and a wiring in the second substrate 20. The through-wiring 48 electrically connects the transfer gate TG and the pixel driving line 23.

[0169] As Figure 8 shown, a plurality of through-wirings 54, a plurality of through-wirings 48, and a plurality of through-wirings 47 are arranged side by side in a strip shape in a plane of the first substrate 10 along the second direction V2 ( Figure 8 vertical direction in). Figure 8 illustrates a case where a plurality of through-wirings 54, a plurality of through-wirings 48, and a plurality of through-wirings 47 are arranged side by side in two rows along the second direction V2.

[0170] As Figure 9 shown, a plurality of through-wirings 54, a plurality of through-wirings 48, and a plurality of through-wirings 47 are arranged side by side in a strip shape in a plane of the first substrate 10 along the first direction V1 ( Figure 9 horizontal direction in). Figure 9 illustrates a case where a plurality of through-wirings 54, a plurality of through-wirings 48, and a plurality of through-wirings 47 are arranged side by side in two rows along the first direction V1.

[0171] In four sensor pixels 12 of the common pixel circuit 22, for example, four floating diffusion portions FD are arranged close to each other with an element isolation portion 43 therebetween. In four sensor pixels 12 of the common pixel circuit 22, four transfer gates TG are arranged to surround the four floating diffusion portions FD, and for example, a ring shape is formed by the four transfer gates TG.

[0172] As Figure 8As shown, the isolation insulating layer 53 includes a plurality of blocks extending in the second direction V2. The second semiconductor substrate 21 includes a plurality of island-like blocks 21A extending in the second direction V2 and arranged side by side in the second direction V2. Each block 21A includes, for example, multiple sets of reset transistors RST, amplification transistors AMP, and selection transistors SEL. A pixel circuit 22 shared by four sensor pixels 12 includes, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL present in a region corresponding to the four sensor pixels 12. For example, the pixel circuit 22 includes an amplification transistor AMP in the left adjacent block 21A of the isolation insulating layer 53 and a reset transistor RST and a selection transistor SEL in the right adjacent block 21A of the isolation insulating layer 53.

[0173] In addition, as Figure 9 shown, the isolation insulating layer 53 includes a plurality of blocks extending in the first direction V1. The second semiconductor substrate 21 includes a plurality of island-like blocks 21A extending in the first direction V1 and arranged side by side in the first direction V1. Each block 21A includes, for example, multiple sets of reset transistors RST, amplification transistors AMP, and selection transistors SEL. A pixel circuit 22 shared by four sensor pixels 12 includes, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL present in a region corresponding to the four sensor pixels 12. For example, the pixel circuit 22 includes an amplification transistor AMP in the left adjacent block 21A of the isolation insulating layer 53 and a reset transistor RST and a selection transistor SEL in the right adjacent block 21A of the isolation insulating layer 53.

[0174] Figures 10 to 13 are schematic diagrams of examples of the wiring layout in the horizontal plane of the imaging device 1. Similar to Figure 8 , Figures 10 to 13 respectively show examples of the wiring layout in the case where a pixel circuit 22 shared by four sensor pixels 12 is provided in a region corresponding to the four sensor pixels 12. Figures 10 to 13 respectively show, for example, the layout of wirings provided in different layers in the wiring layer 56.

[0175] As Figure 10 shown, for example, four through wirings 54 adjacent to each other are electrically connected to a connection wiring 55. The through wirings 54 are electrically connected to the gates of the amplification transistors AMP included in the left adjacent block 21A of the isolation insulating layer 53 and the gates of the reset transistors RST included in the right adjacent block 21A of the isolation insulating layer 53 via the connection wiring 55 and the connection portion 59.

[0176] As Figure 11As shown, for example, a power supply line VDD is arranged at a position corresponding to each pixel circuit 22 arranged side by side in the first direction V1. The power supply line VDD is electrically connected to the drains of the respective amplification transistors AMP and the drains of the respective reset transistors RST of the pixel circuits 22 arranged side by side in the first direction V1 via a connection portion 59. For example, two pixel drive lines 23 are arranged at positions corresponding to the respective pixel circuits 22 arranged side by side in the first direction V1. One pixel drive line 23 serves as, for example, a wiring RSTG that is electrically connected to the gates of the respective reset transistors RST of the pixel circuits 22 arranged side by side in the first direction V1. The other pixel drive line 23 serves as, for example, a wiring SELG that is electrically connected to the gates of the respective selection transistors SEL of the pixel circuits 22 arranged side by side in the first direction V1. For example, the source of the amplification transistor AMP and the drain of the selection transistor SEL are electrically connected to each other via a wiring 25.

[0177] As Figure 12 shown, for example, two reference potential lines VSS are arranged at positions corresponding to the respective pixel circuits 22 arranged side by side in the first direction V1. Each reference potential line VSS is electrically connected to a plurality of through wirings 47 at positions corresponding to the sensor pixels 12 arranged side by side in the second direction V2. For example, four pixel drive lines 23 are arranged at positions corresponding to the respective pixel circuits 22 arranged side by side in the first direction V1. Each of the four pixel drive lines 23 serves as a wiring TRG that is electrically connected to a through wiring 48 of one sensor pixel 12 corresponding to the respective pixel circuits 22 arranged side by side in the first direction V1. The four pixel drive lines 23 are respectively electrically connected to the gates of the transfer transistors TR of each sensor pixel 12 arranged side by side in the first direction V1. In Figure 12 order to distinguish the wirings TRG from each other, identification numbers (1, 2, 3, and 4) are assigned to the ends of the respective wirings TRG.

[0178] As Figure 13 shown, for example, a vertical signal line 24 is provided at a position corresponding to the respective pixel circuits 22 arranged side by side in the second direction V2. The vertical signal line 24 is electrically connected to the sources of the amplification transistors AMP of the respective pixel circuits 22 arranged side by side in the second direction V2.

[0179] The technology according to the present disclosure is applied to the above-described stacked imaging device 1. Hereinafter, the technology according to the present disclosure will be specifically described.

[0180] <<2. Technology According to the Present Disclosure>>

[0181] Referring to Figures 14 to 28D, the technology according to an embodiment of the present disclosure is described. The technology according to this embodiment relates to the layout of the second semiconductor substrate 21 and the separation insulating layer 53 of the second substrate 20. It should be noted that the second semiconductor substrate 21 corresponds to the "semiconductor layer" in the claims of the present application, and the separation insulating layer 53 corresponds to the "insulating layer" in the claims of the present application.

[0182] In the imaging device 1 formed by stacking three substrates, when viewed from the light incident surface, the second semiconductor substrate 21 is present behind the photodiode PD provided in the first semiconductor substrate 11. Therefore, when incident light having a long wavelength passes through the first semiconductor substrate 11, the transmitted incident light may sometimes be reflected from the back surface of the second semiconductor substrate 21.

[0183] At the same time, the through-wiring 54 that outputs the charge photoelectrically converted in the photodiode PD to the amplifying transistor AMP is provided between the first substrate 10 and the second substrate 20. The through-wiring 54 is provided inside the separation insulating layer 53 that penetrates the second semiconductor substrate 21, and electrically connects the electrode or wiring provided in the first substrate 10 and the electrode or wiring provided in the second substrate 20. The separation insulating layer 53 is provided to electrically insulate the components of the second semiconductor substrate 21 from each other, and to electrically insulate the through-wiring 54 and the second semiconductor substrate 21 from each other.

[0184] Therefore, on the back surface of the second semiconductor substrate 21 where the light transmitted through the first semiconductor substrate 11 is incident, the second semiconductor substrate 21 and the separation insulating layer 53 exist together in a manner that spans the entire surface of the pixel region 13. The separation insulating layer 53 has a lower light reflectivity than the second semiconductor substrate 21. Therefore, depending on the size and arrangement of the separation insulating layer 53, the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the first semiconductor substrate 11 may be uneven.

[0185] Here, the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the first semiconductor substrate 11 causes a decrease in the sensitivity of the sensor pixel 12 or leakage (crosstalk) to adjacent pixels. Therefore, the uneven distribution of the reflected light reflected to the first semiconductor substrate 11 increases the sensitivity difference between the pixels of the same color among the sensor pixels 12 or the unevenness of the crosstalk to adjacent pixels, resulting in a decrease in the image quality of the image captured by the imaging device 1.

[0186] Generally, the layout of the second semiconductor substrate 21 and the separation insulating layer 53 is designed in consideration of the arrangement of the through-wiring 54 passing through the separation insulating layer 53 and the layout of the wirings in the pixel circuit 22, etc. However, the three-dimensional structure and higher performance of the imaging device 1 enhance the influence on the light reflected inside the imaging device 1, resulting in the in-plane dispersion in the captured image possibly becoming obvious. Therefore, it is desirable to suppress the non-uniformity in the image captured by the imaging device 1.

[0187] The technology according to the present embodiment is conceived in view of such a situation. The technology according to the present embodiment aims to determine the layout of the separation insulating layer 53 in the second semiconductor substrate 21 in a manner corresponding to the layout of the sensor pixels 12 in the first semiconductor substrate 11. Specifically, the technology according to the present embodiment aims to arrange the separation insulating layer 53 such that the center position of the separation insulating layer 53 that divides the second semiconductor substrate 21 or the center position of the second semiconductor substrate 21 divided by the separation insulating layer 53 corresponds to the position of the optical center of the sensor pixel 12 (e.g., the center position of the photodiode PD). Thereby, the technology according to the present embodiment can make the distribution of the incident light reflected at the second semiconductor substrate 21 more uniform, so that the non-uniformity in the image captured by the imaging device 1 can be suppressed, and the image quality of the captured image can be improved.

[0188] Subsequently, with reference to ​ , the technology according to the present embodiment will be described in more detail. ​ is a longitudinal sectional view showing an example of the sectional structure of the imaging device 1 according to the present embodiment in the stacking direction.

[0189] ​ The sectional structure shown is different from the sectional structure shown in ​ in terms of the position where the separation insulating layer 53 is formed. Specifically, as shown in ​ , the separation insulating layer 53 is provided such that the center position of the separation insulating layer 53 is substantially aligned with the position of the optical center OC of the sensor pixel 12. The optical center OC of the sensor pixel 12 refers to, for example, the center in one direction of the region where the photodiode PD is provided in a plane perpendicular to the optical axis direction of the incident light. In other words, the optical center OC of the sensor pixel 12 refers to the center of the width of the photodiode PD in the direction orthogonal to the stacking direction in a sectional view of the imaging device 1 taken along the stacking direction.

[0190] Alternatively, the position of the optical center OC of the sensor pixel 12 can be defined based on elements other than the region forming the photodiode PD. For example, the position of the optical center OC of the sensor pixel 12 can be defined as the center of the width in a direction orthogonal to the stacking direction of the region defined by the element separation portion 43 in a cross-section of the imaging device 1 taken along the stacking direction, the center of the width in a direction orthogonal to the stacking direction of the color filter 40, or the center of the width in a direction orthogonal to the stacking direction of the light receiving lens 50.

[0191] The optical center OC of the sensor pixel 12 refers to the center in one direction of the region where photoelectric conversion is performed in the optical information acquisition unit in a plane perpendicular to the optical axis direction of the incident light. Therefore, the optical center OC of the sensor pixel 12 can be appropriately set according to a suitable definition based on the optical information acquisition mode in each pixel of the imaging device 1.

[0192] The optical information acquisition unit represents one or more pixels used to form one piece of optical information, and can be, for example, any one of a single pixel, the entire pixel including a plurality of sub-pixels, or each sub-pixel included in the pixel. By confirming in the pixel circuit 22 which sensor pixel 12 the charge output from has generated the pixel signal, the optical information acquisition unit can be grasped.

[0193] It is sufficient that the center position of the separation insulating layer 53 is substantially coincident with the position of the optical center OC of the sensor pixel 12 in at least one direction in a plane perpendicular to the optical axis direction of the incident light. In other words, in a cross-section of the imaging device 1 taken along the stacking direction, it is sufficient that the center position of the separation insulating layer 53 is substantially coincident with the position of the optical center OC of the sensor pixel 12 in any direction in a plane orthogonal to the stacking direction. Thereby, the separation insulating layer 53 can be arranged in the imaging device 1 to be more highly symmetric with respect to the region where optical information is acquired in the sensor pixel 12, and thus the uniformity of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the first semiconductor substrate 11 can be improved.

[0194] In addition, the center position of the separation insulating layer 53 can be substantially coincident with the position of the optical center OC of the sensor pixel 12 in a plurality of directions (or throughout the entire periphery) in a plane perpendicular to the optical axis direction of the incident light. This enables the imaging device 1 to further improve the uniformity of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the first semiconductor substrate 11.

[0195] However, the central position of the separation insulating layer 53 may not exactly coincide with the position of the optical center OC of the sensor pixel 12. For example, the central position of the region where the photodiode PD is provided and the central position of the separation insulating layer 53 may deviate by a dimension of 1 / 3 or less of the formation pitch of the photodiode PD. When the central position of the separation insulating layer 53 and the central position of the region where the photodiode PD is provided deviate by 1 / 3 or less of the formation pitch of the photodiode PD, it can be considered that the two are substantially in agreement with each other, and thus the imaging device 1 can achieve the above effects.

[0196] Here, the longer the wavelength of light, the higher its transmittance; thus, light with a longer wavelength passes through the first semiconductor substrate 11 more to enter the second semiconductor substrate 21 and the separation insulating layer 53. Therefore, the amount of light with a longer wavelength reflected from the second semiconductor substrate 21 and the separation insulating layer 53 toward the first semiconductor substrate 11 is greater.

[0197] Therefore, as described above, at least in the sensor pixel 12 that performs photoelectric conversion on the light with the longest wavelength among the light received by the imaging device 1, the central position of the separation insulating layer 53 preferably substantially coincides with the position of the optical center OC of the sensor pixel 12. Specifically, when the imaging device 1 receives light beams corresponding to red, green, and blue in each sensor pixel 12, at least in the sensor pixel 12 that receives red light with the longest wavelength, the central position of the separation insulating layer 53 preferably substantially coincides with the position of the optical center OC of the sensor pixel 12. In addition, similarly, in each of the sensor pixels 12 that receive green light and the sensor pixels 12 that receive blue light, the central position of the separation insulating layer 53 may substantially coincide with the position of the optical center OC of the sensor pixel 12.

[0198] According to the technology of this embodiment, the separation insulating layer 53 can be provided symmetrically with respect to the center of the photodiode PD provided in the first semiconductor substrate 11 in one direction on a plane perpendicular to the optical axis direction of the incident light. Therefore, the technology of this embodiment can equalize the distribution of the reflected light reflected from the second semiconductor substrate 21 to the photodiode PD. This enables the imaging device 1 according to this embodiment to reduce the non-uniformity of sensitivity between pixels of the same color or the non-uniformity of the crosstalk amount to adjacent pixels.

[0199] Note that, in the case where the second substrate 20 includes a plurality of semiconductor substrates stacked in the thickness direction, the separation insulating layer 53 in the plurality of stacked semiconductor substrates (i.e., the second semiconductor substrate 21 and at least one or more semiconductor substrates provided on the second semiconductor substrate 21) may be provided such that the respective center positions are substantially aligned with the position of the optical center OC of the sensor pixel 12. This enables the imaging device 1 according to the present embodiment to make the reflected light reflected from the second substrate 20 to the photodiode PD more uniform, thereby further reducing the non-uniformity of the sensitivity between pixels of the same color or the non-uniformity of the crosstalk amount to adjacent pixels.

[0200] Although not shown, the separation insulating layer 53 may be provided such that the center position of the second semiconductor substrate 21 divided by the separation insulating layer 53 is substantially aligned with the position of the optical center OC of the sensor pixel 12. In the technology according to the present embodiment, importantly, the separation insulating layer 53 and the second semiconductor substrate 21 that generate reflected light are arranged symmetrically with respect to the center of the photodiode PD in one direction on a plane perpendicular to the optical axis direction of the incident light. Therefore, the above effect can also be achieved by making the center position of the second semiconductor substrate 21 divided by the separation insulating layer 53 substantially coincide with the optical center OC of the sensor pixel 12 instead of the separation insulating layer 53 that divides the second semiconductor substrate 21.

[0201] Next, with reference to ​ , a modification of the planar arrangement of the sensor pixel 12 and the separation insulating layer 53 in the imaging device 1 to which the technology according to the present embodiment is applied will be described. ​ are respectively plan views of modifications of the planar arrangement of each sensor pixel 12 and the second semiconductor substrate 21.

[0202] Note that, although not shown, in ​ , the separation insulating layer 53 is provided in a region other than the region where the second semiconductor substrate 21 is provided. In addition, in ​ , the difference in the pixel corresponding to each color is represented by the difference in the type of hatching. That is, pixels to which the same type of hatching is applied are pixels that perform photoelectric conversion on light of the same color, and pixels to which different types of hatching are applied are pixels that perform photoelectric conversion on different types of light.

[0203] (First modification)

[0204] As ​As shown, for example, the pixel region 13 is formed by arranging in a matrix the red pixel PixR that photoelectrically converts light corresponding to red, the green pixel PixG that photoelectrically converts light corresponding to green, and the blue pixel PixB that photoelectrically converts light corresponding to blue. Specifically, the pixel region 13 is formed by arranging in a matrix the repeating units in the first direction V1 and the second direction V2 that are orthogonal to each other, and each repeating unit includes one red pixel PixR, two green pixels PixG, and one blue pixel PixB.

[0205] In addition, the red pixel PixR, the green pixel PixG, and the blue pixel PixB are each formed by arranging four sub-pixels in a matrix. For example, the red pixel PixR is formed by arranging the sub-pixels 12R1, 12R2, 12R3, and 12R4 in a 2×2 matrix. It should be noted that hereinafter, when it is not necessary to distinguish the sub-pixels included in the red pixel PixR, the green pixel PixG, and the blue pixel PixB from each other, these sub-pixels are collectively referred to as sub-pixel 12N.

[0206] Here, the position of the optical center OC of the sensor pixel 12 is set to a position on a straight line that passes between the sub-pixels 12N of the same color and extends in the second direction V2. Specifically, the position of the optical center OC of the red pixel PixR is set to a position on a straight line that passes between the sub-pixels 12R1 and 12R2 and between the sub-pixels 12R3 and 12R4 and extends in the second direction V2. One reason for this is that in the imaging device 1 including such a pixel region 13, in addition to the case where the optical information is individually obtained by each sub-pixel 12N, there is also a case where the optical information is obtained by the entire sub-pixels 12N of the same color. That is, the unit for obtaining the optical information can be the red pixel PixR, the green pixel PixG, and the blue pixel PixB, so the position of the optical center OC is set to a position on a straight line that passes between the sub-pixels 12N of the same color and extends in the second direction V2.

[0207] At the same time, the second semiconductor substrate 21 is arranged in a square shape corresponding to each sub-pixel 12N included in the red pixel PixR, the green pixel PixG, and the blue pixel PixB. Specifically, the second semiconductor substrate 21 is separated and insulated by the insulating layer 53 and divided in the first direction V1 and the second direction V2, and is arranged in a matrix with a square shape that is one circle smaller than each sub-pixel 12N and spaced apart from each other.

[0208] Therefore, in ​In the planar arrangement shown, in the first direction V1, the center position of the region where the separation insulating layer 53 is provided and the position of the optical center OC of the sensor pixel 12 are substantially the same as each other. According to this planar arrangement, the imaging device 1 can make the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the photodiode PD more uniform.

[0209] (Second modification)

[0210] As ​ shown, in the second modification, similar to the first modification, the red pixels PixR, the green pixels PixG, and the blue pixels PixB are arranged in a matrix in the pixel region 13. In addition, similar to the first modification, the red pixels PixR, the green pixels PixG, and the blue pixels PixB are each constituted by arranging four sub-pixels in a matrix.

[0211] Here, similar to the first modification, the position of the optical center OC of the sensor pixel 12 is set to a position on a straight line that passes between the sub-pixels 12N of the same color and extends in the second direction V2. Specifically, the position of the optical center OC of the red pixel PixR is set to a position on a straight line that passes between the sub-pixels 12R1 and 12R2 and between the sub-pixels 12R3 and 12R4 and extends in the second direction V2, for example.

[0212] Meanwhile, the second semiconductor substrate 21 is provided in a longitudinal shape that extends in the second direction V2 in a manner corresponding to each sub-pixel 12N included in the red pixels PixR, the green pixels PixG, and the blue pixels PixB. Specifically, the second semiconductor substrate 21 is divided by the separation insulating layer 53 in the first direction V1 and is provided in a longitudinal shape that extends in the second direction V2 and is spaced apart from each other in the row direction.

[0213] Therefore, in ​ the planar arrangement shown, in the first direction V1, the center position of the region where the separation insulating layer 53 is provided and the position of the optical center OC of the sensor pixel 12 are substantially the same as each other. According to this planar arrangement, the imaging device 1 can make the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the photodiode PD uniform by means of the separation insulating layer 53 having a simpler planar arrangement than the first modification.

[0214] (Third modification)

[0215] As ​As shown, in the third variant, similar to the first variant, red pixels PixR, green pixels PixG, and blue pixels PixB are arranged in a matrix in the pixel region 13. Additionally, similar to the first variant, the red pixels PixR, green pixels PixG, and blue pixels PixB are each formed by arranging four sub-pixels in a matrix.

[0216] Here, different from the first variant, the position of the optical center OC of the sensor pixel 12 can be set to a position on a straight line that passes between sub-pixels 12N of the same color and extends in the first direction V1. Specifically, the position of the optical center OC of the red pixel PixR can be set, for example, to a position on a straight line that passes between sub-pixels 12R1 and 12R3 and between sub-pixels 12R2 and 12R4 and extends in the first direction V1. In the pixel region 13 where red pixels PixR, green pixels PixG, and blue pixels PixB are arranged in a matrix, the first direction V1 and the second direction V2 are interchangeable. Therefore, the optical center OC of the sensor pixel 12 can be set in the first direction V1 or can be set in the second direction V2.

[0217] Meanwhile, the second semiconductor substrate 21 is arranged in a longitudinal shape extending in the first direction V1 in a manner corresponding to each sub-pixel 12N included in the red pixels PixR, green pixels PixG, and blue pixels PixB. Specifically, the second semiconductor substrate 21 is separated by the isolation insulating layer 53 in the second direction V2 and is arranged in a longitudinal shape extending in the first direction V1 and spaced apart from each other in the column direction.

[0218] Therefore, in ​ the planar arrangement shown, in the second direction V2, the central position of the region where the isolation insulating layer 53 is provided and the position of the optical center OC of the sensor pixel 12 are substantially coincident with each other. According to this planar arrangement, similar to the second variant, the imaging device 1 can equalize the distribution of the reflected light reflected from the second semiconductor substrate 21 and the isolation insulating layer 53 to the photodiode PD.

[0219] (Fourth Variant)

[0220] As ​ shown, in the fourth variant, similar to the first variant, red pixels PixR, green pixels PixG, and blue pixels PixB are arranged in a matrix in the pixel region 13. Additionally, similar to the first variant, the red pixels PixR, green pixels PixG, and blue pixels PixB are each formed by arranging four sub-pixels in a matrix.

[0221] Here, similar to the first modification, the position of the optical center OC of the sensor pixel 12 is set to a position on a straight line that passes between sub-pixels 12N of the same color and extends in the second direction V2. Specifically, the position of the optical center OC of the red pixel PixR is set to a position on a straight line that passes, for example, between sub-pixels 12R1 and 12R2 and between sub-pixels 12R3 and 12R4 and extends in the second direction V2.

[0222] Meanwhile, the second semiconductor substrate 21 is arranged in a square shape in a manner corresponding to the pixel boundaries of the sub-pixels 12N included in the red pixel PixR, the green pixel PixG, and the blue pixel PixB in the first direction V1. Specifically, the second semiconductor substrate 21 is divided by the separation insulating layer 53 in the first direction V1 and the second direction V2 and is arranged in a matrix with a square shape that is one pixel smaller than the sub-pixels 12N and spaced apart from each other. That is, the second semiconductor substrate 21 is arranged in a matrix that is offset by 1 / 2 pitch from the matrix arrangement of the sub-pixels 12N in the first direction V1.

[0223] Therefore, in ​ the planar arrangement shown, in the first direction V1, the central position of the second semiconductor substrate 21 divided by the separation insulating layer 53 and the position of the optical center OC of the sensor pixel 12 are substantially the same as each other. According to this planar arrangement, similar to the first modification, the imaging device 1 can make the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the photodiode PD more uniform.

[0224] (Fifth modification)

[0225] As ​ shown, in the fifth modification, similar to the first modification, the red pixel PixR, the green pixel PixG, and the blue pixel PixB are arranged in a matrix in the pixel region 13. Additionally, similar to the first modification, the red pixel PixR, the green pixel PixG, and the blue pixel PixB are each formed by arranging four sub-pixels in a matrix.

[0226] Here, similar to the first modification, the position of the optical center OC of the sensor pixel 12 is set to a position on a straight line that passes between sub-pixels 12N of the same color and extends in the second direction V2. Specifically, the position of the optical center OC of the red pixel PixR is set to a position on a straight line that passes, for example, between sub-pixels 12R1 and 12R2 and between sub-pixels 12R3 and 12R4 and extends in the second direction V2.

[0227] Meanwhile, the second semiconductor substrate 21 is arranged in a longitudinal shape extending in the second direction V2 in a manner corresponding to the pixel boundaries of the sub-pixels 12N included in the red pixel PixR, the green pixel PixG, and the blue pixel PixB in the first direction V1. Specifically, the second semiconductor substrate 21 is separated by the separation insulating layer 53 in the first direction V1 and arranged in a longitudinal shape extending in the second direction V2, being spaced apart from each other in the row direction. That is, the second semiconductor substrate 21 is arranged in a strip shape that is offset by 1 / 2 pitch in the first direction V1 from the matrix arrangement of the sub-pixels 12N and extends in the second direction V2.

[0228] Therefore, in ​ the planar arrangement shown, in the first direction V1, the central position of the second semiconductor substrate 21 divided by the separation insulating layer 53 and the position of the optical center OC of the sensor pixel 12 are substantially in agreement with each other. According to this planar arrangement, through the separation insulating layer 53 with a simpler planar arrangement than the first variant, the imaging device 1 can equalize the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the photodiode PD.

[0229] (Sixth Variant)

[0230] As ​ shown, in the sixth variant, similar to the fourth variant, the red pixel PixR, the green pixel PixG, and the blue pixel PixB are arranged in a matrix in the pixel region 13. Additionally, similar to the first variant, the red pixel PixR, the green pixel PixG, and the blue pixel PixB are each composed of four sub-pixels arranged in a matrix.

[0231] Here, the position of the optical center OC of the sensor pixel 12 can be set to a position on a straight line that passes between the sub-pixels 12N of the same color and extends in the first direction V1. Specifically, the position of the optical center OC of the red pixel PixR can be set, for example, to a position on a straight line that passes between the sub-pixels 12R1 and 12R3 and between the sub-pixels 12R2 and 12R4 and extends in the first direction V1. In the pixel region 13 where the red pixel PixR, the green pixel PixG, and the blue pixel PixB are arranged in a matrix, the first direction V1 and the second direction V2 are interchangeable. Therefore, the optical center OC of the sensor pixel 12 can be set in the first direction V1 or can be set in the second direction V2.

[0232] Meanwhile, the second semiconductor substrate 21 is arranged in a longitudinal shape extending in the first direction V1 in a manner corresponding to the pixel boundaries of the sub-pixels 12N included in the red pixel PixR, the green pixel PixG, and the blue pixel PixB in the second direction V2. Specifically, the second semiconductor substrate 21 is divided by the separation insulating layer 53 in the second direction V2 and is arranged in a longitudinal shape extending in the first direction V1 and spaced apart from each other in the column direction. That is, the second semiconductor substrate 21 is arranged in a strip shape that is offset by 1 / 2 pitch in the second direction V2 from the matrix arrangement of the sub-pixels 12N and extends in the first direction V1.

[0233] Therefore, in ​ the planar arrangement shown, in the second direction V2, the central position of the second semiconductor substrate 21 divided by the separation insulating layer 53 and the position of the optical center OC of the sensor pixel 12 are substantially aligned with each other. According to this planar arrangement, similar to the fifth modification, the imaging device 1 can equalize the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the photodiode PD.

[0234] (Seventh Modification)

[0235] As ​ shown, for example, the pixel region 13 is composed of a red pixel 12R that photoelectrically converts light corresponding to red, a green pixel 12G that photoelectrically converts light corresponding to green, and a blue pixel 12B that photoelectrically converts light corresponding to blue, which are arranged in a matrix. Specifically, the pixel region 13 is composed of repeating units arranged in a matrix in the first direction V1 and the second direction V2 that are orthogonal to each other, and each repeating unit includes one red pixel 12R, two green pixels 12G, and one blue pixel 12B. Hereinafter, without distinguishing the red pixel 12R, the green pixel 12G, and the blue pixel 12B from each other, these pixels are collectively referred to as the sensor pixel 12.

[0236] Here, the position of the optical center OC of the sensor pixel 12 is set to a position on a straight line that passes through the center of the sensor pixel 12 in the first direction V1 and extends in the second direction V2. In the imaging device 1 having such a pixel region 13, each of the red pixel 12R, the green pixel 12G, and the blue pixel 12B serves as a unit for acquiring optical information, so the position on the straight line passing through the center of the sensor pixel 12 is the position of the optical center OC. In addition, in the pixel region 13, the optical center OC is set for the red pixel 12R that photoelectrically converts red light, which has the longest wavelength among red light, green light, and blue light. One reason is that red light, which has the longest wavelength among red light, green light, and blue light, is most likely to pass through the first semiconductor substrate 11 and be reflected at the second semiconductor substrate 21 and the separation insulating layer 53.

[0237] Meanwhile, the second semiconductor substrate 21 is arranged in a square shape corresponding to the blue pixels 12B that are arranged obliquely with respect to the red pixels 12R. Specifically, the second semiconductor substrate 21 is divided by the separation insulating layer 53 in the first direction V1 and the second direction V2, and is arranged in a square shape that is one size larger than the blue pixels 12B and spaced apart from each other in a matrix.

[0238] Therefore, in ​ the planar arrangement shown, in the first direction V1, the center position of the region where the separation insulating layer 53 is provided and the position of the optical center OC of the sensor pixel 12 are substantially the same as each other. According to this planar arrangement, the imaging device 1 can make the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the photodiode PD more uniform.

[0239] (Eighth modification)

[0240] As ​ shown, in the eighth modification, similar to the seventh modification, the red pixels 12R, the green pixels 12G, and the blue pixels 12B are arranged in a matrix in the pixel region 13.

[0241] Here, similar to the seventh modification, the position of the optical center OC of the sensor pixel 12 is set to a position on a straight line that passes through the center of the sensor pixel 12 in the first direction V1 and extends in the second direction V2. In addition, in the pixel region 13, the optical center OC is set for the red pixels 12R that perform photoelectric conversion on red light, which has the longest wavelength among red light, green light, and blue light.

[0242] Meanwhile, the second semiconductor substrate 21 is arranged in a longitudinal shape that extends in the second direction V2 corresponding to the columns in which the green pixels 12G and the blue pixels 12B are arranged. Specifically, the second semiconductor substrate 21 is divided by the separation insulating layer 53 in the first direction V1, and is arranged in a longitudinal shape that extends in the second direction V2 and is spaced apart from each other in the row direction.

[0243] Therefore, in ​ the planar arrangement shown, in the first direction V1, the center position of the region where the separation insulating layer 53 is provided and the position of the optical center OC of the sensor pixel 12 are substantially the same as each other. According to this planar arrangement, the imaging device 1 can make the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the photodiode PD uniform by the separation insulating layer 53 with a simpler planar arrangement than the seventh modification.

[0244] (Ninth modification)

[0245] As ​As shown, in the ninth variant, similar to the seventh variant, the red pixels 12R, green pixels 12G, and blue pixels 12B are arranged in a matrix in the pixel region 13.

[0246] Here, different from the seventh variant, the position of the optical center OC of the sensor pixel 12 can be set to a position on a straight line that passes through the center of the sensor pixel 12 in the second direction V2 and extends in the first direction V1. The optical center OC is set for the red pixel 12R that performs photoelectric conversion on red light, which has the longest wavelength among red, green, and blue light. In the pixel region 13 where the red pixels 12R, green pixels 12G, and blue pixels 12B are arranged in a matrix, the first direction V1 and the second direction V2 are interchangeable. Thus, the optical center OC of the sensor pixel 12 can be set in the first direction V1 or can be set in the second direction V2.

[0247] Meanwhile, the second semiconductor substrate 21 is arranged in a longitudinal shape extending in the first direction V1 in a manner corresponding to the rows in which the green pixels 12G and blue pixels 12B are arranged. Specifically, the second semiconductor substrate 21 is divided by the separation insulating layer 53 in the second direction V2 and is arranged in a longitudinal shape extending in the first direction V1 and spaced apart from each other in the column direction.

[0248] Therefore, in ​ the planar arrangement shown, in the second direction V2, the center position of the region where the separation insulating layer 53 is arranged and the position of the optical center OC of the sensor pixel 12 are substantially in agreement with each other. According to this planar arrangement, similar to the eighth variant, the imaging device 1 can equalize the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the photodiode PD.

[0249] (Tenth Variant)

[0250] As ​ shown, in the tenth variant, similar to the seventh variant, the red pixels 12R, green pixels 12G, and blue pixels 12B are arranged in a matrix in the pixel region 13.

[0251] Here, similar to the seventh variant, the position of the optical center OC of the sensor pixel 12 is set to a position on a straight line that passes through the center of the sensor pixel 12 in the first direction V1 and extends in the second direction V2. Additionally, in the pixel region 13, the optical center OC is set for the red pixel 12R that performs photoelectric conversion on red light, which has the longest wavelength among red, green, and blue light.

[0252] Meanwhile, the second semiconductor substrate 21 is arranged in a square shape corresponding to the red pixels 12R. Specifically, the second semiconductor substrate 21 is divided by the separation insulating layer 53 in the first direction V1 and the second direction V2, and is arranged in a square shape one circle larger than the red pixels 12R and spaced apart from each other in a matrix.

[0253] Therefore, in ​ the planar arrangement shown, in the first direction V1, the central positions of the second semiconductor substrates 21 divided by the separation insulating layer 53 and the optical centers OC of the sensor pixels 12 are substantially aligned with each other. According to this planar arrangement, similar to the seventh modification, the imaging device 1 can make the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the photodiode PD more uniform.

[0254] (Eleventh modification)

[0255] As ​ shown, in the eleventh modification, similar to the seventh modification, the red pixels 12R, the green pixels 12G, and the blue pixels 12B are arranged in a matrix in the pixel region 13.

[0256] Here, similar to the seventh modification, the position of the optical center OC of the sensor pixel 12 is set to a position on a straight line passing through the center of the sensor pixel 12 in the first direction V1 and extending in the second direction V2. In addition, in the pixel region 13, the optical center OC is set for the red pixel 12R that performs photoelectric conversion on red light, which has the longest wavelength among red light, green light, and blue light.

[0257] Meanwhile, the second semiconductor substrate 21 is arranged in a longitudinal shape extending in the second direction V2 corresponding to the columns in which the red pixels 12R and the green pixels 12G are arranged. Specifically, the second semiconductor substrate 21 is divided by the separation insulating layer 53 in the first direction V1 and is arranged in a longitudinal shape extending in the second direction V2 and spaced apart from each other in the row direction.

[0258] Therefore, in ​ the planar arrangement shown, in the first direction V1, the central positions of the second semiconductor substrates 21 divided by the separation insulating layer 53 and the optical centers OC of the sensor pixels 12 are substantially aligned with each other. According to this planar arrangement, through the separation insulating layer 53 with a simpler planar arrangement than the seventh modification, the imaging device 1 can make the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 uniform.

[0259] (Twelfth modification)

[0260] As ​As shown, in the twelfth variant, similar to the seventh variant, red pixels 12R, green pixels 12G, and blue pixels 12B are arranged in a matrix in the pixel region 13.

[0261] Here, different from the seventh variant, the position of the optical center OC of the sensor pixel 12 can be set to a position on a straight line that passes through the center of the sensor pixel 12 in the second direction V2 and extends in the first direction V1. The optical center OC is set for the red pixel 12R that performs photoelectric conversion on red light, which has the longest wavelength among red, green, and blue light. In the pixel region 13 where the red pixels 12R, green pixels 12G, and blue pixels 12B are arranged in a matrix, the first direction V1 and the second direction V2 are interchangeable, so the optical center OC of the sensor pixel 12 can be set in the first direction V1 or can be set in the second direction V2.

[0262] Meanwhile, the second semiconductor substrate 21 is provided in a longitudinal shape extending in the first direction V1 in a manner corresponding to the rows in which the red pixels 12R and the green pixels 12G are arranged. Specifically, the second semiconductor substrate 21 is divided by the separation insulating layer 53 in the second direction V2 and is provided in a longitudinal shape extending in the first direction V1 and spaced apart from each other in the column direction.

[0263] Therefore, in ​ the planar arrangement shown, in the second direction V2, the central position of the second semiconductor substrate 21 divided by the separation insulating layer 53 and the position of the optical center OC of the sensor pixel 12 are substantially in agreement with each other. According to this planar arrangement, similar to the eleventh variant, the imaging device 1 can equalize the distribution of the reflected light reflected from the second semiconductor substrate 21 and the separation insulating layer 53 to the photodiode PD.

[0264] Subsequently, with reference to ​ , a further variant of the technology according to this embodiment will be described. ​ are respectively schematic longitudinal sectional views of the partial sectional structure of the imaging device 1 according to the thirteenth variant. ​ are respectively schematic longitudinal sectional views of the partial sectional structure of the imaging device 1 according to the fourteenth variant.

[0265] (Thirteenth Variant)

[0266] As ​ shown, the imaging device 1 according to the thirteenth variant includes a first semiconductor substrate 11, color filters 40R and 40G, a light receiving lens 50, a first insulating layer 46, a second semiconductor substrate 21, and a first antireflection film 71. That is, the imaging device 1 according to the thirteenth variant is the same as ​The imaging device 1 shown in etc. is different in that a first antireflection film 71 is provided between the first insulating layer 46 and the second semiconductor substrate 21.

[0267] The first semiconductor substrate 11 includes photodiodes PD1, PD2, PD3, and PD4 (referred to as photodiodes PD without distinguishing them from each other) separated from each other by the element isolation portion 43. Although for convenience, ​ only the photodiodes PD1, PD2, PD3, and PD4 are shown respectively, needless to say, the photodiodes PD are Figures 27A to 27D arranged in a matrix on each paper surface in a manner extending in the normal direction of each paper surface of Figures 27A to 27D each paper surface.

[0268] Color filters 40R and 40G and light receiving lenses 50 are provided on the back side (light receiving surface side) of the first semiconductor substrate 11.

[0269] The color filter 40R is, for example, an optical filter that selectively transmits light in a wavelength band corresponding to red, and the color filter 40G is an optical filter that selectively transmits light in a wavelength band corresponding to green. The light receiving lens 50 is, for example, a microlens, and converges light to enter the photodiode PD. It should be noted that a color filter that selectively transmits light in a wavelength band corresponding to blue is provided on Figures 27A to 27D the front side or the back side of each paper surface, and thus is not shown in Figures 27A to 27D each structure.

[0270] Here, in Figures 27A to 27C each structure, the correspondence between the photodiode PD and the color filters 40R and 40G and the light receiving lens 50 is different. In addition, in Figure 27D each structure, the correspondence between the photodiode PD and the second semiconductor substrate 21 or the separation insulating layer 53 is different from Figures 27A to 27C the correspondence in each structure shown in etc.

[0271] In Figure 27A one example shown in etc., a color filter 40R or 40G and a light receiving lens 50 are provided in a one-to-one correspondence for each of the photodiodes PD1, PD2, PD3, and PD4.

[0272] In Figure 27B one example shown in etc., one color filter 40R is provided for two photodiodes PD1 and PD2, and one color filter 40G is provided for two photodiodes PD3 and PD4. In addition, light receiving lenses 50 are provided in a one-to-one correspondence for each of the photodiodes PD1, PD2, PD3, and PD4.

[0273] InFigure 27C In one example shown, a color filter 40R is provided for two photodiodes PD1 and PD2, and a color filter 40G is provided for two photodiodes PD3 and PD4. Additionally, a light receiving lens 50 is provided for two photodiodes PD1 and PD2, and a light receiving lens 50 is provided for two photodiodes PD3 and PD4.

[0274] As Figures 27A to 27C shown, the color filters 40R and 40G and the light receiving lens 50 can be provided in a one-to-one correspondence for one photodiode PD (i.e., one pixel), or the color filters 40R and 40G and the light receiving lens 50 can be shared by multiple photodiodes PD (i.e., multiple pixels).

[0275] Figures 27A to 27C Examples are respectively shown where the position of the optical center OC of the sensor pixel 12 and the center position of the second semiconductor substrate 21 divided by the separation insulating layer 53 are substantially the same as each other. At the same time, as Figure 27D shown, the position of the optical center OC of the sensor pixel 12 can be substantially the same as the center position of the separation insulating layer 53. In the technology according to this embodiment, it is important that the separation insulating layer 53 and the second semiconductor substrate 21 are arranged symmetrically with respect to the position of the optical center OC of the sensor pixel 12. Therefore, the position of the optical center OC of the sensor pixel 12 can be substantially the same as the center position of the separation insulating layer 53, or can be substantially the same as the center position of the second semiconductor substrate 21.

[0276] The first insulating layer 46 is stacked on the front side of the first semiconductor substrate 11 and attached to the back side of the second semiconductor substrate 21. The second semiconductor substrate 21 is divided by the separation insulating layer 53 and attached to the first insulating layer 46 on the back side.

[0277] In the thirteenth modification, a first antireflection film 71 is provided between the second semiconductor substrate 21 and the first insulating layer 46. The first antireflection film 71 is a thin film containing a material whose refractive index value is between the refractive index of the material contained in the first insulating layer 46 and the refractive index of the material contained in the second semiconductor substrate 21. By further gradually changing the refractive index in the optical path from the first insulating layer 46 to the second semiconductor substrate 21, the first antireflection film 71 can suppress the reflection of incident light between the first insulating layer 46 and the second semiconductor substrate 21.

[0278] For example, when the first insulating layer 46 is made of aluminum oxide (AlO x)When the first semiconductor substrate 11 is formed of silicon (Si) and the second semiconductor substrate 21 is formed of silicon (Si), the first antireflection film 71 can be formed of silicon nitride (SiN) having a refractive index between the refractive index of aluminum oxide and the refractive index of silicon.

[0279] In the imaging device 1 according to the thirteenth modification, by providing the first antireflection film 71 at the attachment interface between the first insulating layer 46 and the second semiconductor substrate 21, reflection itself from the second semiconductor substrate 21 to the first semiconductor substrate 11 can be suppressed. Therefore, the imaging device 1 according to the thirteenth modification can further reduce the non-uniformity of sensitivity between pixels of the same color or the non-uniformity of the amount of crosstalk to adjacent pixels.

[0280] (Fourteenth modification)

[0281] As Figures 28A to 28D shown, the imaging device 1 according to the fourteenth modification includes a first semiconductor substrate 11, color filters 40R and 40G, a light receiving lens 50, a first insulating layer 46, a second semiconductor substrate 21, a first antireflection film 71, and a second antireflection film 72. That is, the imaging device 1 according to the fourteenth modification is different from the imaging device 1 shown in Figure 14 etc. in that a first antireflection film 71 and a second antireflection film 72 are provided between the first insulating layer 46 and the second semiconductor substrate 21.

[0282] The first semiconductor substrate 11 includes photodiodes PD1, PD2, PD3, and PD4 (referred to as photodiodes PD without distinguishing them from each other) separated from each other by an element isolation portion 43. Although for convenience Figures 28A to 28D only photodiodes PD1, PD2, PD3, and PD4 are shown respectively, needless to say, the photodiodes PD are arranged in a matrix pattern so as to extend in the normal direction of each paper surface of Figures 28A to 28D each paper surface of Figures 28A to 28D each paper surface.

[0283] The color filters 40R and 40G and the light receiving lens 50 are provided on the back side (light receiving surface side) of the first semiconductor substrate 11.

[0284] The color filter 40R is, for example, an optical filter that selectively transmits light in a wavelength band corresponding to red, and the color filter 40G is an optical filter that selectively transmits light in a wavelength band corresponding to green. The light receiving lens 50 is, for example, a microlens, and converges light to enter the photodiode PD. It should be noted that a color filter that selectively transmits light in a wavelength band corresponding to blue is provided on the front side or the back side of each paper surface of Figures 28A to 28D each paper surface, and thus is not shown in Figures 28A to 28D this figure.

[0285] Here, in Figures 28A to 28C the correspondence relationships among the photodiode PD, the color filters 40R and 40G, and the light receiving lens 50 are different. Additionally, in Figure 28D the correspondence relationship between the photodiode PD and the second semiconductor substrate 21 or the separation insulating layer 53 is different from that in each structure shown in Figures 28A to 28C .

[0286] In Figure 28A one example shown, color filters 40R or 40G and the light receiving lens 50 are provided in a one-to-one correspondence for each of the photodiodes PD1, PD2, PD3, and PD4.

[0287] In Figure 28B one example shown, one color filter 40R is provided for two photodiodes PD1 and PD2, and one color filter 40G is provided for two photodiodes PD3 and PD4. Additionally, the light receiving lens 50 is provided in a one-to-one correspondence for each of the photodiodes PD1, PD2, PD3, and PD4.

[0288] In Figure 28C one example shown, one color filter 40R is provided for two photodiodes PD1 and PD2, and one color filter 40G is provided for two photodiodes PD3 and PD4. Additionally, one light receiving lens 50 is provided for two photodiodes PD1 and PD2, and one light receiving lens 50 is provided for two photodiodes PD3 and PD4.

[0289] As Figures 28A to 28C shown, color filters 40R and 40G and the light receiving lens 50 can be provided in a one-to-one correspondence for one photodiode PD (i.e., one pixel), or color filters 40R and 40G and the light receiving lens 50 can be shared by multiple photodiodes PD (i.e., multiple pixels).

[0290] Figures 28A to 28C Examples are respectively shown where the position of the optical center OC of the sensor pixel 12 and the center position of the second semiconductor substrate 21 divided by the separation insulating layer 53 are substantially the same as each other. Meanwhile, as Figure 28D shown, the position of the optical center OC of the sensor pixel 12 can be substantially the same as the center position of the separation insulating layer 53. In the technology according to this embodiment, importantly, the separation insulating layer 53 and the second semiconductor substrate 21 are arranged symmetrically with respect to the position of the optical center OC of the sensor pixel 12. Therefore, the position of the optical center OC of the sensor pixel 12 can be substantially the same as the center position of the separation insulating layer 53, or can be substantially the same as the center position of the second semiconductor substrate 21.

[0291] The first insulating layer 46 is stacked on the front side of the first semiconductor substrate 11 and attached to the back side of the second semiconductor substrate 21. The second semiconductor substrate 21 is divided by the separation insulating layer 53 and attached to the first insulating layer 46 on the back side.

[0292] In the fourteenth modification, the first antireflection film 71 and the second antireflection film 72 are provided between the second semiconductor substrate 21 and the first insulating layer 46. The second antireflection film 72 is a thin film containing a material having a refractive index value between the refractive index of the material contained in the first insulating layer 46 and the refractive index of the material contained in the first antireflection film 71. In addition, the first antireflection film 71 is a thin film containing a material having a refractive index value between the refractive index of the material contained in the second antireflection film 72 and the refractive index of the material contained in the second semiconductor substrate 21. By changing the refractive index in a more stepwise manner than in the thirteenth modification in the optical path from the first insulating layer 46 to the second semiconductor substrate 21, the first antireflection film 71 and the second antireflection film 72 can further suppress the reflection of incident light between the first insulating layer 46 and the first antireflection film 71.

[0293] For example, when the first insulating layer 46 is formed of aluminum oxide (AlO x ) and the second semiconductor substrate 21 is formed of silicon (Si), the first antireflection film 71 and the second antireflection film 72 can be formed of silicon nitride (SiN) having a refractive index between the refractive index of aluminum oxide and the refractive index of silicon, respectively.

[0294] In the imaging device 1 according to the fourteenth modification, by providing the first antireflection film 71 and the second antireflection film 72 at the attachment interface between the first insulating layer 46 and the second semiconductor substrate 21, the reflection itself from the second semiconductor substrate 21 to the first semiconductor substrate 11 can be suppressed. Therefore, the imaging device 1 according to the fourteenth modification can further reduce the non-uniformity of sensitivity between pixels of the same color or the non-uniformity of the amount of crosstalk to adjacent pixels.

[0295] <<3. Modification Examples>>

[0296] Hereinafter, modification examples of the imaging device 1 to which the technology according to the present disclosure is applied will be described. Note that, in the following modification examples, components the same as those of the above-described imaging device 1 are denoted by the same reference numerals.

[0297] (First Modification Example)

[0298] First, with reference to Figure 29 , a first modification example, which is a modification example of the cross-sectional structure of the imaging device 1 in the stacking direction, will be described. Figure 29 is Figure 7Longitudinal sectional view of a modified example of the cross-sectional structure shown

[0299] As Figure 29 shown, in the imaging device 1 according to the first modified example, the transfer transistor TR includes a planar transfer gate TG. Therefore, the transfer gate TG does not penetrate the p-well layer 42 and is formed on the front surface of the first semiconductor substrate 11. Even when the planar transfer gate TG is used for the transfer transistor TR, the imaging device 1 can achieve an effect similar to the above effect.

[0300] (Second Modified Example)

[0301] Next, with reference to Figure 30 , a second modified example of the cross-sectional structure of the imaging device 1 in the stacking direction will be described. Figure 30 is Figure 7 Longitudinal sectional view of a modified example of the cross-sectional structure shown

[0302] As Figure 30 shown, in the imaging device 1 according to the second modified example, the electrical connection between the second substrate 20 and the third substrate 30 is formed in a region corresponding to the peripheral region 14 in the first substrate 10. The peripheral region 14 is a region corresponding to a frame region provided along the periphery of the pixel region 13 of the first substrate 10. In the imaging device 1 according to the second modified example, the second substrate 20 includes a plurality of pad electrodes 58 in the region corresponding to the peripheral region 14, and the third substrate 30 includes a plurality of pad electrodes 64 in the region corresponding to the peripheral region 14. This enables the second substrate 20 and the third substrate 30 to be electrically connected to each other by bonding between the pad electrodes 58 and 64 provided in the region corresponding to the peripheral region 14. Therefore, compared with the case where the pad electrodes 58 and 64 are bonded together in the region corresponding to the pixel region 13, the imaging device 1 according to the second modified example can reduce the possibility that the bonding between the pad electrodes 58 and 64 may affect the pixel region 13.

[0303] (Third Modified Example)

[0304] Furthermore, with reference to Figures 31 to 36 , a structural example of the imaging device 1B according to the third modified example will be described. Figures 31 to 33 are cross-sectional views of a structural example of the imaging device 1B according to the third modified example in the thickness direction, respectively. Figures 34 to 36 are cross-sectional views of a layout example of a plurality of pixel units PU of the imaging device 1B according to the third modified example in the horizontal direction, respectively. It should be noted that Figures 34 to 36 each cross-sectional view shown is only a schematic diagram and is not a diagram intended to strictly and precisely show the actual structure. In Figures 34 to 36In each of the cross-sectional views shown, in order to describe the structure of the imaging device 1B in an easily understandable manner on the paper surface, the horizontal positions of the transistors and impurity diffusion layers are intentionally changed at positions sec1 to sec3.

[0305] Specifically, in the pixel unit PU of the imaging device 1B shown in Figure 31 , the cross-section at position sec1 corresponds to the cross-section taken along the line A1 - A1' in Figure 34 ; the cross-section at position sec2 corresponds to the cross-section taken along the line B1 - B1' in Figure 35 ; the cross-section at position sec3 corresponds to the cross-section taken along the line C1 - C1' in Figure 36 . Similarly, in the imaging device 1B shown in Figure 32 , the cross-section at position sec1 corresponds to the cross-section taken along the line A2 - A2' in Figure 34 ; the cross-section at position sec2 corresponds to the cross-section taken along the line B2 - B2' in Figure 35 ; the cross-section at position sec3 corresponds to the cross-section taken along the line C2 - C2' in Figure 36 . In the imaging device 1B shown in Figure 33 , the cross-section at position sec1 corresponds to the cross-section taken along the line A3 - A3' in Figure 34 ; the cross-section at position sec2 corresponds to the cross-section taken along the line B3 - B3' in Figure 35 ; the cross-section at position sec3 corresponds to the cross-section taken along the line C3 - C3' in Figure 36 .

[0306] As shown in Figures 31 to 36 , the second substrate 20 is stacked on the front side (one surface) 10a of the first substrate (bottom substrate) 10. A photodiode PD, a transfer transistor TR, and a floating diffusion section FD are provided on the front side 10a of the first substrate 10. The photodiode PD, the transfer transistor TR, and the floating diffusion section FD are provided for each sensor pixel 12.

[0307] The other side (e.g., the back side) of the first substrate 10 is a light incident surface. The imaging device 1B is a back-illuminated type imaging device and includes a color filter and a light receiving lens on the back surface. The color filter and the light receiving lens are provided for each sensor pixel 12.

[0308] The first semiconductor substrate 11 of the first substrate 10 includes, for example, a silicon substrate. The first semiconductor substrate 11 includes a well layer WE of a first conductivity type (e.g., p-type) in a part of and near the front surface, and includes a photodiode PD of a second conductivity type (e.g., n-type) in a region deeper than the well layer WE. In addition, the well layer WE includes a well contact layer having a higher p-type concentration than the well layer WE and an n-type floating diffusion portion FD in the well layer WE. The well contact layer is provided to reduce the contact resistance between the well layer WE and the wiring.

[0309] The first semiconductor substrate 11 includes an element isolation layer 16 that electrically separates adjacent sensor pixels 12 from each other. The element isolation layer 16 includes, for example, an STI (Shallow Trench Isolation) structure and extends in the depth direction of the first semiconductor substrate 11. The element isolation layer 16 contains, for example, silicon oxide. In addition, the first semiconductor substrate 11 includes an impurity diffusion layer 17 between the element isolation layer 16 and the photodiode PD. For example, the impurity diffusion layer 17 includes a p-type layer and an n-type layer provided to extend in the thickness direction of the first semiconductor substrate 11. The p-type layer is positioned on the element isolation layer 16 side, and the n-type layer is positioned on the photodiode PD side.

[0310] An insulating film 2015 is provided on the front surface 11a side of the first semiconductor substrate 11. The insulating film 2015 is a film formed by stacking one or more materials of, for example, a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), and a silicon carbonitride film (SiCN).

[0311] The second substrate 20 includes a lower substrate 2210 and an upper substrate 2220. The lower substrate 2210 includes a semiconductor substrate 2211. The semiconductor substrate 2211 is a silicon substrate containing, for example, single crystal silicon. An amplifying transistor AMP and an element isolation layer 2213 surrounding the periphery of the amplifying transistor AMP are provided on one surface (e.g., the front surface 2211a) side of the semiconductor substrate 2211. The element isolation layer 2213 electrically separates one amplifying transistor AMP and other amplifying transistors AMP of adjacent pixel units PU from each other.

[0312] The lower substrate 2210 includes an insulating film 2215 covering the front surface 2211a of the semiconductor substrate 2211. The insulating film 2215 covers the amplifying transistor AMP and the element isolation layer 2213. In addition, the lower substrate 2210 includes an insulating film 2217 covering the other surface (e.g., the back surface 2211b) of the semiconductor substrate 2211. The insulating films 2215 and 2217 are films formed by stacking one or more materials selected from, for example, SiO, SiN, SiON, and SiCN, respectively. The insulating film 2015 of the first substrate 10 and the insulating film 2217 of the lower substrate 2210 are joined to each other to form an interlayer insulating film 2051.

[0313] The upper substrate 2220 includes a semiconductor substrate 2221. The semiconductor substrate 2221 is a silicon substrate containing, for example, single crystal silicon. A reset transistor RST, a selection transistor SEL, and an element isolation layer 2223 are provided on one surface (e.g., the front surface 2221a) side of the semiconductor substrate 2221. For example, the element isolation layer 2223 is provided between the reset transistor RST and the selection transistor SEL, and between the selection transistor SEL and the well layer of the semiconductor substrate 2221.

[0314] The upper substrate 2220 includes an insulating film 2225 covering the front surface 2221a, the back surface 2221b, and the side surfaces of the semiconductor substrate 2221. The insulating film 2225 is a film formed by stacking one or more materials selected from, for example, SiO, SiN, SiON, and SiCN. The insulating film 2215 of the lower substrate 2210 and the insulating film 2225 of the upper substrate 2220 are joined to each other to form an interlayer insulating film 2053.

[0315] The imaging device 1B includes a plurality of wirings L1 to L10 provided in the interlayer insulating films 2051 and 2053 and electrically connected to at least one of the first substrate 10 and the second substrate 20. The wiring L1 electrically connects the drain of the amplifying transistor AMP and the power supply line VDD together. The wiring L2 electrically connects the four floating diffusion portions FD included in one pixel unit PU and the gate electrode AG of the amplifying transistor AMP together. The wiring L3 electrically connects the source of the amplifying transistor AMP and the drain of the selection transistor SEL together. The wiring L4 electrically connects the gate electrode SG of the selection transistor SEL and the pixel driving line together.

[0316] The wiring L5 electrically connects the source of the selection transistor SEL and the vertical signal line together. The wiring L6 electrically connects the drain of the reset transistor RST and the power supply line VDD together. The wiring L7 electrically connects the gate electrode RG of the reset transistor RST and the pixel driving line together. The wiring L8 electrically connects the source of the reset transistor RST and the wiring L2 together. The wiring L9 electrically connects the gate electrode TG of the transfer transistor TR and the pixel driving line together. The wiring L10 electrically connects the well contact layer and the reference potential line that supplies a reference potential (e.g., ground potential: 0V) together.

[0317] Among the wirings L1 to L10, the portion provided to extend in the thickness direction of the stacked body contains tungsten (W), and the portion provided to extend in a direction orthogonal to the thickness direction of the stacked body (e.g., horizontal direction) contains copper (Cu) or a Cu alloy mainly composed of Cu. However, the materials included in the wirings L1 to L10 are not limited to this; other materials may be included.

[0318] The second substrate 20 includes a plurality of pad electrodes 2227 connected to any of the wirings L1 to L10 described above (e.g., wirings L1, L4 to L7, L9, and L10). Each of the plurality of pad electrodes 2227 contains, for example, Cu or a Cu alloy.

[0319] The third substrate 30 is provided on the side of the second substrate 20 opposite to the surface facing the first substrate 10 (e.g., the front side). The third substrate 30 includes a semiconductor substrate 2301, an insulating film 2304 covering the front side 2301a of the semiconductor substrate 2301, a plurality of wirings L30 provided on the front side 2301a of the semiconductor substrate 2301, and pad electrodes 2305 connected to each of the wirings L30. Note that, as will be described later, the front side of the third substrate 30 and the second substrate 20 are attached together. For this reason, the front side 2301a of the semiconductor substrate 2301 faces downward.

[0320] The semiconductor substrate 2301 is a silicon substrate containing, for example, single crystal silicon. The semiconductor substrate 2301 includes an impurity diffusion layer included in the logic circuit and a plurality of transistors on the front side 2301a side. The insulating film 2304 covers the impurity diffusion layer and the plurality of transistors included in the logic circuit. The insulating film 2304 includes contact holes connected to these transistors and the impurity diffusion layer.

[0321] The wiring L30 is disposed in the contact hole. In the wiring L30, the portion disposed to extend in the thickness direction of the third substrate 30 contains titanium (Ti) or cobalt (Co), and the portion disposed to extend in a direction orthogonal to the thickness direction of the third substrate 30 (e.g., the horizontal direction) contains Cu or a Cu alloy having Cu as a main component. However, the material contained in the wiring L30 is not limited thereto; other materials may be contained.

[0322] A silicide 2303 (e.g., titanium silicide (TiSi) or cobalt silicide (CoSi 2 )) is formed at the connection portion between the wiring L30 and the semiconductor substrate 2301. The silicide 2303 makes the connection between the wiring L30 and the semiconductor substrate 2301 closer to an ohmic contact, and thus the contact resistance can be reduced. This achieves a higher operation speed of the logic circuit.

[0323] Note that no silicide is formed in the first substrate 10 and the second substrate 20. This enables heat treatment, etc. to be performed at a temperature exceeding the heat-resistant temperature of the silicide when forming the first substrate 10 and the second substrate 20. However, a silicide may be formed in at least one of the first substrate 10 and the second substrate 20.

[0324] The plurality of pad electrodes 2305 each contain, for example, Cu or a Cu alloy. In the thickness direction of the imaging device 1B, the pad electrode 2305 of the third substrate 30 faces the pad electrode 2227 of the second substrate 20 to allow electrical connection. For example, the pad electrodes 2305 and 2227 are integrated by Cu-Cu bonding in a state where they face each other. This allows electrical connection between the second substrate 20 and the third substrate 30 and enhances the attachment strength between the second substrate 20 and the third substrate 30.

[0325] In the imaging device 1B according to the third modification, one contact for the floating diffusion portion may be provided for each of the plurality of sensor pixels 12. For example, four adjacent sensor pixels 12 may share one contact for the floating diffusion portion. Similarly, one contact for the well may be provided for each of the plurality of sensor pixels 12. For example, four adjacent sensor pixels 12 may share one contact for the well.

[0326] Specifically, as Figure 32 and Figure 36As shown, the imaging device 1B can share a common pad electrode 2102 provided across a plurality of sensor pixels 12 and a wiring L2 provided on the common pad electrode 2102. For example, in the imaging device 1B, in a plan view, there is a region where the floating diffusion portions FD1 to FD4 of four sensor pixels 12 are adjacent to each other across an element isolation layer 16. The common pad electrode 2102 is provided in this region. The common pad electrode 2102 is provided to extend across the four floating diffusion portions FD1 to FD4 and is electrically connected to each of the four floating diffusion portions FD1 to FD4. The common pad electrode 2102 includes, for example, a polysilicon film doped with n-type impurities or p-type impurities.

[0327] One wiring L2 (i.e., a contact for the floating diffusion portion) is provided on the central portion of the common pad electrode 2102. As Figure 32 and Figures 34 to 36 shown, the wiring L2 provided on the central portion of the common pad electrode 2102 is provided to extend from the first substrate 10 through the lower substrate 2210 of the second substrate 20 to the upper substrate 2220 of the second substrate 20; the wiring L2 is connected to the gate electrode AG of the amplification transistor AMP via wirings and the like provided in the upper substrate 2220.

[0328] In addition, as Figure 31 and Figure 36 shown, the imaging device 1B can share a common pad electrode 2110 provided across a plurality of sensor pixels 12 and a wiring L10 provided on the common pad electrode 2110. For example, in the imaging device 1B, in a plan view, there is a region where the respective well layers WE of four sensor pixels 12 are adjacent to each other across an element isolation layer 16. The common pad electrode 2110 is provided in this region. The common pad electrode 2110 is provided to extend across the respective well layers WE of the four sensor pixels 12 and is electrically connected to the respective well layers WE of the four sensor pixels 12. For example, the common pad electrode 2110 is provided between one common pad electrode 2102 and another common pad electrode 2102 arranged along the Y-axis direction. In the Y-axis direction, the common pad electrodes 2102 and 2110 are alternately arranged side by side. The common pad electrode 2110 includes, for example, a polysilicon film doped with n-type impurities or p-type impurities.

[0329] In addition, one wiring L10 (i.e., a contact for the well) is provided on the central portion of the common pad electrode 2110. As Figure 31 and Figures 34 to 36As shown, the wiring L10 provided at the center of the common pad electrode 2110 is provided to extend from the first substrate 10 through the lower substrate 2210 of the second substrate 20 to the upper substrate 2220 of the second substrate 20; the wiring L10 is connected to a reference potential line that supplies a reference potential (for example, a ground potential: 0V) via wirings and the like provided in the upper substrate 2220.

[0330] The wiring L10 provided at the center of the common pad electrode 2110 is electrically connected to each of the top surface of the common pad electrode 2110, the inner surface of the through hole provided in the lower substrate 2210, and the inner surface of the through hole provided in the upper substrate 2220. This connects the well layer WE of the first semiconductor substrate 11 of the first substrate 10, the well layer of the lower substrate 2210 of the second substrate 20, and the well layer of the upper substrate 2220 to a reference potential (for example, a ground potential: 0V).

[0331] The imaging device 1B according to the third modification example further includes common pad electrodes 2102 and 2110 provided on the front surface 11a side of the first semiconductor substrate 11 included in the first substrate 10 and provided to straddle a plurality of (for example, four) sensor pixels 12 adjacent to each other. The common pad electrode 2102 is electrically connected to the floating diffusion portions FD of the four sensor pixels 12, and thus the wiring L2 connected to the floating diffusion portions FD can be shared by every four sensor pixels 12. In addition, the common pad electrode 2110 is electrically connected to the well layers WE of the four sensor pixels 12, and thus the wiring L10 connected to the well layers WE can be shared by every four sensor pixels 12. This reduces the number of wirings L2 and L10, and thus the area of the sensor pixels 12 can be reduced and the imaging device 1B can be miniaturized.

[0332] (Fourth Modification Example)

[0333] Subsequently, with reference to Figure 37 and Figure 38 , a fourth modification example, which is a modification example of the cross-sectional structure in the horizontal direction of the imaging device 1, will be described. Figure 37 and Figure 38 The upper diagrams in Figure 7 are respectively schematic diagrams of a modification example of the cross-sectional structure along the cut surface Sec1 in Figure 37 and Figure 38 The lower diagrams in Figure 7 are respectively schematic diagrams of a modification example of the cross-sectional structure along the cut surface Sec2 in

[0334] As in Figure 37 and Figure 38As shown, a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 are arranged side by side in a strip shape in the plane of the first substrate 10 along a first direction V1 ( Figure 37 and Figure 38 the horizontal direction in Figure 37 and Figure 38 FIGS. respectively illustrate a case where a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 are arranged side by side in two rows along the first direction V1.

[0335] Among the four sensor pixels 12 of the shared pixel circuit 22, for example, the four floating diffusion parts FD are arranged close to each other with the element separation part 43 therebetween. Among the four sensor pixels 12 of the shared pixel circuit 22, the four transfer gates TG (TG1, TG2, TG3, and TG4) are arranged to surround the four floating diffusion parts FD. For example, the four transfer gates TG are arranged to form an annular shape.

[0336] The separation insulating layer 53 includes a plurality of blocks extending in the first direction V1. The second semiconductor substrate 21 includes a plurality of island-shaped blocks 21A extending in the first direction V1 and arranged side by side in the first direction V1. Each block 21A includes, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. For example, one pixel circuit 22 shared by the four sensor pixels 12 is not arranged corresponding to the four sensor pixels 12, but is arranged to be offset in a second direction V2.

[0337] In Figure 37 FIG., one pixel circuit 22 shared by the four sensor pixels 12 includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL in a region of the second substrate 20 that is offset in the second direction V2 from the region corresponding to the four sensor pixels 12. For example, one pixel circuit 22 shared by the four sensor pixels 12 includes the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL in one block 21A.

[0338] In Figure 38 FIG., one pixel circuit 22 shared by the four sensor pixels 12 includes a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD conversion gain switching transistor FDG in a region of the second substrate 20 that is offset in the second direction V2 from the region corresponding to the four sensor pixels 12. For example, one pixel circuit 22 shared by the four sensor pixels 12 includes the amplification transistor AMP, the reset transistor RST, the selection transistor SEL, and the FD conversion gain switching transistor FDG in one block 21A.

[0339] In the imaging device 1 according to the fourth modification, a single pixel circuit 22 shared by four sensor pixels 12 is not arranged to face the four sensor pixels 12 directly, but is arranged to be offset in the second direction V2 from the position facing the four sensor pixels 12. According to this configuration, the imaging device 1 according to the fourth modification can shorten the wiring 25, or can omit the wiring 25 and use a common impurity region to form the source of the amplification transistor AMP and the drain of the selection transistor SEL. Therefore, the imaging device 1 according to the fourth modification can reduce the size of the pixel circuit 22.

[0340] (Fifth Modification)

[0341] Next, with reference to Figure 39 , a fifth modification, which is a modification of the cross-sectional structure of the imaging device 1 in the horizontal direction, will be described. Figure 39 is a schematic diagram of a modification of the cross-sectional structure along the cut surfaces Sec1 and Sec2 in Figure 7 .

[0342] As shown in Figure 39 , the second semiconductor substrate 21 includes a plurality of island-shaped blocks 21A arranged side by side in the first direction V1 and the second direction V2 with a separation insulating layer 53 therebetween. Each block 21A includes, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. In this case, the imaging device 1 according to the fifth modification can cause the separation insulating layer 53 to suppress crosstalk between adjacent pixel circuits 22, and thus can suppress a decrease in image resolution or deterioration of image quality due to color mixing.

[0343] (Sixth Modification)

[0344] Subsequently, with reference to Figure 40 , a sixth modification, which is a modification of the cross-sectional structure of the imaging device 1 in the horizontal direction, will be described. Figure 40 is a schematic diagram of a modification of the cross-sectional structure along the cut surfaces Sec1 and Sec2 in Figure 7 .

[0345] In Figure 40In the second semiconductor substrate 21, for example, one pixel circuit 22 shared by four sensor pixels 12 is not arranged corresponding to the four sensor pixels 12, but is arranged to be offset in the first direction V1. In addition, in the imaging device 1 according to the sixth modification, the second semiconductor substrate 21 includes a plurality of island-like blocks 21A arranged side by side in the first direction V1 and the second direction V2 with a separation insulating layer 53 therebetween. Each block 21A includes, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. Further, in the imaging device 1 according to the sixth modification, a plurality of through wirings 47 and a plurality of through wirings 54 are arranged in the second direction V2.

[0346] This causes the plurality of through wirings 47 to be arranged between four through wirings 54 sharing one pixel circuit 22 and four through wirings 54 sharing another pixel circuit 22 adjacent to the pixel circuit 22 in the second direction V2. This enables the imaging device 1 according to the sixth modification to suppress crosstalk between adjacent pixel circuits 22 by the separation insulating layer 53 and the through wirings 47, and thus can suppress a decrease in image resolution or deterioration of image quality due to color mixing.

[0347] (Seventh modification)

[0348] Next, with reference to Figures 41 to 43 , a seventh modification which is a modification of the cross-sectional structure of the imaging device 1 in the horizontal direction will be described. Figure 41 is a schematic diagram of a modification of the cross-sectional structure along the cut surfaces Sec1 and Sec2 in Figure 7 .

[0349] As shown in Figure 41 , in the imaging device 1 according to the seventh modification, the first substrate 10 includes a photodiode PD and a transfer transistor TR (i.e., transfer gate TG) for each sensor pixel 12, and the floating diffusion portion FD is shared by every four sensor pixels 12. For this reason, the imaging device 1 according to the seventh modification includes one through wiring 54 for every four sensor pixels 12.

[0350] In addition, in the imaging device 1 according to the seventh modification, through wirings 47 are provided in each region obtained by shifting a unit region corresponding to four sensor pixels 12 sharing a floating diffusion portion FD by one sensor pixel 12 in the second direction V2. That is, in the imaging device 1 according to the seventh modification, the through wirings 47 are provided between a unit region corresponding to four sensor pixels 12 sharing a floating diffusion portion FD and an adjacent unit region adjacent to the unit region in the second direction V2. In addition, the through wirings 47 are shared by two sensor pixels 12 in the unit region around the through wirings 47 and two sensor pixels 12 in the adjacent unit region around the through wirings 47.

[0351] Furthermore, in the imaging device 1 according to the seventh modification, the first substrate 10 includes an element isolation portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12. When looking down on the main surface of the first semiconductor substrate 11 along the normal direction, the element isolation portion 43 does not completely surround the periphery of the sensor pixel 12, and thus voids (unformed regions) exist near the floating diffusion portion FD (i.e., the through wiring 54) and near the through wiring 47. These voids enable four sensor pixels 12 to share the through wiring 54 and enable four sensor pixels 12 to share the through wiring 47 between the unit region and the adjacent unit region. Note that, in the imaging device 1 according to the seventh modification, the second substrate 20 includes pixel circuits 22 for every four sensor pixels 12 sharing a floating diffusion portion FD.

[0352] Figure 42 and Figure 43 are schematic views of another example of the cross-sectional structure along the cut surface Sec2 of the imaging device 1 according to the seventh modification. As Figure 42 shown, the first substrate 10 may include a photodiode PD and a transfer transistor TR for each sensor pixel 12, and the floating diffusion portion FD may be shared by every four sensor pixels 12. In addition, the first substrate 10 may include an element isolation portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12. Further, as Figure 43 shown, for each sensor pixel 12, a photodiode PD and a transfer transistor TR may be included, and the floating diffusion portion FD may be shared by every four sensor pixels 12. In addition, the first substrate 10 may include an element isolation portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0353] (Eighth Modification)

[0354] Subsequently, with reference to Figure 44, a description is given of an eighth modification example of the circuit configuration of the imaging device 1. Figure 44 It is a schematic diagram of the circuit configuration of a CMOS image sensor equipped with a column-parallel ADC (Analog to Digital Converter).

[0355] As Figure 44 shown, the imaging device 1 according to the eighth modification example includes a pixel region 13, a vertical drive circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal drive circuit 35, a horizontal output line 37, and a system control circuit 36. In the pixel region 13, a plurality of sensor pixels 12 each including a photoelectric conversion element are two-dimensionally arranged in a square matrix (i.e., a matrix).

[0356] Based on the main clock MCK, the system control circuit 36 generates clock signals and control signals, etc., which serve as a reference for the operations of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc. The system control circuit 36 further supplies the generated clock signals and control signals, etc., to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, and the horizontal drive circuit 35.

[0357] The vertical drive circuit 33 is formed respectively in the first substrate 10 in which each sensor pixel 12 of the pixel region 13 is formed and the second substrate 20 in which the pixel circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 are formed in the third substrate 30.

[0358] Although not shown here, the sensor pixel 12 includes, for example, a photodiode PD and a transfer transistor TR that transfers the charge after photoelectric conversion in the photodiode PD to the floating diffusion portion FD. The pixel circuit 22 includes, for example, a reset transistor RST that controls the potential of the floating diffusion portion FD, an amplification transistor AMP that outputs a signal corresponding to the potential of the floating diffusion portion FD, and a selection transistor SEL for selecting a pixel.

[0359] The sensor pixels 12 are two-dimensionally arranged in the pixel region 13. For example, in the pixel region 13 where the sensor pixels 12 are arranged in an n-row and m-column matrix, pixel drive lines 23 are wired for each row, and vertical signal lines 24 are wired for each column. One ends of the plurality of pixel drive lines 23 are respectively connected to the corresponding output terminals of the rows of the vertical drive circuit 33. The vertical drive circuit 33 includes a shift register, etc., and controls the row address or row scan of the pixel region 13 via the plurality of pixel drive lines 23.

[0360] The column signal processing circuit 34 includes, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for respective pixel columns of the pixel region 13, that is, for respective vertical signal lines 24. The column signal processing circuit 34 causes the ADCs to convert the analog signals output from the sensor pixels 12 of the pixel region 13 for each column into digital signals for output.

[0361] The reference voltage supply unit 38 includes, for example, a DAC (digital-to-analog conversion circuit) 38A, and generates a reference voltage Vref having a so-called ramp waveform with a level that changes in a sloping manner as time elapses. Note that the reference voltage supply unit 38 may use a device other than the DAC 38A to generate the reference voltage Vref having a ramp waveform.

[0362] Based on the control signal CS1 and the clock CK from the system control circuit 36, the DAC 38A generates the reference voltage Vref having a ramp waveform, and supplies the generated reference voltage Vref to the ADCs 34-1 to 34-m of the column signal processing circuit 34.

[0363] Note that each of the ADCs 34-1 to 34-m is configured to be able to selectively perform an AD conversion operation corresponding to each operation mode, and each operation mode is: a normal frame rate mode that employs a progressive scan method of reading out information of all the sensor pixels 12; and a high-speed frame rate mode that sets the exposure time of the sensor pixels 12 to 1 / N as compared with the exposure time of the normal frame rate mode, thereby increasing the frame rate to N times (for example, twice). The switching between the operation modes is performed under the control of the control signals CS2 and CS3 from the system control circuit 36. In addition, based on instruction information from an external system controller (not shown), the system control circuit 36 generates the control signals CS2 and CS3 for switching between the operation mode of the normal frame rate mode and the operation mode of the high-speed frame rate mode.

[0364] All of the ADCs 34-1 to 34-m have the same configuration, and thus the ADC 34-m will be described as an example here.

[0365] The ADC 34-m includes a comparator 34A, a reversible counter (U / D CNT) 34B, a transfer switch 34C, and a memory 34D.

[0366] Comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 in the m-th column of the pixel region 13 with the reference voltage Vref of the ramp waveform supplied from the reference voltage supply unit 38. For example, when the reference voltage Vref is greater than the signal voltage Vx, comparator 34A sets the output Vco to the "H (high)" level, and when the reference voltage Vref is equal to or less than the signal voltage Vx, comparator 34A sets the output Vco to the "L (low)" level.

[0367] The reversible counter 34B is an asynchronous counter. Based on the control signal CS2 provided by the system control circuit 36, the system control circuit 36 supplies the clock CK to the reversible counter 34B. The reversible counter 34B counts down (DOWN) or up (UP) synchronously with the clock CK to measure the comparison period from the start to the end of the comparison operation in the comparator 34A.

[0368] Specifically, in the normal frame rate mode, the reversible counter 34B counts down at the first read operation of one sensor pixel 12 to measure the comparison time at the first read. In addition, the reversible counter 34B counts up at the second read operation to measure the comparison time at the second read.

[0369] Meanwhile, in the high-speed frame rate mode, the reversible counter 34B keeps the count result of the sensor pixels 12 in a certain row unchanged. Thereafter, for the sensor pixels 12 in the next row, the reversible counter 34B counts down at the first read operation by continuing the previous count result to measure the comparison time at the first read. In addition, the reversible counter 34B counts up at the second read operation to measure the comparison time at the second read.

[0370] The transfer switch 34C operates based on the control signal CS3 provided by the system control circuit 36. In the normal frame rate mode, when the counting operation of the reversible counter 34B for the sensor pixels 12 in a certain row is completed, the transfer switch 34C enters the on (closed) state to transfer the count result of the reversible counter 34B to the memory 34D.

[0371] Meanwhile, for example, at a high-speed frame rate of N = 2, when the counting operation of the reversible counter 34B for the sensor pixels 12 in a certain row is completed, the transfer switch 34C remains off (open). Thereafter, when the counting operation of the reversible counter 34B for the sensor pixels 12 in the next row is completed, the transfer switch 34C enters the on state to transfer the count results of the reversible counter 34B for two vertical pixels to the memory 34D.

[0372] In this manner, the analog signals supplied for each column from the respective sensor pixels 12 of the pixel region 13 via the vertical signal lines 24 are converted into N-bit digital signals by the corresponding operations of the comparators 34A and the reversible counters 34B in the ADCs 34-1 to 34-m, and are stored in the memory 34D.

[0373] The horizontal drive circuit 35 includes a shift register or the like, and controls the column addresses and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. The horizontal drive circuit 35 controls each of the ADCs 34-1 to 34-m so that the N-bit digital signals after AD conversion are sequentially read out via the horizontal output lines 37. The read N-bit digital signals are output as imaging data via the horizontal output lines 37.

[0374] It should be noted that, although not particularly illustrated, in addition to the above-described components, a circuit or the like that performs various types of signal processing on the imaging data output via the horizontal output lines 37 may be provided.

[0375] In the imaging device 1 according to the eighth modification example, the count result of the reversible counter 34B can be selectively transmitted to the memory 34D via the transmission switch 34C. This enables the imaging device 1 according to the eighth modification example to independently control the counting operation of the reversible counter 34B and the read operation of the count result of the reversible counter 34B being read out to the horizontal output lines 37.

[0376] (Ninth Modification Example)

[0377] Next, with reference to Figure 45 , a ninth modification example, which is a modification example of the stacked structure of the imaging device 1, will be described. Figure 45 is Figure 38 a schematic diagram showing an example of the configuration of the imaging device 1 including a structure of three stacked substrates.

[0378] As Figure 45As shown, the imaging device 1 according to the ninth modification has a structure in which a first substrate 10, a second substrate 20, and a third substrate are stacked. A pixel region 13 including a plurality of sensor pixels 12 is formed in the central portion of the first substrate 10, and a vertical drive circuit 33 is formed around the pixel region 13. In addition, a pixel circuit region 15 including a plurality of pixel circuits 22 is formed in the central portion of the second substrate 20, and a vertical drive circuit 33 is formed around the pixel circuit region 15. Further, a column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, horizontal output lines 37, and a reference voltage supply unit 38 are formed in the third substrate 30. Note that the vertical drive circuit 33 can be formed in both the first substrate 10 and the second substrate 20 as described above, can be formed only in the first substrate 10, or can be formed only in the second substrate 20.

[0379] The imaging device 1 according to the ninth modification can suppress an increase in chip size or an increase in pixel area due to the electrical connection structure between the substrates. This enables the imaging device 1 according to the ninth modification to further miniaturize the area of each pixel.

[0380] (Tenth Modification)

[0381] Subsequently, with reference to Figure 46 and Figure 47 , a tenth modification, which is a modification of the cross-sectional structure of the imaging device 1, will be described. Figure 46 is a schematic diagram of an example of the cross-sectional structure of the imaging device 1 according to the tenth modification.

[0382] The above-described embodiments and modifications illustrate a structure in which the imaging device 1 includes three substrates, i.e., a stacked first substrate 10, a second substrate 20, and a third substrate 30. However, the technology according to the present disclosure is not limited to the above examples. For example, the imaging device 1 may be configured by stacking two substrates, i.e., the first substrate 10 and the second substrate 20.

[0383] As Figure 46 shown, in this case, for example, the processing circuit 32 is separately formed in the first substrate 10 and the second substrate 20.

[0384] The circuit 32A of the processing circuit 32 provided on the first substrate 10 side includes a transistor having a gate structure in which a high-k (high dielectric constant) film containing a material capable of withstanding a high-temperature process (e.g., a high-k (high dielectric constant) material) and a metal gate electrode are stacked.

[0385] At the same time, in the circuit 32B of the processing circuit 32 provided on the second substrate 20 side, a low-resistance region 26 is formed on the front surface of the impurity diffusion region in contact with the source electrode and the drain electrode, and the low-resistance region 26 contains, for example, CoSi2 or silicides such as NiSi. The low-resistance region containing the silicide is formed of a compound of a semiconductor substrate material and a metal and has high heat resistance. Therefore, when forming the sensor pixel 12, a high-temperature process such as thermal oxidation can be used. In addition, the low-resistance region 26 containing silicides such as CoSi 2 or NiSi can reduce the contact resistance, and thus a higher operating speed of the processing circuit 32 can be achieved.

[0386] Note that the low-resistance region 26 containing silicides such as CoSi 2 or NiSi can be provided in the imaging device 1 according to any of the above-described embodiments and modified examples. Specifically, the imaging device 1 constituted by stacking three substrates, i.e., the first substrate 10, the second substrate 20, and the third substrate 30, further has a low-resistance region 26 containing silicides such as CoSi 2 or NiSi. Figure 47 is a schematic diagram showing an example in which the low-resistance region 26 containing silicides such as CoSi 2 or NiSi is applied to the imaging device 1 having a structure formed by stacking three substrates.

[0387] As Figure 47 shown, in the processing circuit 32 of the third substrate 30, a low-resistance region 26 containing silicides such as CoSi can be formed on the front surface of the impurity diffusion region in contact with the source electrode and the drain electrode. Thus, when forming the sensor pixel 12, a high-temperature process such as thermal oxidation can be used. In addition, the low-resistance region 26 containing silicides such as CoSi 2 or NiSi can reduce the contact resistance, and thus a higher operating speed of the processing circuit 32 can be achieved. 2 or NiSi can reduce the contact resistance, and thus a higher operating speed of the processing circuit 32 can be achieved.

[0388] <<4. Specific Examples>>

[0389] The above-described technology according to the present disclosure is applicable to various imaging devices and the like. Hereinafter, with reference to specific examples, an imaging device to which the technology according to the present disclosure is applied and a device including the imaging device will be described.

[0390] <4.1. Embodiment>

[0391] [Functional Configuration of Imaging Device 1]

[0392] Figure 48 is a block diagram showing an example of the functional configuration of an imaging device (imaging device 1) according to an embodiment of the present disclosure.

[0393] Figure 48The imaging device 1 includes, for example, an input unit 510A, a row driving unit 520, a timing controller 530, a pixel array unit 540, a column signal processor 550, an image signal processor 560, and an output unit 510B.

[0394] In the pixel array unit 540, pixels 541 are repeatedly arranged in an array. More specifically, pixel sharing units 539 each including a plurality of pixels are repetition units, and are repeatedly arranged in an array in the row direction and the column direction. Note that, in the present specification, for convenience, the row direction and the column direction orthogonal to the row direction are sometimes referred to as the "H direction" and the "V direction", respectively. In Figure 48 the example of, one pixel sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). The pixels 541A, 541B, 541C, and 541D each include a photodiode PD (shown in Figure 53 etc. described later). The pixel sharing unit 539 is a unit that shares one pixel circuit (the pixel circuit 210 in Figure 50 described later). In other words, one pixel circuit (the pixel circuit 210 described later) is included for every four pixels (pixels 541A, 541B, 541C, and 541D). The pixel circuit is driven in a time-division manner to sequentially read out pixel signals of the respective pixels 541A, 541B, 541C, and 541D. For example, the pixels 541A, 541B, 541C, and 541D are arranged in 2 rows × 2 columns. The pixel array unit 540 includes a plurality of row driving signal lines 542, a plurality of vertical signal lines (column readout lines) 543, and the pixels 541A, 541B, 541C, and 541D. The row driving signal lines 542 drive the pixels 541 included in the plurality of pixel sharing units 539 and arranged in the row direction in the pixel array unit 540. The row driving signal lines 542 drive each pixel arranged in the row direction in the pixel sharing unit 539. As described in detail later with reference to Figure 51 a plurality of transistors are provided in the pixel sharing unit 539. In order to drive each of the plurality of transistors, the plurality of row driving signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal line (column readout line) 543. Pixel signals are read out from the respective pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 via the vertical signal line (column readout line) 543.

[0395] For example, the row driving unit 520 includes a row address controller that determines the position of the row for pixel driving, in other words, a row decoder unit, and includes a row driving circuit unit that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0396] The column signal processor 550 is connected to, for example, the vertical signal line 543, and includes a load circuit section that forms a source follower circuit together with the pixels 541A, 541B, 541C, and 541D (pixel common unit 539). The column signal processor 550 may include an amplifier circuit section that amplifies the signal read out from the pixel common unit 539 via the vertical signal line 543. The column signal processor 550 may include a noise processor. The noise processor removes, for example, the system noise level from the signal that is the result of photoelectric conversion and read out from the pixel common unit 539.

[0397] The column signal processor 550 includes, for example, an analog-to-digital converter (ADC). The analog-to-digital converter converts the signal read out from the pixel common unit 539 or the analog signal that has undergone the above-described noise processing into a digital signal. The ADC includes, for example, a comparator section and a counter section. The comparator section compares the analog signal to be converted with a reference signal as the comparison object. The counter section measures the time until the comparison result in the comparator section is inverted. The column signal processor 550 may include a horizontal scan circuit section that controls the scanning of the read column.

[0398] Based on the reference clock signal and the timing control signal input to the device, the timing controller 530 supplies a signal for controlling the timing to the row driver section 520 and the column signal processor 550.

[0399] The image signal processor 560 is a circuit that performs various types of signal processing on the data obtained as a result of photoelectric conversion, in other words, the data obtained as a result of the imaging operation in the imaging device 1. The image signal processor 560 includes, for example, an image signal processing circuit section and a data holding section. The image signal processor 560 may also include a processor section.

[0400] An example of the signal processing performed in the image signal processor 560 is the tone curve correction processing, in which, when the AD-converted imaging data is data obtained by photographing a darker subject, the gray level is increased, and when the AD-converted imaging data is data obtained by photographing a brighter subject, the gray level is decreased. In this case, regarding which tone curve is used to correct the gray level of the imaging data, it is desirable to pre-store the characteristic data of the tone curve in the data holding section of the image signal processor 560.

[0401] For example, the input unit 510A inputs the above-mentioned reference clock signal, timing control signal, characteristic data, etc. from outside the apparatus into the imaging apparatus 1. Examples of the timing control signal include a vertical synchronization signal, a horizontal synchronization signal, etc. For example, the characteristic data will be stored in the data holding unit of the image signal processor 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0402] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 brings the signal input to the input terminal 511 into the imaging apparatus 1. The input amplitude changing unit 513 changes the amplitude of the signal acquired by the input circuit unit 512 to an amplitude that is easy to use inside the imaging apparatus 1. The input data conversion circuit unit 514 changes the order of the data columns of the input data. The input data conversion circuit unit 514 includes, for example, a serial-parallel conversion circuit. The serial-parallel conversion circuit converts the serial signal received as the input data into a parallel signal. Note that in the input unit 510A, the input amplitude changing unit 513 and the input data conversion circuit unit 514 may be omitted. The power supply unit supplies power of various types set to be required inside the imaging apparatus 1 using the power supplied to the imaging apparatus 1 from the outside.

[0403] When the imaging apparatus 1 is connected to an external memory device, a memory interface circuit for receiving data from the external memory device can be provided in the input unit 510A. Examples of the external memory device include a flash memory, an SRAM, a DRAM, etc.

[0404] The output unit 510B outputs image data to the outside of the apparatus. Examples of the image data include the image data captured by the imaging apparatus 1 and the image data that has been signal-processed by the image signal processor 560, etc. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude changing unit 516, an output circuit unit 517, and an output terminal 518.

[0405] The output data conversion circuit unit 515 includes, for example, a parallel-serial conversion circuit. The output data conversion circuit unit 515 converts the parallel signal used inside the imaging apparatus 1 into a serial signal. The output amplitude changing unit 516 changes the amplitude of the signal used inside the imaging apparatus 1. The signal with the changed amplitude is easy to use in an external device connected to the outside of the imaging apparatus 1. The output circuit unit 517 is a circuit that outputs data from inside the imaging apparatus 1 to the outside of the apparatus, and the output circuit unit 517 drives the wiring outside the imaging apparatus 1 connected to the output terminal 518. At the output terminal 518, data is output from the imaging apparatus 1 to the outside of the apparatus. In the output unit 510B, the output data conversion circuit unit 515 and the output amplitude changing unit 516 may be omitted.

[0406] When the imaging device 1 is connected to an external memory device, the output unit 510B may include a memory interface circuit that outputs data to the external memory device. Examples of the external memory device include a flash memory, SRAM, and DRAM.

[0407] [Schematic configuration of imaging device 1]

[0408] Figure 49 and Figure 50 Examples of the schematic configuration of the imaging device 1 are shown respectively. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). Figure 49 The planar configurations of the first substrate 100, the second substrate 200, and the third substrate 300 are schematically shown, and Figure 50 the cross-sectional configurations of the first substrate 100, the second substrate 200, and the third substrate 300 stacked on one another are schematically shown. Figure 50 Corresponds to the cross-sectional configuration taken along the Figure 49 line III-III' shown. The imaging device 1 is an imaging device having a three-dimensional structure in which three substrates (the first substrate 100, the second substrate 200, and the third substrate 300) are attached together. The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film around it is referred to as the wiring layer (100T, 200T, or 300T) provided in each substrate (each of the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in sequence, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S are provided in sequence along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. Figure 50The arrow shown indicates the incident direction of the light L onto the imaging device 1. In this specification, for convenience, in the following cross-sectional views, the light incident side in the imaging device 1 is sometimes referred to as the "bottom", "lower side", or "below", and the side opposite to the light incident side is sometimes referred to as the "top", "upper side", or "above". Additionally, in this specification, for convenience, in a substrate including a semiconductor layer and a wiring layer, the wiring layer side is sometimes referred to as the front side, and the semiconductor layer side is sometimes referred to as the back side. Note that the descriptions in the specification are not limited to the above names. The imaging device 1 is, for example, a back-illuminated type imaging device in which light is incident from the back side of the first substrate 100 including a photodiode.

[0409] Both the pixel array section 540 and the pixel common unit 539 included in the pixel array section 540 are formed using both the first substrate 100 and the second substrate 200. The first substrate 100 includes a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel common unit 539. Each pixel 541 includes a photodiode (photodiode PD described later) and a transfer transistor (transfer transistor TR described later). The second substrate 200 includes a pixel circuit (pixel circuit 210 described later) included in the pixel common unit 539. The pixel circuit reads out the pixel signals transferred from the photodiodes of each of the pixels 541A, 541B, 541C, and 541D via the transfer transistor, or resets the photodiodes. In addition to such a pixel circuit, the second substrate 200 also includes a plurality of row driving signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 also includes a power supply line 544 (power supply line VDD etc. described later) extending in the row direction. The third substrate 300 includes, for example, an input section 510A, a row driving section 520, a timing controller 530, a column signal processor 550, an image signal processor 560, and an output section 510B. The row driving section 520 is provided, for example, in a region that partially overlaps with the pixel array section 540 in the stacking direction (hereinafter, simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driving section 520 is provided in a region that overlaps with the vicinity of the end portion of the pixel array section 540 in the H direction in the stacking direction ( Figure 49 ). The column signal processor 550 is provided, for example, in a region that partially overlaps with the pixel array section 540 in the stacking direction. More specifically, the column signal processor 550 is provided in a region that overlaps with the vicinity of the end portion of the pixel array section 540 in the V direction in the stacking direction ( Figure 49)。Although the illustration is omitted, the input section 510A and the output section 510B can be provided in a part other than the third substrate 300, and can be provided, for example, in the second substrate 200. Alternatively, the input section 510A and the output section 510B can be provided on the back surface (light incident surface) side of the first substrate 100. Note that the pixel circuit provided in the second substrate 200 as described above is also referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit. In this specification, the name "pixel circuit" is used.

[0410] The first substrate 100 and the second substrate 200 are electrically connected to each other through, for example, through electrodes (through electrodes 120E and 121E described later Figure 53 ). The second substrate 200 and the third substrate 300 are electrically connected to each other through, for example, contact portions 201, 202, 301, and 302. The second substrate 200 is provided with the contact portions 201 and 202, and the third substrate 300 is provided with the contact portions 301 and 302. The contact portion 201 of the second substrate 200 is in contact with the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 is in contact with the contact portion 302 of the third substrate 300. The second substrate 200 includes a contact region 201R provided with a plurality of contact portions 201 and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 includes a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. The contact regions 201R and 301R are provided between the pixel array section 540 and the row driver section 520 in the stacking direction ( Figure 50 ). In other words, the contact regions 201R and 301R are provided in a region where, for example, the row driver section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap each other in the stacking direction, or in a region near this region. For example, the contact regions 201R and 301R are provided at the ends in the H direction of such a region ( Figure 49 ). In the third substrate 300, the contact region 301R is provided in a part of the row driver section 520, specifically, at a position overlapping the end in the H direction of the row driver section 520 ( Figure 49 and Figure 50 ). The contact portions 201 and 301 connect, for example, the row driver section 520 provided in the third substrate 300 and the row driving signal line 542 provided in the second substrate 200 to each other. The contact portions 201 and 301 can, for example, connect the input section 510A provided in the third substrate 300 to the power supply line 544 and the reference potential line (reference potential line VSS described later). The contact regions 202R and 302R are provided between the pixel array section 540 and the column signal processor 550 in the stacking direction ( Figure 50)。In other words, the contact regions 202R and 302R are provided in a region where, for example, the column signal processor 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, or in a region near this region. The contact regions 202R and 302R are provided at the ends of such a region in the V direction ( Figure 49 )。In the third substrate 300, the contact region 302R is provided in, for example, a part of the column signal processor 550, specifically, at a position overlapping with the end of the column signal processor 550 in the V direction ( Figure 49 and Figure 50 )。The contact portions 202 and 302 connect, for example, pixel signals (signals corresponding to the amount of electric charge generated as a result of photoelectric conversion of a photodiode) output from each of the plurality of pixel common units 539 included in the pixel array unit 540 to the column signal processor 550 provided in the third substrate 300. The pixel signals are transmitted from the second substrate 200 to the third substrate 300.

[0411] Figure 50 is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected to each other via the wiring layers 100T, 200T, and 300T. For example, the imaging device 1 includes an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 to each other. Specifically, the contact portions 201, 202, 301, and 302 are formed using electrodes made of a conductive material. The conductive material is formed of a metal material such as copper (Cu), aluminum (Al), and gold (Au), for example. The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate and the third substrate to each other by directly joining, for example, the wiring formed as an electrode, so that signals can be input to and / or output from the second substrate 200 and the third substrate 300.

[0412] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 to each other can be provided at a desired position. For example, as described for the contact regions 201R, 202R, 301R, and 302R in Figure 50 , the electrical connection portion can be provided in a region overlapping with the pixel array unit 540 in the stacking direction. In addition, the electrical connection portion can be provided in a region that does not overlap with the pixel array unit 540 in the stacking direction. Specifically, the electrical connection portion can be provided in a region overlapping with a peripheral portion provided outside the pixel array unit 540 in the stacking direction.

[0413] The first substrate 100 and the second substrate 200 are provided with, for example, connection hole portions H1 and H2. The connection hole portions H1 and H2 penetrate the first substrate 100 and the second substrate 200 (Figure 50 )。The connection hole portions H1 and H2 are provided outside the pixel array portion 540 (or a portion overlapping with the pixel array portion 540). Figure 49 )。For example, the connection hole portion H1 is provided outside the pixel array portion 540 in the H direction, and the connection hole portion H2 is provided outside the pixel array portion 540 in the V direction. For example, the connection hole portion H1 reaches the input portion 510A provided in the third substrate 300, and the connection hole portion H2 reaches the output portion 510B provided in the third substrate 300. The connection hole portions H1 and H2 may be cavities, or may at least partially include a conductive material. For example, there is a configuration in which bonding wires are connected to electrodes formed as the input portion 510A and / or the output portion 510B. Alternatively, there is a configuration in which the electrodes formed as the input portion 510A and / or the output portion 510B and the conductive material provided in the connection hole portions H1 and H2 are connected to each other. The conductive material provided in the connection hole portions H1 and H2 may be embedded in a part or all of the connection hole portions H1 and H2, or the conductive material may be formed on the side walls of each of the connection hole portions H1 and H2.

[0414] Note that Figure 50 The structure in which the third substrate 300 is provided with the input portion 510A and the output portion 510B is shown, but this is not restrictive. For example, by transmitting the signals of the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T, the input portion 510A and / or the output portion 510B may be provided in the second substrate 200. Similarly, by transmitting the signals of the second substrate 200 to the first substrate 100 via the wiring layers 100T and 200T, the input portion 510A and / or the output portion 510B may be provided in the first substrate 100.

[0415] Figure 51 is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541( Figure 51Four pixels 541, namely pixels 541A, 541B, 541C, and 541D, a pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210 are shown. The pixel circuit 210 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel sharing unit 539 drives one pixel circuit 210 in a time-division manner to sequentially output pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543. One pixel circuit 210 is connected to the plurality of pixels 541, and a mode in which pixel signals of the plurality of pixels 541 are output by one pixel circuit 210 in a time-division manner is referred to as "the plurality of pixels 541 sharing one pixel circuit 210".

[0416] Pixels 541A, 541B, 541C, and 541D include constituent elements common to each other. Hereinafter, in order to distinguish the constituent elements of pixels 541A, 541B, 541C, and 541D from each other, an identification number 1 is given to the end of the symbol of the constituent element of pixel 541A, an identification number 2 is given to the end of the symbol of the constituent element of pixel 541B, an identification number 3 is given to the end of the symbol of the constituent element of pixel 541C, and an identification number 4 is given to the end of the symbol of the constituent element of pixel 541D. When it is not necessary to distinguish the constituent elements of pixels 541A, 541B, 541C, and 541D from each other, the identification number at the end of the symbol of the constituent element of each of pixels 541A, 541B, 541C, and 541D is omitted.

[0417] Each of pixels 541A, 541B, 541C, and 541D includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion portion FD electrically connected to the transfer transistor TR. In the photodiodes PD (PD1, PD2, PD3, and PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion on incident light and generates charges corresponding to the received light amount. The transfer transistor TR (transfer transistors TR1, TR2, TR3, and TR4) is, for example, an n-type CMOS (Complementary Metal Oxide Semiconductor) transistor. In the transfer transistor TR, the drain is electrically connected to the floating diffusion portion FD, and the gate is electrically connected to a drive signal line. This drive signal line is one of the plurality of row drive signal lines 542 connected to one pixel sharing unit 539 (see Figure 48) is a part of. The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion section FD. The floating diffusion section FD (floating diffusion sections FD1, FD2, FD3, and FD4) is an n-type diffusion layer region formed in the p-type semiconductor layer. The floating diffusion section FD is a charge holding device that temporarily holds the charge transferred from the photodiode PD and a charge-voltage conversion device that generates a voltage corresponding to the amount of charge.

[0418] The four floating diffusion sections FD (floating diffusion sections FD1, FD2, FD3, and FD4) included in one pixel common unit 539 are electrically connected to each other and are electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to the drive signal line. This drive signal line is a part of the plurality of row drive signal lines 542 connected to one pixel common unit 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. This drive signal line is a part of the plurality of row drive signal lines 542 connected to one pixel common unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion section FD, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. This drive signal line is a part of the plurality of row drive signal lines 542 connected to one pixel common unit 539.

[0419] When the transfer transistor TR enters the conducting state, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion section FD. The gate of the transfer transistor TR (transfer gate TG) includes, for example, a so-called vertical electrode and, as described later Figure 53 shown, is arranged to extend from the front surface of the semiconductor layer (the semiconductor layer 100S in Figure 53 ) to reach the depth of the PD. The reset transistor RST resets the potential of the floating diffusion section FD to a predetermined potential. When the reset transistor RST enters the conducting state, the potential of the floating diffusion section FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates a signal of a voltage corresponding to the level of the charge held by the floating diffusion section FD as the pixel signal. The amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. The amplification transistor AMP is connected to the load circuit section (see Figure 48)Together, they form a source follower. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion section FD to the column signal processor 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.

[0420] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion in the floating diffusion section FD. Generally, when shooting in the dark, the pixel signal is small. When performing charge-voltage conversion based on Q = CV, if the capacitance of the floating diffusion section FD (FD capacitance C) is large, the value V when converted into voltage in the amplification transistor AMP will be small. At the same time, in the bright area, the pixel signal becomes large; therefore, unless the FD capacitance C is very large, it is impossible for the floating diffusion section FD to fully receive the charge of the photodiode PD. In addition, it is necessary for the FD capacitance C to be large so that the value V when converted into voltage in the amplification transistor AMP will not be too large (in other words, become smaller). Considering these situations, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, thus causing the entire FD capacitance C to become large. At the same time, when the FD conversion gain switching transistor FDG is turned off, the entire FD capacitance C becomes small. In this way, by switching the on / off of the FD conversion gain switching transistor FDG, the FD capacitance C can be made variable, so the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0421] It should be noted that a structure without the FD conversion gain switching transistor FDG is also possible. In this case, the pixel circuit 210 includes, for example, three transistors, namely, the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST. The pixel circuit 210 includes at least one of, for example, the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0422] The selection transistor SEL can be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (see Figure 48)。The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. It should be noted that although not shown in the figure, the number of pixels 541 sharing a pixel circuit 210 may not be four. For example, two or eight pixels 541 may share a pixel circuit 210.

[0423] Figure 52 An example of the connection mode between the plurality of pixel sharing units 539 and the vertical signal line 543 is shown. For example, four pixel sharing units 539 arranged in the column direction are divided into four groups, and the vertical signal line 543 is connected to each of the four groups. For the sake of simplicity of explanation, Figure 52 An example in which each of the four groups includes one pixel sharing unit 539 is shown; however, each of the four groups may include a plurality of pixel sharing units 539. As described above, in the imaging device 1, a plurality of pixel sharing units 539 arranged in the column direction can be divided into groups including one or more pixel sharing units 539. For example, the vertical signal line 543 and the column signal processor 550 are connected to each group, so that pixel signals can be read out from each group simultaneously. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to a plurality of pixel sharing units 539 arranged in the column direction. At this time, pixel signals are sequentially read out from the plurality of pixel sharing units 539 connected to one vertical signal line 543 in a time-division manner.

[0424] [Specific Structure of Imaging Device 1]

[0425] Figure 53 An example of the cross-sectional structure of the imaging device 1 in the vertical direction with respect to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300 is shown. For the sake of easy understanding, Figure 53 The positional relationship of the components is schematically shown and may be different from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in sequence. The imaging device 1 further includes an optical receiving lens 401 on the back side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the optical receiving lens 401 and the first substrate 100. For example, the optical receiving lens 401 is provided for each of the pixels 541A, 541B, 541C, and 541D. The imaging device 1 is, for example, a back-illuminated type imaging device. The imaging device 1 includes a pixel array portion 540 provided in the central portion and a peripheral portion 540B provided outside the pixel array portion 540.

[0426] The first substrate 100 includes, in order from the light receiving lens 401 side, an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. The semiconductor layer 100S includes, for example, a silicon substrate. The semiconductor layer 100S includes, for example, a p-well layer 115 in a part of and near the front surface (the surface on the wiring layer 100T side), and includes an n-type semiconductor region 114 in a region other than the p-well layer 115 (a region deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 are included in a pn junction type photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0427] Figure 54A An example of the planar structure of the first substrate 100 is shown. Figure 54A The planar structures of the pixel isolation portion 117, the photodiode PD, the floating diffusion portion FD, the VSS contact region 118, and the transfer transistor TR of the first substrate 100 are mainly shown. Use Figure 54A and Figure 53 to describe the structure of the first substrate 100.

[0428] The floating diffusion portion FD and the VSS contact region 118 are provided near the front surface of the semiconductor layer 100S. The floating diffusion portion FD includes an n-type semiconductor region provided in the p-well layer 115. For example, the floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D are provided close to each other in the central portion of the pixel common unit 539 ( Figure 54A ). As will be described in detail later, the four floating diffusion portions (floating diffusion portions FD1, FD2, FD3, and FD4) included in the pixel common unit 539 are electrically connected to each other via electrical connection means (pad portion 120 described later) in the first substrate (more specifically, in the wiring layer 100T). In addition, the floating diffusion portion FD is connected from the first substrate 100 to the second substrate 200 via electrical means (through electrode 120E described later) (more specifically, from the wiring layer 100T to the wiring layer 200T). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion portion FD is electrically connected to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG via electrical means.

[0429] The VSS contact region 118 is a region electrically connected to the reference potential line VSS and is provided separately from the floating diffusion portion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion portion FD is provided at one end of each pixel in the V direction, while the VSS contact region 118 is provided at the other end ( Figure 54A)。The VSS contact region 118 includes, for example, a p-type semiconductor region. For example, the VSS contact region 118 is connected to a ground potential and a fixed potential. Thus, a reference potential is supplied to the semiconductor layer 100S.

[0430] The first substrate 100 includes a transfer transistor TR, a photodiode PD, a floating diffusion portion FD, and a VSS contact region 118. The photodiode PD, the floating diffusion portion FD, the VSS contact region 118, and the transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front side of the semiconductor layer 100S (the side opposite to the light incident surface side, the second substrate 200 side). The transfer transistor TR includes a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front of the semiconductor layer 100S and a vertical portion TGa provided inside the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided inside the n-type semiconductor region 114. By using such a vertical transistor to form the transfer transistor TR, the occurrence of transmission failures of pixel signals can be prevented, and thus the readout efficiency of pixel signals can be improved.

[0431] The horizontal portion TGb of the transfer gate TG extends in the H direction from a position opposite to the vertical portion TGa toward the central portion of the pixel common unit 539, for example ( Figure 54A ). Thereby, the position of the through electrode (through electrode TGV described later) reaching the transfer gate TG in the H direction can be made close to the position of the through electrodes (through electrodes 120E and 121E described later) connected to the floating diffusion portion FD and the VSS contact region 118 in the H direction. For example, the plurality of pixel common units 539 provided in the first substrate 100 have the same structure as each other ( Figure 54A ).

[0432] The semiconductor layer 100S includes a pixel isolation portion 117 that separates the pixels 541A, 541B, 541C, and 541D from each other. The pixel isolation portion 117 is formed to extend in the normal direction of the semiconductor layer 100S (the direction perpendicular to the front of the semiconductor layer 100S). The pixel isolation portion 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from each other and has a lattice-like planar shape ( Figure 54A and Figure 54B)。The pixel isolation section 117 electrically and optically isolates the pixels 541A, 541B, 541C, and 541D from each other, for example. The pixel isolation section 117 includes, for example, a light-shielding film 117A and an insulating film 117B. For example, tungsten (W) or the like is used for the light-shielding film 117A. The insulating film 117B is provided between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B contains, for example, silicon oxide (SiO). The pixel isolation section 117 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel isolation section 117 is not limited to the FTI structure that penetrates the semiconductor layer 100S. For example, the pixel isolation section 117 may have a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S. The pixel isolation section 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

[0433] The semiconductor layer 100S includes, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S and is provided between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on the side surface of the pixel isolation section 117, specifically, between the pixel isolation section 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 each include, for example, a p-type semiconductor region.

[0434] The fixed charge film 112 having negative fixed charges is provided between the semiconductor layer 100S and the insulating film 111. By the electric field induced by the fixed charge film 112, the first pinning region 113 of the hole accumulation layer is formed at the interface on the light-receiving surface (back surface) side of the semiconductor layer 100S. Thereby, the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor layer 100S is suppressed. The fixed charge film 112 is formed using, for example, an insulating film having negative fixed charges. Examples of the material of the insulating film having negative fixed charges include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0435] A light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. The light-shielding film 117A provided between the fixed charge film 112 and the insulating film 111 may be continuously provided with the light-shielding film 117A included in the pixel isolation section 117. For example, the light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided at a position in the semiconductor layer 100S opposite to the pixel isolation section 117. The insulating film 111 is provided to cover the light-shielding film 117A. The insulating film 111 contains, for example, silicon oxide.

[0436] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 includes, in order from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124. For example, the horizontal portion TGb of the transfer gate TG is provided in the wiring layer 100T. The interlayer insulating film 119 is provided over the entire front surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 includes, for example, a silicon oxide film. Note that the structure of the wiring layer 100T is not limited to the above structure, and it is sufficient that the wiring layer 100T has a structure including wirings and insulating films.

[0437] Figure 54B The structure of the pad portions 120 and 121 and Figure 54A the planar structure shown. The pad portions 120 and 121 are provided in selected regions on the interlayer insulating film 119. The pad portion 120 connects the floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to each other. In a plan view, the pad portion 120 is provided in the central portion of the pixel common unit 539 for each pixel common unit 539 ( Figure 54B ). The pad portion 120 is provided so as to straddle the pixel separation portion 117 and is provided so as to at least partially overlap each of the floating diffusion portions FD1, FD2, FD3, and FD4 ( Figure 53 and Figure 54B ). Specifically, the pad portion 120 is formed in a region that overlaps at least a part of each of the plurality of floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of the common pixel circuit 210 and at least a part of the pixel separation portion 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) of the common pixel circuit 210 in a direction perpendicular to the front surface of the semiconductor layer 100S. The interlayer insulating film 119 includes connection vias 120C for electrically connecting the pad portion 120 and the floating diffusion portions FD1, FD2, FD3, and FD4 to each other. The connection vias 120C are provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a part of the pad portion 120 is embedded in the connection vias 120C, thereby electrically connecting the pad portion 120 and the floating diffusion portions FD1, FD2, FD3, and FD4 to each other.

[0438] The pad portion 121 connects the plurality of VSS contact regions 118 to each other. For example, the VSS contact regions 118 provided in pixels 541C and 541D of one pixel sharing unit 539 adjacent to each other in the V direction and the VSS contact regions 118 provided in pixels 541A and 541B of another pixel sharing unit 539 are electrically connected to each other through the pad portion 121. The pad portion 121 is provided to straddle, for example, the pixel separation portion 117, and is provided to at least partially overlap each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps at least a part of each of the plurality of VSS contact regions 118 and at least a part of the pixel separation portion 117 formed between the plurality of VSS contact regions 118 in a direction perpendicular to the front surface of the semiconductor layer 100S. The interlayer insulating film 119 includes connection vias 121C for electrically connecting the pad portion 121 and the VSS contact regions 118 to each other. The connection vias 121C are provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a part of the pad portion 121 is embedded in the connection vias 121C, thereby electrically connecting the pad portion 121 and the VSS contact regions 118. For example, the pad portions 120 and 121 of each of the plurality of pixel sharing units 539 arranged in the V direction are provided at substantially the same positions in the H direction ( Figure 54B ).

[0439] By providing the pad portion 120, the number of wirings for connecting from each floating diffusion portion FD to the pixel circuit 210 (for example, the gate electrode of the amplifying transistor AMP) in the entire chip can be reduced. Similarly, by providing the pad portion 121, the number of wirings for supplying potential to each VSS contact region 118 in the entire chip can be reduced. As a result, reduction in the area of the entire chip, suppression of electrical interference between wirings in miniaturized pixels, and / or cost reduction by reducing the number of components can be achieved.

[0440] The pad portions 120 and 121 can be disposed at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pad portions 120 and 121 can be disposed in one of the insulating regions 212 of the wiring layer 100T and the semiconductor layer 200S. When the pad portions 120 and 121 are disposed in the wiring layer 100T, the pad portions 120 and 121 can be in direct contact with the semiconductor layer 100S. Specifically, the pad portions 120 and 121 can have a structure directly connected to at least a part of the floating diffusion portion FD and / or the VSS contact region 118. In addition, the following structure can be adopted: connection vias 120C and 121C are provided respectively from the floating diffusion portion FD and / or the VSS contact region 118 connected to the pad portions 120 and 121, and the pad portions 120 and 121 are disposed at desired positions in the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S.

[0441] In particular, when the pad portions 120 and 121 are disposed in the wiring layer 100T, the number of wirings in the insulating region 212 of the semiconductor layer 200S connected to the floating diffusion portion FD and / or the VSS contact region 118 can be reduced. Thereby, the area of the insulating region 212 of the second substrate 200 for forming the through-wiring for forming the pixel circuit 210, which is used to connect the floating diffusion portion FD to the pixel circuit 210, can be reduced. Therefore, a larger area of the second substrate 200 for forming the pixel circuit 210 can be ensured. By ensuring the area of the pixel circuit 210, large pixel transistors can be formed, which helps to improve the image quality by noise reduction and the like.

[0442] In particular, when the pixel separation portion 117 uses the FTI structure, the floating diffusion portion FD and / or the VSS contact region 118 are preferably disposed in each pixel 541; therefore, by using the structure of the pad portions 120 and 121, the number of wirings connecting the first substrate 100 and the second substrate 200 to each other can be significantly reduced.

[0443] In addition, as Figure 54B shown, for example, the pad portions 120 connected to a plurality of floating diffusion portions FD and the pad portions 121 connected to a plurality of VSS contact regions 118 are alternately and linearly arranged in the V direction. In addition, the pad portions 120 and 121 are formed at positions surrounded by a plurality of photodiodes PD, a plurality of transfer gates TG, and a plurality of floating diffusion portions FD. Thereby, elements other than the floating diffusion portion FD and the VSS contact region 118 can be freely disposed in the first substrate 100 on which a plurality of elements are formed, and the layout efficiency of the entire chip can be improved. In addition, the symmetry of the layout of the elements formed in each pixel common unit 539 can be ensured, thereby suppressing the deviation of the characteristics of the pixel 541.

[0444] The pad portions 120 and 121 include, for example, polysilicon (Poly Si), more specifically, doped polysilicon doped with impurities. The pad portions 120 and 121 preferably include conductive materials having high heat resistance such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). Thus, the pixel circuit 210 can be formed after attaching the semiconductor layer 200S of the second substrate 200 to the first substrate 100. Hereinafter, the reason therefor will be described. It should be noted that, in the following description, the method of forming the pixel circuit 210 after attaching the semiconductor layer 200S of the first substrate 100 and the second substrate 200 is referred to as the first manufacturing method.

[0445] Here, a method of forming the pixel circuit 210 in the second substrate 200 and then attaching the pixel circuit 210 to the first substrate 100 (hereinafter, referred to as the second manufacturing method) can be conceived. In the second manufacturing method, electrodes for electrical connection are formed in advance on each of the front surface of the first substrate 100 (the front surface of the wiring layer 100T) and the front surface of the second substrate 200 (the front surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are attached together, the electrodes for electrical connection formed on the front surface of the first substrate 100 and the front surface of the second substrate 200 come into contact with each other at the same time. Therefore, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Thus, the imaging device 1 is configured using the second manufacturing method, so that the imaging device 1 can be manufactured using, for example, an appropriate process corresponding to the structures of the first substrate 100 and the second substrate 200, and an imaging device having high quality and high performance can be manufactured.

[0446] In this second manufacturing method, when the first substrate 100 and the second substrate 200 are attached together, an alignment error may occur due to the manufacturing apparatus for attachment. In addition, the first substrate 100 and the second substrate 200 each have a diameter of, for example, approximately several tens of cm, and when the first substrate 100 and the second substrate 200 are joined together, expansion and contraction of the substrates may occur in the microscopic regions of each part of the first substrate 100 and the second substrate 200. The expansion and contraction of the substrates is caused by minute deviations in the timing when the substrates come into contact with each other. Due to this expansion and contraction of the first substrate 100 and the second substrate 200, an error may occur at the positions of the electrodes for electrical connection formed on the front surfaces of the first substrate 100 and the second substrate 200. In the second manufacturing method, it is preferable that the electrodes of the first substrate 100 and the electrodes of the second substrate 200 come into contact with each other even when such an error occurs. Specifically, in consideration of the above-described error, at least one of, preferably both, the electrodes of the first substrate 100 and the electrodes of the second substrate 200 are made larger. Therefore, when the second manufacturing method is used, for example, the size (the size in the substrate plane direction) of the electrodes formed on the front surface of the first substrate 100 or the second substrate 200 becomes larger than the size of the internal electrodes extending from the inside of the first substrate 100 or the second substrate 200 in the thickness direction to the front surface.

[0447] Meanwhile, the pad portions 120 and 121 include a heat-resistant conductive material, and thus the above-described first manufacturing method can be used. In the first manufacturing method, after the first substrate 100 including the photodiode PD and the transfer transistor TR is formed, the first substrate 100 and the second substrate 200 (the semiconductor layer 2000S) are attached together. At this time, the second substrate 200 is in a state where patterns such as active elements and wiring layers included in the pixel circuit 210 have not been formed. The second substrate 200 is in a state before the patterns are formed; therefore, even when an error occurs at the attachment position when the first substrate 100 and the second substrate 200 are attached together, an alignment error between the pattern of the first substrate 100 and the pattern of the second substrate 200 is not caused due to this attachment error. One reason is that the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are attached together. It should be noted that when forming a pattern on the second substrate, for example, in an exposure apparatus for forming the pattern, the pattern formed in the first substrate is used as an alignment target to form the pattern. For the above reasons, in the first manufacturing method, an error in the attachment position between the first substrate 100 and the second substrate 200 is not a problem for the manufacture of the imaging device 1. For similar reasons, an error caused by the expansion and contraction of the substrates generated in the second manufacturing method is also not a problem for the manufacture of the imaging device 1.

[0448] In the first manufacturing method, in this way, after attaching the first substrate 100 and the second substrate 200 (semiconductor layer 200S) together, active elements are formed on the second substrate 200. Thereafter, through electrodes 120E and 121E and through electrode TGV ( Figure 53 ) are formed. For example, in the formation of the through electrodes 120E, 121E, and TGV, reduction projection exposure of an exposure apparatus is used to form a pattern of the through electrodes from above the second substrate 200. Since reduction projection exposure is used, even if an error occurs in the alignment between the second substrate 200 and the exposure apparatus, the magnitude of this error in the second substrate 200 is only a fraction (the reciprocal of the reduction projection exposure magnification) of the error in the above-described second manufacturing method. Therefore, by configuring the imaging device 1 using the first manufacturing method, alignment between the elements formed in each of the first substrate 100 and the second substrate 200 becomes easy, and an imaging device with high quality and high performance can be manufactured.

[0449] The imaging device 1 manufactured using this first manufacturing method has characteristics different from those of the imaging device manufactured by the second manufacturing method. Specifically, in the imaging device 1 manufactured by the first manufacturing method, for example, from the second substrate 200 to the first substrate 100, the through electrodes 120E, 121E, and TGV each have a substantially constant thickness (dimension in the substrate plane direction). Alternatively, when the through electrodes 120E, 121E, and TGV each have a tapered shape, they have a tapered shape with a constant slope. In the imaging device 1 including such through electrodes 120E, 121E, and TGV, the pixels 541 are easily miniaturized.

[0450] Here, when manufacturing the imaging device 1 by the first manufacturing method, after attaching the first substrate 100 and the second substrate 200 (semiconductor layer 200S) together, active elements are formed in the second substrate 200; thus, the heat treatment required for forming the active elements also affects the first substrate 100. Therefore, as described above, the pad portions 120 and 121 provided in the first substrate 100 preferably use a conductive material with higher heat resistance. For example, the pad portions 120 and 121 preferably use a material with a higher melting point (i.e., higher heat resistance) compared to at least a part of the wiring material included in the wiring layer 200T of the second substrate 200. For example, the pad portions 120 and 121 use conductive materials with high heat resistance such as doped polysilicon, tungsten, titanium, and titanium nitride. Thereby, the imaging device 1 can be manufactured using the above-described first manufacturing method.

[0451] For example, a passivation film 122 is provided over the entire front surface of the semiconductor layer 100S to cover the pad portions 120 and 121 ( Figure 53)。The passivation film 122 includes, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 with the passivation film 122 interposed therebetween. For example, the interlayer insulating film 123 is provided over the entire front surface of the semiconductor layer 100S. The interlayer insulating film 123 includes, for example, a silicon oxide (SiO) film. The bonding film 124 is provided at the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. The bonding film 124 is provided over the entire main surface of the first substrate 100. The bonding film 124 includes, for example, a silicon nitride film.

[0452] For example, the light receiving lens 401 faces the semiconductor layer 100S with the fixed charge film 112 and the insulating film 111 interposed therebetween ( Figure 53 ). For example, the light receiving lens 401 is provided at a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D.

[0453] The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T in this order from the first substrate 100 side. The semiconductor layer 200S includes a silicon substrate. In the semiconductor layer 200S, a well region 211 is provided in the thickness direction. The well region 211 is, for example, a p-type semiconductor region. In the second substrate 200, a pixel circuit 210 is provided for each pixel common unit 539. For example, the pixel circuit 210 is provided on the front side (wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is attached to the first substrate 100 such that the back side (semiconductor layer 200S side) of the second substrate 200 faces the front side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is attached to the first substrate 100 in a back-to-back manner.

[0454] Figures 55 to 59 Examples of the planar configuration of the second substrate 200 are schematically shown. Figure 55 The configuration of the pixel circuit 210 provided near the front surface of the semiconductor layer 200S is shown. Figure 56 The configurations of each of the wiring layer 200T (specifically, the first wiring layer W1 described later), the semiconductor layer 200S connected to the wiring layer 200T, and the first substrate 100 are schematically shown. Figures 57 to 59 Examples of the planar configuration of the wiring layer 200T are shown respectively. Below, using Figures 55 to 59 and Figure 53 the configuration of the second substrate 200 is described. In Figure 55 and Figure 56In the figure, the outer shape of the photodiode PD (the boundary between the pixel separation section 117 and the photodiode PD) is indicated by a dashed line, and the boundary between the semiconductor layer 200S and the element separation region 213 or the insulating region 212 in the portion overlapping with the gate electrode of each transistor included in the pixel circuit 210 is indicated by a dotted line. In the portion overlapping with the gate electrode of the amplification transistor AMP, the boundary between the semiconductor layer 200S and the element separation region 213 and the boundary between the element separation region 213 and the insulating region 212 are provided in one channel width direction.

[0455] The second substrate 200 includes an insulating region 212 that divides the semiconductor layer 200S and an element separation region 213 provided in a part of the semiconductor layer 200S in the thickness direction ( Figure 53 ). For example, in the insulating region 212 provided between two pixel circuits 210 adjacent to each other along the H direction, through electrodes 120E and 121E of two pixel common units 539 connected to the two pixel circuits 210 and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) are provided ( Figure 56 ).

[0456] The insulating region 212 has a thickness substantially the same as the thickness of the semiconductor layer 200S ( Figure 53 ). The semiconductor layer 200S is divided by the insulating region 212. The through electrodes 120E and 121E and the through electrodes TGV are provided in the insulating region 212. The insulating region 212 contains, for example, silicon oxide.

[0457] The through electrodes 120E and 121E are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wirings of the wiring layer 200T (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4 described later). The through electrodes 120E and 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends of the through electrodes 120E and 121E are connected to the pad portions 120 and 121 ( Figure 53 ). The through electrode 120E electrically connects the pad portion 120 and the pixel circuit 210 to each other. That is, the floating diffusion portion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 through the through electrode 120E. The through electrode 121E electrically connects the pad portion 121 and the reference potential line VSS of the wiring layer 200T to each other. That is, the VSS contact region 118 of the first substrate 100 is electrically connected to the reference potential line VSS of the second substrate 200 through the through electrode 121E.

[0458] The through electrode TGV is configured to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring layer 200T. The through electrode TGV is configured to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and the lower end of the through electrode TGV is connected to the transmission gate TG( Figure 53 ). Such a through electrode TGV electrically connects the transmission gates TG (transmission gates TG1, TG2, TG3, and TG4) of the pixels 541A, 541B, 541C, and 541D and the wiring of the wiring layer 200T (a part of the row drive signal line 542, specifically the wiring TRG1, TRG2, TRG3, and TRG4 in Figure 58 to be described later) to each other. That is, the transmission gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 through the through electrode TGV to transmit a drive signal to each transmission transistor TR (transmission transistors TR1, TR2, TR3, and TR4).

[0459] The insulating region 212 is a region for insulating the semiconductor layer 200S from the through electrodes 120E and 121E and the through electrode TGV that electrically connect the first substrate 100 and the second substrate 200 to each other. For example, in the insulating region 212 provided between two pixel circuits 210 (pixel common unit 539) adjacent to each other in the H direction, the through electrodes 120E and 121E and the through electrode TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) connected to the two pixel circuits 210 are provided. The insulating region 212 is configured to extend in the V direction, for example ( Figure 55 and 56 ). Here, the setting of the horizontal portion TGb of the transmission gate TG is designed such that the position of the through electrode TGV in the H direction is set closer to the position of the through electrodes 120E and 121E in the H direction than the position of the vertical portion TGa ( Figure 54A and Figure 56)。For example, the through electrode TGV is disposed at substantially the same position in the H direction as the through electrodes 120E and 120E. Thus, the through electrodes 120E and 121E and the through electrode TGV can be uniformly disposed in the insulating region 212 extending along the V direction. As another layout example, it is conceivable to dispose the horizontal portion TGb only in the region superimposed on the vertical portion TGa. In this case, the through electrode TGV is formed substantially directly above the vertical portion TGa, and the through electrode TGV is disposed, for example, in the substantially central portions of each pixel 541 in the H direction and the Y direction. At this time, the position of the through electrode TGV in the H direction significantly deviates from the positions of the through electrodes 120E and 121E in the H direction. For example, the insulating region 212 is disposed around the through electrode TGV and the through electrodes 120E and 121E to electrically insulate these through electrodes from the semiconductor layer 200S in the vicinity thereof. When the position of the through electrode TGV in the H direction and the positions of the through electrodes 120E and 121E in the H direction are far apart from each other, it is necessary to independently dispose the insulating region 212 around each of the through electrodes 120E, 121E, and TGV. Therefore, the semiconductor layer 200S is finely divided. In contrast, the layout in which the through electrodes 120E and 121E and the through electrode TGV are uniformly disposed in the insulating region 212 extending along the V direction can increase the size of the semiconductor layer 200S in the H direction. Thus, a larger area of the semiconductor element formation region in the semiconductor layer 200S can be ensured. Therefore, for example, the size of the amplifying transistor AMP can be increased and the noise can be reduced.

[0460] As described with reference to Figure 51 above, the pixel sharing unit 539 electrically connects the floating diffusion portions FD provided in the respective pixels 541 together and has a structure in which a plurality of pixels 541 share one pixel circuit 210. In addition, the electrical connection between the floating diffusion portions FD is achieved by the pad portion 120 provided in the first substrate 100 ( Figure 53 and Figure 54B ). The electrical connection portion (pad portion 120) provided in the first substrate 100 and the pixel circuit 210 provided in the second substrate 200 are electrically connected together via one through electrode 120E. Alternatively, as another structural example, it is also conceivable to dispose the electrical connection portion between the floating diffusion portions FD in the second substrate 200. In this case, the pixel sharing unit 539 includes four through electrodes respectively connected to the floating diffusion portions FD1, FD2, FD3, and FD4. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 for insulating the periphery of the through electrodes becomes larger. In contrast, the structure of the first substrate 100 including the pad portion 120 ( Figure 53 andFigure 54B )The number of via electrodes can be reduced and the insulating region 212 can be made smaller. Therefore, a larger area of the semiconductor element formation region in the semiconductor layer 200S can be ensured. Thus, for example, the size of the amplifying transistor AMP can be increased, thereby suppressing noise.

[0461] The element isolation region 213 is provided on the front side of the semiconductor layer 200S. The element isolation region 213 has an STI (shallow trench isolation) structure. In the element isolation region 213, the semiconductor layer 200S is excavated in the thickness direction (the direction perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in the excavation portion. The insulating film contains, for example, silicon oxide. According to the layout of the pixel circuit 210, the element isolation region 213 performs element isolation between the plurality of transistors included in the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (the deep part of the semiconductor layer 200S).

[0462] Here, with reference to Figure 54A 、 Figure 54B and Figure 55 , the difference between the outer shape (the outer shape in the substrate plane direction) of the pixel sharing unit 539 in the first substrate 100 and the outer shape of the pixel sharing unit 539 in the second substrate 200 will be described.

[0463] In the imaging device 1, the pixel sharing unit 539 is provided on both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel sharing unit 539 provided in the first substrate 100 and the outer shape of the pixel sharing unit 539 provided in the second substrate 200 are different from each other.

[0464] In Figure 54A and Figure 54B , the outer shape lines of the respective pixels 541A, 541B, 541C, and 541D are represented by alternately long and short dashed lines, and the outer shape line of the pixel sharing unit 539 is represented by a thick line. For example, the pixel sharing unit 539 of the first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to these two pixels 541 in the V direction. That is, the pixel sharing unit 539 of the first substrate 100 includes four pixels 541 in two adjacent rows and two columns, and the pixel sharing unit 539 of the first substrate 100 has a substantially square outer shape. In the pixel array unit 540, such pixel sharing units 539 are arranged adjacent to each other at two pixel pitches (corresponding to the pitch of two pixels 541) in the H direction and two pixel pitches (corresponding to the pitch of two pixels 541) in the V direction.

[0465] In Figure 55 and Figure 56 , the outer shape lines of each of the pixels 541A, 541B, 541C, and 541D are represented by alternately long and short dashed lines, and the outer shape line of the pixel common unit 539 is represented by a thick line. For example, the outer shape of the pixel common unit 539 of the second substrate 200 is smaller than that of the pixel common unit 539 of the first substrate 100 in the H direction and larger than that of the pixel common unit 539 of the first substrate 100 in the V direction. For example, the pixel common unit 539 of the second substrate 200 is formed to have a size (area) equivalent to one pixel in the H direction and a size equivalent to four pixels in the V direction. That is, the pixel common unit 539 of the second substrate 200 is formed to have a size equivalent to pixels arranged adjacent to each other in 1 row × 4 columns, and the pixel common unit 539 of the second substrate 200 has a substantially rectangular outer shape.

[0466] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged side by side in sequence in the V direction ( Figure 55 ). As described above, the outer shape of each pixel circuit 210 is a substantially rectangular shape, so that four transistors (the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG) can be arranged side by side in one direction ( Figure 55 the V direction in). Thus, the drain of the amplification transistor AMP and the drain of the reset transistor RST can be shared in one diffusion region (the diffusion region connected to the power supply line VDD). For example, the formation region of each pixel circuit 210 having a substantially square shape can be provided (see Figure 68 described later). In this case, two transistors are arranged in one direction, so that it is difficult to share the drain of the amplification transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by providing the formation region of the pixel circuit 210 having a substantially rectangular shape, it is easy to arrange the four transistors close to each other, and the formation region of the pixel circuit 210 can be reduced. That is, the pixel can be miniaturized. In addition, when it is not necessary to reduce the formation region of the pixel circuit 210, the formation region of the amplification transistor AMP can be increased, thereby suppressing noise.

[0467] For example, near the front surface of the semiconductor layer 200S, in addition to the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided. The VSS contact region 218 includes, for example, a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through electrode 121E. For example, the VSS contact region 218 is provided at a position adjacent to the source of the FD conversion gain switching transistor FDG with the element isolation region 213 therebetween ( Figure 55 ).

[0468] Next, with reference to Figure 54B and Figure 55 , the positional relationship between the pixel common unit 539 provided in the first substrate 100 and the pixel common unit 539 provided in the second substrate 200 will be described. For example, one of the two pixel common units 539 arranged along the V direction of the first substrate 100 (e.g., Figure 54B the upper side of the paper surface) pixel common unit 539 is connected to one of the two pixel common units 539 arranged along the H direction of the second substrate 200 (e.g., Figure 55 the left side of the paper surface) pixel common unit 539. For example, the other of the two pixel common units 539 arranged along the V direction of the first substrate 100 (e.g., Figure 54B the lower side of the paper surface) pixel common unit 539 is connected to the other of the two pixel common units 539 arranged along the H direction of the second substrate 200 (e.g., Figure 55 the right side of the paper surface) pixel common unit 539.

[0469] For example, among the two pixel common units 539 arranged along the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel common unit 539 is substantially the same as the layout obtained by inverting the internal layout of the other pixel common unit 539 in the V direction and the H direction. The effects achieved by this layout will be described below.

[0470] Among the two pixel common units 539 arranged along the V direction of the first substrate 100, each pad portion 120 is provided in the central portion of the outer shape of the pixel common unit 539, that is, in the central portions of the pixel common unit 539 in the V direction and the H direction ( Figure 54B)。Meanwhile, as described above, the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outer shape that is longer in the V direction. Therefore, for example, the amplification transistor AMP connected to the pad portion 120 is disposed at a position deviated upward from the center of the pixel sharing unit 539 in the V direction toward the paper surface. For example, when the internal layouts of the two pixel sharing units 539 arranged along the H direction of the second substrate 200 are the same, the distance between the amplification transistor AMP of one pixel sharing unit 539 and the pad portion 120 (e.g., Figure 7 the pad portion 120 of the pixel sharing unit 539 on the upper side of the paper surface) is relatively short. However, the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad portion 120 (e.g., Figure 7 the pad portion 120 of the pixel sharing unit 539 on the lower side of the paper surface) is long. Therefore, the area of the wiring required for connecting the amplification transistor AMP and the pad portion 120 increases, which may complicate the wiring layout of the pixel sharing unit 539. The presence of this situation may affect the possibility of miniaturizing the imaging device 1.

[0471] In contrast, the internal layouts of the two pixel sharing units 539 arranged along the H direction of the second substrate 200 are inverted at least in the V direction, so that the distance between the amplification transistor AMP of these two pixel sharing units 539 and the pad portion 120 can be shortened. Therefore, compared with the structure in which the internal layouts of the two pixel sharing units 539 arranged along the H direction of the second substrate 200 are the same, it is easier to implement miniaturization of the imaging device 1. It should be noted that the planar layout of each of the plurality of pixel sharing units 539 of the second substrate 200 is symmetric about the left and right within the range shown in Figure 55 shown, however, the layout including the layout of the first wiring layer W1 shown in Figure 56 described later is asymmetric about the left and right.

[0472] In addition, the internal layouts of the two pixel sharing units 539 arranged along the H direction of the second substrate 200 are preferably inverted with respect to each other also in the H direction. The reason will be described below. As Figure 56As shown, the two pixel sharing units 539 arranged along the H direction of the second substrate 200 are respectively connected to the pad portions 120 and 121 of the first substrate 100. For example, the pad portions 120 and 121 are provided in the central portions in the H direction (between the two pixel sharing units 539 arranged along the H direction) of the two pixel sharing units 539 arranged along the H direction of the second substrate 200. Therefore, the internal layouts of the two pixel sharing units 539 arranged along the H direction of the second substrate 200 are also reversed from each other in the H direction, so that the distances between each of the multiple pixel sharing units 539 of the second substrate 200 and the pad portions 120 and 121 can be reduced. That is, this further promotes the miniaturization of the imaging device 1.

[0473] In addition, the positions of the outer contour lines of the pixel sharing units 539 of the second substrate 200 may not be the same as those of any of the pixel sharing units 539 of the first substrate 100. For example, in one of the two pixel sharing units 539 arranged along the H direction of the second substrate 200 (for example, Figure 56 the left side of the paper surface), one outer contour line in the V direction (for example, Figure 56 the upper side of the paper surface) is arranged outside one outer contour line in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, Figure 54B the upper side of the paper surface). In addition, in the other of the two pixel sharing units 539 arranged along the H direction of the second substrate 200 (for example, Figure 56 the right side of the paper surface), the other outer contour line in the V direction (for example, Figure 56 the lower side of the paper surface) is arranged outside the other outer contour line in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, Figure 54B the lower side of the paper surface). By providing both the pixel sharing units 539 of the second substrate 200 and the pixel sharing units 539 of the first substrate 100, the distance between the amplifying transistor AMP and the pad portion 120 can be shortened. This promotes the miniaturization of the imaging device 1.

[0474] In addition, the positions of the outer contour lines of the multiple pixel sharing units 539 of the second substrate 200 may not be the same. For example, the two pixel sharing units 539 arranged along the H direction of the second substrate 200 are arranged such that the positions of the outer contour lines in the V direction are offset. Thereby, the distance between the amplifying transistor AMP and the pad portion 120 can be shortened. Therefore, the miniaturization of the imaging device 1 is promoted.

[0475] Refer to Figure 54B and Figure 56, the repeated arrangement of the pixel sharing unit 539 in the pixel array unit 540 is described. The pixel sharing unit 539 of the first substrate 100 has a size of two pixels 541 in the H direction and a size of two pixels 541 in the V direction ( Figure 54B ). For example, in the pixel array unit 540 of the first substrate 100, the pixel sharing unit 539 having a size equivalent to four pixels 541 is repeatedly arranged adjacent to each other in such a manner that the pitch in the H direction is two pixel pitches (equivalent to the pitch of two pixels 541) and the pitch in the V direction is two pixel pitches (equivalent to the pitch of two pixels 541). Alternatively, in the pixel array unit 540 of the first substrate 100, a pair of pixel sharing units 539 that are two pixel sharing units 539 adjacent to each other in the V direction may be provided. In the pixel array unit 540 of the first substrate 100, for example, this pair of pixel sharing units 539 is repeatedly arranged adjacent to each other in such a manner that the pitch in the H direction is two pixel pitches (equivalent to the pitch of two pixels 541) and the pitch in the V direction is four pixel pitches (equivalent to the pitch of four pixels 541). The pixel sharing unit 539 of the second substrate 200 has a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction ( Figure 56 ). For example, in the pixel array unit 540 of the second substrate 200, a pair of pixel sharing units 539 is provided, and this pair of pixel sharing units 539 includes two pixel sharing units 539 having a size equivalent to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and are arranged to be offset in the V direction. In the pixel array unit 540 of the second substrate 200, for example, the pair of pixel sharing units 539 is repeatedly arranged adjacent to each other without a gap and in such a manner that the pitch in the H direction is two pixel pitches (equivalent to the pitch of two pixels 541) and the pitch in the V direction is four pixel pitches (equivalent to the pitch of four pixels 541). Through this repeated arrangement of the pixel sharing unit 539, the pixel sharing unit 539 can be arranged without a gap. Therefore, miniaturization of the imaging device 1 is promoted.

[0476] For example, the amplification transistor AMP preferably has a three-dimensional structure such as a fin type ( Figure 53 ). Thereby, the size of the effective gate width is increased, and thus noise can be suppressed. The selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG have, for example, a planar structure. The amplification transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switching transistor FDG may have a three-dimensional structure.

[0477] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221 is in contact with, for example, the front surface of the semiconductor layer 200S and covers the entire front surface of the semiconductor layer 200S. The passivation film 221 covers the respective gate electrodes of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. The interlayer insulating film 222 separates the plurality of wirings (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4). The interlayer insulating film 222 contains, for example, silicon oxide.

[0478] In the wiring layer 200T, for example, starting from the semiconductor layer 200S side, the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, the fourth wiring layer W4, and the contact portions 201 and 202 are sequentially provided, and these elements are insulated from each other by the interlayer insulating film 222. The interlayer insulating film 222 includes a plurality of connection portions that connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to the layer therebelow. The connection portion is a portion in which a connection hole provided in the interlayer insulating film 222 is embedded with a conductive material. For example, the interlayer insulating film 222 includes a connection portion 218V that connects the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S to each other. For example, the aperture diameter of such a connection portion that connects the elements of the second substrate 200 to each other is different from the aperture diameters of the through electrodes 120E and 121E and the through electrode TGV. Specifically, the aperture diameter of the connection hole that connects the elements of the second substrate 200 to each other is preferably smaller than the aperture diameters of the through electrodes 120E and 121E and the through electrode TGV. The reason therefor will be described below. The depth of the connection portion (such as the connection portion 218V, etc.) provided in the wiring layer 200T is smaller than the depths of the through electrodes 120E and 121E and the through electrode TGV. Therefore, in the connection portion, the conductive material can be more easily embedded in the connection hole as compared with the through electrodes 120E and 121E and the through electrode TGV. By making the aperture diameter of the connection portion smaller than the aperture diameters of the through electrodes 120E and 121E and the through electrode TGV, miniaturization of the imaging device 1 can be promoted.

[0479] For example, the through electrode 120E is connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, the connection hole reaching the source of the FD conversion gain switching transistor FDG) via the first wiring layer W1. The first wiring layer W1 connects the through electrode 121E and the connection portion 218V to each other, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S to each other.

[0480] Next, with reference to Figures 57 to 59 , the planar structure of the wiring layer 200T will be described. Figure 57 An example of the planar structure of the first wiring layer W1 and the second wiring layer W2 is shown. Figure 58 An example of the planar structure of the second wiring layer W2 and the third wiring layer W3 is shown. Figure 59 An example of the planar structure of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0481] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL that extend in the H direction (row direction) ( Figure 58 ). These wirings correspond to the multiple row drive signal lines 542 described with reference to Figure 51 . The wirings TRG1, TRG2, TRG3, and TRG4 transmit drive signals to the transmission gates TG1, TG2, TG3, and TG4, respectively. The wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transmission gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through electrode 120E, respectively. The wiring SELL transmits a drive signal to the gate of the selection transistor SEL, the wiring RSTL transmits a drive signal to the gate of the reset transistor RST, and the wiring FDGL transmits a drive signal to the gate of the FD conversion gain switching transistor FDG. The wirings SELL, RSTL, and FDGL are connected to the gate of the selection transistor SEL, the gate of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG via the second wiring layer W2, the first wiring layer W1, and the connection portion, respectively.

[0482] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 that extend in the V direction (column direction) ( Figure 59 ). The power supply line VDD is connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion. The reference potential line VSS is connected to the VSS contact area 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion 218V. In addition, the reference potential line VSS is connected to the VSS contact area 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion.

[0483] In the plan view, the contact portions 201 and 202 may be disposed at positions overlapping with the pixel array portion 540 (e.g., Figure 50 ), or may be disposed in the peripheral portion 540B outside the pixel array portion 540 (e.g., Figure 53 ). The contact portions 201 and 202 are disposed on the front surface of the second substrate 200 (the surface on the side of the wiring layer 200T). For example, the contact portions 201 and 202 include metals such as Cu (copper) and Al (aluminum). The contact portions 201 and 202 are exposed on the front surface of the wiring layer 200T (the surface on the side of the third substrate 300). The contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and attachment between the second substrate 200 and the third substrate 300.

[0484] Figure 53 An example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 200 is shown. The peripheral circuit may include a part of the row driver portion 520 or a part of the column signal processor 550. In addition, as Figure 50 shown, a peripheral circuit may not be provided in the peripheral portion 540B of the second substrate 200, and the connection hole portions H1 and H2 may be provided near the pixel array portion 540.

[0485] The third substrate 300 includes, for example, a wiring layer 300T and a semiconductor layer 300S in this order from the side of the second substrate 200. For example, the front surface of the semiconductor layer 300S is disposed on the side of the second substrate 200. The semiconductor layer 300S includes a silicon substrate. A circuit is provided in a part of the front surface side of the semiconductor layer 300S. Specifically, for example, at least a part of the input portion 510A, the row driver portion 520, the timing controller 530, the column signal processor 550, the image signal processor 560, and the output portion 510B is provided in a part of the front surface side of the semiconductor layer 300S. The wiring layer 300T disposed between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and the contact portions 301 and 302. The contact portions 301 and 302 are exposed on the front surface of the wiring layer 300T (the surface on the side of the second substrate 200). The contact portion 301 is connected to the contact portion 201 of the second substrate 200, and the contact portion 302 is connected to the contact portion 202 of the second substrate 200. The contact portions 301 and 302 are electrically connected to a circuit formed in the semiconductor layer 300S (e.g., at least one of the input portion 510A, the row driver portion 520, the timing controller 530, the column signal processor 550, the image signal processor 560, and the output portion 510B). For example, the contact portions 301 and 302 include metals such as Cu (copper) and aluminum (Al). For example, the external terminal TA is connected to the input portion 510A via the connection hole portion H1, and the external terminal TB is connected to the output portion 510B via the connection hole portion H2.

[0486] Here, the characteristics of the imaging device 1 are described.

[0487] Generally, an imaging device includes a photodiode and a pixel circuit as main components. Here, when the area of the photodiode increases, the charge generated by photoelectric conversion increases, so the signal-to-noise ratio (S / N ratio) of the pixel signal can be improved, enabling the imaging device to output more favorable image data (image information). At the same time, when the size of the transistors included in the pixel circuit (specifically, the size of the amplifying transistors) increases, the noise generated in the pixel circuit decreases, so the S / N ratio of the imaging signal can be improved, enabling the imaging device to output more favorable image data (image information).

[0488] However, in an imaging device where the photodiode and the pixel circuit are provided on the same semiconductor substrate, it can be conceived that when the area of the photodiode increases within the limited area of the semiconductor substrate, the size of the transistors included in the pixel circuit will decrease. Additionally, it can be conceived that when the size of the transistors included in the pixel circuit increases, the area of the photodiode will decrease.

[0489] To solve these problems, for example, the imaging device 1 according to the present embodiment uses the following structure: wherein, a plurality of pixels 541 share a single pixel circuit 210, and the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD. Thus, the area of the photodiode PD can be made as large as possible within the limited area of the semiconductor substrate, and the size of the transistors included in the pixel circuit 210 can be made as large as possible. Thereby, the S / N ratio of the pixel signal can be improved, enabling the imaging device 1 to output more favorable image data (image information).

[0490] When implementing the structure in which a plurality of pixels 541 share a single pixel circuit 210 and the pixel circuit 210 is arranged to be superimposed on the photodiode PD, a plurality of wirings extend from the floating diffusion portions FD of each of the plurality of pixels 541 to a single pixel circuit 210. To ensure a relatively large area for the second substrate 200 on which the pixel circuit 210 is formed, for example, connection wirings can be formed to connect the extended plurality of wirings to each other to combine them into one. Regarding the plurality of wirings extending from the VSS contact region 118, connection wirings can be formed to connect the extended plurality of wirings to each other to combine them into one.

[0491] For example, it can be conceived that when forming a connection wiring that connects multiple wirings extending from the floating diffusion portions FD of respective ones of the multiple pixels 541 to each other in the second substrate 200 on which the pixel circuit 210 is formed, the area of the transistors included in the pixel circuit 210 is reduced. Similarly, it can be conceived that when forming a connection wiring that connects multiple wirings extending from the VSS contact regions 118 of respective ones of the multiple pixels 541 to each other in the second substrate 200 on which the pixel circuit 210 is formed to combine them into one, the area of the transistors included in the pixel circuit 210 is reduced.

[0492] To solve these problems, for example, the imaging device 1 according to the present embodiment can have a structure in which multiple pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is provided so as to be superimposed on the photodiode PD, and can also have a structure in which the first substrate 100 includes a connection wiring that connects the respective floating diffusion portions FD of the multiple pixels 541 to each other to combine them into one and a connection wiring that connects the VSS contact regions 118 included in the respective pixels 541 to each other to combine them into one.

[0493] Here, when using the above-described second manufacturing method as a manufacturing method for providing a connection wiring that connects the respective floating diffusion portions FD of the multiple pixels 541 to each other to combine them into one and a connection wiring that connects the respective VSS contact regions 118 of the multiple pixels 541 to each other to combine them into one in the first substrate 100, manufacturing can be performed using an appropriate process corresponding to the respective structures of the first substrate 100 and the second substrate 200, and an imaging device having high quality and high performance can be manufactured. In addition, the connection wirings of the first substrate 100 and the second substrate 200 can be formed by a simple process. Specifically, in the case of using the above-described second manufacturing method, on the front surface of the first substrate 100 and the front surface of the second substrate 200 that form the attachment boundary surface between the first substrate 100 and the second substrate 200, an electrode connected to the floating diffusion portion FD and an electrode connected to the VSS contact region 118 are respectively provided. In addition, the sizes of the electrodes formed on the front surfaces of the two substrates are preferably increased so that when the first substrate 100 and the second substrate 200 are attached together, even when a positional shift occurs between the electrodes formed on the front surfaces of the two substrates, the electrodes formed on the front surfaces of the two substrates will contact each other. In this case, it is considered difficult to provide the above-described electrodes in the limited area of each pixel included in the imaging device 1.

[0494] In order to solve the problem that a relatively large electrode is required on the attachment boundary surface between the first substrate 100 and the second substrate 200, for example, in the imaging device 1 according to the present embodiment, the above-described first manufacturing method can be used as a manufacturing method in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is provided so as to be superimposed on the photodiode PD. Thereby, alignment of elements in each of the first substrate 100 and the second substrate 200 can be promoted, and an imaging device having high quality and high performance can be manufactured. In addition, an inherent structure formed by using this manufacturing method can be provided. That is, it includes a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in sequence. In other words, it includes a structure in which the first substrate 100 and the second substrate 200 are stacked back-to-back, and includes through electrodes 120E and 121E that penetrate from the front side of the semiconductor layer 200S of the second substrate 200 through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 to reach the front of the semiconductor layer 100S of the first substrate 100.

[0495] When, in a structure in which connection wirings that connect the respective floating diffusion portions FD of a plurality of pixels 541 to each other to combine them into one and connection wirings that connect the respective VSS contact regions 118 of a plurality of pixels 541 to each other to combine them into one are provided in the first substrate 100, the first manufacturing method is used to stack this structure and the second substrate 200 to form the pixel circuit 210 in the second substrate 200, there is a possibility that the heat treatment required for forming the active elements included in the pixel circuit 210 may affect the above-described connection wirings formed in the first substrate 100.

[0496] Therefore, in order to solve the problem that the heat treatment for forming the above-described active elements affects the above-described connection wirings, in the imaging device 1 according to the present embodiment, it is desirable to use a conductive material having high heat resistance for the connection wirings that connect the respective floating diffusion portions of a plurality of pixels 541 to each other to combine them into one and the connection wirings that connect the respective VSS contact regions 118 of a plurality of pixels 541 to each other to combine them into one. Specifically, as the conductive material having high heat resistance, a material having a higher melting point than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200 can be used.

[0497] As described above, for example, the imaging device 1 according to the present embodiment has the following structure: (1) a structure in which the first substrate 100 and the second substrate 200 are stacked back-to-back (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in sequence); (2) a structure in which through electrodes 120E and 121E are provided that penetrate from the front side of the semiconductor layer 200S of the second substrate 200 through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 to reach the front side of the semiconductor layer 100S of the first substrate 100; and (3) a structure in which connection wirings that connect the respective floating diffusion portions FD included in the plurality of pixels 541 to each other to combine them into one and connection wirings that connect the respective VSS contact regions 118 included in the plurality of pixels 541 to each other to combine them into one are formed using a conductive material having high heat resistance. Thus, connection wirings that connect the respective floating diffusion portions FD included in the plurality of pixels 541 to each other to combine them into one and connection wirings that connect the respective VSS contact regions 118 included in the plurality of pixels 541 to each other to combine them into one can be provided in the first substrate 100 without providing large electrodes at the interface between the first substrate 100 and the second substrate 200.

[0498] [Operation of Imaging Device 1]

[0499] Next, use Figure 60 and Figure 61 to describe the operation of the imaging device 1. Figure 60 and Figure 61 For Figure 50 arrows indicating the paths of each signal are added. Figure 60 The paths of the input signals, power supply potential, and reference potential input to the imaging device 1 from the outside, indicated by the arrows, are shown. Figure 61The signal path of the pixel signal output from the imaging device 1 to the outside, indicated by arrows, is shown. For example, the input signals (e.g., pixel clock and synchronization signal) input to the imaging device 1 via the input unit 510A are transmitted to the row driver unit 520 of the third substrate 300, and the row driver signal is generated by the row driver unit 520. The row driver signal is transmitted to the second substrate 200 via the contact portions 301 and 201. Further, the row driver signal reaches each pixel common unit 539 of the pixel array unit 540 via the row driver signal line 542 in the wiring layer 200T. Among the row driver signals reaching the pixel common unit 539 of the second substrate 200, the drive signals other than the transfer gate TG are input to the pixel circuit 210 to drive each transistor included in the pixel circuit 210. The drive signal of the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV to drive the pixels 541A, 541B, 541C, and 541D( Figure 60 ). In addition, the power supply potential and the reference potential supplied to the input unit 510A (input terminal 511) of the third substrate 300 from the outside of the imaging device 1 are transmitted to the second substrate 200 via the contact portions 301 and 201, and are supplied to the pixel circuit 210 of each pixel common unit 539 via the wiring in the wiring layer 200T. The reference potential is further supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. At the same time, the pixel signals photoelectrically converted in the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to the pixel circuit 210 of the second substrate 200 for each pixel common unit 539 via the through electrode 120E. The pixel signals based on the pixel signals are transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact portions 202 and 302. The pixel signals are processed in the column signal processor 550 and the image signal processor 560 of the third substrate 300, and then output to the outside via the output unit 510B.

[0500] [Effect]

[0501] In this embodiment, pixels 541A, 541B, 541C, and 541D (pixel common unit 539) and the pixel circuit 210 are provided on different substrates (the first substrate 100 and the second substrate 200). Thus, compared with the case where the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 are formed on the same substrate, the areas of the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 can be increased. Therefore, the amount of pixel signals obtained by photoelectric conversion can be increased, and the transistor noise of the pixel circuit 210 can be reduced. As a result, the signal-to-noise ratio of the pixel signals can be improved, enabling the imaging device 1 to output more favorable pixel data (image information). In addition, the imaging device 1 can be miniaturized (in other words, the pixel size can be reduced and the size of the imaging device 1 can be shrunk). By reducing the pixel size, the number of pixels per unit area can be increased, and the imaging device 1 can output an image with high image quality.

[0502] In addition, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other through through electrodes 120E and 121E provided in the insulating region 212. For example, a method of connecting the first substrate 100 and the second substrate 200 to each other by bonding pad electrodes together and a method of connecting the first substrate 100 and the second substrate 200 to each other through a through wiring (e.g., TSV (Thorough Si Via)) penetrating the semiconductor layer can be conceived. Compared with such methods, by providing the through electrodes 120E and 121E in the insulating region 212, the area required for connecting the first substrate 100 and the second substrate 200 can be reduced. Thereby, the pixel size can be reduced and the size of the imaging device 1 can be further shrunk. In addition, through further miniaturization of the area of each pixel, the resolution can be further improved. When it is not necessary to reduce the chip size, the formation regions of the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 can be enlarged. Therefore, the amount of pixel signals obtained by photoelectric conversion can be increased, and the noise of the transistors included in the pixel circuit 210 can be reduced. As a result, the signal-to-noise ratio of the pixel signals can be improved, enabling the imaging device 1 to output more favorable pixel data (image information).

[0503] In addition, in the imaging device 1, the pixel circuit 210, the column signal processor 550, and the image signal processor 560 are provided on different substrates (the second substrate 200 and the third substrate 300). Therefore, compared with the case where the pixel circuit 210, the column signal processor 550, and the image signal processor 560 are formed on the same substrate, the area of the pixel circuit 210 and the areas of the column signal processor 550 and the image signal processor 560 can be increased. As a result, the noise generated in the column signal processor 550 can be reduced, and a more advanced image processing circuit can be installed in the image signal processor 560. Therefore, the signal-to-noise ratio of the pixel signal can be improved, so that the imaging device 1 outputs more favorable pixel data (image information).

[0504] In addition, in the imaging device 1, the pixel array unit 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processor 550 and the image signal processor 560 are provided on the third substrate 300. In addition, the contact portions 201, 202, 301, and 302 that connect the second substrate 200 and the third substrate 300 to each other are formed above the pixel array unit 540. As a result, the contact portions 201, 202, 301, and 302 can be freely arranged without disturbing the layout of various types of wirings included in the pixel array. Therefore, the contact portions 201, 202, 301, and 302 can be used for electrical connection between the second substrate 200 and the third substrate 300. By using the contact portions 201, 202, 301, and 302, for example, the degree of freedom in the layout of the column signal processor 550 and the image signal processor 560 is increased. As a result, the noise generated in the column signal processor 550 can be reduced, and a more advanced image processing circuit can be installed in the image signal processor 560. Therefore, the signal-to-noise ratio of the pixel signal can be improved, so that the imaging device 1 outputs more favorable pixel data (image information).

[0505] In addition, in the imaging device 1, the pixel separation portion 117 penetrates the semiconductor layer 100S. Therefore, even when the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) is reduced due to the miniaturization of the area of each pixel, color mixing between the pixels 541A, 541B, 541C, and 541D can be suppressed. Therefore, the signal-to-noise ratio of the pixel signal can be improved, so that the imaging device 1 outputs more favorable pixel data (image information).

[0506] In addition, in the imaging device 1, the pixel circuits 210 are provided for each pixel common unit 539. Therefore, compared with the case where the pixel circuits 210 are provided for each of the pixels 541A, 541B, 541C, and 541D, the formation regions of the transistors (amplification transistor AMP, reset transistor RST, selection transistor SEL, and FD conversion gain switching transistor FDG) included in the pixel circuits 210 can be increased. For example, by increasing the formation region of the amplification transistor AMP, noise can be suppressed. Therefore, the signal-to-noise ratio of the pixel signal can be improved, so that the imaging device 1 outputs more favorable pixel data (image information).

[0507] In addition, in the imaging device 1, the first substrate 100 includes a pad portion 120 that electrically connects the floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of four pixels (pixels 541A, 541B, 541C, and 541D). Therefore, compared with the case where such a pad portion 120 is provided in the second substrate 200, the number of through electrodes (through electrode 120E) that connect the first substrate 100 and the second substrate 200 to each other can be reduced. As a result, the size of the insulating region 212 can be reduced, and a sufficiently large formation region (semiconductor layer 200S) of the transistors included in the pixel circuits 210 can be ensured. Thereby, the noise of the transistors included in the pixel circuits 210 can be reduced, so that the signal-to-noise ratio of the pixel signal can be improved, and thus the imaging device 1 outputs more favorable pixel data (image information).

[0508] Next, a modification of the imaging device 1 according to the above-described embodiment will be described. In the following modifications, components common to the above-described embodiment are denoted by the same reference numerals.

[0509] <4.2. Modification 1>

[0510] Figures 62 to 66 A modification of the planar structure of the imaging device 1 according to the above-described embodiment is shown. Figure 62 Schematically shows the planar structure near the front surface of the semiconductor layer 200S of the second substrate 200, and corresponds to that described in the above-described embodiment Figure 55 . Figure 63 Schematically shows the structure of each of the components of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100, and corresponds to that described in the above-described embodiment Figure 56 . Figure 64 An example of the planar structure of the first wiring layer W1 and the second wiring layer W2 is shown, and corresponds to that described in the above-described embodiment Figure 57 . Figure 65An example of the planar structure of the second wiring layer W2 and the third wiring layer W3 is shown, and it corresponds to that described in the above embodiment Figure 58 . Figure 66 An example of the planar structure of the third wiring layer W3 and the fourth wiring layer W4 is shown, and it corresponds to that described in the above embodiment Figure 59 .

[0511] In this modified example, as Figure 63 shown, in two pixel sharing units 539 arranged along the H direction of the second substrate 200, the internal layout of one pixel sharing unit 539 (for example, on the right side of the paper surface) has a structure obtained by inverting only the internal layout of the other pixel sharing unit 539 (for example, on the left side of the paper surface) in the H direction. In addition, the offset in the V direction between the outer contour lines of one pixel sharing unit 539 and the outer contour lines of the other pixel sharing unit 539 is greater than the offset described in the above embodiment ( Figure 56 ). In this way, by increasing the offset in the V direction, the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad portion 120 connected to the amplification transistor AMP ( Figure 7 the pad portion 120 of the other (on the lower side of the paper surface) among the two pixel sharing units 539 arranged along the V direction shown) can be reduced. This layout makes Figures 62 to 66 the modified example 1 of the imaging device 1 shown unable to reverse the planar layouts of the two pixel sharing units 539 arranged along the H direction in the V direction, but makes their areas the same as the area of the pixel sharing unit 539 of the second substrate 200 described in the above embodiment. It should be noted that the planar layout of the pixel sharing unit 539 of the first substrate 100 is the same as the planar layout described in the above embodiment ( Figure 54A and Figure 54B ). Therefore, the imaging device 1 according to this modified example can achieve an effect similar to that of the imaging device 1 described in the above embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangements described in the above embodiment and this modified example.

[0512] <4.3. Modified Example 2>

[0513] Figures 67 to 72 An example of the planar structure modification of the imaging device 1 according to the above embodiment is shown. Figure 67 The planar structure of the first substrate 100 is schematically shown, and it corresponds to that described in the above embodiment Figure 54A . Figure 68 The planar structure near the front surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, and it corresponds to that described in the above embodiment Figure 55 . Figure 69Schematically shows the structure of each of the components of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100, and corresponds to those described in the above embodiments Figure 56 . Figure 70 Shows an example of the planar structure of the first wiring layer W1 and the second wiring layer W2, and corresponds to those described in the above embodiments Figure 57 . Figure 71 Shows an example of the planar structure of the second wiring layer W2 and the third wiring layer W3, and corresponds to those described in the above embodiments Figure 58 . Figure 72 Shows an example of the planar structure of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to those described in the above embodiments Figure 59 .

[0514] In this modified example, the outer shape of each pixel circuit 210 has a substantially square planar shape ( Figure 68 etc.). The planar structure of the imaging device 1 according to this modified example is different from the planar structure of the imaging device 1 described in the above embodiments in this regard.

[0515] For example, the pixel common unit 539 of the first substrate 100 is formed on a 2-row × 2-column pixel region in a manner similar to that described in the above embodiments, and has a substantially square planar shape ( Figure 67 ). For example, in each pixel common unit 539, the horizontal portions TGb of the transfer gates TG1 and TG3 of the pixels 541A and 541C in one pixel column extend in a direction from the position where they overlap the vertical portion TGa toward the central portion of the pixel common unit 539 in the H direction (more specifically, in a direction toward the outer edges of the pixels 541A and 541C and in a direction toward the central portion of the pixel common unit 539), and the horizontal portions TGb of the transfer gates TG2 and TG4 of the pixels 541B and 541D in the other pixel column extend in a direction from the position where they overlap the vertical portion TGa toward the outside of the pixel common unit 539 in the H direction (more specifically, in a direction toward the outer edges of the pixels 541B and 541D and in a direction toward the outside of the pixel common unit 539). The pad portion 120 connected to the floating diffusion portion FD is provided in the central portion of the pixel common unit 539 (the central portion of the pixel common unit 539 in the H direction and the V direction), and the pad portion 121 connected to the VSS contact region 118 is provided at least in the H direction (in Figure 67 the H direction and the V direction in) at the end of the pixel common unit 539.

[0516] As another arrangement example, it can also be conceived that the horizontal portions TGb of the transfer gates TG1, TG2, TG3, and TG4 are only provided in the region opposite to the vertical portion TGa. At this time, in a manner similar to the case described in the above embodiment, the semiconductor layer 200S is easily finely divided. Therefore, it is difficult to increase the size of the transistors in the pixel circuit 210. In contrast, when the horizontal portions TGb of the transfer gates TG1, TG2, TG3, and TG4 extend along the H direction from the position overlapping the vertical portion TGa, as in the above modification example, the width of the semiconductor layer 200S can be increased. Specifically, the positions of the through electrodes TGV1 and TGV3 connected to the transfer gates TG1 and TG3 in the H direction can be set to be close to the positions of the through electrode 120E in the H direction, and the positions of the through electrodes TGV2 and TGV4 connected to the transfer gates TG2 and TG4 in the H direction can be set to be close to the positions of the through electrode 121E in the H direction( Figure 69 ). Thus, in a manner similar to the case described in the above embodiment, the width (size in the H direction) of the semiconductor layer 200S extending in the V direction can be increased. Therefore, the size of the transistors in the pixel circuit 210 can be increased, particularly the size of the amplifying transistor AMP. Therefore, the signal-to-noise ratio of the pixel signal can be improved, enabling the imaging device 1 to output more favorable pixel data (image information).

[0517] The pixel sharing unit 539 of the second substrate 200 has, for example, substantially the same size as the pixel sharing unit 539 of the first substrate 100 in the H direction and the V direction, and is provided in a region substantially corresponding to a 2-row × 2-column pixel region. For example, in each pixel circuit 210, the selection transistor SEL and the amplifying transistor AMP are arranged side by side along the V direction in a semiconductor layer 200S extending along the V direction, and the FD conversion gain switching transistor FDG and the reset transistor RST are arranged side by side along the V direction in a semiconductor layer 200S extending along the V direction. One semiconductor layer 200S provided with the selection transistor SEL and the amplifying transistor AMP and one semiconductor layer 200S provided with the FD conversion gain switching transistor FDG and the reset transistor RST are arranged in the H direction with an insulating region 212 therebetween. The insulating region 212 extends in the V direction( Figure 68 ).

[0518] Here, with reference to Figure 68 and Figure 69 , the outer shape of the pixel sharing unit 539 of the second substrate 200 will be described. For example, Figure 67 the pixel sharing unit 539 of the first substrate 100 shown is connected to one side in the H direction of the pad portion 120 (in Figure 69The amplifying transistor AMP and the selection transistor SEL on the left side of the paper surface) and the FD conversion gain switching transistor FDG and the reset transistor RST on the other side in the H direction of the pad portion 120 (on Figure 69 the right side of the paper surface). The outer shape of the pixel common unit 539 of the second substrate 200 including the amplifying transistor AMP, the selection transistor SEL, the FD conversion gain switching transistor FDG, and the reset transistor RST is determined by the following four outer edges.

[0519] The first outer edge is one end in the V direction of the semiconductor layer 200S including the selection transistor SEL and the amplifying transistor AMP ( Figure 69 the end on the upper side of the paper surface). The first outer edge is provided between the amplifying transistor AMP included in the pixel common unit 539 and the selection transistor SEL included in the pixel common unit 539 adjacent to the pixel common unit 539 on one side in the V direction ( Figure 69 the upper side of the paper surface). More specifically, the first outer edge is provided in the central portion in the V direction of the element isolation region 213 between the amplifying transistor AMP and the selection transistor SEL. The second outer edge is the other end in the V direction of the semiconductor layer 200S including the selection transistor SEL and the amplifying transistor AMP ( Figure 69 the end on the lower side of the paper surface). The second outer edge is provided between the selection transistor SEL included in the pixel common unit 539 and the amplifying transistor AMP included in the pixel common unit 539 adjacent to the pixel common unit 539 on the other side in the V direction ( Figure 69 the lower side of the paper surface). More specifically, the second outer edge is provided in the central portion in the V direction of the element isolation region 213 between the selection transistor SEL and the amplifying transistor AMP. The third outer edge is the other end in the V direction of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG ( Figure 69 the end on the lower side of the paper surface). The third outer edge is provided between the FD conversion gain switching transistor FDG included in the pixel common unit 539 and the reset transistor RST included in the pixel common unit 539 adjacent to the pixel common unit 539 on the other side in the V direction ( Figure 69 the lower side of the paper surface). More specifically, the third outer edge is provided in the central portion in the V direction of the element isolation region 213 between the FD conversion gain switching transistor FDG and the reset transistor RST. The fourth outer edge is one end in the V direction of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG ( Figure 69the outer edge of the end portion on the upper side of the paper surface). The fourth outer edge is provided between the reset transistor RST included in the pixel sharing unit 539 and the FD conversion gain switching transistor FDG (not shown) included in the pixel sharing unit 539 adjacent to one side of the pixel sharing unit 539 in the V direction ( Figure 69 the upper side of the paper surface). More specifically, the fourth outer edge is provided in the central portion in the V direction of the element isolation region 213 (not shown) between the reset transistor RST and the FD conversion gain switching transistor FDG.

[0520] In the outer shape of the pixel sharing unit 539 of the second substrate 200 including such first, second, third, and fourth outer edges, the third and fourth outer edges are arranged to be offset from the first and second outer edges toward one side in the V direction (in other words, offset toward one side in the V direction). By using such a layout, the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG can be arranged as close as possible to the pad portion 120. As a result, it is possible to more easily reduce the area of the wiring connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG, and it is possible to more easily miniaturize the imaging device 1. Note that the VSS contact region 218 is provided between the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. For example, the plurality of pixel circuits 210 have the same arrangement as each other.

[0521] The imaging device 1 including such a second substrate 200 also achieves an effect similar to the effect described in the above embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangements described in the above embodiment and this modification.

[0522] <4.4. Modification 3>

[0523] Figures 73 to 78 A modification of the planar structure of the imaging device 1 according to the above embodiment is shown. Figure 73 The planar structure of the first substrate 100 is schematically shown and corresponds to that described in the above embodiment Figure 54B . Figure 74 The planar structure near the front surface of the semiconductor layer 200S of the second substrate 200 is schematically shown and corresponds to that described in the above embodiment Figure 55 . Figure 75 The structure of each of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the components of the first substrate 100 is schematically shown and corresponds to that described in the above embodiment Figure 56 .Figure 76 shows an example of the planar structure of the first wiring layer W1 and the second wiring layer W2, and corresponds to that described in the above embodiment Figure 57 . Figure 77 shows an example of the planar structure of the second wiring layer W2 and the third wiring layer W3, and corresponds to that described in the above embodiment Figure 58 . Figure 78 shows an example of the planar structure of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to that described in the above embodiment Figure 59 .

[0524] In this modification, the semiconductor layer 200S of the second substrate 200 extends in the H direction ( Figure 75 ). That is, this modification basically corresponds to the structure obtained by rotating the planar structure of the imaging device 1 shown in the above Figure 68 etc. by 90 degrees

[0525] For example, the pixel sharing unit 539 of the first substrate 100 is formed on a 2-row × 2-column pixel region in a manner similar to that described in the above embodiment, and has a substantially square planar shape ( Figure 73 ). For example, in each pixel sharing unit 539, the transfer gates TG1 and TG2 of the pixels 541A and 541B in one pixel row extend in the V direction toward the central portion of the pixel sharing unit 539, and the transfer gates TG3 and TG4 of the pixels 541C and 541D in the other pixel row extend in the V direction toward the outside of the pixel sharing unit 539. The pad portion 120 connected to the floating diffusion portion FD is provided in the central portion of the pixel sharing unit 539, and the pad portion 121 connected to the VSS contact region 118 is provided at least in the V direction (in the Figure 73 V direction and H direction in) at the end of the pixel sharing unit 539. At this time, the positions of the through electrodes TGV1 and TGV2 of the transfer gates TG1 and TG2 in the V direction are close to the position of the through electrode 120E in the V direction, and the positions of the through electrodes TGV3 and TGV4 of the transfer gates TG3 and TG4 in the V direction are close to the position of the through electrode 121E in the V direction ( Figure 75 ). Therefore, for reasons similar to those described in the above embodiment, the width (the dimension in the V direction) of the semiconductor layer 200S extending in the H direction can be increased. As a result, the size of the amplification transistor AMP can be increased, and noise can be suppressed

[0526] In each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged side by side along the H direction, and the reset transistor RST is arranged at a position adjacent to the selection transistor SEL in the V direction with an insulating region 212 therebetweenFigure 74 )。The FD conversion gain switching transistor FDG is arranged side by side with the reset transistor RST in the H direction. The VSS contact region 218 is arranged in an island shape in the insulating region 212. For example, the third wiring layer W3 extends in the H direction ( Figure 77 ), and the fourth wiring layer W4 extends in the V direction ( Figure 78 ).

[0527] The imaging device 1 having such a second substrate 200 also achieves an effect similar to the effect described in the above embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangements described in the above embodiment and this modification example. For example, the semiconductor layer 200S described in the above embodiment and modification example 1 may extend in the H direction.

[0528] <4.5. Modification Example 4>

[0529] Figure 79 A modification of the cross-sectional structure of the imaging device 1 according to the above embodiment is schematically shown. Figure 79 Corresponding to that described in the above embodiment Figure 50 . In this modification example, in addition to the contact portions 201, 202, 301, and 302, the imaging device 1 further includes contact portions 203, 204, 303, and 304. The imaging device 1 according to this modification example is different from the imaging device 1 described in the above embodiment in this regard.

[0530] The contact portions 203 and 204 are provided in the second substrate 200 and are exposed on the bonding surface with the third substrate 300. The contact portions 303 and 304 are provided in the third substrate 300 and are exposed on the bonding surface with the second substrate 200. The contact portion 203 is in contact with the contact portion 303, and the contact portion 204 is in contact with the contact portion 304. That is, in the imaging device 1, the second substrate 200 and the third substrate 300 are connected to each other not only through the contact portions 201, 202, 301, and 302 but also through the contact portions 203, 204, 303, and 304.

[0531] Next, Figure 80 and Figure 81 are used to describe the operation of the imaging device 1. Figure 80 Shows the paths of the input signal, power supply potential, and reference potential input to the imaging device 1 from the outside represented by arrows. Figure 81The signal path of the pixel signal output from the imaging device 1 to the outside, which is indicated by an arrow, is shown. For example, an input signal input to the imaging device 1 via the input unit 510A is transmitted to the row driver unit 520 of the third substrate 300, and a row driving signal is generated in the row driver unit 520. The row driving signal is transmitted to the second substrate 200 via the contact portions 303 and 203. Further, the row driving signal reaches each pixel common unit 539 of the pixel array unit 540 via the row driving signal line 542 in the wiring layer 200T. Among the row driving signals reaching the pixel common unit 539 of the second substrate 200, the driving signals other than the transfer gate TG are input to the pixel circuit 210 to drive each transistor included in the pixel circuit 210. The driving signal of the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV to drive the pixels 541A, 541B, 541C, and 541D. In addition, the power supply potential and the reference potential supplied to the input unit 510A (input terminal 511) of the third substrate 300 from the outside of the imaging device 1 are transmitted to the second substrate 200 via the contact portions 303 and 203, and are supplied to the pixel circuit 210 of each pixel common unit 539 via the wiring in the wiring layer 200T. The reference potential is further supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. At the same time, the pixel signals photoelectrically converted in the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to the pixel circuit 210 of the second substrate 200 for each pixel common unit 539. The pixel signal based on the pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact portions 204 and 304. The pixel signal is processed in the column signal processor 550 and the image signal processor 560 of the third substrate 300, and then output to the outside via the output unit 510B.

[0532] The imaging device 1 including such contact portions 203, 204, 303, and 304 also achieves an effect similar to the effect described in the above embodiment. The position, number, etc. of the contact portions can be changed according to the design of the circuit, etc. of the third substrate 300 which is the connection object of the wiring via the contact portions 303 and 304.

[0533] <4.6. Modified Example 5>

[0534] Figure 82 A modified example of the cross-sectional structure of the imaging device 1 according to the above embodiment is shown. Figure 82 Corresponding to that described in the above embodiment Figure 53。In this modification example, a transfer transistor TR having a planar structure is provided in the first substrate 100. The imaging device 1 according to this modification example is different from the imaging device 1 described in the above embodiment in this regard.

[0535] In the transfer transistor TR, the transfer gate TG includes only a horizontal portion TGb. In other words, the transfer gate TG does not include a vertical portion TGa and is disposed opposite to the semiconductor layer 100S.

[0536] The imaging device 1 including the transfer transistor TR having such a planar structure also achieves an effect similar to the effect described in the above embodiment. In addition, it can be conceived that by providing a planar transfer gate TG in the first substrate 100, compared with the case where a vertical transfer gate TG is provided in the first substrate 100, the photodiode PD can be formed closer to the front surface of the semiconductor layer 100S, thereby increasing the saturation signal amount (Qs). Further, it can be conceived that compared with the method of forming a vertical transfer gate TG in the first substrate 100, the method of forming a planar transfer gate TG in the first substrate 100 involves a smaller number of manufacturing processes, thereby preventing the photodiode PD from being adversely affected by the manufacturing processes.

[0537] <4.7. Modification Example 6>

[0538] Figure 83 A modification example of the pixel circuit of the imaging device according to the above embodiment is shown. Figure 83 Corresponding to that described in the above embodiment Figure 51 。In this modification example, a pixel circuit 210 is provided for each pixel (pixel 541A). That is, the pixel circuit 210 is not shared by a plural...

Claims

1. An imaging device, which comprises: a first substrate including a plurality of sensor pixels that perform photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal based on charges output from the sensor pixels; and a third substrate including a processing circuit that performs signal processing on the pixel signal, wherein the first substrate, the second substrate, and the third substrate are stacked in sequence, a semiconductor layer including the pixel circuit is divided by an insulating layer, and in at least one direction in a plane perpendicular to the optical axis direction of the sensor pixels, in each of the plurality of sensor pixels, the insulating layer divides the semiconductor layer in such a manner that a central position of the semiconductor layer divided by the insulating layer or a central position of a region where the insulating layer divides the semiconductor layer coincides with a position of an optical center of the sensor pixel.

2. The imaging device according to claim 1, wherein the plurality of sensor pixels are arranged in a matrix in a plane direction of the first substrate.

3. The imaging device according to claim 2, wherein the insulating layer divides the semiconductor layer in at least one or more directions among a row direction and a column direction in which the sensor pixels are arranged.

4. The imaging device according to claim 3, wherein in at least one or more directions among the row direction and the column direction, a central position of the semiconductor layer divided by the insulating layer or a central position of a region where the insulating layer divides the semiconductor layer coincides with a position of the optical center of the sensor pixel.

5. The imaging device according to claim 2, wherein the insulating layer divides the semiconductor layer so as to span an entire surface of a pixel region where the sensor pixels are provided.

6. The imaging device according to claim 1, wherein the plurality of sensor pixels perform photoelectric conversion on light in mutually different wavelength bands, and the insulating layer divides the semiconductor layer in such a manner that a position of the optical center of the sensor pixel that performs photoelectric conversion on light having the longest wavelength corresponds to a central position of the semiconductor layer divided by the insulating layer or a central position of a region where the insulating layer divides the semiconductor layer.

7. The imaging device according to claim 1, wherein the first substrate is formed by stacking a first insulating layer on a first semiconductor substrate, the first substrate is attached to the semiconductor layer with the first insulating layer interposed therebetween, and an antireflection film is further provided on a surface of the semiconductor layer on the first substrate side, and a refractive index value of the antireflection film is between a refractive index of the semiconductor layer and a refractive index of the first insulating layer.

8. The imaging device according to claim 1, wherein the sensor pixel includes a photoelectric conversion element that performs photoelectric conversion on light that has passed through an optical receiving lens and a color filter, and a position of the optical center of the sensor pixel includes a central position of a region where one or more photoelectric conversion elements of the sensor pixels serving as units for acquiring optical information are provided.

9. The imaging device according to claim 8, wherein, in a case where the unit for acquiring the optical information includes a plurality of the sensor pixels, the position of the optical center of the sensor pixels includes a center position of a region formed by connecting regions where respective photoelectric conversion elements are provided in the plurality of sensor pixels.

10. The imaging device according to claim 9, wherein, the plurality of sensor pixels are provided with one or both of the color filter and the light receiving lens in a continuous manner.

11. The imaging device according to any one of claims 1 to 10, wherein the sensor pixel comprises: a photoelectric conversion element; a transfer transistor electrically connected to the photoelectric conversion element; and a floating diffusion portion that temporarily holds the charge output from the photoelectric conversion element via the transfer transistor, and the pixel circuit includes: a reset transistor that resets the potential of the floating diffusion portion to a predetermined potential; an amplification transistor that generates a signal of a voltage corresponding to the level of the charge held in the floating diffusion portion as the pixel signal; and a selection transistor that controls the output timing of the pixel signal from the amplification transistor.

12. The imaging device according to claim 11, wherein, the reset transistor, the amplification transistor, and the selection transistor are respectively provided in the semiconductor layer.

13. The imaging device according to claim 11, wherein, a through-wiring for electrically connecting the floating diffusion portion of the first substrate and the pixel circuit of the second substrate to each other is provided to penetrate the insulating layer.

14. The imaging device according to claim 11, wherein the first substrate includes the photoelectric conversion element, the transfer transistor, and the floating diffusion portion for each sensor pixel, and the second substrate includes the pixel circuit for each sensor pixel.

15. The imaging device according to claim 11, wherein the first substrate includes the photoelectric conversion element, the transfer transistor, and the floating diffusion portion for each sensor pixel, and the second substrate includes the pixel circuit for every plurality of sensor pixels.

16. The imaging device according to claim 11, wherein the first substrate includes the photoelectric conversion element and the transfer transistor for each sensor pixel, and includes a floating diffusion portion shared by every plurality of sensor pixels, and the second substrate includes the pixel circuit for every plurality of sensor pixels that share the floating diffusion portion.

Images