Display device

Abstract

A display device is disclosed, comprising: a substrate including a display area and a non-display area; a first thin film transistor located in the non-display area; and a second thin film transistor and a third thin film transistor located in the display area. The second thin film transistor comprises: a second semiconductor pattern and a third semiconductor pattern including a first oxide semiconductor; a second gate electrode overlapping the second semiconductor pattern; a third gate electrode overlapping the third semiconductor pattern; and a second source electrode and a second drain electrode connected to the second semiconductor pattern and the third semiconductor pattern. The third thin film transistor comprises: a fourth semiconductor pattern including a first oxide semiconductor; a fourth gate electrode overlapping the fourth semiconductor pattern; and a third source electrode and a third drain electrode connected to the fourth semiconductor pattern.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2020-0080576, filed on Jun. 30, 2020, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0002] The present invention relates to a display device including thin film transistors of different types. Background Art

[0003] In recent years, with the advent of the information age, various types of display devices for displaying images have been developed. Among these display devices, there is a display device in which a self-luminous light-emitting element is formed on a display panel, thereby eliminating the need to provide a backlight unit outside the display panel.

[0004] In addition, a display device having a light emitting element formed on a display panel includes an array substrate in which a plurality of pixels are defined in a display area displaying an image, wherein at least one thin film transistor is mounted in each sub-pixel of each of the plurality of pixels.

[0005] For example, the array substrate includes a driving thin film transistor in each sub-pixel that provides a driving current to the light emitting element and a switching thin film transistor that provides a gate signal to the driving thin film transistor.

[0006] Among them, it is necessary to design the array substrate of the display device so that the driving thin film transistor can advantageously realize grayscale expression and the switching thin film transistor has a good on / off ratio. The reason is that as the ratio of current change to voltage change becomes smaller, the ability of the driving thin film transistor to express grayscale increases, and the switching thin film transistor needs to be turned on and off quickly.

[0007] However, since the driving thin film transistor and the switching thin film transistor disposed on the array substrate include the same semiconductor material and thus have the same characteristics, it is difficult to design the driving thin film transistor and the switching thin film transistor to have different characteristics from each other in consideration of the characteristics of the thin film transistors.

[0008] Furthermore, when a plurality of transistors having different semiconductors are designed, a manufacturing process thereof may become complicated and a manufacturing cost thereof may increase. Summary of the invention

[0009] An object of the present invention is to provide a display device in which thin film transistors having respective different characteristics are arranged together on an array substrate, thereby improving the performance of the display device.

[0010] Another object of the present invention is to provide a display device in which an oxide semiconductor is applied to an active layer, whereby a thin film transistor including a single active layer and a top gate and a thin film transistor including a double active layer and a double gate can be used for a switching transistor or a driving transistor.

[0011] Another object of the present invention is to provide a display device, which includes thin film transistors having different operating characteristics by configuring the thin film transistors so as to have different current values ​​in the saturation region when measuring a drive current curve (output curve or Ids-Vd curve) or an IV curve (transfer curve or Ids-Vgs curve), wherein Ids represents the source-drain current (i.e., drive current) of the thin film transistor, Vd represents the drain voltage of the thin film transistor, and Vgs represents the gate-source voltage of the thin film transistor.

[0012] Still another object of the present invention is to provide a display device including a plurality of thin film transistors which exhibit different values ​​of the ratio of current change to voltage change (S factor) and thus have respective different operating characteristics.

[0013] The above objects and other objects can be achieved by providing a display device according to an embodiment of the present invention.

[0014] A display device according to an embodiment of the present invention may include: a substrate including a display area (also referred to as an "active area" herein) and a non-display area (also referred to as an "inactive area" herein); a first thin film transistor located in the non-display area; and a second thin film transistor and a third thin film transistor located in the display area.

[0015] The first thin film transistor may include: a first semiconductor pattern including first polysilicon; a first gate electrode overlapping the first semiconductor pattern; and a first source electrode and a first drain electrode connected to the first semiconductor pattern.

[0016] The second thin film transistor may include: a second semiconductor pattern and a third semiconductor pattern including a first oxide semiconductor; a second gate electrode overlapping the second semiconductor pattern; a third gate electrode overlapping the third semiconductor pattern; and a second source electrode and a second drain electrode connected to the second semiconductor pattern and the third semiconductor pattern through contact holes.

[0017] The third thin film transistor may include: a fourth semiconductor pattern including a first oxide semiconductor; a fourth gate electrode overlapping the fourth semiconductor pattern; and a third source electrode and a third drain electrode connected to the fourth semiconductor pattern.

[0018] A display device according to another embodiment of the present invention may include: a substrate including a display area and a non-display area; a driving circuit unit located in the non-display area; and a pixel unit located in the display area. The pixel unit may include a switching transistor and a driving transistor, and the switching transistor and the driving transistor are configured to have respective different structures.

[0019] The driving transistor may include: a first active layer including a source / drain region and a channel region; a second active layer located above the first active layer; a source / drain electrode located above the second active layer and connected to the source / drain region of the first active layer and the source / drain region of the second active layer; a lower gate electrode located below the first active layer; and an upper gate electrode located above the second active layer. The source / drain region of the first active layer may be connected to the source / drain electrode through a first contact hole, the source / drain region of the second active layer may be connected to the source / drain electrode through a second contact hole, and the first contact hole may be located at a position farther away from the upper gate electrode than the second contact hole in the channel direction.

[0020] A display device according to another embodiment of the present invention may include: a substrate including a display area and a non-display area; a driving circuit unit located in the non-display area; and a pixel unit located in the display area. The pixel unit includes a switching transistor and a driving transistor. The driving transistor includes: a second semiconductor pattern and a third semiconductor pattern including a first oxide semiconductor; a second gate electrode overlapping the second semiconductor pattern; a third gate electrode overlapping the third semiconductor pattern; and a second source electrode and a second drain electrode connected to the second semiconductor pattern and the third semiconductor pattern through a contact hole. The switching transistor includes: a fourth semiconductor pattern including a second oxide semiconductor; a fourth gate electrode overlapping the fourth semiconductor pattern; and a third source electrode and a third drain electrode connected to the fourth semiconductor pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings illustrate embodiments of the present invention and together with the description are used to explain the principles of the present invention. The accompanying drawings are included to provide a further understanding of the present invention and are incorporated into and constitute a part of this application. In the drawings:

[0022] Figure 1 is a schematic diagram of a display device according to an embodiment of the present invention;

[0023] Figure 2A and Figure 2B It is shown Figure 1 A plan view of sub-pixels arranged in the display area AA shown;

[0024] Figure 3is a circuit diagram showing a pixel driving circuit in a display device according to an embodiment of the present invention;

[0025] Figure 4 yes Figure 3 Detailed circuit diagram of the pixel emission driving element T2;

[0026] Figure 5 is a cross-sectional view of a display device according to an embodiment of the present invention;

[0027] Figure 6 is a cross-sectional view of a display device according to another embodiment of the present invention;

[0028] Figure 7 is a cross-sectional view of a display device according to another embodiment of the present invention;

[0029] Figure 8 yes Figure 5 A detailed cross-sectional view of a second thin film transistor;

[0030] Fig. 9 yes Figure 5 A detailed plan view of a second thin film transistor;

[0031] Fig.10 is a circuit diagram of a pixel emission driving element undergoing simulation according to the present invention;

[0032] Fig.11A It is shown that by Fig.10 A graph of an IV curve obtained by simulation performed under condition I;

[0033] Fig. 11B It is shown that by Fig.10 a graph of an IV curve obtained by simulation performed under condition II of FIG.

[0034] Fig. 11C It is shown that by Fig.10 FIG. 5 is a graph of an IV curve obtained by simulation performed under condition III. DETAILED DESCRIPTION

[0035] The advantages and features of the present invention and the methods for achieving them will become clear through the embodiments described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The present invention is limited only by the scope of the claims.

[0036] In the accompanying drawings for illustrating exemplary embodiments of the present invention, for example, the shapes, sizes, ratios, angles and numbers shown are given as examples and, therefore, do not limit the disclosure of the present invention. Throughout the specification, the same reference numerals refer to the same constituent elements. In addition, in the following description of the present invention, when the detailed description of the known functions and configurations contained herein may make the subject matter of the present invention quite unclear, the detailed description will be omitted.

[0037] Unless used with the term “only”, the terms “comprising”, “including”, “consisting of” and / or “having” used in this specification do not exclude the existence or addition of other elements. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0038] In interpreting constituent elements included in various embodiments of the present invention, even if there is no explicit description thereof, the constituent elements are interpreted to include an error range.

[0039] In the description of various embodiments of the present invention, when describing the positional relationship, for example, when using "on", "above", "below", "next to", etc. to describe the positional relationship between two parts, unless the term "directly" or "closely" is used, one or more other parts may be located between the two parts.

[0040] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. It will be understood that the spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, the elements described as "below" or "below" other elements will be oriented "above" the other elements. Thus, the exemplary terms "below" or "below" may include both the orientation of above and below. Similarly, the exemplary terms "above" or "on" may include both the orientation of above and below.

[0041] In the description of various embodiments of the present invention, when describing a time relationship, for example, when using "after", "subsequently", "next", "before", etc. to describe the time relationship between two actions, unless it is used with the term "directly" or "immediately", the actions may not occur continuously.

[0042] It is understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one element from another element. Therefore, in this specification, unless otherwise mentioned, the element represented by "first" may be the same as the element represented by "second" without exceeding the technical scope of the present invention.

[0043] The term "at least one" should be understood to include all possible combinations that can be proposed from one or more related items. For example, the meaning of "at least one of the first, second, or third item" can be each of the first, second, or third item, and can also be all possible combinations that can be proposed from two or more of the first, second, and third items.

[0044] The various features of the various embodiments of the present invention may be coupled and combined with each other in part or in whole, and various technical connections and operation modes thereof are possible. These various embodiments may be performed independently of each other, or may be performed in association with each other.

[0045] It should be noted that when reference numerals are assigned to elements of the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings.

[0046] In the embodiments of the present invention, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode can be interchanged. The source electrode can be a drain electrode, and the drain electrode can be a source electrode. In addition, the source electrode in any embodiment can be a drain electrode in another embodiment, and the drain electrode in any embodiment can be a source electrode in another embodiment.

[0047] In one or more embodiments of the present invention, for ease of description, the source region is separated from the source electrode region, and the drain region is separated from the drain electrode region. However, the embodiments of the present invention are not limited thereto. For example, the source region may be a source electrode, and the drain region may be a drain electrode. In addition, the source region may be a drain electrode, and the drain region may be a source electrode.

[0048] As will be fully understood by those skilled in the art, the various features of the various embodiments of the present invention may be partially or completely coupled and combined with each other, and may be interlocked and operated in various technical ways, and the various embodiments may be performed independently of each other or in association with each other.

[0049] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0050] Figure 1is a plan view showing a display device 100 according to the present invention.

[0051] The display panel 102 has a display area AA disposed on a substrate 101 and a non-display area NA disposed adjacent to the display area AA. The substrate 101 is formed of a flexible plastic material so as to be bendable. The substrate 101 is formed of polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyether sulfone (PES), polyacrylate (PAR), polysulfone (PSF) or cyclic olefin copolymer (COC).

[0052] The sub-pixels in the display area AA include thin film transistors including an oxide semiconductor layer.

[0053] At least one of the data driving unit 104 or the gate driving unit 103 may be disposed in the non-display area NA, and the substrate 101 may further include a bending area BA that is bent in the non-display area NA. The gate driving unit 103 may be directly formed on the substrate 101 using a thin film transistor having a polycrystalline semiconductor layer.

[0054] A thin film transistor having an oxide semiconductor layer and a thin film transistor having a polycrystalline semiconductor layer have high electron mobility and thus can exhibit high resolution and can be driven with low power.

[0055] A plurality of data lines and a plurality of gate lines may be arranged in the display area AA. For example, a plurality of data lines may be arranged in rows or columns, and a plurality of gate lines may be arranged in columns or rows. In addition, a pixel PX may be arranged in an area defined by the data lines and the gate lines. Each pixel PX may include one or more sub-pixels SPX ( Figure 1 not shown).

[0056] The gate driving unit 103 including the gate driving circuit may be disposed in the non-display area NA. The gate driving circuit of the gate driving unit 103 sequentially provides a scanning signal to the plurality of gate lines GL, thereby sequentially driving the pixel rows. Here, the gate driving circuit may also be referred to as a scanning driving circuit. In addition, a pixel row refers to a pixel connected to one gate line.

[0057] The gate driving circuit may be composed of a thin film transistor having a polycrystalline semiconductor layer, may be composed of a thin film transistor having an oxide semiconductor layer, or may be composed of both a thin film transistor having a polycrystalline semiconductor layer and a thin film transistor having an oxide semiconductor layer. When the semiconductor layer of the thin film transistor of the gate driving circuit and the semiconductor layer of the thin film transistor provided in the sub-pixel in the display area AA include the same material, they may be formed simultaneously by the same process.

[0058] The gate driving circuit may include a shift register and a level shifter.

[0059] In the display device according to the embodiment of the present invention, the gate driving circuit may be implemented in a gate in panel (GIP) type and may be directly disposed on the substrate 101 .

[0060] The gate driving unit 103 including a gate driving circuit sequentially supplies a scan signal having an on voltage or an off voltage to a plurality of gate lines.

[0061] The display device 100 according to the embodiment of the present invention may further include a data driving circuit. When the gate driving unit 103 including the gate driving circuit turns on a specific gate line, the data driving circuit converts image data into an analog data voltage and supplies the analog data voltage to a plurality of data lines.

[0062] The plurality of gate lines GL provided on the substrate 101 may include a plurality of scan lines and a plurality of emission control lines, which are wirings for transmitting different types of gate signals (scan signals and emission control signals) to gate nodes of different types of transistors (scan transistors and emission control transistors).

[0063] The gate driving unit 103 including the gate driving circuit may include: a scan driving circuit that outputs scan signals to a plurality of scan lines as one type of gate lines GL; and an emission driving circuit that outputs emission control signals to a plurality of emission control lines as another type of gate lines GL.

[0064] The data lines DL may be disposed to pass through the bending area BA. The various data lines DL may be disposed to be connected to a data pad PAD (not shown).

[0065] The bending area BA may be an area in which the substrate 101 is bent. The substrate 101 may be configured to remain in a flat state without bending in areas other than the bending area BA, and to bend in the bending area BA. Therefore, two non-bending areas of the substrate 101 isolated from each other may face each other with the bending area BA of the substrate 101 interposed therebetween.

[0066] Figure 2A and Figure 2B It is shown in Figure 1 A plan view of sub-pixels arranged in the display area AA is shown.

[0067] The display area AA displays an image through unit pixels arranged in a matrix form. Each unit pixel includes a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or includes a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, and a white (W) sub-pixel. For example, Figure 2A As shown, the red (R) sub-pixel, the green (G) sub-pixel, and the blue (B) sub-pixel may be arranged in a row along the same imaginary horizontal line. Figure 2B As shown, the red (R) sub-pixel, the green (G) sub-pixel, and the blue (B) sub-pixel may be spaced apart from each other to be arranged in an imaginary triangle structure. The configuration of the unit pixel is not limited to Figure 2A and Figure 2B The configuration shown is for reference only, and the unit pixel may be formed in any of a variety of other configurations.

[0068] Figure 3 1 is a circuit diagram showing a pixel driving circuit in a display device according to an embodiment of the present invention. The sub-pixel SPX includes a light emitting element EL and a pixel driving circuit, and the pixel driving circuit includes six transistors and a capacitor to supply a driving current to the light emitting element EL. Figure 3 The equivalent circuit of the sub-pixel SPX shown is not limited thereto and may be implemented in any of various other configurations.

[0069] Specifically, the pixel driving circuit includes a driving transistor T2, a first switching transistor T1, and third to sixth switching transistors T3 to T6, and a storage capacitor Cst.

[0070] The driving transistor T2 includes a gate node connected to a first node N1, a drain node connected to a second node N2, and a source node connected to a third node N3. The first node N1 is connected to one node of the storage capacitor Cst, the second node N2 is connected to the third switching transistor T3 and the fourth switching transistor T4, and the third node N3 is connected to the first switching transistor T1 and the fifth switching transistor T5. The source node of the driving transistor T2 is electrically connected to a light emitting element EL such as an organic light emitting element. The driving transistor T2 may also be referred to as a pixel emission driving element.

[0071] Specifically, the source node of the driving transistor T2 is connected to the drain node of the fifth switching transistor T5 and the third node N3. In addition, the driving transistor T2 is electrically connected to the anode of the light emitting element EL such as an organic light emitting element.

[0072] The drain node of the driving transistor T2 is connected to a high potential voltage line providing a high potential voltage VDDEL via the fourth switching transistor T4. Therefore, during the light emission period, the driving transistor T2 is turned on by receiving the high potential voltage VDDEL via the fourth switching transistor T4 and provides a driving current to the light emitting element EL.

[0073] The first switch transistor T1 includes a gate node connected to a second scan signal line providing a second scan signal Scan2, a drain node connected to a data line providing a data signal Data, and a source node connected to a third node N3. The first switch transistor T1 is turned on or off by the second scan signal Scan2. When the second scan signal Scan2 has a turn-on level, the first switch transistor T1 is turned on and provides the data voltage Data to the third node N3.

[0074] The third switching transistor T3 includes a gate node connected to the first scan signal line to which the first scan signal Scan1 is provided, a drain node connected to the second node N2, and a source node connected to the first node. When the first scan signal Scan1 has a turn-on level, the third switching transistor T3 is turned on to diode-connect the gate node and the drain node of the driving transistor T2, thereby sensing the threshold voltage of the driving transistor T2.

[0075] The fourth switch transistor T4 includes a gate node connected to the nth emission control signal line to which the nth emission control signal EM[n] is provided, a drain node connected to the high potential voltage line, and a source node connected to the second node N2. The fourth switch transistor T4 is turned on by the nth emission control signal EM[n] and provides the high potential voltage VDDEL to the drain node of the driving transistor T2.

[0076] Since the fourth switching transistor T4 provides the high potential voltage VDDEL to the drain node of the driving transistor T2, the drain-source current Ids of the driving transistor T2 flows to the light emitting element EL. Therefore, the driving transistor T2 can express grayscale by adjusting the amount of current provided to the light emitting element EL according to the data voltage Data.

[0077] The fifth switch transistor T5 includes a gate node connected to the n-1th emission control signal line to which the n-1th emission control signal EM[n-1] is provided, a drain node connected to the third node N3, and a source node connected to the fourth node N4. In order to sample the threshold voltage of the driving transistor T2 using the coupling effect of the storage capacitor Cst, the fifth switch transistor T5 is turned on and the data voltage Data of the third node N3 is provided to the fourth node N4. In addition, when the light emitting element EL emits light, the fifth switch transistor T5 is turned on and provides a driving current to the light emitting element EL.

[0078] The sixth switching transistor T6 includes a gate node connected to the first scan signal line to which the first scan signal Scan1 is supplied, a source node connected to the initialization voltage line to which the initialization voltage Vini is supplied, and a drain node connected to the fourth node N4.

[0079] The sixth switching transistor T6 is turned on by the first scan signal Scan1 and supplies the initialization voltage Vini to the fourth node N4 , thereby discharging the anode of the light emitting element EL.

[0080] The storage capacitor Cst is connected to the first node N1 and the fourth node N4 to store a voltage applied to the gate node of the driving transistor T2.

[0081] The storage capacitor Cst is electrically connected to the first node N1 and the fourth node N4 to store a difference between a voltage supplied to the gate node of the driving transistor T2 and a voltage supplied to the anode of the light emitting element EL.

[0082] Hereinafter, the structure of the driving transistor T2 will be described in detail.

[0083] Figure 4 yes Figure 3 Detailed circuit diagram of the pixel emission driving element T2.

[0084] According to an embodiment of the present invention, since the driving transistor T2 needs to improve the driving current supply performance and enable the expression of the S factor characteristic of the low gray scale, it can be achieved by Figure 4 As shown in FIG. 1 , two transistors are connected in parallel to design the driving transistor T2. Therefore, the driving performance of the sub-pixel SPX can be greatly improved. Figure 4 In , g, d and s represent the gate node, drain node and source node of the driving transistor T2, respectively, VDD represents the voltage applied to the drain node d of the driving transistor T2, and VSS represents the voltage applied to the source node s of the driving transistor T2 (which may be a ground voltage).

[0085] In the embodiments of the present invention, although reference has been made to Figure 3 Each sub-pixel SPX is described as including a light-emitting element EL such as an organic light-emitting element, first to sixth transistors T1 to T6, and a storage capacitor Cst, but the embodiment is not limited thereto. For example, in a display device according to an embodiment of the present invention, each sub-pixel SPX may include a light-emitting element, first to sixth transistors T1 to T6, a seventh transistor, and a storage capacitor Cst.

[0086] Figure 5 It is shown along Figure 1 A diagram of a cross-sectional structure taken along line II' in FIG. Figure 6 and Figure 7 FIG. 4 is a diagram showing another embodiment of the structure of the storage capacitor Cst in the pixel driving circuit in the display area AA. Figure 8 and Fig. 9, respectively, are a cross-sectional view and a plan view showing a parallel connection structure of pixel driving transistors in the display area AA. Figures 5 to 9 A display device according to an embodiment of the present invention is described in detail.

[0087] Reference Figure 5 , a polycrystalline semiconductor layer 210 (an example of a first semiconductor pattern) of a first thin film transistor 200 in a gate driving unit disposed in a non-display area NA is formed on the lower buffer layer 112. The polycrystalline semiconductor layer 210 includes a first channel region 210C, a first source region 210S, and a first drain region 210D. The first channel region 210C overlaps with the first gate electrode 211, wherein the first gate insulating film 113 is inserted between the first channel region 210C and the first gate electrode 211, and the first channel region 210C is formed between the first source electrode 212 and the first drain electrode 213. The first source region 210S is electrically connected to the first source electrode 212 through a first source contact hole 212a. The first drain region 210D is electrically connected to the first drain electrode 213 through a first drain contact hole 213a. The polycrystalline semiconductor layer 210 has a higher mobility than the amorphous semiconductor layer and the oxide semiconductor layer 310, 411 and 412, thereby showing low energy / power consumption and improved reliability. Therefore, the polycrystalline semiconductor layer 210 is suitable for application to the gate driving unit 103 for driving the scan line SL (not shown). The multi-buffer layer 111 and the lower buffer layer 112 are arranged between the polycrystalline semiconductor layer 210 and the substrate 110. The multi-buffer layer 111 prevents the diffusion of moisture and / or oxygen that has penetrated the substrate 110. The multi-buffer layer 111 is formed in a manner that silicon nitride (SiNx) and silicon oxide (SiOx) are alternately stacked at least once. The lower buffer layer 112 plays a role in protecting the polycrystalline semiconductor layer 210 and interrupting the diffusion of various types of defects from the substrate 110. The lower buffer layer 112 can be formed of amorphous silicon, silicon nitride (SiNx), silicon oxide (SiOx), etc.

[0088] The first gate electrode 211 is formed on the first gate insulating film 113. The first gate electrode 211 overlaps the first channel region 210C of the polycrystalline semiconductor layer 210, wherein the first gate insulating film 113 is interposed between the first gate electrode 211 and the first channel region 210C. The first gate electrode 211 may be a single layer or a multilayer formed of the same material as the lower storage electrode 510 and the second gate electrode 410, for example, one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the embodiment is not limited thereto.

[0089] The first interlayer insulating film 114 located on the polycrystalline semiconductor layer 210 is configured as an inorganic film having a higher hydrogen particle content than the second gate insulating film 115 and the upper buffer layer 116. For example, the first interlayer insulating film 114 is formed of silicon nitride (SiNx) by a deposition process using an ammonia (NH3) gas, and the second gate insulating film 115 and the upper buffer layer 116 are formed of silicon oxide (SiOx). The hydrogen particles contained in the first interlayer insulating film 114 diffuse into the polycrystalline semiconductor layer 210 during the hydrogenation process, thereby filling the holes in the polycrystalline semiconductor layer 210 with hydrogen. Therefore, the polycrystalline semiconductor layer 210 is stabilized, thereby preventing the characteristics of the first thin film transistor 200 from being degraded.

[0090] The first source electrode 212 is connected to the first source region 210S of the polycrystalline semiconductor layer 210 through a first source contact hole 212a penetrating the first gate insulating film 113, the first interlayer insulating film 114, the second gate insulating film 115, the upper buffer layer 116, the third gate insulating film 117, and the second interlayer insulating film 118. The first drain electrode 213 faces the first source electrode 212 and is connected to the first drain region 210D of the polycrystalline semiconductor layer 210 through a first drain contact hole 213a penetrating the first gate insulating film 113, the first interlayer insulating film 114, the second gate insulating film 115, the upper buffer layer 116, the third gate insulating film 117, and the second interlayer insulating film 118. Since the first source electrode 212 and the first drain electrode 213 are located in the same plane as the storage supply line 512 and are formed of the same material as the storage supply line 512, the first source electrode 212 and the first drain electrode 213 can be formed simultaneously through the same mask process as the storage supply line 512.

[0091] After the activation and hydrogenation processes of the polycrystalline semiconductor layer 210 of the first thin film transistor 200, the first oxide semiconductor layer 411 (an example of the second semiconductor pattern and / or the first active layer) and the second oxide semiconductor layer 412 (an example of the third semiconductor pattern and / or the second active layer) of the second thin film transistor 400 are formed. That is, the first oxide semiconductor layer 411 and the second oxide semiconductor layer 412 are located on the polycrystalline semiconductor layer 210. Therefore, the first oxide semiconductor layer 411 and the second oxide semiconductor layer 412 are not exposed to the high temperature atmosphere of the activation and hydrogenation processes of the polycrystalline semiconductor layer 210, thereby preventing damage to the first oxide semiconductor layer 411 and the second oxide semiconductor layer 412, thereby improving reliability.

[0092] The second thin film transistor 400 is disposed on the substrate 110 to be spaced apart from the first thin film transistor 200 . The second thin film transistor 400 includes a second gate electrode 410 , a first oxide semiconductor layer 411 , a second oxide semiconductor layer 412 , a third gate electrode 413 , a second source electrode 414 , and a second drain electrode 415 .

[0093] The second gate electrode 410 overlaps the first oxide semiconductor layer 411, wherein the first interlayer insulating film 114 and the second gate insulating film 115 are interposed between the second gate electrode 410 and the first oxide semiconductor layer 411. The second oxide semiconductor layer 412 is formed on the upper buffer layer 116 to overlap with the third gate electrode 413, and the first oxide semiconductor layer 411 and the second oxide semiconductor layer 412 form a channel between the second source electrode 414 and the second drain electrode 415. The first oxide semiconductor layer 411 and the second oxide semiconductor layer 412 are formed of an oxide including at least one metal selected from the group consisting of Zn, Cd, Ga, In, Sn, Hf, and Zr. The first oxide semiconductor layer 411 and the second oxide semiconductor layer 412 may be formed of the same oxide or different oxides.

[0094] The second interlayer insulating film 118, the third gate insulating film 117, the upper buffer layer 116, and the second gate insulating film 115 of the second thin film transistor 400 are configured as inorganic films having a lower hydrogen particle content than the first interlayer insulating film 114. For example, the second interlayer insulating film 118, the third gate insulating film 117, the upper buffer layer 116, and the second gate insulating film 115 are formed of silicon oxide (SiOx), and the first interlayer insulating film 114 is formed of silicon nitride (SiNx). Therefore, when the heat treatment process is performed on the first oxide semiconductor layer 411 and the second oxide semiconductor layer 412, hydrogen contained in the first interlayer insulating film 114 and hydrogen contained in the polycrystalline semiconductor layer 210 can be prevented from diffusing into the first oxide semiconductor layer 411 and the second oxide semiconductor layer 412.

[0095] Each of the second source electrode 414 and the second drain electrode 415 may be a single layer or a multilayer located on the second interlayer insulating film 118, and may be formed of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the embodiment is not limited thereto.

[0096] The second source electrode 414 is connected to the third source region 412S of the second oxide semiconductor layer 412 through a second source contact hole 414b penetrating the second interlayer insulating film 118 and the third gate insulating film 117, and the second drain electrode 415 is connected to the drain region 412D of the second oxide semiconductor layer 412 through a second drain contact hole 415b penetrating the second interlayer insulating film 118 and the third gate insulating film 117. In addition, for the connection between the first oxide semiconductor layer 411 and the second oxide semiconductor layer 412, the second source electrode 414 is connected to the second source region 411S of the first oxide semiconductor layer 411 through a second source contact hole 414a penetrating the second interlayer insulating film 118, the third gate insulating film 117, and the upper buffer layer 116, and the second drain electrode 415 is connected to the second drain region 411D of the first oxide semiconductor layer 411 through a second drain contact hole 415a penetrating the second interlayer insulating film 118, the third gate insulating film 117, and the upper buffer layer 116. In addition, the second source electrode 414 and the second drain electrode 415 are formed to face each other with the channel regions 411C and 412C of the first oxide semiconductor layer 411 and the second oxide semiconductor layer 412 interposed therebetween.

[0097] Since the second thin film transistor 400 in which the first oxide semiconductor layer 411 and the second oxide semiconductor layer 412 are connected to each other and includes a second gate electrode 410, a third gate electrode 413, a second source electrode 414 and a second drain electrode 415 has the following advantages: the amount of its driving current is greater than the amount of the driving current of the third thin film transistor 300 and the ratio of the current change to the voltage change is not large, the second thin film transistor 400 is suitable for application in the pixel driving transistor T2.

[0098] The third thin film transistor 300 is disposed on the substrate 110 to be spaced apart from the first thin film transistor 200 . The third thin film transistor 300 includes a fourth gate electrode 311 , a third oxide semiconductor layer 310 (an example of a fourth semiconductor pattern), a third source electrode 312 , and a third drain electrode 313 .

[0099] The fourth gate electrode 311 overlaps the third oxide semiconductor layer 310, wherein the third gate insulating film 117 is interposed between the fourth gate electrode 311 and the third oxide semiconductor layer 310. The third oxide semiconductor layer 310 is formed on the upper buffer layer 116 to overlap with the fourth gate electrode 311, and the third oxide semiconductor layer 310 forms a channel between the third source electrode 312 and the third drain electrode 313. The third oxide semiconductor layer 310 is formed of an oxide including at least one metal selected from the group consisting of Zn, Cd, Ga, In, Sn, Hf, and Zr. The third oxide semiconductor layer 310 may be formed of the same material as the second oxide semiconductor layer 412 and formed by the same process as the second oxide semiconductor layer 412.

[0100] Since the second interlayer insulating film 118 , the third gate insulating film 117 , the upper buffer layer 116 , and the second gate insulating film 115 of the third thin film transistor 300 have the same configuration and function as corresponding portions of the second thin film transistor, a detailed description thereof will be omitted.

[0101] Each of the third source electrode 312 and the third drain electrode 313 may be a single layer or a multilayer located on the second interlayer insulating film 118, and may be formed of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the embodiment is not limited thereto.

[0102] The third source electrode 312 is connected to the source region 310S of the third oxide semiconductor layer 310 through a third source contact hole 312b penetrating the second interlayer insulating film 118 and the third gate insulating film 117, and the third drain electrode 313 is connected to the drain region 310D of the third oxide semiconductor layer 310 through a third drain contact hole 313b penetrating the second interlayer insulating film 118 and the third gate insulating film 117. The third source electrode 312 and the third drain electrode 313 are formed to face each other with the channel region 310C of the third oxide semiconductor layer 310 interposed therebetween.

[0103] The source regions 411S, 412S and 310S of the first oxide semiconductor layer 411, the second oxide semiconductor layer 412 and the third oxide semiconductor layer 310 and the drain regions 411D, 412D and 310D of the first oxide semiconductor layer 411, the second oxide semiconductor layer 412 and the third oxide semiconductor layer 310 may be formed in the same doping process, and the dopant used in the doping process may include at least one of boron (B), phosphorus (P), fluorine (F) or hydrogen (H).

[0104] In addition, the first source contact hole 212a and the first drain contact hole 213a connecting the polycrystalline semiconductor layer 210 to the first source electrode 212 and the first drain electrode 213 and the second source contact hole 414a and the second drain contact hole 415a connecting the first oxide semiconductor layer 411 to the second source electrode 414 and the second drain electrode 415 are formed in the same process. In addition, the second source contact hole 414b and the second drain contact hole 415b connecting the second oxide semiconductor layer 412 to the second source electrode 414 and the second drain electrode 415 and the third source contact hole 312b and the third drain contact hole 313b connecting the third oxide semiconductor layer 310 to the third source electrode 312 and the third drain electrode 313 are formed in the same process.

[0105] Since the third thin film transistor 300 including the third oxide semiconductor layer 310, the fourth gate electrode 311, the third source electrode 312 and the third drain electrode 313 is characterized in that the leakage current is lower than that of the first thin film transistor 200, the third thin film transistor 300 is suitable for being applied to a pixel switch TFT with a short on-time period and a long off-time period.

[0106] The lower storage electrode 510 is connected to any one of the third gate electrode 413 and the second source electrode 414 of the second thin film transistor 400. The lower storage electrode 510 is located on the first gate insulating film 113 and is formed of the same material and in the same layer as the first gate electrode 211.

[0107] The upper storage electrode 511 is connected to the remaining one of the third gate electrode 413 and the second source electrode 414 of the second thin film transistor 400 through the storage supply line 512. The upper storage electrode 511 is located on the first interlayer insulating film 114 and the second gate insulating film 115. The upper storage electrode 511 may be formed of the same material as the first oxide semiconductor layer 411 and in the same layer as the first oxide semiconductor layer 411, and may also be made conductive in the process of making the second source region 411S and the second drain region 411D of the first oxide semiconductor layer 411 conductive. The upper storage electrode 511 is exposed through the storage contact hole 512a penetrating the upper buffer layer 116, the third gate insulating film 117 and the second interlayer insulating film 118, and is connected to the storage supply line 512.

[0108] The light emitting element 600 includes an anode 610 connected to the second source electrode 414 , at least one light emitting stack 611 formed on the anode 610 , and a cathode 612 formed on the light emitting stack 611 .

[0109] The anode 610 is connected to the pixel connection electrode 416 exposed through the second pixel contact hole 610c penetrating the second planarization layer 120. The pixel connection electrode 416 is connected to the second source electrode 414 exposed through the first pixel contact hole 416c penetrating the first planarization layer 119.

[0110] The anode 610 is formed into a multilayer structure including a transparent conductive film and an opaque conductive film having a high reflection efficiency. The transparent conductive film is formed of a material having a relatively high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive film is formed into a single layer or multilayer structure including one of Al, Ag, Cu, Pb, Mo and Ti or an alloy thereof. For example, the anode 610 may be formed into a structure in which a transparent conductive film, an opaque conductive film and a transparent conductive film are stacked in sequence, or a structure in which a transparent conductive film and an opaque conductive film are stacked in sequence. The anode 610 is disposed on the second planarization layer 120 so as to overlap not only the light emitting region provided by the bank 122, but also the circuit region in which the second thin film transistor 400 and the third thin film transistor 300 and the storage capacitor 500 are disposed, thereby increasing the size of the light emitting region.

[0111] The light-emitting stack 611 of the light-emitting element 600 is formed by stacking a hole-related layer, an organic emission layer, and an electron-related layer on the anode 610 in this order or in the reverse order. In addition, the light-emitting stack 611 may include a first light-emitting stack and a second light-emitting stack facing each other, wherein the charge generation layer is inserted between the first light-emitting stack and the second light-emitting stack. In this case, the organic emission layer of either the first light-emitting stack and the second light-emitting stack generates blue light, and the organic emission layer of the remaining one of the first light-emitting stack and the second light-emitting stack generates yellow-green light, where the result is that white light is generated by the first light-emitting stack and the second light-emitting stack. Since the white light generated from the light-emitting stack 611 is introduced into a color filter (not shown) provided on the light-emitting stack 611, a color image can be realized. Alternatively, a color image can be realized in a manner such that each light-emitting stack 611 generates color light for a corresponding sub-pixel without a separate color filter. That is, the light emitting stack 611 of the red (R) sub-pixel may generate red light, the light emitting stack 611 of the green (G) sub-pixel may generate green light, and the light emitting stack 611 of the blue (B) sub-pixel may generate blue light.

[0112] The bank 122 may be formed to expose the anode 610 of each sub-pixel. The bank 122 may be formed of an opaque material (e.g., a black material) to prevent optical interference between adjacent sub-pixels. In this case, the bank 122 is formed of a light blocking material including at least one of a color pigment, organic black, or carbon. A spacer 121 may be further disposed on the bank 122.

[0113] The cathode 612 is formed on the upper surface and the side surface of the light emitting stack 611 to face the anode 610, wherein the light emitting stack 611 is interposed between the cathode 612 and the anode 610. In the case where the cathode 612 is applied to a top emission type organic light emitting display device, the cathode 612 is configured as a transparent conductive film formed of, for example, indium tin oxide (ITO) or indium zinc oxide (IZO). An encapsulation unit 700 for preventing moisture penetration may be further provided on the cathode 612 of the light emitting element 600.

[0114] The encapsulation unit 700 may include a first inorganic encapsulation layer 710, a second organic encapsulation layer 711, and a third inorganic encapsulation layer 712. The first inorganic encapsulation layer 710 of the encapsulation unit 700 may be disposed on the cathode 612. The second organic encapsulation layer 711 may be disposed on the first inorganic encapsulation layer 710. The third inorganic encapsulation layer 712 may be disposed on the second organic encapsulation layer 711. The first inorganic encapsulation layer 710 and the third inorganic encapsulation layer 712 of the encapsulation unit 700 may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (Siox). The second organic encapsulation layer 711 of the encapsulation unit 700 may be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0115] Figure 6 and Figure 7 is a cross-sectional view showing a display device according to another embodiment of the present invention. The following description will focus on Figure 5 The differences between the embodiments shown in the figure and the descriptions that are redundant with the above contents will be omitted or briefly described. For example, the substrate 110, the multi-buffer layer 111, the lower buffer layer 112, the first gate insulating film 113, the first interlayer insulating film 114, the second gate insulating film 115, the upper buffer layer 116, the third gate insulating film 117, the second interlayer insulating film 118, the first planarizing layer 119, the second planarizing layer 120, the embankment 122, the spacer 121, the first thin film transistor 200, the second thin film transistor 400 and the third thin film transistor 300, the light emitting element 600 and the encapsulation unit 700 are substantially the same as the corresponding parts described above. Therefore, the descriptions that are redundant with the above contents will be omitted or briefly described. Figure 5 The configuration is basically the same Figure 6 and Figure 7 Configuration.

[0116] Figure 6 1 is a diagram showing another embodiment of the structure of the storage capacitor of the display device 100 according to the embodiment of the present invention. A substrate 110, a multi-buffer layer 111, a lower buffer layer 112, a first gate insulating film 113, a first interlayer insulating film 114, a second gate insulating film 115, an upper buffer layer 116, a third gate insulating film 117, a second interlayer insulating film 118, a first planarizing layer 119, a second planarizing layer 120, a bank 122, a spacer 121, a first thin film transistor 200, a second thin film transistor 400, and a third thin film transistor 300, a light emitting element 600, and an encapsulation unit 700 are provided with Figure 5 The corresponding parts shown in are basically the same.

[0117] The lower storage electrode 510c is connected to any one of the third gate electrode 413 and the second source electrode 414 of the second thin film transistor 400. The lower storage electrode 510c is located on the second gate insulating film 115, is formed of the same material as the first oxide semiconductor layer 411 and is formed in the same layer as the first oxide semiconductor layer 411, and is also conductively made in the process of conductively making the second source region 411S and the second drain region 411D of the first oxide semiconductor layer 411.

[0118] The upper storage electrode 511c is connected to the remaining one of the third gate electrode 413 and the second source electrode 414 of the second thin film transistor 400 through the storage supply line 512. The upper storage electrode 511c is located on the upper buffer layer 116. The upper storage electrode 511c is formed of the same material as the second oxide semiconductor layer 412 and is formed in the same layer as the second oxide semiconductor layer 412, and is also conductive in the process of conductively conducting the source region 412S and the drain region 412D of the second oxide semiconductor layer 412. The upper storage electrode 511c is exposed through the storage contact hole 512a penetrating the third gate insulating film 117 and the second interlayer insulating film 118, and is connected to the storage supply line 512.

[0119] Figure 7 1 is a diagram showing another embodiment of the structure of the storage capacitor of the display device 100 according to the embodiment of the present invention. A substrate 110, a multi-buffer layer 111, a lower buffer layer 112, a first gate insulating film 113, a first interlayer insulating film 114, a second gate insulating film 115, an upper buffer layer 116, a third gate insulating film 117, a second interlayer insulating film 118, a first planarizing layer 119, a second planarizing layer 120, a bank 122, a spacer 121, a first thin film transistor 200, a second thin film transistor 400, and a third thin film transistor 300, a light emitting element 600, and an encapsulation unit 700 are provided. Figure 5 The corresponding parts shown in are basically the same.

[0120] The lower storage electrode 510d is connected to any one of the third gate electrode 413 and the second source electrode 414 of the second thin film transistor 400. The lower storage electrode 510d is located on the first gate insulating film 113 and is formed of the same material and in the same layer as the first gate electrode 211 and the second gate electrode 410.

[0121] The intermediate storage electrode 511d is connected to any one of the third gate electrode 413 and the second source electrode 414 of the second thin film transistor 400. The intermediate storage electrode 511d is located on the second gate insulating film 115, is formed of the same material as the first oxide semiconductor layer 411 and is formed in the same layer as the first oxide semiconductor layer 411, and is also made conductive in the process of making the second source region 411S and the second drain region 411D of the first oxide semiconductor layer 411 conductive.

[0122] The upper storage electrode 512d is connected to the remaining one of the third gate electrode 413 and the second source electrode 414 of the second thin film transistor 400 through the storage supply line 513. The upper storage electrode 512d is located on the upper buffer layer 116. The upper storage electrode 512d is formed of the same material as the second oxide semiconductor layer 412 and is formed in the same layer as the second oxide semiconductor layer 412, and is also conductively made in the process of conductively making the source region 412S and the drain region 412D of the second oxide semiconductor layer 412. The upper storage electrode 512d is exposed through the storage contact hole 512a penetrating the third gate insulating film 117 and the second interlayer insulating film 118, and is connected to the storage supply line 513.

[0123] and Figure 5 and Figure 6 Compared with the structure of the storage capacitor Cst shown in Figure 7 The parallel connection structure of the storage capacitors Cst shown has an advantage of exhibiting a larger storage capacity.

[0124] Figure 8 yes Figure 5 Detailed cross-sectional view of the second thin film transistor 400. The second thin film transistor 400 includes a second gate electrode 410, a first oxide semiconductor layer 411, a second oxide semiconductor layer 412, a third gate electrode 413, a second source electrode 414, and a second drain electrode 415.

[0125] The second gate electrode 410 overlaps the first oxide semiconductor layer 411, wherein the first interlayer insulating film 114 and the second gate insulating film 115 are interposed between the second gate electrode 410 and the first oxide semiconductor layer 411. The second oxide semiconductor layer 412 is formed on the upper buffer layer 116 to overlap the third gate electrode 413, and the first oxide semiconductor layer 411 and the second oxide semiconductor layer 412 form a channel between the second source electrode 414 and the second drain electrode 415.

[0126] The first oxide semiconductor layer 411 includes a second source region 411S, a second drain region 411D, and a second channel region 411C. In addition, the second oxide semiconductor layer 412 includes a third source region 412S, a third drain region 412D, and a third channel region 412C.

[0127] The second source region 411S and the second drain region 411D and the third source region 412S and the third drain region 412D include regions that are made conductive by a doping process. When the length of each of the conductive second source region 411S and the second drain region 411D in the X direction (i.e., the channel direction) is represented by L2 and the length of each of the conductive third source region 412S and the third drain region 412D in the X direction is represented by L1, L2 may be set to be greater than L1.

[0128] Fig. 9 yes Figure 8 The second thin film transistor 400 includes a second gate electrode 410 , a first oxide semiconductor layer 411 , a second oxide semiconductor layer 412 , a third gate electrode 413 , a second source electrode 414 , and a second drain electrode 415 .

[0129] The second gate electrode 410 is formed to overlap the first oxide semiconductor layer 411, and the second oxide semiconductor layer 412 is formed to overlap the third gate electrode 413. The first oxide semiconductor layer 411 and the second oxide semiconductor layer 412 are connected to the second source electrode 414 and the second drain electrode 415.

[0130] The second source electrode 414 is connected to the second oxide semiconductor layer 412 through the second source contact hole 414b, and the second drain electrode 415 is connected to the second oxide semiconductor layer 412 through the second drain contact hole 415b. In addition, for the connection between the first oxide semiconductor layer 411 and the second oxide semiconductor layer 412, the second source electrode 414 is connected to the first oxide semiconductor layer 411 through the second source contact hole 414a, and the second drain electrode 415 is connected to the first oxide semiconductor layer 411 through the second drain contact hole 415a.

[0131] The second source electrode 414 and the second drain electrode 415 include contact holes 414 a and 415 a connected to the first oxide semiconductor layer 411 and contact holes 414 b and 415 b connected to the second oxide semiconductor layer 412 .

[0132] When the spacing distance in the X direction from each of the contact holes 414a and 415a connected to the first oxide semiconductor layer 411 to the third gate electrode 413 is represented by L4, and the spacing distance in the X direction from each of the contact holes 414b and 415b connected to the second oxide semiconductor layer 412 to the third gate electrode 413 is represented by L3, L4 can be set to be greater than L3.

[0133] It should be noted that although reference has been made above Figures 5 to 9 The specific configurations of the first thin film transistor 200, the second thin film transistor 400, and the third thin film transistor 300 are described, however, the first thin film transistor 200, the second thin film transistor 400, and the third thin film transistor 300 may also adopt other configurations, as long as the corresponding functions of the first thin film transistor 200, the second thin film transistor 400, and the third thin film transistor 300 can be achieved. For example, the example in which the first thin film transistor 200 includes the polycrystalline semiconductor layer 210 is described above, however, the first thin film transistor 200 may also adopt other suitable semiconductor layers instead of the polycrystalline semiconductor layer 210.

[0134] Fig.10 and Figures 11A to 11C The results of simulations performed to test embodiments of the present invention are shown. FIG. 11A to FIG. 11C In , Vg represents the voltage applied to the gate node of the light-emitting pixel driving transistor. FIG. 11A to FIG. 11C In FIG. 1 , the vertical axis represents relative current, and the letter “n” in the vertical axis represents an arbitrary current used for relative comparison.

[0135] Fig.10 is a circuit diagram of a light-emitting pixel driving transistor according to an embodiment of the present invention. Fig.10 In, g, d and s represent the gate node, drain node and source node of the luminescent pixel driving transistor, respectively, VDD represents the voltage applied to the drain node d of the luminescent pixel driving transistor, and VSS represents the voltage applied to the source node s of the luminescent pixel driving transistor (which may be a ground voltage). The luminescent pixel driving transistor is configured so that the dual transistors are connected in parallel. For simulation, a dual transistor satisfying conditions I, II and III is provided. Here, conditions I, II and III are set to have different combinations of values ​​of the "width / length" (W / L) of the channel of the dual transistor, and the dual transistors are connected in parallel so that the upper transistor (①) and the lower transistor (②) overlap each other.

[0136] Fig.11A The simulation results are shown, that is, Fig.10 Characteristics (IV curve) of the dual parallel structure light-emitting pixel driving transistor that meets condition I (①W / L②W / L).

[0137] Reference Fig.11A , the luminescent pixel driving transistor composed of only a single transistor (①W / L or ②W / L) produces the result represented by the curve graph I (○), and the luminescent pixel driving transistor composed of two transistors connected in parallel (①W / L+②W / L) produces the result represented by the curve graph II (△). It can be seen from the curve graph I (○) and the curve graph II (△) that the driving current Id (curve graph II (△)) of the luminescent pixel driving transistor composed of two transistors connected in parallel is higher than the driving current Id (curve graph I (○)) of the luminescent pixel driving transistor composed of a single transistor.

[0138] Fig. 11B The simulation results are shown, that is, Fig.10 Characteristics (IV curve) of the dual parallel structure light-emitting pixel driving transistor that meets condition II (①W / L②W / 2L).

[0139] Reference Fig. 11B , the luminescent pixel driving transistor composed of a single transistor (①W / L) produces the result represented by the graph I (○), and the luminescent pixel driving transistor composed of another single transistor (②W / 2L) produces the result represented by the graph II (△). The luminescent pixel driving transistor composed of two transistors connected in parallel (①W / L+②W / 2L) produces the result represented by the graph III (□). It can be seen from the graphs I (○), II (△) and III (□) that the driving current Id of the luminescent pixel driving transistor composed of two transistors connected in parallel (graph III (□)) is higher than the driving current Id of the luminescent pixel driving transistor composed of a single transistor (graph I (○) or graph II (△)).

[0140] Fig. 11C The simulation results are shown, that is, Fig.10 Characteristics (IV curve) of the dual parallel structure light-emitting pixel driving transistor that meets condition III (①2W / L②W / L).

[0141] Reference Fig. 11C, the luminescent pixel driving transistor composed of a single transistor (①2W / L) produces the result represented by graph I (○), and the luminescent pixel driving transistor composed of another single transistor (②W / L) produces the result represented by graph II (□). The luminescent pixel driving transistor composed of two transistors connected in parallel (①2W / L+②W / L) produces the result represented by graph III (△). It can be seen from graphs I (○), II (□) and III (△) that the driving current Id of the luminescent pixel driving transistor composed of two transistors connected in parallel (graph III (△)) is higher than the driving current Id of the luminescent pixel driving transistor composed of a single transistor (graph I (○) or graph II (□)).

[0142] Display devices according to embodiments of the present invention include a liquid crystal display (LCD) device, a field emission display (FED) device, an organic light emitting display (OLED) device, and a quantum dot display device.

[0143] The display device according to an embodiment of the present invention may also include a set device (or set apparatus) or a set electronic apparatus as a complete product (or final product) including a liquid crystal module (LCM) or an OLED module, such as a laptop computer, a television, a computer monitor, equipment including an automobile display or another type of transportation equipment, or a mobile electronic device such as a smart phone or an electronic tablet.

[0144] The display device according to the embodiment of the present invention can be described as follows.

[0145] A display device according to an embodiment of the present invention includes: a substrate including a display area and a non-display area; a first thin film transistor located in the non-display area; and a second thin film transistor and a third thin film transistor located in the display area. The first thin film transistor may include: a first semiconductor pattern including first polysilicon; a first gate electrode overlapping the first semiconductor pattern; and a first source electrode and a first drain electrode connected to the first semiconductor pattern.

[0146] The third thin film transistor may include: a fourth semiconductor pattern including a first oxide semiconductor; a fourth gate electrode overlapping the fourth semiconductor pattern; and a third source electrode and a third drain electrode connected to the fourth semiconductor pattern.

[0147] The second thin film transistor may include: a second semiconductor pattern and a third semiconductor pattern including a first oxide semiconductor; a third gate electrode overlapping the third semiconductor pattern; a second gate electrode overlapping the second semiconductor pattern; and a second source electrode and a second drain electrode connected to the second semiconductor pattern and the third semiconductor pattern through contact holes.

[0148] The third semiconductor pattern and the second semiconductor pattern may be connected in parallel through the second source electrode and the second drain electrode.

[0149] The third semiconductor pattern and the second semiconductor pattern may overlap each other.

[0150] The third semiconductor pattern may include a third source region and a third drain region, and the second source electrode and the second drain electrode are respectively in contact with the third source region and the third drain region, and the second semiconductor pattern may include a second source region and a second drain region, and the second source electrode and the second drain electrode are respectively in contact with the second source region and the second drain region.

[0151] Each of the third source region, the third drain region, the second source region, and the second drain region may be doped using a dopant and may include a conductive region.

[0152] When the length of the conductive region of the third semiconductor pattern in the channel direction is denoted by L1 and the length of the conductive region of the second semiconductor pattern in the channel direction is denoted by L2, L2 may be set to be greater than L1.

[0153] The dopant may include at least one of boron (B), phosphorus (P), fluorine (F), or hydrogen (H).

[0154] A value of the driving current of the second thin film transistor (a saturation region in an Ids-Vgs curve) may be greater than a value of the driving current of the third thin film transistor.

[0155] A value of a ratio of a current change to a voltage change (S factor) of the second thin film transistor may be greater than the S factor of the third thin film transistor.

[0156] A display device according to another embodiment of the present invention may include: a substrate including a display area and a non-display area; a driving circuit unit located in the non-display area; and a pixel unit located in the display area. The pixel unit may include a switching transistor and a driving transistor, and the switching transistor and the driving transistor are configured to have different structures.

[0157] The driving transistor may include: a first active layer including a source / drain region and a channel region; a second active layer located above the first active layer; a source / drain electrode located above the second active layer and connected to the source / drain region of the first active layer and the source / drain region of the second active layer; a lower gate electrode located below the first active layer; and an upper gate electrode located above the second active layer. The source / drain region of the first active layer may be connected to the source / drain electrode through a first contact hole, the source / drain region of the second active layer may be connected to the source / drain electrode through a second contact hole, and the first contact hole may be located at a position farther away from the upper gate electrode than the second contact hole in the channel direction.

[0158] As is apparent from the above description, according to an embodiment of the present invention, a single active layer top gate type thin film transistor and a double active layer double gate type thin film transistor having respective different electrical characteristics are used for different purposes suitable for their characteristics, thereby improving the performance of a display device.

[0159] Specifically, since the single active layer top gate type thin film transistor and the double active layer double gate type thin film transistor have respective different characteristics, either one of them can be used as a switching transistor and the other one of them can be used as a driving transistor according to their respective characteristics.

[0160] However, the effects achievable by the present invention are not limited to the above-mentioned effects, and other effects not mentioned herein will be clearly understood by those skilled in the art from the above description.

[0161] It should be understood that the technical spirit of the present invention is described herein by the above description and the accompanying drawings for the purpose of illustration only, and without departing from the scope and spirit of the present invention, those skilled in the art may combine, separate, replace and modify the components. Therefore, the exemplary embodiments of the present invention are provided for illustration purposes only and are not intended to limit the technical spirit of the present invention. The scope of the technical spirit of the present invention is not limited thereto. The protection scope of the present invention should be interpreted based on the attached claims, and it should be understood that all technical spirits falling within the scope equivalent to the claims are included in the protection scope of the present invention.

Claims

1. A display device, comprising: A substrate including a display area and a non-display area; A first thin film transistor located in the non-display area; as well as a second thin film transistor, a third thin film transistor and a storage capacitor located in the display area, Wherein, the first thin film transistor comprises: a first semiconductor pattern including first polysilicon; a first gate electrode overlapping the first semiconductor pattern; and A first source electrode and a first drain electrode connected to the first semiconductor pattern, wherein the second thin film transistor comprises: a second semiconductor pattern and a third semiconductor pattern including a first oxide semiconductor; a second gate electrode overlapping the second semiconductor pattern; a third gate electrode overlapping the third semiconductor pattern; a second source electrode and a second drain electrode connected to the second semiconductor pattern and the third semiconductor pattern through a contact hole; a first interlayer insulating film between the second semiconductor pattern and the second gate electrode; a second gate insulating film between the second semiconductor pattern and the first interlayer insulating film; an upper buffer layer between the second semiconductor pattern and the third semiconductor pattern; a third gate insulating film between the third semiconductor pattern and the third gate electrode; and a second interlayer insulating film on the second semiconductor pattern, the second gate electrode, the third semiconductor pattern, and the third gate electrode, the second source electrode and the second drain electrode being disposed on the second interlayer insulating film, Wherein, the third thin film transistor comprises: a fourth semiconductor pattern including a first oxide semiconductor; a fourth gate electrode overlapping the fourth semiconductor pattern; and A third source electrode and a third drain electrode connected to the fourth semiconductor pattern, wherein the storage capacitor comprises: an upper storage electrode connected to a storage supply line; and a lower storage electrode disposed between the substrate and the upper storage electrode, wherein the upper storage electrode and the second semiconductor pattern or the third semiconductor pattern of the second thin film transistor are disposed on the same layer, wherein the second gate insulating film, the upper buffer layer, the third gate insulating film and the second interlayer insulating film have a lower hydrogen particle content than the first interlayer insulating film, wherein the storage supply line, the first source electrode, and the first drain electrode are arranged on the same layer as the second source electrode, the second drain electrode, the third source electrode, and the third drain electrode, and The upper storage electrode includes a conductive region formed by conducting a source region and a drain region of the second semiconductor pattern or the third semiconductor pattern.

2. The display device according to claim 1, wherein: The second semiconductor pattern and the third semiconductor pattern are connected in parallel through the second source electrode and the second drain electrode.

3. The display device according to claim 1, wherein: The second semiconductor pattern and the third semiconductor pattern overlap each other.

4. The display device according to claim 3, wherein: The second semiconductor pattern includes a second source region and a second drain region, the second source electrode and the second drain electrode are in contact with the second source region and the second drain region, respectively, and The third semiconductor pattern includes a third source region and a third drain region, and the second source electrode and the second drain electrode are in contact with the third source region and the third drain region, respectively.

5. The display device according to claim 4, wherein: Each of the second source region, the second drain region, the third source region, and the third drain region is doped with a dopant and includes a conductive region.

6. The display device according to claim 5, wherein: When the length of the conductive region of the second semiconductor pattern in the channel direction is denoted by L2 and the length of the conductive region of the third semiconductor pattern in the channel direction is denoted by L1, L2 is set to be greater than L1.

7. The display device according to claim 5, wherein: The dopant includes at least one of boron B, phosphorus P, fluorine F and hydrogen H.

8. The display device according to claim 1, wherein: In a saturation region in an Ids-Vgs curve, a value of the driving current of the second thin film transistor is greater than a value of the driving current of the third thin film transistor, where Ids represents source-drain current and Vgs represents gate-source voltage.

9. The display device according to claim 1, wherein: The value of an S factor of the second thin film transistor is greater than the value of an S factor of the third thin film transistor, wherein the S factor represents a ratio of a current change to a voltage change.

10. A display device, comprising: A substrate including a display area and a non-display area; a driving circuit unit located in the non-display area; as well as A pixel unit located in the display area; The pixel unit includes a switch transistor, a drive transistor and a storage capacitor, and the switch transistor and the drive transistor are configured to have different structures. Wherein, the driving transistor comprises: a first active layer including source / drain regions and a channel region; a second active layer located above the first active layer; a source / drain electrode located above the second active layer, the source / drain electrode connected to the source / drain region of the first active layer and the source / drain region of the second active layer; a lower gate electrode located below the first active layer; an upper gate electrode located above the second active layer; a first interlayer insulating film between the first active layer and the lower gate electrode; a second gate insulating film between the first active layer and the first interlayer insulating film; an upper buffer layer between the second active layer and the first active layer; a third gate insulating film between the second active layer and the upper gate electrode; and a second interlayer insulating film covering the upper gate electrode, the source / drain electrodes being arranged on the second interlayer insulating film, The source / drain region of the first active layer is connected to the source / drain electrode through a first contact hole. The source / drain region of the second active layer is connected to the source / drain electrode through a second contact hole. The first contact hole is located at a position farther from the upper gate electrode than the second contact hole in the channel direction. Wherein, the storage capacitor comprises: an upper storage electrode connected to a storage supply line; and a lower storage electrode disposed between the substrate and the upper storage electrode, The upper storage electrode and the first active layer or the second active layer of the driving transistor are arranged on the same layer. wherein the second gate insulating film, the upper buffer layer, the third gate insulating film and the second interlayer insulating film have a lower hydrogen particle content than the first interlayer insulating film, wherein the storage supply line and the source / drain electrodes of the switch transistor are arranged on the same layer as the source / drain electrodes of the drive transistor, and The upper storage electrode includes a conductive region formed by conducting the source / drain region of the first active layer or the second active layer.

11. The display device according to claim 10, wherein: The driving transistor is configured such that the first active layer and the second active layer are connected in parallel through the source / drain electrodes.

12. The display device according to claim 10, wherein: The first active layer and the second active layer overlap each other.

13. The display device according to claim 10, wherein: When a spacing distance from the lower gate electrode to the first contact hole in a channel direction is represented by L4 and a spacing distance from the lower gate electrode to the second contact hole in the channel direction is represented by L3, L4 is set to be greater than L3.

14. The display device according to claim 10, wherein: Each of the source / drain region of the first active layer and the source / drain region of the second active layer is doped with a dopant and includes a conductive region.

15. The display device according to claim 13, wherein: When the length of the conductive region of the first active layer in the channel direction is denoted by L2 and the length of the conductive region of the second active layer in the channel direction is denoted by L1, L2 is set to be greater than L1.

16. The display device according to claim 14, wherein: The dopant includes at least one of boron B, phosphorus P, fluorine F and hydrogen H.

17. The display device according to claim 10, wherein: Each of the first active layer and the second active layer includes an oxide semiconductor.

18. The display device according to claim 10, wherein: In a saturation region in an Ids-Vgs curve, a value of a driving current of the driving transistor of the pixel unit is greater than a value of a driving current of the switching transistor of the pixel unit, wherein Ids represents a source-drain current and Vgs represents a gate-source voltage.

19. The display device according to claim 10, wherein: The value of the S factor of the driving transistor of the pixel unit is greater than the value of the S factor of the switching transistor of the pixel unit, wherein the S factor represents a ratio of a current change to a voltage change.

20. A display device, comprising: A substrate including a display area and a non-display area; a driving circuit unit located in the non-display area; as well as A pixel unit located in the display area; The pixel unit includes a switch transistor, a drive transistor and a storage capacitor. Wherein, the driving transistor comprises: a second semiconductor pattern and a third semiconductor pattern including a first oxide semiconductor; a second gate electrode overlapping the second semiconductor pattern; a third gate electrode overlapping the third semiconductor pattern; a second source electrode and a second drain electrode connected to the second semiconductor pattern and the third semiconductor pattern through a contact hole, a first interlayer insulating film between the second semiconductor pattern and the second gate electrode; a second gate insulating film between the second semiconductor pattern and the first interlayer insulating film; an upper buffer layer between the second semiconductor pattern and the third semiconductor pattern; a third gate insulating film between the third semiconductor pattern and the third gate electrode; and a second interlayer insulating film on the second semiconductor pattern, the second gate electrode, the third semiconductor pattern, and the third gate electrode, the second source electrode and the second drain electrode being disposed on the second interlayer insulating film, Wherein, the switching transistor comprises: a fourth semiconductor pattern including a second oxide semiconductor; a fourth gate electrode overlapping the fourth semiconductor pattern; and A third source electrode and a third drain electrode connected to the fourth semiconductor pattern, wherein the storage capacitor comprises: an upper storage electrode connected to a storage supply line; and a lower storage electrode disposed between the substrate and the upper storage electrode, The upper storage electrode and the second semiconductor pattern or the third semiconductor pattern of the driving transistor are arranged on the same layer, wherein the second gate insulating film, the upper buffer layer, the third gate insulating film and the second interlayer insulating film have a lower hydrogen particle content than the first interlayer insulating film, wherein the storage supply line is arranged on the same layer as the second source electrode, the second drain electrode, the third source electrode and the third drain electrode, and The upper storage electrode includes a conductive region formed by conducting a source region and a drain region of the second semiconductor pattern or the third semiconductor pattern.

21. The display device according to claim 20, wherein: The first oxide semiconductor is the same as the second oxide semiconductor.

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