Semiconductor device and method of forming the same

Abstract

Methods for forming a pseudo-ubm structure and semiconductor devices formed by the methods are disclosed. In embodiments, a semiconductor device includes: a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under bump metallization (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure electrically isolated from the second redistribution line by the first passivation layer. Embodiments of the present application also relate to methods of forming semiconductor devices.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor layers of material over a semiconductor substrate and using photolithography to pattern the various material layers to form circuit components and elements thereover.

[0003] The semiconductor industry continues to move toward smaller feature sizes of the individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. SUMMARY

[0004] Some embodiments of the present application provide a semiconductor device comprising: a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under bump metallization (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure electrically isolated from the second redistribution line by the first passivation layer.

[0005] Other embodiments of this application provide a semiconductor device including: a redistribution line and a plurality of conductive traces above a semiconductor substrate; a passivation structure above the redistribution line and the plurality of conductive traces; a first under-bump metallization (UBM) structure above the redistribution line, the first under-bump metallization structure extending through the passivation structure and electrically coupled to the redistribution line; and a second under-bump metallization structure above the plurality of conductive traces, the second under-bump metallization structure being electrically isolated from the plurality of conductive traces through the passivation structure. Some embodiments of this application provide a method comprising: forming a first conductive component and a second conductive component over a semiconductor substrate; forming a passivation structure over the first conductive component and the second conductive component; etching the passivation structure to form a first opening exposing the first conductive component; etching the passivation structure to form a second opening over the second conductive component, wherein a first portion of the passivation structure remains between the second opening and the second conductive component; forming a first under-bump metallization (UBM) structure electrically coupled to the first conductive component in the first opening; and forming a second under-bump metallization structure in the second opening, wherein the second under-bump metallization structure is electrically isolated from the second conductive component through the first portion of the passivation structure. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1 to 18 This is a cross-sectional view of an intermediate stage in the manufacturing of a semiconductor device according to some embodiments. Detailed Implementation

[0008] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0009] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0010] Various embodiments provide methods for forming improved dummy bumps over redistribution layers (RDLs) and conductive traces and semiconductor devices formed by the methods. The methods include forming a passivation structure over the RDLs and / or conductive traces and forming a polymer structure over the passivation structure. The passivation structure can include one or more dielectric layers, such as an oxide layer and a nitride layer over the oxide layer. An opening for an active bump extends through the polymer structure and the passivation structure, and an opening for a dummy bump extends through the polymer structure and partially through the passivation structure. In some embodiments, the polymer structure can be omitted, and an opening for a dummy bump can be formed that extends only partially through the passivation structure. In embodiments where the passivation structure includes two layers, the opening for the dummy bump extends through the top layer of the passivation structure while being separated from the RDLs and / or conductive traces by the bottom layer of the passivation structure. Then, an active bump and a dummy bump are formed in the respective openings, where the active bump is in physical contact with and electrically coupled to the respective RDL, and the dummy bump is physically separated from and electrically isolated from the respective RDL and / or conductive trace by at least a portion of the passivation structure. The dummy bump includes a via portion that extends through a portion of the polymer structure and / or the passivation structure, which improves the shear strength of the dummy bump. This reduces device defects and improves device performance. In addition, the dummy bump is electrically isolated from the underlying RDL and / or conductive trace by a portion of the passivation structure, which allows active routing to extend under the dummy bump and increases the area available for routing. This facilitates device layout and reduces device size. In addition, a greater number of dummy bumps can be included, which can be used to improve bonding between semiconductor devices.

[0011] Figures 1 to 18 Cross-sectional views of intermediate stages in the formation of a device are shown, in accordance with some embodiments of the application. It should be appreciated that while device wafers and device dies are used as examples, embodiments of the application can also be applied to the formation of conductive components in, for example, a package assembly, including but not limited to a package substrate, an interposer, a package, and the like.

[0012] Figure 1A cross-sectional view of a semiconductor device 100 is shown. In some embodiments, the semiconductor device 100 is a device wafer that includes active devices and / or passive devices, which are denoted as integrated circuit devices 104. The semiconductor device 100 can be diced to form a plurality of chips / dies 106 therefrom. In Figure 1 In some embodiments, the semiconductor device 100 is an interposer wafer that does not contain active devices and can include passive devices. In some embodiments, the semiconductor device 100 is a package substrate strip that includes a coreless package substrate or a core package substrate having a core therein. In the subsequent discussion, a device wafer is used as an example of the semiconductor device 100, and the semiconductor device 100 can be referred to as a wafer. Embodiments of the present disclosure can also apply to interposer wafers, package substrates, packages, etc.

[0013] In some embodiments, the die 106 is a logic die (e.g., a central processing unit (CPU) die, a graphics processing unit (GPU) die, a system on a chip (SoC) die, an application processor (AP) die, a microcontroller die, an application specific integrated circuit (ASIC) die, a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a high bandwidth memory (HBM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die, a radio frequency (RF) die, a sensor die, a microelectromechanical systems (MEMS) die, a signal processing die (e.g., a digital signal processor (DSP) die, etc.), a front-end die (e.g., an analog front end (AFE) die), etc., or a combination thereof.

[0014] In some embodiments, the semiconductor device 100 includes a semiconductor substrate 102 and components formed at a top surface of the semiconductor substrate 102. The semiconductor substrate 102 can be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor substrate 102 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or graded substrates, can also be used. In some embodiments, the semiconductor material of the semiconductor substrate 102 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Shallow trench isolation (STI) regions (not shown separately) can be formed in the semiconductor substrate 102 to isolate active regions in the semiconductor substrate 102. Through holes can be formed to extend into or through the semiconductor substrate 102 (not shown separately) (e.g., through holes) and can be used to electrically couple components on opposite sides of the semiconductor device 100.

[0015] In some embodiments, the semiconductor device 100 includes an integrated circuit device 104 formed on a top surface of the semiconductor substrate 102. The integrated circuit device 104 can include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of the integrated circuit device 104 are not shown herein. In some embodiments, the semiconductor device 100 is used to form an interposer (without active devices), and the semiconductor substrate 102 can be a semiconductor substrate or a dielectric substrate.

[0016] An interlayer dielectric (ILD) 108 is formed over the semiconductor substrate 102 and fills spaces between gate stacks (not shown separately) of transistors in the integrated circuit device 104. In some embodiments, the ILD 108 is formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, combinations or multilayers thereof, etc. The ILD 108 can be formed using spin-on, flowable chemical vapor deposition (FCVD), etc. In some embodiments, the ILD 108 is formed using a deposition method such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0017] Contact plugs 110 are formed in ILD 108 and electrically couple integrated circuit device 104 to overlying metal lines and / or vias. In some embodiments, contact plugs 110 are formed of an electrically conductive material, such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), alloys or multilayers thereof, etc. Forming contact plugs 110 can include forming contact openings in ILD 108, filling the contact openings with an electrically conductive material, and performing a planarization process, such as a chemical mechanical polishing (CMP) process, a mechanical grinding process, an etch-back process, etc., to level the top surface of contact plugs 110 with the top surface of ILD 108.

[0018] Interconnect structure 112 is formed over ILD 108 and contact plugs 110. Interconnect structure 112 includes metal lines 114 and metal vias 116 formed in dielectric layer 118 (also referred to as an intermetal dielectric (IMD)). Metal lines 114 formed at the same level are collectively referred to as a metal layer. In some embodiments, interconnect structure 112 includes multiple metal layers including metal lines 114 interconnected by metal vias 116. Metal lines 114 and metal vias 116 can be formed of copper, copper alloys, other metals, etc.

[0019] In some embodiments, dielectric layer 118 is formed of a low-k dielectric material. The low-k dielectric material can have a dielectric constant (k-value) less than about 3.0. Dielectric layer 118 can include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), combinations or multilayers thereof, etc. In some embodiments, dielectric layer 118 can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, dielectric layer 118 can include oxides (e.g., silicon oxide, etc.), nitrides (e.g., silicon nitride, etc.), combinations thereof, etc. Dielectric layer 118 can be formed by FCVD, PECVD, LPCVD, etc. In some embodiments, forming dielectric layer 118 includes depositing a pore- containing dielectric material in dielectric layer 118, and then performing a curing process to drive out the pores. As such, dielectric layer 118 can be porous.

[0020] Forming the metal lines 114 and the metal vias 116 in the dielectric layers 118 can include a single damascene process and / or a dual damascene process. In a single damascene process, a trench or via opening is formed in one of the dielectric layers 118, and the trench or via opening is filled with an electrically conductive material. A planarization process, such as a CMP process, is then performed to remove excess portions of the electrically conductive material, which can be above a top surface of the dielectric layer 118, leaving the metal lines 114 or the metal vias 116 in the corresponding trench or via opening. In a dual damascene process, both a trench and a via opening are formed in the dielectric layer 118, where the via opening is below and connected to the trench. An electrically conductive material is filled into the trench and the via opening to form the metal lines 114 and the metal vias 116, respectively. The electrically conductive material can include a diffusion barrier layer and a copper-containing metal material above the diffusion barrier layer. The diffusion barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0021] A top metal component 120 can be formed in a top dielectric layer 121. The top metal component 120 can be formed of the same or similar material as the metal lines 114 and by the same or similar process thereof, and the metal vias 116 and the top dielectric layer 121 can be formed of the same or similar material as the dielectric layers 118 and by the same or similar process thereof. The top dielectric layer 121 and the underlying dielectric layer 118 directly below the top dielectric layer 121 can be formed as a single continuous dielectric layer, or can be formed as different dielectric layers using different processes from each other.

[0022] A first passivation layer 122 and a second passivation layer 124 can be formed over the interconnect structure 112. The first passivation layer 122 and the second passivation layer 124 can be collectively referred to as a first passivation structure. In some embodiments, the first passivation layer 122 and the second passivation layer 124 can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. In some embodiments, the first passivation layer 122 and the second passivation layer 124 can include an inorganic dielectric material, which can include a material selected from silicon nitride (SiNx), silicon oxide (Si02), silicon oxynitride (SiONx), silicon oxycarbide (SiOCx), silicon carbide (SiC), combinations or multilayers thereof, or the like. The first passivation layer 122 and the second passivation layer 124 can be formed of different materials. For example, the first passivation layer 122 can include silicon nitride (SiN), and the second passivation layer 124 can include undoped silicate glass (USG). In some embodiments, the first passivation layer 122 can include a single layer, and the second passivation layer 124 can be omitted. In some embodiments, a top surface of the top dielectric layer 121 and a top surface of the top metal component 120 are coplanar (e.g., flush with each other). Thus, the first passivation layer 122 and the second passivation layer 124 can be planar layers. In some embodiments, the top metal component 120 protrudes above the top surface of the top dielectric layer 121, and the first passivation layer 122 and the second passivation layer 124 are non-planar. The first passivation layer 122 and the second passivation layer 124 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like.

[0023] In Figure 2 the first passivation layer 122 and the second passivation layer 124. The opening 126 can be patterned through the first passivation layer 122 and the second passivation layer 124, and can expose the top metal component 120.

[0024] In Figure 3 the second passivation layer 124, the first passivation layer 122, and the top metal component 120, and in the opening 126. The seed layer 128 can include a titanium layer and a copper layer over the titanium layer. In some embodiments, the seed layer 128 includes a copper layer in contact with the second passivation layer 124, the first passivation layer 122, and the top metal component 120. The seed layer 128 can be formed by a deposition process such as PVD or the like.

[0025] InFigure 4 In this process, a patterned photoresist 130 is formed above a seed layer 128. The patterned photoresist 130 can be formed by depositing a photosensitive layer above the seed layer 128 using a spin coating or similar method. The photosensitive layer is then patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove exposed or unexposed portions, thereby forming the patterned photoresist 130. An opening 132 in the exposed seed layer 128 is formed to extend through the patterned photoresist 130. The pattern of the patterned photoresist 130 corresponds to a redistribution layer (RDL) to be formed in the patterned photoresist 130, as will be discussed below. Figure 5 The discussion.

[0026] exist Figure 5 In this process, conductive material 134 is formed above the exposed portion of seed layer 128 and fills openings 126 and 132. Conductive material 134 can be formed by plating, such as electroplating or electroless plating. Conductive material 134 may include metals such as copper, titanium, tungsten, aluminum, etc. The combination of conductive material 134 and the lower portion of seed layer 128 forms RDL 136A and RDL 136B (collectively referred to as RDL 136). Each RDL 136 may include a via portion extending through the second passivation layer 124 and the first passivation layer 122, and a trace / line portion located above the second passivation layer 124. Although in Figure 5 Only two RDL 136s are shown, but any number of RDL 136s can be formed above each die 106.

[0027] exist Figure 6 In this process, the patterned photoresist 130 and the portion of the seed layer 128 where the conductive material 134 is not formed are removed. The patterned photoresist 130 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the patterned photoresist 130 has been removed, the exposed portions of the seed layer 128 are removed using an acceptable etching process (such as wet etching or dry etching).

[0028] exist Figure 7In some embodiments, a third passivation layer 138, a fourth passivation layer 140, and a protective layer 142 are formed over the second passivation layer 124, and over and along the sidewalls and top surfaces of the RDLs 136. The third passivation layer 138 and the fourth passivation layer 140 can be collectively referred to as a second passivation structure. The third passivation layer 138 and the fourth passivation layer 140 can be formed of the same or different materials as the first passivation layer 122 and the second passivation layer 124. In some embodiments, the third passivation layer 138 and the fourth passivation layer 140 can be formed of inorganic dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbide, combinations or multilayers thereof, or the like. In some embodiments, the third passivation layer 138 can comprise silicon oxide, and the fourth passivation layer 140 can comprise silicon nitride. The third passivation layer 138 can be made of a material having a high etch selectivity with respect to the material of the fourth passivation layer 140, such that the third passivation layer 138 can serve as an etch stop layer for a process to etch the fourth passivation layer 140. In some embodiments, the third passivation layer 138 can comprise a single layer, and the fourth passivation layer 140 can be omitted. The third passivation layer 138 and the fourth passivation layer 140 can be deposited by CVD, ALD, or the like.

[0029] In some embodiments, the third passivation layer 138 can have a thickness T1 ranging from about 0.3 pm to about 2.5 pm. Providing the third passivation layer 138 with a thickness within this range provides sufficient material to electrically isolate subsequently formed pseudo-bumps (such as the UBM structure 150B discussed below) from the RDLs 136, while minimizing the thickness of the third passivation layer 138. The fourth passivation layer 140 can have a thickness T2 ranging from about 0.3 pm to about 2.5 pm. Figure 10

[0030] A protective layer 142 is then formed over the fourth passivation layer 140. In some embodiments, the protective layer 142 is formed of a polymeric material (which can be photosensitive) such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy, or the like. The protective layer 142 can be formed by CVD, PECVD, a spin-on process, or the like. In some embodiments, forming the protective layer 142 includes applying the protective layer 142 in a flowable form, and then baking to harden the protective layer 142. A planarization process such as CMP or a mechanical lapping process can be performed to level the top surface of the protective layer 142. The protective layer 142 can be formed over the RDLs 136 with a height H3 ranging from about 1.5 pm to about 10 pm. The protective layer 142 can also have a height H4 over the second passivation layer 124 between the RDLs 136 ranging from about 4.5 pm to about 20 pm.

[0031] In some embodiments, the UBM structure 150B is formed over the protective layer 142. The UBM structure 150B can be formed by a process such as sputtering, evaporation, or the like. In some embodiments, the UBM structure 150B is formed by a process such as electroplating, electroless plating, or the like. In some embodiments, the UBM structure 150B is formed by a process such as electroplating, electroless plating, or the like. Figure 8 ​In this embodiment, a first opening 144 is formed above RDL 136A, penetrating through the protective layer 142, the fourth passivation layer 140, and the third passivation layer 138. In embodiments where the protective layer 142 comprises a photosensitive material, the protective layer 142 is patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove exposed or unexposed portions. The first opening 144 can then be extended through the fourth passivation layer 140 and the third passivation layer 138 to expose RDL 136A using the protective layer 142 as a mask. The fourth passivation layer 140 and the third passivation layer 138 can be etched using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching process can be anisotropic. Figure 8 As shown, the first opening 144 may have tapered sidewalls that narrow in the direction toward the semiconductor substrate 102. In some embodiments, the sidewalls of the first opening 144 may be substantially vertical or may be tapered and widen in the direction toward the semiconductor substrate 102. The first opening 144 may have a width W1 ranging from about 5 μm to about 50 μm flush with the top surface of the protective layer 142 and a width W2 ranging from about 5 μm to about 50 μm flush with the bottom surface of the third passivation layer 138 above the RDL 136A.

[0032] exist Figure 9 In this embodiment, a second opening 146 is formed over RDL 136B, extending through the protective layer 142 and the fourth passivation layer 140. In embodiments where the protective layer 142 comprises a photosensitive material, the protective layer 142 can be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove exposed or unexposed portions, thereby forming the second opening 146. The protective layer 142 can then be used as a mask, and the third passivation layer 138 as an etch stop layer to extend the second opening 146 through the fourth passivation layer 140. In embodiments where the fourth passivation layer 140 is omitted, the second opening 146 may extend only through the protective layer 142. Any acceptable etching process can be used to etch the fourth passivation layer 140, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching process can be anisotropic. Figure 9As shown, the second opening 146 can have a tapered sidewall that narrows in a direction toward the semiconductor substrate 102. In some embodiments, the sidewall of the second opening 146 can be substantially vertical or can be tapered and can widen in a direction toward the semiconductor substrate 102. The second opening 146 can have a width W3 ranging from about 5 pm to about 50 pm that is flush with a top surface of the protective layer 142 and a width W4 ranging from about 5 pm to about 50 pm that is flush with a bottom surface of the fourth passivation layer 140 above the RDL 136B. The third passivation layer 138 can be substantially unetched below the second opening 146 such that a thickness above the RDL 136B is maintained in a range from about 0.5 pm to about 2.5 pm.

[0033] A curing process can then be used to cure the protective layer 142. The curing process can include heating the protective layer 142 to a predetermined temperature for a predetermined period of time using an annealing process or other heating process. The curing process can also include an ultraviolet (UV) light exposure process, an infrared (IR) energy exposure process, a combination thereof, or a combination of them with a heating process. Alternatively, other methods can be used to cure the protective layer 142. In some embodiments, the curing process is not included or is performed prior to forming the first opening 144 and the second opening 146.

[0034] Although it has been described that the second opening 146 is formed after the first opening 144, in some embodiments, the second opening 146 can be formed prior to the first opening 144 or concurrently with the first opening 144. For example, the same etching process can be used to form the second opening 146 and partially form the first opening 144, and an additional etching process can be used to complete the first opening 144.

[0035] In Figure 10 UBM structures 150A and 150B (collectively referred to as UBM structures 150) are formed above the RDLs 136A and 136B, respectively. The UBM structure 150A is formed in physical contact with and electrically coupled to the RDL 136A, while the UBM structure 150B is formed above the third passivation layer 138 and electrically isolated from the RDL 136B. The UBM structures 150 can be formed by forming a seed layer (not shown separately) above the protective layer 142 and in the first and second openings 144 and 146, along the sides of the protective layer 142, the fourth passivation layer 140, and the third passivation layer 138, and along the top surface of the RDL 136A (e.g., in the first opening 144) and the top surface of the third passivation layer 138 (e.g., in the second opening 146). In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD or the like.

[0036] A photoresist (not shown separately) is then formed over the seed layer and is patterned. The photoresist can be formed by spin coating, etc., and the photoresist can be exposed to a patterned energy source (e.g., a patterned light source). The photoresist can then be developed to remove exposed or unexposed portions of the photoresist. The pattern of the photoresist corresponds to the pad portion of the UBM structure 150 that extends above and along the top surfaces of the protective layer 142. The patterning forms openings through the photoresist to expose the seed layer.

[0037] A conductive material is then formed over the exposed portions of the seed layer and fills the openings of the photoresist. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the underlying portions of the seed layer form the UBM structure 150A and the UBM structure 150B. The UBM structure 150A includes a via portion that extends through the protective layer 142, the fourth passivation layer 140, and the third passivation layer 138. The via portion of the UBM structure 150A is in physical contact with and electrically coupled to the RDL 136A. The via portion of the UBM structure 150A has a width W1 at a point flush with the top surface of the protective layer 142 that ranges from about 5 pm to about 50 pm, a bottom surface of the via portion of the UBM structure 150A can have a width W2 that ranges from about 5 pm to about 50 pm, and a height H1 of the via portion of the UBM structure 150A measured between the point flush with the top surface of the protective layer 142 and the bottom surface of the via portion of the UBM structure 150A can range from about 1.5 pm to about 20 pm. The UBM structure 150B includes a via portion that extends through the protective layer 142 and the fourth passivation layer 140, and does not extend through the third passivation layer 138. The via portion of the UBM structure 150B is electrically isolated from the RDL 136B by the third passivation layer 138. The via portion of the UBM structure 150B has a width W3 at a point flush with the top surface of the protective layer 142 that ranges from about 5 pm to about 50 pm, a bottom surface of the via portion of the UBM structure 150B can have a width W4 that ranges from about 5 pm to about 50 pm, and a height H2 of the via portion of the UBM structure 150B measured between the point flush with the top surface of the protective layer 142 and the bottom surface of the via portion of the UBM structure 150B can range from about 0.5 pm to about 20 pm. The UBM structure 150 also includes a pad portion that is located above and extends along the top surface of the protective layer 142.

[0038] The UBM structure 150B is electrically isolated from the RDL 136B and is referred to as a dummy UBM structure. Forming the UBM structure 150B with a via portion extending through the protective layer 142 and the fourth passivation layer 140 such that the via portion is in contact with the sidewalls of the protective layer 142 and the fourth passivation layer 140 and the top surface of the third passivation layer 138 increases the contact area between the UBM structure 150B and the underlying dielectric structure, thereby improving the adhesion of the UBM structure 150B and increasing the shear strength of the UBM structure 150B. Further, because the UBM structure 150B is electrically isolated from the RDL 136B, the RDL 136B can be an active RDL, which allows more space for routing the RDL 136. Further, electrically isolating the UBM structure 150B from the RDL 136B allows more dummy UBM structures 150B to be formed, which provides more bump contact areas and allows for a more robust connection between the UBM structure 150 and other semiconductor devices. For example, the UBM structure 150 can be formed with a pitch ranging from about 10 pm to about 150 pm.

[0039] After the UBM structure 150 is formed, a conductive connection 152 is formed on the UBM structure 150. The conductive connection 152 can be a ball grid array (BGA) connection, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, an electroless nickel-electroless palladium immersion gold (ENEPIG) formed bump, or the like. The conductive connection 152 can include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like or combinations thereof. In some embodiments, the conductive connection 152 is formed by first forming a layer of solder by evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the layer of solder is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connection 152 includes a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillar can be solder free and have substantially vertical sidewalls. In some embodiments, a metal protective layer is formed on the top of the metal pillar. The metal protective layer can include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like or combinations thereof and can be formed by a plating process.

[0040] Figure 11 Embodiments are shown in which the protective layer 142 is omitted. In Figure 11In the illustrated embodiment, UBM structure 150A includes a via portion extending through the fourth passivation layer 140 and the third passivation layer 138 to physically contact and electrically couple with RDL 136A. The via portion of UBM structure 150A has a width W5 ranging from about 5 μm to about 50 μm at a point flush with the top surface of the fourth passivation layer 140, a bottom surface of the via portion of UBM structure 150A may have a width W6 ranging from about 5 μm to about 50 μm, and the via portion of UBM structure 150A may have a height H5 ranging from about 1 μm to about 20 μm between the point flush with the top surface of the fourth passivation layer 140 and the bottom surface of the via portion of UBM structure 150A. UBM structure 150B includes a via portion extending through the fourth passivation layer 140 but not through the third passivation layer 138. UBM structure 150B is electrically isolated from RDL 136B via a third passivation layer 138. The via portion of UBM structure 150B has a width W7 ranging from about 5 μm to about 50 μm at a point flush with the top surface of the fourth passivation layer 140. The bottom surface of the via portion of UBM structure 150B may have a width W8 ranging from about 5 μm to about 50 μm, and the via portion of UBM structure 150B may have a height H6 ranging from about 0.5 μm to about 20 μm between the point flush with the top surface of the fourth passivation layer 140 and the bottom surface of the via portion of UBM structure 150B. UBM structure 150 includes pad portions located above and extending along the top surface of the fourth passivation layer 140. In embodiments where widths W5 and W7 are relatively small (e.g., less than about 5 μm), the protective layer 142 may be omitted. Omitting the protective layer 142 reduces the aspect ratio (e.g., height to width ratio) of the opening in the via portion of the UBM structure 150, which allows the UBM structure 150 to be formed more easily and prevents voids or other inconsistencies from forming in the UBM structure 150. This reduces device defects and improves device performance.

[0041] Figures 12 to 18 The following embodiment is shown, wherein UBM structures 180 and 182 are formed on RDL 166 and conductive trace 168, respectively. Figure 17 Above (as shown), rather than formed above RDL 136. In Figure 12 In the middle, an opening 160 is formed, which extends through Figure 1 The structure shown includes a second passivation layer 124 and a first passivation layer 122. The opening 160 can be connected to the structure discussed above and related to... Figure 2 The openings 126 shown are formed using similar or identical methods.

[0042] exist Figure 13In some embodiments, the RDL 166 and conductive traces 168 are formed over the second passivation layer 124. The RDL 166 and conductive traces 168 are formed by first forming a seed layer 162 over the second passivation layer 124, the first passivation layer 122, and over the top of one of the top metal features 120 and in the openings 160. The seed layer 162 can include a titanium layer and a copper layer over the titanium layer. In some embodiments, the seed layer 162 includes a copper layer in contact with the second passivation layer 124, the first passivation layer 122, and the top metal features 120. The seed layer 162 can be formed by a deposition process such as PVD.

[0043] A patterned photoresist (not shown separately) is then formed over the seed layer 162. The patterned photoresist can be formed by depositing a photosensitive layer over the seed layer 162 using spin coating or the like. The photosensitive layer can then be patterned by exposing the photosensitive layer to a patterned energy source (e.g., a patterned light source) and developing the photosensitive layer to remove exposed or unexposed portions of the photosensitive layer, thereby forming the patterned photoresist. Openings exposing the seed layer 162 are formed extending through the patterned photoresist. The pattern of the patterned photoresist 130 corresponds to the RDL 166 and conductive traces 168 to be formed in the patterned photoresist.

[0044] A conductive material 164 is formed over the exposed portions of the seed layer 162 and fills the openings 160 and openings formed in the patterned photoresist. The conductive material 164 can be formed by plating such as electroplating or electroless plating. The conductive material 164 can include a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material 164 and the underlying portions of the seed layer 162 form the RDL 166 and conductive traces 168. The RDL 166 can include via portions extending through the second passivation layer 124 and the first passivation layer 122 and trace / line portions over the second passivation layer 124. In some embodiments, the conductive traces 168 can include only trace / line portions over the second passivation layer 124. Although one RDL 166 and four conductive traces 168 are shown in FIG. 1C, any number of RDLs 166 and conductive traces 168 can be formed over each die 106. Figure 13

[0045] The spacing SI between adjacent conductive traces 168 can be greater than about 1.0 pm. The spacing SI between adjacent conductive traces 168 is ensured to be greater than this minimum value to ensure that a seed layer for a subsequently formed UBM structure (such as the UBM structure 182 discussed below with respect to FIG. 2) can be deposited in an opening (such as the second opening 178 discussed below with respect to FIG. 2) extending between adjacent conductive traces 168. Figure 17 Figure 16

[0046] ​​​The patterned photoresist and portions of the seed layer 162 not formed with the conductive material 164 are then removed. The patterned photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the patterned photoresist is removed, an acceptable etching process, such as wet etching or dry etching, is used to remove the exposed portions of the seed layer 162.

[0047] In Figure 14 the third passivation layer 170 and the fourth passivation layer 172 can be collectively referred to as passivation-2 (or pass-2). The third passivation layer 170 and the fourth passivation layer 172 can be formed of the same or different materials than the materials of the third passivation layer 138 and the fourth passivation layer 140. In some embodiments, the third passivation layer 170 and the fourth passivation layer 172 can be formed of an inorganic dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbide, combinations or multilayers thereof, or the like. In some embodiments, the third passivation layer 170 can include silicon oxide and the fourth passivation layer 172 can include silicon nitride. The third passivation layer 170 can be made of a material having a high etch selectivity with respect to the material of the fourth passivation layer 172, such that the third passivation layer 170 can be used as an etch stop layer for a process to etch the fourth passivation layer 172. In some embodiments, the third passivation layer 170 can include a single layer and the fourth passivation layer 172 can be omitted. The third passivation layer 170 and the fourth passivation layer 172 can be deposited by CVD, ALD, or the like.

[0048] As shown in Figure 14 both the third passivation layer 170 and the fourth passivation layer 172 can be conformally deposited. Portions of the fourth passivation layer 172 disposed between adjacent conductive traces 168 can merge with one another. The top of the fourth passivation layer 172 can remain unmerged, such that a recess is formed in the fourth passivation layer 172 between adjacent conductive traces 168. As shown in Figure 14 the bottom of the recess in the fourth passivation layer 172 can be disposed below the top surface of the conductive traces 168, or the bottom of the recess in the fourth passivation layer 172 can be disposed to be flush with or above the top surface of the conductive traces 168. In some embodiments, portions of the fourth passivation layer 172 disposed between adjacent conductive traces 168 can be merged, such that the top surface of the fourth passivation layer 172 between adjacent conductive traces 168 is substantially flat or planar.

[0049] In some embodiments, the third passivation layer 170 can have a thickness T3 over the RDL 166 and the conductive traces 168 ranging from about 0.3 pm to about 2.5 pm. Providing the third passivation layer 170 with a thickness within this range provides sufficient material to form a subsequent formed dummy bump, such as the dummy bump 190 discussed below Figure 17 with the conductive traces 168 while minimizing the thickness of the third passivation layer 170. The fourth passivation layer 172 can have a thickness T4 over the RDL 166 and the conductive traces 168 ranging from about 0.3 pm to about 2.5 pm.

[0050] A protective layer 174 is then formed over the fourth passivation layer 172. In some embodiments, the protective layer 174 is formed from a polymeric material, which can be photosensitive, such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy, etc. The protective layer 174 can be formed by CVD, PECVD, a spin-on process, etc. In some embodiments, forming the protective layer 174 includes applying the protective layer 174 in a flowable form and then baking to harden the protective layer 174. A planarization process, such as CMP, or a mechanical lapping process can be performed to level the top surface of the protective layer 174. The protective layer 174 can have a height H9 over the RDL 166 and the conductive traces 168 ranging from about 1.5 pm to about 10 pm. The protective layer 174 can also have a height H10 over the second passivation layer 124 between the RDL 166 and the conductive traces 168 ranging from about 1.5 pm to about 10 pm. As shown, the third passivation layer 170 and the fourth passivation layer 172 can be formed between adjacent conductive traces 168. The protective layer 174 can fill any pits in the fourth passivation layer between adjacent conductive traces 168. Figure 14

[0051] In some embodiments, the protective layer 174 is formed over the fourth passivation layer 172 and the third passivation layer 170. The protective layer 174 can be formed by CVD, PECVD, a spin-on process, etc. In some embodiments, forming the protective layer 174 includes applying the protective layer 174 in a flowable form and then baking to harden the protective layer 174. A planarization process, such as CMP, or a mechanical lapping process can be performed to level the top surface of the protective layer 174. The protective layer 174 can have a height H9 over the RDL 166 and the conductive traces 168 ranging from about 1.5 pm to about 10 pm. The protective layer 174 can also have a height H10 over the second passivation layer 124 between the RDL 166 and the conductive traces 168 ranging from about 1.5 pm to about 10 pm. As shown, the third passivation layer 170 and the fourth passivation layer 172 can be formed between adjacent conductive traces 168. The protective layer 174 can fill any pits in the fourth passivation layer between adjacent conductive traces 168. Figure 15 Figure 15 ​​As shown, the first opening 176 can have tapered sidewalls that narrow in a direction toward the semiconductor substrate 102. In some embodiments, the sidewalls of the first opening 176 can be substantially vertical or can be tapered and can widen in a direction toward the semiconductor substrate 102. The first opening 176 can have a width W9 ranging from about 5 μιη to about 50 μιη that is flush with a top surface of the protective layer 174 and a width WlO ranging from about 5 μιη to about 50 μιη that is flush with a bottom surface of the third passivation layer 170 above the RDL 166.

[0052] In Figure 16 embodiments, the second opening 178 can be formed by patterning the protective layer 174 by exposing the protective layer 174 to a patterned energy source (e.g., a patterned light source) and developing the protective layer 174 to remove exposed or unexposed portions of the protective layer 174. The protective layer 174 can then be used as a mask to extend the second opening 178 through the fourth passivation layer 172. In some embodiments, an additional mask can be deposited in the second opening 178, patterned, and used as a mask to extend the second opening 178 into the fourth passivation layer 172. Although the second opening 178 is shown as extending only through a portion of the protective layer 174 and the fourth passivation layer 172, in some embodiments, the second opening 178 can also extend through a portion of the third passivation layer 170. In some embodiments, the third passivation layer 170 can act as an etch stop layer. In embodiments where the fourth passivation layer 172 is omitted, the second opening 178 can extend only through the protective layer 174. Any acceptable etching process can be used to etch the fourth passivation layer 172, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. The etching process can be anisotropic.

[0053] As Figure 16As shown, the second opening 178 can have tapered sidewalls that narrow in a direction toward the semiconductor substrate 102. In some embodiments, the sidewalls of the second opening 178 can be substantially vertical or can be tapered and can widen in a direction toward the semiconductor substrate 102. The portion of the second opening 178 that extends through the protective layer 174 can have a relatively large width, while the portion of the second opening 178 that extends into the fourth passivation layer 172 can have a relatively narrow width. The second opening 178 can have a width W13 that ranges from about 5 pm to about 60 pm that is flush with a top surface of the protective layer 174, and a width Wl l that ranges from about 1.3 pm to about 10 pm that is flush with a top surface of the fourth passivation layer 172, and a bottom surface of the second opening 178 has a width W12 that ranges from about 0.8 pm to about 9.0 pm. The second opening 178 can have a depth Dl that ranges from about 0.2 pm to about 5.0 pm, and the portion of the second opening 178 that extends into the fourth passivation layer 172 can have a depth D2 that ranges from about 0.1 pm to about 3.0 pm. The third passivation layer 170 can be substantially unetched by the process used to form the second opening 178, such that the thickness of the third passivation layer 170 between the conductive trace 168 and the second opening 178 is at least about 1.0 pm to about 2.5 pm.

[0054] In Figure 17 embodiments, a UBM structure 180 and a UBM structure 182 are formed over the RDL 166 and the conductive trace 168, respectively. The UBM structure 180 is formed in physical contact with and electrically coupled to the RDL 166. At least a portion of the third passivation layer 170 is between the UBM structure 182 and the conductive trace 168, such that the UBM structure 182 is electrically isolated from the conductive trace 168. The UBM structure 180 is formed by forming a seed layer (not shown separately) over the protective layer 174 and in the first opening 176, along sidewalls of the protective layer 174, the fourth passivation layer 172, and the third passivation layer 170, and along a top surface of the RDL 166. The UBM structure 182 is formed by forming a seed layer (not shown separately) over the protective layer 174 and in the second opening 178, along sidewalls of the protective layer 174 and the fourth passivation layer 172, and along a top surface of the fourth passivation layer 172. In some embodiments, the seed layer is a metal layer that can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, PVD.

[0055] After the seed layer is formed, photoresist (not shown separately) is formed on the seed layer and is patterned. The photoresist can be formed by spin coating, etc., and the photoresist can be exposed to a patterned energy source (e.g., a patterned light source). The photoresist can then be developed to remove exposed or unexposed portions of the photoresist. The pattern of the photoresist corresponds to the pad portions of the UBM structures 180 and 182 that extend above and along the top surface of the protective layer 174. The patterning forms openings through the photoresist to expose the seed layer.

[0056] The conductive material can be formed by plating, such as electroplating or electroless plating, etc. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the underlying portions of the seed layer form the UBM structures 180 and 182. The UBM structure 180 includes a via portion that extends through the protective layer 174, the fourth passivation layer 172, and the third passivation layer 170 and is in physical contact with and electrically coupled to the RDL 166. The via portion of the UBM structure 180 can have a width W9 ranging from about 5 pm to about 50 pm at a point that is flush with the top surface of the protective layer 174, a width W10 ranging from about 5 pm to about 50 pm above the RDL 166 at a point that is flush with the bottom surface of the third passivation layer 170, and a height H7 ranging from about 1.5 pm to about 20 pm measured between the point that is flush with the top surface of the protective layer 174 and the point that is flush with the bottom surface of the third passivation layer 170 above the RDL 166. The via portion of the UBM structure 180 is in physical contact with the side surface of the protective layer 174, the side surface of the fourth passivation layer 172, the side surface of the third passivation layer 170, and the top surface of the RDL 166. The UBM structure 180 also includes pad portions that extend above and along the top surfaces of the protective layer 174.

[0057] The UBM structure 182 includes a via portion that extends through the protective layer 174 and can further extend through portions of the fourth passivation layer 172 and the third passivation layer 170. The via portion of the UBM structure 182 is disposed between adjacent conductive traces 168. The UBM structure 182 is electrically isolated from the conductive traces 168 by at least a portion of the third passivation layer 170. The via portion of the UBM structure 182 has a width W13 ranging from about 5 pm to about 60 pm at a point that is flush with the top surface of the protective layer 174, a width W11 ranging from about 1.3 pm to about 10 pm at a point that is flush with the top surface of the fourth passivation layer 172, and a bottom surface of the via portion of the UBM structure 182 can have a width W12 ranging from about 0.8 pm to about 9.0 pm. The height H8 of the via portion of the UBM structure 182, measured between a point that is flush with the top surface of the protective layer 174 and the bottom surface of the via portion of the UBM structure 182, ranges from about 0.2 pm to about 5.0 pm. In some embodiments, the via portion of the UBM structure 182 is in physical contact with the side surface of the protective layer 174, the side surface of the fourth passivation layer 172, and the top surface of the fourth passivation layer 172. In some embodiments, the via portion of the UBM structure 182 is in physical contact with the side surface of the protective layer 174, the side surface of the fourth passivation layer 172, the side surface of the third passivation layer 170, and the top surface of the fourth passivation layer 172. The UBM structure 182 also includes a pad portion that extends above and along the top surface of the protective layer 174. Although three via portions are shown extending from the pad portion of the UBM structure 182, any number of via portions, such as more than three, two, or one via portion, can extend from the pad portion of the UBM structure 182. The pitch of the UBM structures 180 and 182 can range from about 10 pm to about 150 pm.

[0058] The UBM structure 182 is electrically isolated from the conductive traces 168 and can be referred to as a pseudo-UBM structure. The UBM structure 182 is formed with one or more via portions that extend below the top surface of the conductive traces 168, which allows for increased contact area between the UBM structure 182 and the underlying layers (e.g., the protective layer 174, the fourth passivation layer 172, and the third passivation layer 170), thereby improving adhesion of the UBM structure and increasing the shear strength of the UBM structure 182. Including multiple via portions for a single UBM structure 182 further increases the shear strength of the UBM structure 182. This reduces device defects and improves device performance. The UBM structure 182 is electrically isolated from the conductive traces 168 by at least the third passivation layer 170, which allows for routing of the conductive traces 168 under the pseudo-UBM structure 182, which increases the available routing space. This reduces device area and simplifies device layout. Furthermore, a greater number of pseudo-UBM structures 182 can be formed, which provides more bump contact areas and allows for more secure connections with other semiconductor devices.

[0059] After forming the UBM structures 180 and 182, conductive connections 184 are formed on the UBM structures 180 and 182. The conductive connections 184 can be ball grid array (BGA) connections, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel, electroless palladium immersion gold (ENEPIG) formed bumps, etc. The conductive connections 184 can include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or combinations thereof. In some embodiments, the conductive connections 184 are formed by first forming a layer of solder by evaporation, electroplating, printing, solder transfer, solder ball placement. Once the layer of solder is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connections 184 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars can be solder free and have substantially vertical sidewalls. In some embodiments, a metal protective layer is formed on top of the metal pillars. The metal protective layer can include nickel, tin, tin lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or combinations thereof and can be formed by a plating process.

[0060] Figure 18 Embodiments are shown that omit the protective layer 174. In Figure 18In the illustrated embodiment, the UBM structure 180 includes a via portion that extends through the fourth passivation layer 172 and the third passivation layer 170 to be in physical contact with and electrically coupled to the RDL 166. The via portion of the UBM structure 180 has a width W14 ranging from about 5 pm to about 50 pm at a point that is flush with the top surface of the fourth passivation layer 172, the bottom surface of the via portion of the UBM structure 180 can have a width W15 ranging from about 5 pm to about 50 pm, and the via portion of the UBM structure 180 can have a height H9 ranging from about 1 pm to about 20 pm measured between the point that is flush with the top surface of the fourth passivation layer 172 and the bottom surface of the via portion of the UBM structure 180. The UBM structure 182 includes a via portion that extends into the fourth passivation layer 172 without extending through the third passivation layer 170. The UBM structure 182 is electrically isolated from the conductive trace 168 by the third passivation layer 170. The via portion of the UBM structure 182 has a width W16 ranging from about 1.3 pm to about 10 pm at a location that is flush with the top surface of the fourth passivation layer 172, the bottom surface of the via portion of the UBM structure 182 can have a width W17 ranging from about 0.8 pm to about 9.0 pm, and the via portion of the UBM structure 182 can have a height H10 ranging from about 0.1 pm to about 3.0 pm measured between the point that is flush with the top surface of the fourth passivation layer 172 and the bottom surface of the via portion of the UBM structure 182. The UBM structures 180 and 182 include pad portions that extend above and along the top surfaces of the fourth passivation layer 172. Omitting the protective layer 174 can reduce the aspect ratio (e.g., height to width ratio) of the openings that form the via portions of the UBM structures 180 and 182, which allows the UBM structures 180 and 182 to be formed more easily and prevents voids or other inconsistencies from being formed in the UBM structures 180 and 182. This reduces device defects and improves device performance.

[0061] Embodiments can achieve various advantages. For example, forming a pseudo-UBM structure that includes a via portion that extends through an underlying polymer layer and / or passivation layer improves adhesion of the pseudo-UBM structure to the underlying layer and increases the shear strength of the pseudo-UBM structure. This reduces device defects and improves device performance. Forming a pseudo-UBM structure with multiple via portions further improves adhesion of the pseudo-UBM structure to the underlying layer and increases the shear strength of the pseudo-UBM structure. Forming a pseudo-UBM structure with a passivation layer between the pseudo-UBM structure and an RDL or conductive trace allows the pseudo-UBM structure to be electrically isolated from the RDL or conductive trace and provides more area for routing under the pseudo-UBM structure to the RDL or conductive trace. This reduces device area and simplifies device layout.

[0062] According to embodiments, a semiconductor device includes: a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under bump metallization (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure electrically isolated from the second redistribution line by the first passivation layer. In embodiments, the semiconductor device further includes a protective layer over the second passivation layer, the first UBM structure and the second UBM structure extending through the protective layer. In embodiments, the protective layer includes a polymeric material. In embodiments, the first passivation layer is a conformal layer, the second passivation layer is a conformal layer, and the protective layer has a planar top surface. In embodiments, the first passivation layer includes an oxide and the second passivation layer includes a nitride. In embodiments, a first width of the first UBM structure at a point flush with a top surface of the second passivation layer and a second width of the second UBM structure at a point flush with the top surface of the second passivation is less than 50 pm. In embodiments, the first UBM structure includes a first via portion extending through the first passivation layer and the second passivation layer, the first via portion having a first height between a bottom surface of the first UBM structure and a point flush with a top surface of the second passivation layer, the second UBM structure includes a second via portion extending through the second passivation layer, the second via portion having a second height between a bottom surface of the second UBM structure and a point flush with the top surface of the second passivation layer, the first height being greater than the second height by 1.0 pm to 2.5 pm.

[0063] According to another embodiment, a semiconductor device includes: a redistribution line and a plurality of conductive traces over a semiconductor substrate; a passivation structure over the redistribution line and the plurality of conductive traces; a first under bump metallization (UBM) structure over the redistribution line, the first UBM structure extending through the passivation structure and electrically coupled to the redistribution line; and a second UBM structure over the plurality of conductive traces, the second UBM structure electrically isolated from the plurality of conductive traces by the passivation structure. In embodiments, the plurality of conductive traces includes a first conductive trace and a second conductive trace, the second UBM structure includes a second via portion extending between the first conductive trace and the second conductive trace, and a bottom surface of the second via portion is below a top surface of the first conductive trace and the second conductive trace. In embodiments, the first conductive trace and the second conductive trace are separated by at least 2.7 pm. In embodiments, the first UBM structure includes a first via portion extending through the passivation structure to physically contact the redistribution line, the first via portion includes a first height measured between a bottom surface of the first via portion and a point that is flush with a top surface of the passivation structure, the second via portion includes a second height between the bottom surface of the second via portion and the point that is flush with the top surface of the passivation structure, and the second height is greater than the first height. In embodiments, the semiconductor device further includes a third conductive trace, the second UBM structure further includes a third via portion extending between the second conductive trace and the third conductive trace, and a pad portion extending over the passivation structure and coupling the second via portion to the third via portion. In embodiments, the passivation structure includes a first passivation layer over the redistribution line and the plurality of conductive traces, and a second passivation layer over the first passivation layer, the first passivation layer includes an oxide, and the second passivation layer includes a nitride. In embodiments, the semiconductor device further includes a protection layer over the second passivation layer, the protection layer includes a polymeric material, the first UBM structure includes a first pad portion extending along a top surface of the protection layer, and the second UBM structure includes a second pad portion extending along the top surface of the protection layer.

[0064] According to yet another embodiment, a method includes forming a first conductive component and a second conductive component over a semiconductor substrate; forming a passivation structure over the first conductive component and the second conductive component; etching the passivation structure to form a first opening exposing the first conductive component; etching the passivation structure to form a second opening over the second conductive component, a first portion of the passivation structure remaining between the second opening and the second conductive component; forming a first under bump metallization (UBM) structure in the first opening and electrically coupling it to the first conductive component; and forming a second UBM structure in the second opening, the second UBM structure being electrically isolated from the second conductive component by the first portion of the passivation structure. In an embodiment, forming the passivation structure includes depositing a first passivation layer over the first conductive component and the second conductive component; and depositing a second passivation layer over the first passivation layer, the first opening extending through the second passivation layer and the first passivation layer, and the second opening extending through the second passivation layer. In an embodiment, forming the first UBM structure includes forming a first via portion in the first opening, and forming a first pad portion extending along a top surface of the second passivation layer, and forming the second UBM structure includes forming a second via portion in the second opening, and forming a second pad portion extending along the top surface of the second passivation layer. In an embodiment, the method further includes depositing a protective layer over the passivation structure, the protective layer including a polymeric material; and planarizing the protective layer. In an embodiment, etching the passivation structure to form the first opening further includes etching the protective layer, and etching the passivation structure to form the second opening further includes etching the protective layer. In an embodiment, the method further includes forming a third conductive component over the semiconductor substrate, the second opening being formed to extend between the second conductive component and the third conductive component in a direction parallel to a major surface of the semiconductor substrate.

[0065] The foregoing has outlined rather generally the features of several embodiments in accordance with this disclosure so that those skilled in the art can better understand the aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: The first redistribution line and the second redistribution line are located above the semiconductor substrate, wherein the bottom surface of the first redistribution line is flush with the bottom surface of the second redistribution line; The first passivation layer is located above the first redistribution line and the second redistribution line; The second passivation layer is located above the first passivation layer; A first under-bump metallization (UBM) structure is located above the first redistribution line, extending through the first passivation layer and the second passivation layer and electrically coupled to the first redistribution line; and The second under-bump metallization structure is located above the second redistribution line, extends through the second passivation layer, and is electrically isolated from the second redistribution line through the first passivation layer. The first passivation layer extends along the sidewalls of the first redistribution line and the second redistribution line.

2. The semiconductor device according to claim 1, further comprising a protective layer above the second passivation layer, wherein, The first under-bump metallization structure and the second under-bump metallization structure extend through the protective layer.

3. The semiconductor device according to claim 2, wherein, The protective layer comprises a polymer material.

4. The semiconductor device according to claim 3, wherein, The first passivation layer is a conformal layer, the second passivation layer is a conformal layer, and the protective layer has a flat top surface.

5. The semiconductor device according to claim 1, wherein, The first passivation layer comprises an oxide, and the second passivation layer comprises a nitride.

6. The semiconductor device according to claim 1, wherein, The first width of the first under-bump metallization structure at the point flush with the top surface of the second passivation layer and the second width of the second under-bump metallization structure at the point flush with the top surface of the second passivation layer are both less than 50 μm.

7. The semiconductor device according to claim 1, wherein, The first under-bump metallization structure includes a first via portion extending through the first passivation layer and the second passivation layer, the first via portion having a first height between a point on the bottom surface of the first under-bump metallization structure and a point flush with the top surface of the second passivation layer, wherein the second under-bump metallization structure includes a second via portion extending through the second passivation layer, the second via portion having a second height between a point on the bottom surface of the second under-bump metallization structure and a point flush with the top surface of the second passivation layer, and wherein the first height is 1.0 μm to 2.5 μm greater than the second height.

8. A semiconductor device, comprising: Redistribution lines and multiple conductive traces are positioned above the semiconductor substrate; A passivated structure is located above the redistribution line and the plurality of conductive traces; A first under-bump metallization (UBM) structure is located above the redistribution line, the first under-bump metallization structure extending through the passivation structure and electrically coupled to the redistribution line; and The second under-bump metallization structure is located above the plurality of conductive traces, and is electrically isolated from the plurality of conductive traces through the passivation structure. The second bump under-metallization structure extends to a position below the top surface of the conductive trace between adjacent conductive traces.

9. The semiconductor device according to claim 8, wherein, The plurality of conductive traces include a first conductive trace and a second conductive trace, wherein the second under-bump metallization structure includes a second through-hole portion extending between the first conductive trace and the second conductive trace, and wherein the bottom surface of the second through-hole portion is below the top surface of the first conductive trace and the second conductive trace.

10. The semiconductor device according to claim 9, wherein, The first conductive trace is separated from the second conductive trace by at least 2.7 μm.

11. The semiconductor device according to claim 9, wherein, The first under-bump metallization structure includes a first through-hole portion extending through the passivation structure to physically contact the redistribution line, wherein the first through-hole portion includes a first height measured between a point on the bottom surface of the first through-hole portion and a point flush with the top surface of the passivation structure, wherein the second through-hole portion includes a second height between the bottom surface of the second through-hole portion and a point flush with the top surface of the passivation structure, and wherein the second height is greater than the first height.

12. The semiconductor device of claim 9, further comprising a third conductive trace, wherein, The second under-bump metallization structure also includes a third via portion extending between the second conductive trace and the third conductive trace, and a pad portion extending above the passivation structure and coupling the second via portion to the third via portion.

13. The semiconductor device according to claim 8, wherein, The passivation structure includes a first passivation layer above the redistribution line and the plurality of conductive traces, and a second passivation layer above the first passivation layer, wherein the first passivation layer comprises an oxide, and wherein the second passivation layer comprises a nitride.

14. The semiconductor device of claim 13, further comprising a protective layer above the second passivation layer, the protective layer comprising a polymer material, wherein, The first under-bump metallization structure includes a first pad portion extending along the top surface of the protective layer, and wherein the second under-bump metallization structure includes a second pad portion extending along the top surface of the protective layer.

15. A method of forming a semiconductor device, comprising: A first conductive component and a second conductive component are formed above a semiconductor substrate; A passivation structure is formed above the first conductive component and the second conductive component; The passivation structure is etched to form a first opening that exposes the first conductive component; The passivation structure is etched to form a second opening above the second conductive component, wherein a first portion of the passivation structure remains between the second opening and the second conductive component; A first under-bump metallization (UBM) structure electrically coupled to the first conductive component is formed in the first opening; and A second under-bump metallization structure is formed in the second opening, wherein the second under-bump metallization structure is electrically isolated from the second conductive component through the first portion of the passivation structure, wherein the bottom surface of the first conductive component and the bottom surface of the second conductive component are flush, and the passivation structure extends along the sidewalls of the first conductive component and the second conductive component.

16. The method according to claim 15, wherein, Forming the passivation structure includes: A first passivation layer is deposited over the first conductive component and the second conductive component; and A second passivation layer is deposited over the first passivation layer, wherein the first opening extends through the second passivation layer and the first passivation layer, and wherein the second opening extends through the second passivation layer.

17. The method according to claim 16, wherein, Forming the first under-bump metallization structure includes: forming a first through-hole portion in the first opening and forming a first pad portion extending along the top surface of the second passivation layer, wherein forming the second under-bump metallization structure includes: forming a second through-hole portion in the second opening and forming a second pad portion extending along the top surface of the second passivation layer.

18. The method of claim 15, further comprising: A protective layer is deposited over the passivation structure, the protective layer comprising a polymer material; as well as The protective layer is planarized.

19. The method according to claim 18, wherein, Etching the passivation structure to form the first opening further includes etching the protective layer, and wherein etching the passivation structure to form the second opening further includes etching the protective layer.

20. The method of claim 15, further comprising: A third conductive component is formed above the semiconductor substrate, wherein the second opening is formed to extend between the second conductive component and the third conductive component in a direction parallel to the main surface of the semiconductor substrate.

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