Midsection process interconnect structure with air gap and method of manufacturing the same

Abstract

The present disclosure relates to mid-of-line (MOL) interconnect structures having an air gap and methods of manufacturing the same. Disclosed herein are mid-of-line (MOL) interconnects that achieve reduced capacitance and / or resistance and corresponding techniques for forming the MOL interconnects. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer over the first insulator layer. The device-level contact is in physical contact with an integrated circuit feature, and the ruthenium structure is in physical contact with the device-level contact. An air gap separates a sidewall of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to be in physical contact with the ruthenium structure. A remaining portion of a dummy contact spacer layer can separate the first insulator layer and the second insulator layer.

Description

Technical Field

[0001] This disclosure relates to a mid-segment process interconnect structure with an air gap and a method for manufacturing the same. Background Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnected IC devices per chip area) typically increases, while geometry (i.e., the size and / or dimensions of IC features and / or the spacing between these IC features) decreases. Generally, scaling down is limited only by the ability to confine IC features to ever-reducing geometries using lithography. However, as smaller geometries are achieved to obtain ICs with faster operating speeds (e.g., by reducing the distance electrical signals travel), resistance-capacitance (RC) delay has become a significant challenge, offsetting some of the advantages gained through scaling down and limiting further scaling. RC delay typically represents the delay in the speed of electrical signals passing through the IC caused by the product of resistance (R) (i.e., the material's resistance to the flow of current) and capacitance (C) (i.e., the material's ability to store charge). Therefore, it is desirable to reduce both resistance and capacitance to reduce RC delay and optimize the performance of scaled-down ICs. Interconnects of ICs, which physically and / or electrically connect IC components and / or IC features, are particularly problematic in their contribution to RC delay. Therefore, there is a need to improve IC interconnects and / or methods for manufacturing IC interconnects. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a mid-process interconnect structure having: device-level contacts disposed in a first insulating layer, wherein the device-level contacts physically contact integrated circuit (IC) features; a ruthenium structure disposed in a second insulating layer, the second insulating layer being disposed above the first insulating layer, wherein the ruthenium structure physically contacts the device-level contacts; and an air gap separating the sidewalls of the ruthenium structure from the second insulating layer.

[0004] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a first oxide layer disposed on a substrate; a second oxide layer disposed on the first oxide layer; a third oxide layer disposed on the second oxide layer; a device-level contact disposed in the first oxide layer and extending through the first oxide layer, and in physical contact with an IC device feature formed on the substrate; a ruthenium structure disposed in the second oxide layer and in physical contact with the device-level contact, wherein an air gap is disposed between the sidewall of the ruthenium structure and the second oxide layer; and a via disposed in the third oxide layer and the second oxide layer, wherein the via is in physical contact with the ruthenium structure.

[0005] According to another aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a ruthenium structure on and in physical contact with a device-level contact; forming a dummy contact spacer layer along a sidewall of the ruthenium structure; after forming an insulating layer on the dummy contact spacer layer, removing the dummy contact spacer layer from the sidewall of the ruthenium structure to form an air gap between the sidewall of the ruthenium structure and the insulating layer; and forming a via that is in physical contact with the ruthenium structure. Attached Figure Description

[0006] This disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various structures are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various structures may be arbitrarily increased or decreased.

[0007] Figure 1A and Figure 1B This is a flowchart of a method for manufacturing a mid-process interconnect structure according to various aspects of this disclosure.

[0008] Figures 2 to 18 This is a partial schematic diagram of an integrated circuit device at various stages of a mid-process interconnect structure (e.g., a method for manufacturing the mid-process interconnect structure of the integrated circuit device of FIG1) according to various aspects of this disclosure.

[0009] Figures 19 to 27 This is a partial schematic diagram of an integrated circuit device at various stages of a mid-process interconnect structure (e.g., a method for manufacturing the mid-process interconnect structure of the integrated circuit device of FIG1) according to various aspects of this disclosure. Detailed Implementation

[0010] This disclosure generally relates to integrated circuit (IC) devices, and more specifically, to mid-process interconnects for IC devices.

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact.

[0012] Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Additionally, in the following disclosure, the formation of another feature on a feature, another feature connected to a feature, and / or another feature coupled to a feature may include embodiments in which features are formed in direct contact, and may also include embodiments in which additional features are formed in an intercalation manner such that the features are not in direct contact. Furthermore, spatially related terms such as “lower,” “higher,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upper,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to readily describe the relationship of one feature of this disclosure relative to another. Spatially related terms are intended to cover different orientations of the device including the feature.

[0013] IC manufacturing processes are generally categorized into three types: front-end online (FEOL), mid-end online (MOL or MEOL), and back-end online (BEOL). FEOL typically includes processes related to fabricating IC devices (e.g., transistors, resistors, capacitors, and / or inductors) on a wafer. For example, FEOL processes include forming isolation features, gate structures, and source / drain features. BEOL typically includes processes related to fabricating metallization layers that electrically connect the IC devices and / or components of the IC devices fabricated during FEOL (e.g., gate structures and / or source / drain features) to each other and / or external devices, thereby enabling the operation of the IC devices. Metallization layers can route signals between IC devices and / or components of the IC devices and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to IC devices and / or components of the IC devices. Typically, each metallization layer (also called a metallization level) includes at least one interconnect structure (e.g., a metal line) disposed in an insulating layer and a via disposed in a dielectric layer, wherein the via connects the metal line to the interconnect metal lines in different metallization layers. The metal lines and vias of the metallization layer may be referred to as BEOL features or global interconnects. MOL typically encompasses the processes associated with manufacturing contacts that physically and / or electrically connect FEOL features (e.g., electrically active features of an IC device) to a first metallization layer (level) formed during BEOL, such as contacts connecting the gate structure and / or source / drain features of a transistor to the first metallization layer. Contacts manufactured during MOL may be referred to as device-level contacts and / or local interconnects. Sometimes, MOL involves forming multilayer MOL interconnect structures in an insulating layer, such as first and second contacts disposed in a dielectric layer, wherein the first contact connects an electrically active feature of an IC device to a second contact, and the second contact connects the first contact to the first metallization layer. The first contact and the second contact can be referred to as device-level contact and local contact (or interconnect), respectively.

[0014] As IC technology advances to smaller technology nodes, the resistance and capacitance associated with global and local interconnects pose challenges to reducing the resistive-capacitive (RC) delay of IC devices. For example, it has been observed that the high contact resistance and capacitance exhibited by MOL interconnect structures in advanced IC technology nodes significantly delays (and in some cases prevents) the efficient routing of signals to and from IC devices (e.g., transistors), offsetting any performance improvements achieved through scaling down and limiting further scaling of ICs. Therefore, this disclosure proposes an MOL interconnect structure that reduces both resistance and capacitance compared to conventional MOL interconnect structures, thereby reducing RC delay and improving the performance of IC devices for advanced IC technology nodes. This disclosure also proposes fabrication techniques to maintain the low resistance and capacitance characteristics of the proposed MOL interconnect structure.

[0015] Figure 1A and Figure 1BThis is a flowchart of a method 10 for manufacturing an MOL interconnect structure for an IC device according to various aspects of this disclosure. The MOL interconnect structure manufactured by method 10 and its configuration relative to the overlying and connected BEOL interconnect structures can reduce the capacitance and / or resistance associated with the IC device, thereby reducing the associated RC delay. At block 15, method 10 begins by forming a device-level contact layer. The device-level contact layer has device-level contacts disposed in a first insulating layer, and the device-level contacts physically contact IC device features. Method 10 then continues, at block 15, forming a contact adhesion layer over the device-level contact layer; at block 20, forming a ruthenium layer over the contact adhesion layer; at block 25, forming a patterned layer over the ruthenium layer; and at block 30, forming a first patterned mask feature over the patterned layer. At block 35, method 10 includes using a first patterned mask feature as an etching mask to etch a ruthenium layer, a contact adhesion layer, and a patterned layer to form a ruthenium structure in physical contact with a device-level contact layer and a second patterned mask feature disposed on the ruthenium structure. At block 40, a dummy contact spacer layer is formed over the second patterned mask feature, the ruthenium structure, and the device-level contact layer. The dummy contact spacer layer is disposed along the sidewalls of the ruthenium structure. In some embodiments, method 10 includes removing the dummy contact spacer layer from the device-level contact layer at block 45. At block 50, method 10 continues by forming a second insulating layer over the dummy contact spacer layer, the ruthenium structure, and the device-level contact layer. During the formation of the second insulating layer, a portion of the second patterned mask feature is removed. At block 55, the remaining portion of the second patterned mask feature is removed to form a groove exposing the top surface of the ruthenium structure. At block 60, method 10 includes removing a dummy contact spacer layer from the sidewall of the ruthenium structure to form an air gap between the sidewall of the ruthenium structure and the second insulating layer. At block 65, method 10 includes forming a third insulating layer over the second insulating layer and the ruthenium structure. At block 70, a via and a metal wire are formed in the third insulating layer. The via extends below the top surface of the second insulating layer and is in physical contact with the ruthenium structure. Additional steps may be provided before, during, and after method 10, and for additional embodiments of method 700, some of the described steps may be moved, replaced, or eliminated. The following discussion illustrates MOL interconnect structures that can be manufactured according to various embodiments of method 10.

[0016] Figures 2 to 18This is a partial schematic diagram of an integrated circuit (IC) device 100 at various stages of the mid-process (MOL) interconnection of the manufacturing IC device 100 (e.g., those stages associated with method 10 in FIG. 1), according to various aspects of this disclosure. The IC device 100 may be included in a microprocessor, memory, and / or other IC device. In some embodiments, the IC device 100 is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. Depending on the design requirements of the IC device 100, the various transistors may be planar transistors or non-planar transistors, such as fin FETs (FinFETs) or gate-all-around (GAA) transistors. For clarity, simplified representations have been provided. Figures 2 to 18 To better understand the inventive concept of this disclosure. Additional features may be added to IC device 100, and some of the features described below may be replaced, modified, or eliminated in other embodiments of IC device 100.

[0017] Go to Figure 2The IC device 100 undergoes a FEOL process, in which various IC devices, IC features, and / or IC components are fabricated on a substrate (wafer) 110. In the depicted embodiment, the substrate 110 comprises silicon. Alternatively or additionally, the substrate 110 comprises another basic semiconductor, such as germanium; compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide); alloy semiconductors (e.g., silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof). Alternatively, the substrate 110 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements of the IC device 100, the substrate 110 may include doped regions formed by ion implantation, diffusion, and / or other suitable doping processes. In some embodiments, the substrate 110 includes p-type doped regions (e.g., p-type wells) doped with substances such as boron, indium, other p-type dopants, or combinations thereof. In some embodiments, the substrate 110 includes n-type doped regions (e.g., n-type wells) doped with substances such as phosphorus, arsenic, other n-type dopants, or combinations thereof. In some embodiments, the substrate 110 includes doped regions formed by a combination of p-type and n-type dopants. Various doped regions may be formed directly on and / or in the substrate 110, thereby providing, for example, p-well structures, n-well structures, double-well structures, bump structures, or combinations thereof.

[0018] In the depicted embodiments, various IC features and / or IC components include gate structures 120A and 120B disposed on substrate 110, wherein gate structure 120A has a metal gate (MG) stack 122A and a gate spacer 126A, and gate structure 120B has a metal gate stack 122B and a gate spacer 126B. To further describe the depicted embodiments, various IC features and / or IC components include epitaxial source / drain features 130A and 130B, a contact etch stop layer (CESL) 140, and an interlayer dielectric (ILD) layer 142, which will be further described below. In some embodiments, the transistor of the IC device 100 includes a gate structure 120A disposed between a source region (e.g., epitaxial source / drain feature 130A) and a drain region (e.g., epitaxial source / drain feature 130B), wherein a channel region is defined in the substrate 110 and located between the source and drain regions. The gate structure 120A engages the channel region such that current can flow between the source and drain regions (collectively referred to as the source / drain regions) (i.e., between the epitaxial source / drain feature 130A and epitaxial source / drain feature 130B) during operation. In some embodiments, another transistor of the IC device 100 includes a gate structure 120B disposed between a source and drain region, wherein a channel region is defined in the substrate 110 and located between the source and drain regions. In some embodiments, gate structures 120A and / or 120B are formed on a fin structure (e.g., a semiconductor fin extending from substrate 110) such that gate structures 120A and / or 120B encompass a portion of the fin structure and are inserted into corresponding source and drain regions of the fin structure. In such embodiments, gate structures 120A and / or 120B are coupled to corresponding channel regions defined in the fin structure. Figure 2 In this disclosure, the various IC components and their corresponding configurations are merely exemplary. This disclosure contemplates an IC device 100 having any combination of IC components and / or IC devices manufactured through FEOL processing and any configuration of such IC components and / or IC devices.

[0019] Metal gate stacks 122A and 122B are configured to achieve desired functionality according to the design requirements of IC device 100, such that the metal gate stack 122A of gate structure 120A may include layers and / or materials that are the same as or different from the metal gate stack 122B of gate structure 120B. In some embodiments, metal gate stacks 122A and 122B include a gate dielectric (e.g., a gate dielectric layer) and a gate electrode (e.g., a work function layer and a body (or fill) conductive layer). Metal gate stacks 122A and 122B may include many other layers, such as a capping layer, an interface layer, a diffusion layer, a barrier layer, a hard mask layer, or a combination of the foregoing. In some embodiments, the gate dielectric layer is disposed over an interface layer (including a dielectric material, e.g., silicon oxide), and the gate electrode is disposed over the gate dielectric layer. The gate dielectric layer includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination of the foregoing. Examples of high-k dielectric materials include hafnium dioxide (HfO2), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials that have a high dielectric constant (k value) relative to the dielectric constant of silicon dioxide (k≈3.9). For example, high-k dielectric materials have a dielectric constant greater than about 3.9. In some embodiments, the gate dielectric layer is a high-k dielectric layer. The gate electrode comprises a conductive material, such as polysilicon, Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the work function layer is a conductive layer tuned to have a desired work function (e.g., an n-type work function or a p-type work function), and the bulk conductive layer is a conductive layer formed on top of the work function layer. In some embodiments, the work function layer includes an n-type work function material, such as Ti, Ag, Mn, Zr, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations thereof. In some embodiments, the work function layer includes a p-type work function material, such as Ru, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The bulk conductive layer includes a suitable conductive material, such as Al, W, and / or Cu. The bulk conductive layer may include polycrystalline silicon, Ti, Ta, metal alloys, other suitable materials, or combinations thereof.

[0020] The metal gate stacks 122A and 122B are formed by deposition, photolithography, etching, other suitable processes, or combinations thereof. Deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plasma-enhanced ALD (PEALD), electroplating, other suitable methods, or combinations thereof. Photolithography patterning processes include resist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, resist development, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. Alternatively, photolithography exposure processes can be assisted, implemented, or replaced by other methods, such as maskless lithography, electron beam writing, or ion beam writing. The etching process includes dry etching, wet etching, other etching processes, or combinations thereof. The metal gate stacks 122A and 122B are fabricated according to a post-gate process, a pre-gate process, or a hybrid post-gate / pre-gate process. In a post-gate process, the gate structures 120A and 120B include dummy gate stacks, which are subsequently partially or completely replaced, respectively, by the metal gate stacks 122A and 122B. The dummy gate stacks include, for example, an interface layer (including, for example, silicon oxide) and a dummy gate electrode layer (including, for example, polysilicon). In such embodiments, the dummy gate electrode layer is removed, thereby forming gate openings that are subsequently filled by the metal gate stacks 122A and 122B.

[0021] Gate spacers 126A and 126B are respectively arranged adjacent to the metal gate stacks 122A and 122B (e.g., along their sidewalls). Gate spacers 126A and 126B are formed by any suitable process and include a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, a dielectric layer comprising silicon and nitrogen (e.g., a silicon nitride layer) may be deposited on substrate 110 and subsequently anisotropically etched to form gate spacers 126A and 126B. In some embodiments, gate spacers 126A and 126B include a multilayer structure, e.g., a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some embodiments, more than one set of spacers is formed adjacent to the metal gate stacks 122A and 122B, e.g., sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers. In such embodiments, each set of spacers may comprise materials with different etch rates. For example, a first dielectric layer comprising silicon and oxygen (e.g., silicon oxide) may be deposited on substrate 110 and subsequently anisotropically etched to form a first set of spacers adjacent to metal gate stacks 122A, 122B (or, in some embodiments, dummy metal gate stacks). A second dielectric layer comprising silicon and nitrogen (e.g., silicon nitride) may be deposited on substrate 110 and subsequently anisotropically etched to form a second set of spacers adjacent to the first set of spacers. Depending on the design requirements of IC device 100, implantation, diffusion, and / or annealing processes may be performed before and / or after forming gate spacers 126A, 126B to form lightly doped source and drain (LDD) features and / or heavily doped source and drain (HDD) features in substrate 110.

[0022] Epitaxial source and drain features (referred to as epitaxial source / drain features), such as epitaxial source / drain features 130A and 130B, are disposed in the source / drain region of substrate 110. In some embodiments, semiconductor material is epitaxially grown on and / or from substrate 110 to form epitaxial source / drain features 130A, 130B over the source / drain region of substrate 110. In some embodiments, an etching process is performed on the source / drain region of substrate 110 to form source / drain trenches, wherein epitaxial source / drain features 130A, 130B are grown to fill the source / drain trenches. In some embodiments, where substrate 110 represents part of a fin structure, depending on the design requirements of IC device 100, epitaxial source / drain features 130A, 130B enclose the source / drain region of the fin structure and / or are disposed in the source / drain trenches of the fin structure. The epitaxial process can be implemented using CVD deposition techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process can use gaseous and / or liquid precursors that interact with the composition of the substrate 110. Epitaxial source / drain features 130A, 130B are doped with n-type and / or p-type dopants. In some embodiments, epitaxial source / drain features 130A, 130B are epitaxial layers comprising silicon and / or carbon, wherein the silicon-complementing epitaxial layer or the silicon-carbon-complementing epitaxial layer is doped with phosphorus, other n-type dopants, or combinations thereof. In some embodiments, epitaxial source / drain features 130A, 130B are epitaxial layers comprising silicon and germanium, wherein the silicon- and germanium-damaging epitaxial layer is doped with boron, other p-type dopants, or combinations thereof. In some embodiments, the epitaxial source / drain features 130A, 130B include materials and / or dopants that achieve desired tensile and / or compressive stresses in the channel region. In some embodiments, the epitaxial source / drain features 130A, 130B are doped during deposition by adding impurities to the source material of the epitaxial process. In some embodiments, the epitaxial source / drain features 130A, 130B are doped by an ion implantation process after the deposition process. In some embodiments, an annealing process is performed to activate the dopants in the epitaxial source / drain features 130A, 130B and / or other source / drain regions (e.g., HDD regions and / or LDD regions) of the IC device 100.

[0023] Isolation features, such as isolation feature 135, can be formed on and / or in substrate 110 to isolate various regions of IC device 100 (e.g., device regions). For example, isolation feature 135 defines active device regions and / or passive device regions and electrically isolates them from each other. Isolation feature 135 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or combinations thereof. Isolation feature 135 can include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or localized oxidation of silicon (LOCOS) structures. In some embodiments, isolation feature 135 is formed by etching trenches in substrate 110 and filling the trenches with an insulating material (e.g., using CVD or spin-coating glass processes). A chemical mechanical polishing (CMP) process can be performed to remove excess insulating material and / or planarize the top surface of the isolation feature. In some embodiments, the isolation feature 135 can be formed by depositing an insulating material on the substrate 110 and etching back the insulating material layer after the fin structure has been formed (in some embodiments, such that an insulating material layer fills the gaps (trenches) between the fin structures). In some embodiments, the isolation feature 135 includes a multilayer structure that fills the trenches, such as a bulk dielectric layer disposed on a pad dielectric layer, wherein the bulk dielectric layer and the pad dielectric layer comprise materials depending on design requirements (e.g., a bulk dielectric layer of silicon nitride disposed on a liner dielectric layer comprising thermal oxides). In some embodiments, the isolation feature 135 includes a dielectric layer disposed on a doped liner layer (including, for example, borosilicate glass (BSG) or phosphosilicate glass (PSG)).

[0024] CESL 140 is disposed over the following components: substrate 110; gate structures 120A, 120B (specifically, along the sidewalls of gate spacers 126A, 126B); epitaxial source / drain features 130A, 130B; and isolation feature 135. ILD layer 142 is disposed over CESL 140. ILD layer 142 includes a dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS) oxide, PSG, BPSG, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Low-k dielectric materials generally refer to dielectric materials having a low dielectric constant relative to silicon dioxide. For example, a low-k dielectric material has a dielectric constant less than about 3.9. In some examples, a low-k dielectric material has a dielectric constant less than about 2.5, which may be referred to as an ultra-low-k dielectric material. Exemplary low-k dielectric materials include fluorosilicone glass (FSG), carbon-doped silicon oxide, (Applied Materials, Santa Clara, California), degel, aerogel, amorphous fluorocarbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In the depicted embodiments, ILD layer 142 comprises a low-k dielectric material and is generally referred to as a low-k dielectric layer. CESL 140 comprises a material different from ILD layer 142, such as a dielectric material different from the dielectric material of ILD layer 142. ILD layer 142 and / or CESL 140 may comprise a multilayer structure having multiple dielectric materials. In the depicted embodiments, ILD layer 142 comprises silicon and oxygen (e.g., SiCOH, SiO2). X The CESL 140 comprises silicon and nitrogen and / or carbon (e.g., SiN, SiCN, SiCON, SiON, SiC, and / or SiCO) (and may therefore be referred to as a silicon nitride layer). The ILD layer 142 and / or CESL 140 are formed on the substrate 110 by a deposition process, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, other suitable methods, or combinations thereof. In some embodiments, the ILD layer 142 is formed by a flowable CVD (FCVD) process, which includes, for example, depositing a flowable material on the substrate 110 and converting the flowable material into a solid material using suitable techniques (e.g., thermal annealing and / or treating the flowable material with ultraviolet radiation). After depositing ILD layer 142 and / or CESL 140, CMP process and / or other planarization process are performed so that ILD layer 142, CESL 140 and / or gate structures 120A, 120B have substantially flat surfaces.

[0025] Go to Figure 3The MOL process begins with the formation of device-level contacts, such as metal-polysilicon (MP) contacts (typically referring to contacts to gate structures (e.g., gate structures 120A, 120B)) and metal-to-device (MD) contacts (typically referring to contacts to electrically active regions of IC device 100 (e.g., epitaxial source / drain features 130A, 130B)). Device-level contacts electrically and physically connect IC device features to local contacts (interconnects), which will be further described below. Device-level contacts can be collectively referred to as the device-level contact layer disposed on substrate 110. Forming device-level contacts may include: forming a CESL 150 over ILD layer 142, CESL 140, and gate structures 120A, 120B; forming an ILD layer 152 over CESL 150; and forming source / drain contacts 160 (i.e., device-level contacts) extending through ILD layer 152, CESL 150, ILD layer 142, and CESL 140 to physically contact epitaxial source / drain features 130A. CESL 150 is similar to CESL 140, and ILD layer 152 is similar to ILD layer 142. Therefore, CESL 150 and / or ILD layer 152 can be configured and formed as described above with reference to CESL 140 and ILD layer 142. For example, CESL 150 may include silicon and nitrogen and / or carbon (e.g., SiN, SiCN, SiCON, SiON, SiC, and / or SiCO) (and may therefore be referred to as a silicon nitride layer), and ILD layer 152 may include silicon and oxygen (e.g., SiCOH, SiO) X(or other materials including silicon and oxygen) (therefore it may be referred to as a silicon oxide layer or oxide layer). The source / drain contact 160 includes a contact barrier layer 162 and a contact bulk layer 164 disposed on the contact barrier layer 162. The contact barrier layer 162 includes a material that promotes adhesion between the surrounding dielectric material (here, CESL 140, ILD layer 142, CESL 150, and / or ILD layer 152) and the contact bulk layer 164. The material of the contact barrier layer 162 also prevents metallic components from diffusing from the source / drain contact 160 into the surrounding dielectric material. In some embodiments, the contact barrier layer 162 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, palladium, palladium alloy, other suitable components configured to promote and / or enhance adhesion between the metallic material and the dielectric material and / or prevent metallic components from diffusing from the metallic material into the dielectric material, or combinations thereof. For example, contact barrier layer 162 comprises tantalum, tantalum nitride, aluminum tantalum nitride, silicon tantalum nitride, tantalum carbide, titanium, titanium nitride, silicon titanium nitride, aluminum titanium nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium, or combinations thereof. In some embodiments, contact barrier layer 162 comprises multiple layers. For example, contact barrier layer 162 may include a first sublayer and a second sublayer, the first sublayer comprising titanium and the second sublayer comprising titanium nitride. In another example, contact barrier layer 162 may include a first sublayer and a second sublayer, the first sublayer comprising tantalum and the second sublayer comprising tantalum nitride. Contact body layer 164 comprises tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, low resistivity metal components, alloys thereof, or combinations thereof. In the depicted embodiments, contact body layer 164 comprises tungsten, ruthenium, and / or cobalt. In some embodiments, the source / drain contact 160 does not include a contact barrier layer 162 (i.e., the source / drain contact 160 is unobstructed), such that the contact body layer 164 is in physical contact with CESL 140, ILD layer 142, CESL 150, and / or ILD layer 152. In some embodiments, the source / drain contact 160 is partially unobstructed, wherein the contact barrier layer 162 is disposed between only a portion of the contact body layer 164 and the dielectric layer. In some embodiments, the contact body layer 164 comprises multiple layers.

[0026] Forming the source / drain contact 160 may include: performing photolithography and etching processes (e.g., as described herein) to form contact openings extending through ILD layer 152, CESL 150, ILD layer 142, and / or CESL 140 to expose the epitaxial source / drain features 130A; performing a first deposition process to form a contact barrier material that partially fills the contact openings over ILD layer 152; and performing a second deposition process to form a contact body material over the contact barrier material, wherein the contact body material fills the remainder of the contact openings. In such an embodiment, the contact barrier material and the contact body material are disposed in the contact openings and over the top surface of ILD layer 152. The first and second deposition processes may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods, or combinations thereof. In some embodiments, the contact barrier layer 162 has a substantially uniform thickness along the sidewalls and bottom of the contact opening. The contact barrier layer 162 can therefore be formed by a conformal deposition process. In some embodiments, a silicide layer is formed over the epitaxial source / drain feature 130A prior to the formation of the contact barrier material (e.g., by depositing a metal layer over the epitaxial source / drain feature 130A and heating the IC device 100 to cause the epitaxial source / drain feature 130A to react with the metal components of the metal layer). In some embodiments, the silicide layer comprises a metal component (e.g., nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, zirconium, other suitable metals, or combinations thereof) and the composition of the epitaxial source / drain feature 130A (e.g., silicon and / or germanium). A CMP process and / or other planarization processes are performed to remove, for example, excess contact body material and contact barrier material from the top surface of the ILD layer 152, thereby obtaining the source / drain contact 160 (in other words, obtaining the contact barrier layer 162 and contact body layer 164 filling the contact opening). The CMP process planarizes the top surface of the source / drain contact 160, such that in some embodiments, the top surface of the ILD layer 152 and the top surface of the source / drain contact 160 form a substantially flat surface.

[0027] Transfer to Figures 4 to 16The MOL process continues, forming a local contact (interconnect) layer above the device-level contact layer, wherein the local contact layer is configured to exhibit lower capacitance and / or resistance than a conventional local contact layer. The local contact layer includes local contacts that physically and electrically connect the device-level contacts to the first metallization (routing) layer of the multilayer interconnect (MLI) feature of the IC device 100. The local contact layer may be referred to as the metal zero (M0) layer, and the metal contacts (also referred to as metal lines) of the local contact layer may be referred to as M0 contacts / lines. As further described below, the first metallization layer includes metal lines and vias, wherein the vias physically and electrically connect the local contacts to the metal lines. The metal lines of the first metallization layer may be collectively referred to as the metal one (M1) layer (and each referred to as an M1 metal line), and the vias of the first metallization layer may be collectively referred to as the via zero (V0) layer (and each referred to as a V0 via). The V0 layer is the bottommost via layer of the MLI feature. Therefore, the MOL interconnect structure typically refers to the device-level contacts of the device-level contact layer and the local contacts of the local contact layer, which, together, form a BEOL interconnect structure (e.g., a metal line disposed over a via, wherein the via connects the local contacts to the metal line) that connects an IC feature such as an epitaxial source / drain feature 130A to a first metallization layer. The MLI feature electrically couples various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures and / or source / drain features) of the IC feature 100, enabling the various devices and / or components to operate according to the design requirements of the IC device 100. During operation of the IC device 100, the device-level contact layer, local contact layer, first metallization layer, and / or other metallization layers of the MLI feature can route signals between the IC device and / or components of the IC device and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to the IC device and / or components of the IC device. In some embodiments, device-level contact layers and / or local contact layers are considered part of the MLI feature.

[0028] Go to Figure 4The MOL process includes: forming an adhesion layer 172 over the ILD layer 152; forming a ruthenium layer 174 over the adhesion layer 172; and forming a mask layer 180 over the ruthenium layer 174. The adhesion layer 172 includes a material that promotes adhesion between the ruthenium layer 174 and the source / drain contacts 160 and / or other underlying local contacts. For example, the adhesion layer 172 includes titanium, titanium alloys, tantalum, tantalum alloys, cobalt, cobalt alloys, ruthenium, ruthenium alloys, molybdenum, molybdenum alloys, other suitable components configured to promote and / or enhance adhesion between the ruthenium layer 174 and the underlying local contacts, or combinations thereof. In the depicted embodiments, the adhesion layer 172 includes titanium and nitrogen, for example, a titanium nitride layer. In some embodiments, the adhesion layer 172 includes titanium, for example, a titanium layer. In some embodiments, the adhesion layer 172 includes multiple layers. For example, the adhesion layer 172 may include a titanium sublayer and a titanium nitride sublayer disposed over the titanium sublayer. The ruthenium layer 174 comprises ruthenium or a ruthenium alloy (e.g., including titanium, tantalum, tungsten, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, low-resistivity metal components, other suitable ruthenium alloy components, alloys thereof, or combinations thereof). In some embodiments, the ruthenium concentration is uniform throughout the ruthenium layer 174. In some embodiments, the ruthenium concentration is graded throughout the ruthenium layer 174, for example, increasing or decreasing along its thickness from the bottom surface of the ruthenium layer 174 near the source / drain contact 160 to the top surface of the ruthenium layer 174 near the mask layer 180. As described below, in some embodiments, the ruthenium concentration in the ruthenium layer 174 has any profile configured to minimize the resistive and / or capacitive contribution from the ruthenium layer 174 in the subsequently formed ruthenium structure. Figure 4 In this configuration, the thickness of the adhesion layer 172 is t1, and the thickness of the ruthenium layer 174 is t2. In some embodiments, the thickness t1 is about 1 nm to about 5 nm. In some embodiments, the thickness t2 is about 10 nm to about 50 nm. In some embodiments, the ratio of thickness t1 to thickness t2 is about 1:2 to about 1:50. The adhesion layer 172 and / or the ruthenium layer 174 are formed by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, other suitable methods, or combinations thereof. In some embodiments, the adhesion layer 172 is deposited on the ILD layer 152 by ALD, and the ruthenium layer 174 is deposited on the adhesion layer 172 by CVD.

[0029] In the depicted embodiments, mask layer 180 includes multiple layers, such as a metal mask layer 182, a dielectric mask layer 184, a metal mask layer 186, and a dielectric mask layer 188. The metal mask layer 182 has a thickness of t3, the dielectric mask layer 184 has a thickness of t4, the metal mask layer 186 has a thickness of t5, and the dielectric mask layer 188 has a thickness of t6. In some embodiments, thicknesses t3, t4, t5, and t6 are from about 10 nm to about 30 nm. Depending on processing and / or design considerations, this disclosure contemplates any configuration or thicknesses t3, t4, t5, and t6 (e.g., one thickness greater than another). The metal mask layers 182 and 186 comprise metals, such as tungsten, titanium, other suitable metals, or combinations thereof. In some embodiments, the metal mask layers 182 and 186 comprise the same material. In some embodiments, the metal mask layers 182 and 186 comprise different materials. In some embodiments, the metal mask layer 182 and / or the metal mask layer 186 is a tungsten layer. In some embodiments, the metal mask layer 182 and / or the metal mask layer 186 is a titanium nitride layer. The dielectric mask layers 184 and 188 comprise silicon, oxygen, nitrogen, carbon, other suitable dielectric components, or combinations thereof. In some embodiments, the dielectric mask layers 184 and 188 comprise the same material. In some embodiments, the dielectric mask layers 184 and 188 comprise different materials. In some embodiments, the dielectric mask layer 184 and / or the dielectric mask layer 188 is a silicon oxide layer. In some embodiments, the dielectric mask layer 184 and / or the dielectric mask layer 188 is a silicon nitride layer. In some embodiments, the dielectric mask layer 184 and / or the dielectric mask layer 188 is a silicon carbide layer. In some embodiments, mask layer 184 and / or mask layer 188 comprising a dielectric are silicon carbonitride layers. In the illustrated embodiments, mask layers 182 and 186 comprising a metal are carbon-doped tungsten (WDC) layers, mask layer 184 comprising a dielectric is a silicon nitride layer, and mask layer 188 comprising a dielectric is a silicon oxide layer. This disclosure contemplates mask layer 180 having any number of materials, compositions, and / or layers suitable for achieving the patterning of ruthenium layer 174 and adhesion layer 172 as described herein, and the formation of contact air spacers.

[0030] Go to Figure 5A patterning process is performed on mask layer 180 to form various openings, such as openings 190A, 190B, 190C, and 190D, extending through mask layer 188, which includes a dielectric material, and mask layer 186, which includes a metal material. Thus, the patterning process partially patternes mask layer 180, specifically patterning mask layer 188, which includes a dielectric material, and mask layer 186, which are hereinafter referred to as patterned dielectric mask layer 188' and patterned metal mask layer 186', respectively. Patterned dielectric mask layer 188' and patterned metal mask layer 186' define local contact patterns (also referred to as metal zero (MO) patterns) to be formed on ILD layer 152 during MEOL processing. For example, openings 190A-190D define the location and dimensions of local contacts (MO contacts) to be formed on the ILD layer 152, such as the widths wa, wb, wc, and wd of the local contacts. In some embodiments, the widths wa, wb, wc, and / or wd are from about 8 nm to about 1,000 nm. In a further description of this example, portions of patterned dielectric mask layers 188' and patterned metal mask layers 186' arranged between openings 190A-190D define the spacing of the local contacts, such as spacings s1, s2, and s3. In some embodiments, spacings s1, s2, and / or s3 are from about 8 nm to about 1,000 nm. In some embodiments, the patterned dielectric mask layers 188' and patterned metal mask layers 186' define the spacing of the local contact patterns. In some embodiments, the spacing P of a local contact pattern typically refers to the sum of the width of the local contact and the spacing between directly adjacent local contacts (e.g., spacing P = width wb + spacing s1) (i.e., the lateral distance between the edges of directly adjacent local contacts). In some embodiments, the spacing P of the local contact pattern is from about 16 nm to about 2,000 nm. In some embodiments, the spacing of the local contact pattern is defined as the lateral distance between the centers of directly adjacent local contacts. In some embodiments, the width, spacing, and / or pitch of the local contact pattern are minimum widths, minimum spacings, and / or minimum pitches, which typically refer to the minimum dimensions that can be fabricated on a wafer using a manufacturing process. For example, the minimum pitch of local contacts is the lateral distance between the centers or edges of two minimum-width local contacts separated by a minimum spacing.

[0031] In some embodiments, the patterning process includes photolithography and / or etching. The photolithography process may include: forming a resist layer over a mask layer 180 (e.g., by spin coating); performing a pre-exposure baking process; performing an exposure process using the mask; performing a post-exposure baking process; and performing a development process. During the exposure process, the resist layer is exposed to radiant energy (e.g., ultraviolet (UV), deep ultraviolet (DUV), or extreme ultraviolet (EUV) light), wherein the mask, depending on its mask pattern and / or mask type (e.g., binary mask, phase-shift mask, or EUV mask), blocks, transmits, and / or reflects radiation to the resist layer, such that an image is projected onto the resist layer corresponding to the mask pattern. Because the resist layer is sensitive to radiant energy, during the development process, depending on the characteristics of the resist layer and the characteristics of the developer used in the development process, the exposed portions of the resist layer undergo chemical changes, and the exposed (or unexposed) portions of the resist layer dissolve. After development, the patterned resist layer comprises a resist pattern corresponding to the mask. The etching process uses a patterned resist layer as an etching mask to remove portions of a mask layer (here, a mask layer 188 comprising a dielectric and a mask layer 186 comprising a metal). In some embodiments, a first etching process uses a patterned resist layer as an etching mask to remove portions of the mask layer 188 comprising a dielectric to form a patterned mask layer 188' comprising a dielectric, and a second etching process uses the patterned resist layer and / or the patterned mask layer 188' comprising a dielectric to remove portions of the mask layer 186 comprising a metal to form a patterned mask layer 186' comprising a metal. The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination of the foregoing. In some embodiments, the etching process is a reactive ion etching (RIE) process. After the etching process, the patterned resist layer is removed, for example, by a resist stripping process or other suitable process. In some embodiments, the patterning process is a multiple patterning process, such as a dual patterning lithography (DPL) process (e.g., lithography-etch-lithography-etch (LELE) process, self-aligned dual patterning (SADP) process), a spacer-dielectric (SID) SADP process, other dual patterning processes, or combinations thereof), a triple patterning process (e.g., lithography-etch-lithography-etch-lithography-etch (LELELE) process, self-aligned triple patterning (SATP) process, other triple patterning processes, or combinations thereof), other multiple patterning processes (e.g., self-aligned quadruple patterning (SAQP) process), or combinations thereof. In some embodiments, the patterning process implements directional self-assembly (DSA) technology. Furthermore, in some embodiments, the exposure process can implement maskless lithography, electron beam writing, and / or ion beam writing to pattern the resist layer.In the depicted embodiments, the patterning process is an SADP process and / or includes EUV lithography and etching processes (i.e., directly patterning the mask layer 180 using a patterned EUV resist layer).

[0032] Go to Figure 6An oxide material 192 is formed on a mask layer 180, filling openings 190A-190D. In some embodiments, the oxide material 192 is deposited via an FCVD process, which includes, for example, depositing a flowable oxide material (e.g., liquid) on an IC device 100 and converting the flowable oxide material into a solid oxide material via an annealing process. The flowable oxide material can flow into openings 190A-190D and conform to the exposed surfaces of the IC device 100, allowing for void-free filling of openings 190A-190D. For example, the FCVD process introduces a silicon precursor and an oxidant (collectively referred to as reactants) into a deposition chamber, where the silicon precursor and oxidant react and condense onto the exposed surfaces of the IC device 100 (e.g., a patterned dielectric mask layer 188') to form the flowable oxide material. In some embodiments, the flowable oxide material is a flowable material comprising silicon and oxygen. In some embodiments, the silicon precursor includes a silazane-based precursor (e.g., polysilazane, silylamine, dimethylsilylamine, dimethylsilane, trimethylsilane, tetramethylsilane, diethylsilane, other suitable silicon-containing precursors, or combinations thereof), and the oxidant includes oxygen (e.g., O2, O3, hydrogen peroxide (H2O2), H2O, other suitable oxygen-containing components, or combinations thereof). In some embodiments, the silicon-containing precursor (e.g., a silazane-based precursor) is introduced into the deposition chamber in a liquid or vapor state. In some embodiments, the oxidant is excited to an ionized state by plasma, such that the oxidant is introduced into the deposition chamber in a plasma state. In some embodiments, the silicon-containing precursor and / or oxidant is mixed with a carrier gas (including, for example, hydrogen, helium, argon, nitrogen, xenon, krypton, neon, other suitable components, or combinations thereof) before or after the silicon-containing precursor is introduced into the deposition chamber. In the depicted embodiments, the annealing process transforms the flowable silicon and oxygen material into a silicon and oxygen-containing layer, such as a silicon oxide layer. The oxide material 192 can therefore be referred to as a silicon oxide layer. In some embodiments, the annealing process is thermal annealing, which heats the IC device 100 to a temperature that facilitates the conversion of the flowable oxide material into a solid oxide material. In some embodiments, the annealing process exposes the flowable oxide material to UV radiation. In some embodiments, the oxide material 192 is deposited using a high aspect ratio deposition (HARP) process. The HARP process can realize TEOS precursors and O3 precursors. In some embodiments, the oxide material 192 is deposited using HDPCVD, which can realize SiH4 precursors and O2 precursors. This disclosure contemplates implementing other deposition processes and / or precursors to form the oxide material 192.

[0033] The deposition process fills openings 190A-190D. The thickness of the oxide material 192 is therefore greater than the sum of the thickness t6 of the patterned mask layer 188' (including dielectric) and the thickness t5 of the patterned mask layer 186' (including metal). [Go to...] Figure 7 A CMP process and / or other planarization process are performed on the oxide material 192 to reduce the thickness of the oxide material 192. A patterned metal-including mask layer 186' can be used as a planarization (e.g., CMP) stop layer, such that the CMP process is performed until the patterned metal-including mask layer 186' is reached and exposed. Therefore, the CMP process removes the patterned dielectric-including mask layer 188' and any oxide material 192 disposed on the top surface of the patterned metal-including mask layer 186'. The remaining oxide material 192 forms oxide features 192A, 192B, 192C, and 192D. Oxide features 192A-192D are embedded within the patterned metal-including mask layer 186', forming a portion of mask layer 180, and can be collectively referred to as the patterned oxide layer. In some embodiments, the CMP process planarizes the top surfaces of oxide features 192A-192D and the patterned metal-included mask layer 186', such that the top surfaces of oxide features 192A-192D and the patterned metal-included mask layer 186' are substantially planar. In some embodiments, the thickness of oxide features 192A-192D is substantially equal to the thickness t5 of the patterned metal-included mask layer 186'. In some embodiments, the thickness of oxide features 192A-192D is less than or greater than the thickness t5 of the patterned metal-included mask layer 186'. In some embodiments, an annealing process is performed after CMP to further cure and / or densify oxide features 192A-192D.

[0034] Go to Figure 8 The patterned metal-containing mask layer 186' is selectively removed from mask layer 180, leaving oxide features 192A-192D of local contact patterns defined on mask layer 184, which includes a dielectric. Each of oxide features 192A-192D corresponds to a corresponding one of openings 190A-190D, and therefore each of oxide features 192A-192D corresponds to a local contact to be formed for IC device 100. Figure 8In the process, oxide features 192A-192D have widths wa, wb, wc, and wd, respectively, and are spaced between them by intervals s1, s2, and s3. In some embodiments, the etching process is configured to selectively remove the patterned metal-containing mask layer 186' relative to oxide features 192A-192B and the dielectric-containing mask layer 184. In other words, the etching process substantially removes the patterned metal-containing mask layer 186', but does not remove or substantially does not remove oxide features 192A-192D and the dielectric-containing mask layer 184. In the depicted embodiment, an etchant is selected for the etching process that etches the tungsten-containing material (i.e., the patterned metal-containing mask layer 186') at a higher rate than the etching rate of the oxide material (i.e., oxide features 192A-192D) and silicon nitride (i.e., the dielectric-containing mask layer 184) (i.e., the etchant has high etch selectivity with respect to the tungsten-containing material). In some embodiments, an etchant is selected for the etching process, which etches a metallic material (i.e., a patterned metallic mask layer 186') at a higher rate than etching a dielectric material (i.e., oxide features 192A-192D and / or a mask layer 184 comprising a dielectric) (i.e., the etchant has high etching selectivity with respect to the metallic material). The etching process is a dry etching process, a wet etching process, or a combination thereof.

[0035] Go to Figure 9The oxide features 192A-192D are used as etching masks to perform an etching process on a mask layer 184 including a dielectric. For example, the etching process removes portions of the mask layer 184 including a dielectric that are not covered by the oxide features 192A-192D (i.e., exposed portions of the mask layer 184 including a dielectric), thereby leaving mask features 184A, 184B, 184C, and 184D (collectively referred to as the patterned mask layer 184' including a dielectric) under the oxide features 192A-192D. The etching process is configured to selectively remove the mask layer 184 including a dielectric relative to the mask layer 182 including a metal. In other words, the etching process substantially removes the mask layer 184 including a dielectric, but does not remove or substantially does not remove the mask layer 182 including a metal. For example, an etchant is selected for the etching process that etches the silicon nitride material (i.e., the mask layer 184 including the dielectric) at a higher rate than etching the tungsten-containing material (i.e., the mask layer 182 including the metal) (i.e., the etchant has high etch selectivity with respect to the silicon nitride material). In some embodiments, the etching process is also configured to selectively remove the mask layer 184 including the dielectric with respect to oxide features 192A-192D. In other words, the etching process may also substantially remove the mask layer 184 including the dielectric, but not remove or substantially not remove the oxide features 192A-192D. For example, an etchant is selected for the etching process that also etches the silicon nitride material (i.e., the mask layer 184 including the dielectric) at a higher rate than etching the oxide material (i.e., oxide features 192A-192D). In some embodiments, the etch selectivity of the etchant used on the dielectric mask layer 184 above the metal mask layer 182 is greater than the etch selectivity of the etchant used on the dielectric mask layer 184 above the oxide features 192A-192D. In such embodiments, the etching process may partially etch the oxide features 192A-192D, as shown. In some embodiments, the etching process may not uniformly etch the oxide features 192A-192D, such that the oxide features 192A-192D have different thicknesses above the dielectric mask features 184A-184D. In some embodiments, after the etching process, the thickness of one or more oxide features 192A-192D is less than the thickness t6. In some embodiments, one or more oxide features 192A-192D are completely removed by the etching process. In some embodiments, an etchant is selected for the etching process that etches a dielectric material (i.e., a dielectric mask layer 184) at a higher rate than etching a metallic material (i.e., a mask layer 182 including a metal) (i.e., the etchant has high etch selectivity with respect to the dielectric material).Etching processes include dry etching, wet etching, or a combination thereof.

[0036] Go to Figure 10The patterned dielectric mask layer 184' (and / or, in some embodiments, oxide features 192A-192D) is used as an etching mask to perform an etching process on the metal mask layer 182, the ruthenium layer 174, and the adhesion layer 172. For example, the etching process removes the portion of the metal mask layer 182 not covered by the patterned dielectric mask layer 184' (i.e., the exposed portion of the metal mask layer 182), thereby leaving metal mask features 182A, 182B, 182C, and 182D (collectively referred to as the patterned metal mask layer 182') under the dielectric mask features 184A-184D. The etching process also removes the unpatterned portions of the ruthenium layer 174 and the adhesive layer 172 covered by the dielectric mask layer 184' (i.e., the exposed portions of the ruthenium layer 174 and the adhesive layer 172) to form ruthenium structures 200A (including ruthenium plug 174A and adhesive layer 172A), ruthenium structures 200B (including ruthenium plug 174B and adhesive layer 172B), ruthenium structures 200C (including ruthenium plug 174C and adhesive layer 172C), and ruthenium structures 200D (including ruthenium plug 174D and adhesive layer 172D). Ruthenium structures 200A-200D may alternatively be referred to as ruthenium contacts, ruthenium MO structures, ruthenium-containing contacts, ruthenium partial contacts, or combinations thereof. The etching process is configured to selectively remove the metal-containing mask layer 182, ruthenium layer 174, and adhesion layer 172 relative to the patterned dielectric mask layer 184'. In other words, the etching process substantially removes the metal-containing mask layer 182, ruthenium layer 174, and adhesion layer 172, but does not remove or substantially does not remove the patterned dielectric mask layer 184'. For example, an etchant is selected for the etching process to etch the metal material (i.e., the metal-containing mask layer 182, ruthenium layer 174, and adhesion layer 172) at a higher rate than etching the silicon nitride material (i.e., the patterned dielectric mask layer 184') (i.e., the etchant has high etching selectivity with respect to the metal material). In some embodiments, the etching process is also configured to selectively remove oxide features 192A-192D relative to the patterned dielectric mask layer 184'. In other words, the etching process can also substantially remove oxide features 192A-192D, but does not remove or substantially does not remove the patterned mask layer 184', which includes the dielectric. For example, an etchant is selected for the etching process that also etches the oxide material (i.e., oxide features 192A-192D) at a higher rate than etching the silicon nitride material (i.e., the patterned mask layer 184', which includes the dielectric).In some embodiments, the etchant exhibits greater etch selectivity for the metal mask layer 182, ruthenium layer 174, and adhesion layer 172 (compared to the dielectric mask layer 184) than for the oxide features 192A-192D (compared to the patterned dielectric mask layer 184'). In such embodiments, the etching process may etch one or more oxide features 192A-192D. For example, in the depicted embodiment, the etching process completely removes oxide features 192A-192C and further reduces the thickness of oxide feature 192D. The etching process is a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process includes multiple steps, such as a first etching step selectively etching the metal mask layer 182, a second etching step selectively etching the ruthenium layer 174, and a third etching step selectively etching the adhesion layer 172 (e.g., the first, second, and third etching steps employ different etchants). In another example, various parameters of the etching process (e.g., etchant flow rate and / or etchant concentration) are adjusted to achieve different etch selectivity throughout the etching process, such that the etching process selectively and individually etches the mask layer 182, ruthenium layer 174, and adhesive layer 172 comprising metal. In some embodiments, the etching process is implemented with an etchant having minimum to no etch selectivity among the mask layer 182, ruthenium layer 174, and / or adhesive layer 172 comprising metal.

[0037] Go to Figure 11A dummy contact spacer layer 210 (also referred to as a spacer layer) is formed on the ruthenium structures 200A-200D and the remainder of the mask layer 180 (e.g., oxide features 192D, mask features 184A-184D including dielectrics, and / or mask features 182A-182D including metals) using an appropriate deposition process (e.g., CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof) using an appropriate deposition process (e.g., CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof). The thickness t7 of the dummy contact spacer layer 210 is substantially uniform along the sidewalls of the ruthenium structures 200A-200D, the top surface and sidewalls of the remainder of the mask layer 180, and the top surface of the ILD layer 152. However, this disclosure contemplates embodiments in which the thickness t7 of the dummy contact spacer layer 210 varies, for example, a tapered thickness along the sidewalls of the ruthenium structures 200A-200D. In some embodiments, the thickness t7 is from about 1 nm to about 8 nm. In some embodiments, the thickness t7 along the sidewalls of the ruthenium structures 200A-200D is tailored to define the dimensions of the contact air spacers (gap) for the ruthenium structures 200A-200D. For example, the parameters of the deposition process are adjusted to ensure that the thickness t7 is approximately the target width of the contact air spacers for the ruthenium structures 200A-200D.

[0038] The dummy contact spacer layer 210 comprises a material different from that of the ruthenium structures 200A-200D and the subsequently formed ILD layer to achieve etch selectivity during subsequent etching processes (e.g., those used to form contact air spacers for the ruthenium structures 200A-200D). In other words, the dummy contact spacer layer 210 and the surrounding layers comprise materials with different etch sensitivities to a given etchant. For example, the dummy contact spacer layer 210 comprises a material whose etch rate to an etchant is greater than that to the ruthenium structures 200A-200D (here, ruthenium plugs 174A-174D and adhesion layers 172A-172D) and the subsequently formed ILD layer. The dummy contact spacer layer 210 comprises silicon, germanium, metal, oxygen, nitrogen, carbon, other suitable components, or combinations thereof. In the depicted embodiment, the dummy contact spacer layer 210 is an amorphous silicon layer. In some embodiments, the dummy contact spacer layer 210 is an amorphous carbon layer. In some embodiments, the dummy contact spacer layer 210 is a silicon layer, a germanium layer, or a silicon-germanium layer, which may be doped with a suitable dopant to achieve etch selectivity. In some embodiments, the dummy contact spacer layer 210 is a polycrystalline silicon layer. In some embodiments, the dummy contact spacer layer 210 comprises a metal and oxygen, wherein the metal may include aluminum, hafnium, titanium, copper, manganese, vanadium, other suitable metals, or combinations thereof. For example, the metal is titanium, and the dummy contact spacer layer 210 is a titanium oxide layer. In some embodiments, the dummy contact spacer layer 210 is a dielectric layer, such as a silicon nitride layer or a silicon carbonitride layer. In some embodiments, a dopant (e.g., a p-type dopant, an n-type dopant, or a combination thereof) is introduced into the dummy contact spacer material such that the dummy contact spacer layer 210 comprises a doped material. In some embodiments, the dummy contact spacer layer 210 is a BSG layer or a PSG layer. In some embodiments, the dummy contact spacer layer 210 is, for example, a low-density silicon nitride layer relative to the subsequently formed CESL (which may be configured as a high-density silicon nitride layer). In some embodiments, the dummy contact spacer layer 210 is, for example, a low-density silicon oxide layer relative to the subsequently formed ILD layer (which may be configured as a high-density silicon oxide layer). The degree of density used to achieve "high density" and "low density" can be configured to achieve the etch selectivity required for subsequent etching processes.

[0039] Go to Figure 12 and Figure 13 The process continues, forming the ILD layer 220 of the IC device 100. For example, in Figure 12In this embodiment, a dielectric material 220' is formed on the dummy contact spacer layer 210. The dielectric material 220' and the dummy contact spacer layer 210 fill the space between the ruthenium structures 200A-200D. In the illustrated embodiment, the dielectric material 220' covers the dummy contact spacer layer 210, the ruthenium structures 200A-200D, and the mask layer 180. Therefore, the thickness of the dielectric material 220' is greater than the sum of the thickness t7 of the dummy contact spacer layer 210, the thickness of the ruthenium structures 200A-200D (e.g., the sum of thicknesses t1 and t2), and the thickness of the mask layer 180 (e.g., the sum of thicknesses t3 and t4). The dielectric material 220' includes a dielectric material (and therefore the ILD layer 220 includes a dielectric material), which includes, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS, PSG, BSG, BPSG, FSG, etc. (Applied Materials, Santa Clara, California), degel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric materials, SiLK (Dow Chemical, Midland, Michigan), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, dielectric material 220' comprises a low-k dielectric material. In some embodiments, dielectric material 220' comprises an ELK dielectric material, such as porous silica, silicon carbide, and / or carbon-doped oxides (e.g., SiCOH-based materials (e.g., having Si-CH3 bonds)), wherein each is tuned / configured to exhibit a dielectric constant of less than about 2.5. In the depicted embodiments, dielectric material 220' comprises silicon and oxygen (e.g., SiCOH, SiO2). X (or other materials including silicon and oxygen) (and thus may be referred to as a silicon oxide layer or oxide layer). The dielectric material 220' is formed by a deposition process, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, other suitable methods, or combinations thereof. In some embodiments, the dielectric material 220' is formed by an FCVD process, for example, the FCVD process described above with reference to oxide material 192'. For example, a flowable silicon and oxygen material is converted into a silicon and oxygen-containing layer, such as a silicon oxide layer. In some embodiments, the dielectric material 220' is formed by a HARP process, for example, the HARP process described above with reference to oxide material 192'. In some embodiments, the dielectric material 220' is formed by HDPCVD, for example, the HDPCVD described above with reference to oxide material 192'.

[0040] Go to Figure 13CMP and / or other planarization processes are performed on dielectric material 220'. As shown, the remainder of dielectric material 220' after the CMP process forms an ILD layer 220, in which ruthenium structures 200A-200D are embedded. A patterned metal-included mask layer 182' can be used as a CMP stop layer, such that the CMP process is performed until the patterned metal-included mask layer 182' is reached and exposed. Therefore, the CMP process removes portions of dielectric material 220', portions of dummy spacer layer 210, any remaining portions of oxide features 192A-192D (in this case, oxide feature 192D), and mask features 184A-184B including dielectric material disposed on the top surface of the patterned metal-included mask layer 182'. The CMP process can planarize the top surface of the ILD layer 220, the top surface of the dummy contact spacer layer 210, and the top surface of the mask features 182A-182D including metal, such that in some embodiments, after the CMP process, the top surfaces of the ILD layer 220, the dummy contact spacer layer 210, and the mask features 182A-182D including metal are substantially planar. In some embodiments, an annealing process is performed after CMP to further cure and / or densify the ILD layer 220.

[0041] Go to Figure 14The patterned metal-complementary mask layers 182' (i.e., metal-complementary mask features 182a-182d) are removed from the ruthenium structures 200A-200D to form a recess (trench) 225 having sidewalls defined by the dummy contact spacer layer 210 and a bottom defined by the top surface of the ruthenium structures 200A-200D. The top surface of the ruthenium structures 200A-200D is recessed from the top surface of the ILD layer 220 by a distance d, or in other words, the depth of the recess 225 is approximately the distance d. In some embodiments, the distance d is from about 1 nm to about 20 nm. In some embodiments, the etching process is configured to selectively remove the patterned metal-complementary mask layers 182' relative to the ruthenium structures 200A-200D, the dummy contact spacer layer 210, and the ILD layer 220. In other words, the etching process essentially removes the patterned, metal-containing mask layer 182', but does not remove or substantially does not remove the ruthenium structures 200A-200D, the dummy contact spacer layer 210, and the ILD layer 220. In the illustrated embodiment, an etchant is selected for the etching process that etches the tungsten-containing material (i.e., the patterned, metal-containing mask layer 182') at a higher rate than the etching rate of the ruthenium-containing material (i.e., the ruthenium plugs 174A-174D), the amorphous silicon material (i.e., the dummy contact spacer layer 210), and the oxide material (i.e., the ILD layer 220) (i.e., the etchant has high etch selectivity with respect to the tungsten-containing material). The etching process is a dry etching process, a wet etching process, or a combination thereof.

[0042] Go to Figure 15An etching process is performed to selectively remove the dummy contact spacer layer 210 and form an air gap 230 for the ruthenium structures 200A-200D. The air gap 230 is defined between the ILD layer 220 and the sidewalls of the ruthenium structures 200A-200D. In the depicted embodiment, the air gap 230 has a bottom defined by the ILD layer 152 and sidewalls defined by the ILD layer 220. In some embodiments, such as those shown, the sidewalls of the air gap 230 are also defined by portions of the dummy contact spacer layer 210 retained between the ILD layer 152 and the ILD layer 220. Therefore, the air gap 230 is arranged along the sidewalls of the ruthenium structures 200A-200D and extends through the ILD layer 220 and the dummy contact spacer layer 210 to the ILD layer 152, such that the air gap 230 surrounds the ruthenium structures 200A-200D. The air gap 230 has a width w defined along the x-direction. In the depicted embodiments, the width w is substantially the same as the thickness t7 of the removed dummy contact spacer layer 210. In some embodiments, the width w is from about 1 nm to about 8 nm. The etching process is configured to selectively remove the dummy contact spacer layer 210 relative to the ILD layer 220 and the ruthenium structures 200A-200B. In other words, the etching process substantially removes the dummy contact spacer layer 210, but does not remove or substantially does not remove the ILD layer 220 and / or the ruthenium structures 200A-200D. For example, an etchant is selected for the etching process that etches the amorphous silicon material (i.e., the dummy contact spacer layer 210) at a higher rate than materials comprising metals (e.g., ruthenium structures 200A-200D) and oxide materials (e.g., ILD layer 220) (i.e., the etchant has high etch selectivity with respect to the amorphous silicon material). The etching process is a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the dry etching process implements an etching gas comprising Cl2, NF3, O2, H2, CH4, or a combination thereof, wherein the composition of the etching gas depends on the composition of the dummy contact spacer layer 210, the ruthenium structures 200A-200D, and the ILD layer 220. In some embodiments, the dry etching process is configured to generate plasma from any etching gas disclosed herein, such that the dry etching uses plasma-excited material to remove the dummy contact spacer layer 210. In some embodiments, the wet etching process implements a wet etchant solution configured to selectively remove the dummy contact spacer layer 210, wherein the composition of the wet etchant solution depends on the composition of the dummy contact spacer layer 210, the ruthenium structures 200A-200D, and the ILD layer 220.

[0043] Because the dielectric constant of air is approximately one (k≈1), which is lower than that of insulating materials conventionally used for interconnect structures (e.g., silicon oxide or silicon nitride), the air gap 230 reduces the capacitance between the ruthenium structures 200A-200D, the capacitance between the ruthenium structures 200A-200D and device-level contacts (e.g., device-level contacts 160), and / or the capacitance between the ruthenium structures 200A-200D and the subsequently formed BEOL interconnect structure (e.g., vias and metal wires). In some embodiments, the MOL interconnect structure with the ruthenium structures 200A-200D surrounded by the air gap 230 reduces parasitic capacitance by up to 10% compared to an MOL interconnect structure with ruthenium structures 200A-200D without an air gap. Furthermore, because the disclosed MOL interconnect structure uses ruthenium (i.e., ruthenium structures 200A-200D) instead of copper, the MOL interconnect structure with ruthenium structures 200A-200D exhibits lower resistance than conventional MOL interconnect structures and promotes improved current flow. As a result, the disclosed MOL interconnect structure, which includes ruthenium structures 200A-200D surrounded by an air gap 230, significantly reduces the parasitic capacitance, parasitic resistance, and associated RC delay of the IC device 100.

[0044] Go to Figure 16 and Figure 17 The BEOL process begins with the formation of the first metallization layer (i.e., the V0 layer and the M1 layer) that features the MLI characteristic. Figure 16In this process, a CESL 240 is formed on a local contact layer (or MO layer) (e.g., ILD layer 220, ruthenium structures 200A-200D, and air gap 230) using a suitable deposition process, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods, or combinations thereof. The thickness t8 of the CESL 240 is less than the depth of the groove 225, such that the thickness t8 is less than a larger distance d. In some embodiments, the thickness t8 is from about 1 nm to about 15 nm. The CESL 240 comprises a material different from that of the ruthenium plugs 174A-174D and the subsequently formed ILD layer to achieve etch selectivity during subsequent etching processes (e.g., processes for forming one or more via openings that expose one or more ruthenium structures 200A-200D). In other words, CESL 240 and the surrounding layers will comprise materials with different etch sensitivities to a given etchant. For example, CESL 240 comprises a material whose etch rate to the etchant differs from that of the material of the ILD layer, such that the material of CESL 240 acts as an etch stop layer during etching of the overlying ILD layer (e.g., comprising a low-k dielectric material). In some embodiments, CESL 240 comprises a metal and oxygen, and may therefore be referred to as a metal oxide CESL. The metal may include aluminum, hafnium, titanium, copper, manganese, vanadium, other suitable metals, or combinations thereof. In the depicted embodiment, the metal is aluminum, and CESL 240 is aluminum oxide (Al₂O₃). X CESL.

[0045] exist Figure 17 In this process, an ILD layer 250 is formed on top of CESL 240. The ILD layer 250 fills the remainder of the recess 225 such that a portion of the ILD layer 250 extends below the top surface of the ILD layer 220. The ILD layer 250 includes a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS, PSG, BSG, BPSG, FSG, etc. (Applied Materials, Santa Clara, California), degel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric materials, SiLK (Dow Chemical, Midland, Michigan), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, ILD layer 250 comprises a low-k dielectric material. In some embodiments, ILD layer 250 comprises an ELK dielectric material, such as porous silica, silicon carbide, and / or carbon-doped oxides (e.g., SiCOH-based materials (e.g., having Si-CH3 bonds)), wherein each is tuned / configured to exhibit a dielectric constant of less than about 2.5. In the depicted embodiments, ILD layer 250 comprises silicon and oxygen (e.g., SiCOH, SiO2). X (or other materials including silicon and oxygen) (and thus may be referred to as a silicon oxide layer or oxide layer). In some embodiments, the ILD layer 250 may comprise a multilayer structure having a variety of dielectric materials. The ILD layer 250 is formed by a deposition process, such as CVD, FCVD, HARP, HDP, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, other suitable methods, or combinations thereof. A CMP process and / or other planarization processes may be performed after the deposition of the ILD layer 250 to give the ILD layer 250 a substantially flat surface.

[0046] Then, BEOL interconnect structures are formed in ILD layer 250 and CESL 240 (collectively referred to as insulating layers), wherein each BEOL interconnect structure is physically connected to a corresponding local contact of a local contact layer. In the depicted embodiment, BEOL interconnect structure 260 extends through ILD layer 250 and CESL 240 to physically contact ruthenium structure 200B. BEOL interconnect structure 260 includes via 262 and metal line 264, wherein via 262 physically and electrically connects ruthenium structure 200B to metal line 264. Via 262 has a first via portion VO-1 disposed above a second via portion VO-2. The first via portion VO-1 is defined between metal line 264 and the top surface of ILD layer 220 and extends through a portion of ILD layer 250 and CESL 240. The second through-hole portion V0-2 is defined between the top surface of the ILD layer 220 and the top surface of the ruthenium plug 174B, and extends through a portion of the ILD layer 220 to the ruthenium plug 174B. In this configuration, the through-hole 262 physically contacts the top surface of the ILD layer 220 (e.g., the first through-hole portion V0-1 is disposed directly on the top surface of the ILD layer 220) and the sidewalls of the ILD layer 220 (e.g., the second through-hole portion V0-2 is disposed directly on the first and second sidewalls of the ILD layer 220, and the second through-hole portion V0-2 extends from the first sidewall to the second sidewall). The first width of the first through-hole portion V0-1 is greater than the second width of the second through-hole portion V0-2, and the second width of the second through-hole portion V0-2 is greater than the width of the ruthenium plug 174B, such that the second through-hole portion V0-2 seals the air gap 230 surrounding the ruthenium plug 174B. In some embodiments, the second width of the second through-hole portion V0-2 is approximately equal to the sum of the width of the ruthenium plug 174B and the width of the air gap 230 multiplied by two (i.e., the second width of the second through-hole portion V0-2 = the width of the ruthenium plug 174B + (twice the width of the air gap 230)). Therefore, in the depicted embodiment, the air gap 230 has a length defined along the z-direction between the through-hole 262 and the ILD layer 152 (specifically, between the bottom surface of the through-hole 262 and the top surface of the ILD layer 152).

[0047] The BEOL interconnect structure 260 includes a contact barrier layer 270 and contact plugs 272 disposed on the contact barrier layer 270, wherein vias 262 and metal lines 264 each comprise a portion of the contact barrier layer 270 and a portion of the contact plugs 272. The contact barrier layer 270 includes a material that promotes adhesion between the surrounding dielectric material (here, ILD layer 220, CESL 240, and / or ILD layer 250) and the contact plugs 272. The material of the contact barrier layer 270 also prevents metallic components from diffusing from the BEOL interconnect structure 260 into the surrounding dielectric material. In some embodiments, the contact barrier layer 270 comprises titanium, titanium alloys, tantalum, tantalum alloys, cobalt, cobalt alloys, ruthenium, ruthenium alloys, molybdenum, molybdenum alloys, palladium, palladium alloys, other suitable components configured to promote and / or enhance adhesion between the metallic and dielectric materials and / or prevent metallic components from diffusing from the metallic material into the dielectric material, or combinations thereof. For example, contact barrier layer 270 includes tantalum, tantalum nitride, aluminum tantalum nitride, silicon tantalum nitride, tantalum carbide, titanium, titanium nitride, silicon titanium nitride, titanium aluminum nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium, or combinations thereof. In some embodiments, contact barrier layer 270 includes multiple layers. For example, contact barrier layer 270 may include a first sublayer and a second sublayer, the first sublayer including titanium and the second sublayer including titanium nitride. In another example, contact barrier layer 270 may include a first sublayer and a second sublayer, the first sublayer including tantalum and the second sublayer including tantalum nitride. Contact plug 272 includes tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, low resistivity metal components, alloys thereof, or combinations thereof. In the depicted embodiments, contact plug 272 includes a material different from ruthenium plugs 174A-174D. For example, contact plug 272 includes tungsten, cobalt, and / or copper. In some embodiments, the BEOL interconnect structure 260 does not include a contact barrier layer 270 (i.e., the BEOL interconnect structure 260 is unobstructed), such that the contact plug layer 272 is in physical contact with the ILD layer 220, CESL 240, and / or ILD layer 250. In some embodiments, the BEOL interconnect structure 260 is partially unobstructed, wherein the contact barrier layer 270 is disposed between only a portion of the contact plug 272 and the dielectric layer. In some embodiments, the contact plug 272 comprises multiple layers.

[0048] The BEOL interconnect structure 260 can be formed via a dual damascene process, which involves simultaneously depositing conductive materials for via 262 and metal line 264. In such an embodiment, via 262 and metal line 264 share a contact barrier layer 270 and a contact plug 272, rather than each having its own and different contact barrier layer and contact plug (e.g., the contact barrier layer of metal line 264 would separate the metal plug of metal line 264 from the via plug of via 262). In some embodiments, the dual damascene process includes performing a patterning process to form interconnect openings extending through ILD layer 250 and CESL 240, thereby exposing the ruthenium structure 200B and the air gap 230 surrounding the ruthenium structure 200B. The patterning process may include: a first photolithography step and a first etching step for forming trench openings (corresponding to and defining metal lines 264) in the ILD layer 250 for interconnecting openings; a second photolithography step and a second etching step for forming via openings (corresponding to and defining vias 262) in the ILD layer 250 for interconnecting openings that expose a portion of the CESL 240; and a third etching step for removing the exposed portion of the CESL 240, thereby exposing the ruthenium structure 200B, the air gap 230 surrounding the ruthenium structure 200B, and a portion of the top surface of the ILD layer 220. The first photolithography / first etching step and the second photolithography / second etching step may be performed in any order (e.g., trench first, via last, or via first, trench last). The first and second etching steps are both configured to selectively remove the ILD layer 250 relative to the patterned mask layer and CESL 240, while the third etching step is configured to selectively remove CESL 240 relative to ILD layer 250, ILD layer 220, and ruthenium plug 174B. In other words, the first and second etching steps substantially remove ILD layer 250 but do not remove or substantially do not remove CESL 240, while the third etching step substantially removes CESL 240 but does not remove or substantially does not remove ILD layer 250, ILD layer 220, and ruthenium plug 174B. The first, second, and third etching steps can be implemented using dry etching processes, wet etching processes, or combinations thereof. In some embodiments, the first and second etching steps are dry etching processes, while the third etching step is a wet etching process. Note that because the top surface of the ruthenium structure 200B is lower than the top surface of the ILD layer 220, the via openings of the interconnect openings are self-aligned with the ruthenium structure 200B, thereby minimizing (and in some embodiments, eliminating) any via landing problems that may be caused by overlapping displacement of the interconnect openings (e.g., the interconnect openings are undesirably and unintentionally offset to the left or right from the target location used to expose the ruthenium structure 200B).For example, in a conventional interconnect processing embodiment, the top surface of the ruthenium structures 200A-200D will be substantially planar with the top surface of the ILD layer 220. In such an embodiment, when forming the via 262, overlap displacement can cause the via opening of the interconnect opening to shift to the left, or unintentionally expose the ruthenium structure 200A (which can lead to an electrical short circuit) or cause a lateral spacing (e.g., along the x-direction) between the via 262 and the ruthenium structure 200A, which increases the parasitic resistance between the via 262 and the ruthenium structure 200A. Such a lateral spacing can be referred to as a metal-via leakage spacing. In contrast, in the disclosed embodiment, even if the overlap shift causes the interconnect opening to shift to the left relative to the ruthenium structure 200B, the bottom of the via 262 (i.e., the second via portion V0-2) is self-aligned with and confined within the region corresponding to the ruthenium structure 200B, thereby maintaining the required metal-via leakage spacing, and the top of the via 262 (i.e., the first via portion V0-1) is separated from the local contact layer by the ILD layer 220, thereby minimizing the risk of electrical short circuits. This self-aligned via bottom configuration also contributes to improved resistance and capacitance characteristics of the disclosed MOL interconnect structure compared to conventional MOL interconnect structures.

[0049] Following the patterning process, the dual damascene process includes: performing a first deposition process to form a contact barrier material partially filling the interconnect openings on the ILD layer 250, and performing a second deposition process to form a contact body material on the contact barrier material, wherein the contact body material fills the remainder of the interconnect openings. In such an embodiment, the contact barrier material and the contact body material are disposed in the interconnect openings and on the top surface of the ILD layer 250. The first and second deposition processes may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods, or combinations thereof. In some embodiments, the contact barrier layer 270 has a substantially uniform thickness along the sidewalls and bottom of the interconnect openings. The contact barrier layer 270 can therefore be formed by a conformal deposition process. A CMP process and / or other planarization processes are performed to remove, for example, excess contact body material and contact barrier material from above the top surface of the ILD layer 250, thereby obtaining a BEOL interconnect structure 260 (in other words, obtaining a contact barrier layer 270 and contact plugs 272 filling the interconnect openings). The CMP process planarizes the top surface of the BEOL interconnect structure 260 and the ILD layer 250, such that in some embodiments, the top surface of the ILD layer 250 and the top surface of the metal line 264 form substantially flat surfaces. The contact barrier material and contact body material uninterruptedly fill the trench openings and via openings of the interconnect openings, such that the contact barrier layer 270 and contact plugs 272 each extend uninterruptedly and continuously from the metal line 264 to the via 262.

[0050] Go to Figure 18The BEOL process continues to form additional metallization layers (layers) of the MLI feature on top of the first metallization layer. For example, the BEOL process includes forming a second metallization layer (i.e., metal layer 2 (M2) and via layer 1 (V1)), a third metallization layer (i.e., metal layer 3 (M3) and via layer 2 (V2)), a fourth metallization layer (i.e., metal layer 4 (M4) and via layer 3 (V3)), a fifth metallization layer (i.e., metal layer 5 (M5) and via layer 4 (V4)), a sixth metallization layer (i.e., metal layer 6 (M6) and via layer 5 (V5), a seventh metallization layer (i.e., metal layer 7 (M7) and via layer 6 (V6)) up to the topmost metallization layer (i.e., metal layer X (MX) and via layer Y (VY)), where X is the total number of patterned metal line layers of the MLI feature and Y is the total number of patterned via layers of the MLI feature. Each metallization layer includes a patterned metal wire layer and a patterned via layer configured to provide at least one BEOL interconnect structure disposed in an insulating layer 280, the insulating layer 280 including at least one ILD layer and at least one CESL similar to the ILD layer and CESL described herein. For example, a second metallization layer includes a BEOL interconnect structure 290 (having a V1 via and an M2 metal wire, wherein the V1 via connects the M2 metal wire to metal wire 264), a third metallization layer includes a BEOL interconnect structure 292 (having a V2 via and an M3 metal wire, wherein the V2 via connects the M2 metal wire to the M3 metal wire), a fourth metallization layer includes a BEOL interconnect structure 294 (having a V3 via and an M4 metal wire, wherein the V3 via connects the M3 metal wire to the M4 metal wire), and a fifth metallization layer includes a BEOL interconnect structure 296 (having a V4 via and an M4 metal wire). The system comprises five metal lines (where a V4 via connects the M4 metal line to the M5 metal line), a sixth metallization layer comprising a BEOL interconnect structure 298 (with a V5 via and an M6 metal line, where the V5 via connects the M5 metal line to the M6 ​​metal line), a seventh metallization layer comprising a BEOL interconnect structure 300 (with a V6 via and an M7 metal line, where the V6 via connects the M6 ​​metal line to the M7 metal line), and a topmost metallization layer comprising a BEOL interconnect structure 302 (with a VY via and an MX metal line, where the VY via connects the M(X-1) metal line to the MX metal line). BEOL interconnect structures 290-302 are formed by any suitable process (including by the various dual damascene processes described herein) and comprise any suitable materials and / or layers. It should be noted that although the MLI feature of IC device 100 is shown as having a given number of metallization layers disposed within a given number of dielectric layers, this disclosure contemplates that the MLI feature may have more or fewer metal layers, via layers and / or dielectric layers, depending on the design requirements of IC device 100.In some embodiments, the MLI feature has seven to fourteen metallization layers (e.g., M6 to M14 and V6 to V13).

[0051] Figures 19 to 27 This is a partial schematic diagram of part or whole of the various stages (e.g., those associated with method 10 in FIG. 1) of the manufacturing of IC device 400 according to another embodiment of the present disclosure, in the process of manufacturing the MOL interconnect of IC device 400. IC device 400 is similar to IC device 100 in many respects and is manufactured in a similar manner to IC device 100, for example, by Figures 2 to 18 It is manufactured in the manner described herein. Therefore, for clarity and simplicity, Figures 2 to 18 and Figures 19 to 27 Similar features are identified by the same reference numerals. IC device 400 may be included in a microprocessor, memory, and / or other IC device. In some embodiments, IC device 400 is part of an IC chip, a System-on-a-Chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. Various transistors may be planar transistors or non-planar transistors, such as FinFETs or GAA transistors. For clarity, simplified representations are provided. Figures 19 to 27 To better understand the inventive concept of this disclosure. Additional features may be added to IC device 400, and some of the features described below may be replaced, modified, or eliminated in other embodiments of IC device 400.

[0052] Go to Figure 19 IC device 400 has undergone reference Figures 2 to 11 The described process results in the formation of a dummy contact spacer layer 210 (also referred to as a spacer layer) over the ruthenium structures 200A-200D and the remainder of the mask layer 180 (e.g., oxide features 192D, dielectric-containing mask features 184A-184D, and / or metal-containing mask features 182A-182D). Go to Figure 20 , and reference Figures 12 to 18Compared to the described process, before forming the ILD layer 220, dummy contact spacers 210' are formed along the sidewalls of the ruthenium structures 200A to 200D and the remaining portion of the mask layer 180. For example, portions of the dummy contact spacer layer 210 disposed above the top surface of the ILD layer 152 and the top surface of the remaining portion of the mask layer 180 are removed by any suitable process. In some embodiments, the etching process is configured to remove the dummy contact spacer layer 210 disposed on horizontally oriented (e.g., substantially extending along the XY plane) surfaces, but not remove the dummy contact spacer layer 210 from vertically oriented (e.g., substantially extending along the XZ plane and / or YZ plane) surfaces, or remove the dummy contact spacer layer 210 from vertically oriented surfaces with minimal removal. In some embodiments, the etching process is a dry etching process, which can be configured to generate plasma from any etching gas disclosed herein, such that the dry etching removes the dummy spacer layer 210 from above the ILD layer 250 using plasma-excited material, but does not remove the dummy spacer layer 210 from the sidewalls of the ruthenium structures 200A-200D.

[0053] Go to Figure 21 and Figure 22 Then, a dielectric material 220' is formed and processed to form an ILD layer 220 over the dummy contact spacer 210', the top surface of the remaining portion of the mask layer 180, and the top surface of the ILD layer 152, for example, referring to the above. Figure 12 and Figure 13 As described above, because the dummy contact spacer layer 210 is removed from the top surface of the ILD layer 152, the ILD layer 220 is directly disposed on the ILD layer 152 and in physical contact with the ILD layer 152. Figure 22 Therefore, the thickness of ILD layer 220 is approximately equal to the sum of the thicknesses of ruthenium structures 200A-200D (e.g., the sum of thicknesses t1 and t2) and the thickness of the remaining portion of mask layer 180 (e.g., thickness t3). It should also be noted that since the ruthenium structures 200A-200D are formed by depositing a contact layer and then etching the contact layer (rather than forming contact openings within the dielectric layer and depositing the contact layer in the contact openings), IC device 100 does not yet include an etch stop layer between ILD layer 152 and ILD layer 220. [Go to...] Figure 23 The patterned metal-containing mask layer 182' (i.e., the metal-containing mask features 182A-182D) is removed from the ruthenium structure 200A-200D to form a groove 225, as shown above. Figure 14 As stated above. Figure 23In this embodiment, the groove 225 has sidewalls defined by dummy contact spacers 210'. In these embodiments, the etching process is configured to selectively remove the patterned metal-containing mask layer 182' relative to the ruthenium structures 200A-200D, the dummy contact spacer layer 210', and the ILD layer 220. (Go to...) Figure 24 An etching process is performed to selectively remove the dummy contact spacer layer 210' and form the air gap 230 for the ruthenium structures 200A-200D. The etching process is configured to selectively remove the dummy contact spacer 210' relative to the ILD layer 220 and the ruthenium structures 200A-200D, for example, as referenced above. Figure 15 As described. In Figure 24 In this structure, the air gap 230 has a bottom defined by the ILD layer 152, a first sidewall entirely defined by the ILD layer 220, and a second sidewall defined by the ruthenium structures 200A-200D. Therefore, the air gap 230 is arranged along the sidewalls of the ruthenium structures 200A-200D and extends through the ILD layer 220 to the ILD layer 152, such that the air gap 230 surrounds the ruthenium structures 200A-200D. (Go to...) Figures 25 to 27 Then, BEOL treatment forms various metallization layers on top of the local contact layer, as shown in the reference above. Figures 16 to 18 As described.

[0054] exist Figures 2 to 27The various etching processes performed include dry etching, wet etching, or combinations thereof. Dry etching processes can be performed using hydrogen-containing etching gases (e.g., H2 and / or CH4), nitrogen-containing etching gases (e.g., N2 and / or NH3), chlorine-containing etching gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), oxygen-containing etching gases (e.g., O2), fluorine-containing etching gases (e.g., F2, CH3F, CH2F2, CHF3, CF4, C2F6, SF6, and / or NF3), bromine-containing etching gases (e.g., Br, HBr, CH3Br, CH2, Br2, and / or CHBr3), iodine-containing etching gases, other suitable etching gases, or combinations thereof. Dry etching processes can use a carrier gas to deliver the etching gas. The carrier gas can include nitrogen, argon, helium, xenon, other suitable carrier gas components, or combinations thereof. Wet etching processes can be implemented using wet etching solutions including: H2SO4, H2O2, NH4OH, HCl, HF, DHF, KOH, NH3, CH3COOH, HNO3, H3PO4, H2O (which may be DIW or DIWO3), O3, other suitable chemicals, or combinations thereof. During each etching process, various etching parameters can be adjusted to achieve the desired selective etching, such as the flow rate of the etching gas, the concentration of the etching gas, the concentration of the carrier gas, the ratio of the concentration of the first etching gas to the concentration of the second etching gas, the ratio of the concentration of the carrier gas to the concentration of the etching gas, the concentration of the wet etching solution, the ratio of the concentration of the first wet etching component to the concentration of the second wet etching component, the power of the RF source, the bias voltage, the pressure, the duration of the etching process, the temperature maintained in the process chamber during the etching process, the temperature of the wafer during the etching process, the temperature of the wet etching solution, other suitable etching parameters, or combinations thereof.

[0055] This disclosure provides numerous different embodiments. This document discloses MOL interconnects that contribute to reducing capacitance and / or resistance, and corresponding techniques for forming such MOL interconnects. An exemplary MOL interconnect structure includes device-level contacts disposed in a first insulating layer and a ruthenium structure disposed in a second insulating layer above the first insulating layer. The device-level contacts are in physical contact with integrated circuit features, and the ruthenium structure is in physical contact with the device-level contacts. An air gap separates the sidewalls of the ruthenium structure from the second insulating layer. The top surface of the ruthenium structure is lower than the top surface of the second insulating layer. Through-holes are disposed in a third insulating layer and extend below the top surface of the second insulating layer to physically contact the ruthenium structure. In some embodiments, the remaining portion of a dummy contact spacer layer is disposed between and separates the first and second insulating layers. In some embodiments, the dummy contact spacer layer is an amorphous silicon layer, a titanium oxide layer, or an amorphous carbon layer. In some embodiments, the ruthenium structure includes an adhesion layer and a ruthenium plug disposed on the adhesion layer, and an air gap separates the sidewalls of the ruthenium plug from the second insulating layer. In some embodiments, the air gap also separates the sidewalls of the adhesion layer from the second insulating layer. In some embodiments, the device further includes a back-end process interconnect disposed on a mid-stage process interconnect structure. The back-end process interconnect structure has a via disposed in a third insulating layer and a metal wire disposed in the third insulating layer. The third insulating layer is disposed on the second insulating layer, and the metal wire is in physical contact with the via. In some embodiments, the length of the air gap is defined between the bottom surface of the via and the top surface of the first insulating layer. In some embodiments, the first insulating layer includes an etch stop layer, and the second insulating layer does not have an etch stop layer.

[0056] Another exemplary device includes a first oxide layer disposed on a substrate, a second oxide layer disposed on the first oxide layer, and a third oxide layer disposed on the second oxide layer. Device-level contacts are disposed in the first oxide layer and extend through it, and physically contact an IC device feature formed on the substrate. A ruthenium structure is disposed in the second oxide layer and physically contacts the ruthenium structure. An air gap is disposed between the sidewalls of the ruthenium structure and the second oxide layer. Vias are disposed in the third oxide layer and the second oxide layer, wherein the vias physically contact the ruthenium structure. In some embodiments, the second oxide layer is disposed directly on and physically contacts the first oxide layer, and a metal oxide layer is disposed between the second and third oxide layers, separating the second and third oxide layers. In some embodiments, the remaining portion of a dummy contact spacer layer is disposed between the second and first oxide layers, separating the second oxide layer from the first oxide layer, and a metal oxide layer is disposed between the second and third oxide layers, separating the second oxide layer from the third oxide layer. In some embodiments, the via includes a first via portion disposed in a third oxide layer and a second via portion disposed in a second oxide layer, wherein a first width of the first via portion is greater than a second width of the second via portion, and a third width of the ruthenium structure is less than the second width. In some embodiments, the via is in physical contact with the top surface of the second oxide layer and the sidewalls of the second oxide layer. In some embodiments, the device includes a fourth oxide layer disposed between a substrate and a first oxide layer, wherein device-level contacts are further disposed in the fourth oxide layer. The device also includes a first etch stop layer and a second etch stop layer. The first etch stop layer is disposed between the third oxide layer and the second oxide layer. The second etch stop layer is disposed between the fourth oxide layer and the first oxide layer.

[0057] An exemplary method includes: forming a contact adhesion layer over a device-level contact layer; forming a ruthenium layer over the contact adhesion layer; forming a patterned mask feature over the ruthenium layer; and forming a ruthenium structure by etching the ruthenium layer and the contact adhesion layer using the patterned mask feature as an etching mask. The ruthenium structure is in physical contact with device-level contacts of the device-level contact layer. The method further includes forming a dummy contact spacer layer over the ruthenium structure and the device-level contact layer. The dummy contact spacer layer is disposed along the sidewalls of the ruthenium structure. The method further includes forming an insulating layer over the dummy contact spacer layer, the ruthenium structure, and the device-level contact layer. The method further includes removing the dummy contact spacer layer from the sidewalls of the ruthenium structure to form an air gap between the sidewalls of the ruthenium structure and the insulating layer. The method further includes forming vias that are in physical contact with the ruthenium structure. In some embodiments, the method further includes removing the patterned mask feature after forming the insulating layer and before removing the dummy contact spacer layer. In some embodiments, the method further includes removing a dummy contact spacer layer over the device-level contact layer prior to forming an insulating layer. In some embodiments, the patterned mask feature is a first patterned mask feature, and the method further includes: forming a mask layer over the ruthenium layer prior to forming the first patterned mask feature over the ruthenium layer, and etching the mask layer to form a second patterned mask feature while forming the ruthenium structure. In these embodiments, forming the insulating layer may include using the second patterned mask feature as a planarization stop layer during a planarization process. In these embodiments, the method may further include removing the second patterned mask feature to form a recess defined between the ruthenium structure and the insulating layer, wherein vias fill the recess.

[0058] The foregoing has outlined features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0059] Example 1. A semiconductor device, comprising:

[0060] Mid-stage process interconnect structure, has:

[0061] Device-level contacts are disposed within a first insulating layer, wherein the device-level contacts physically contact features of an integrated circuit (IC).

[0062] A ruthenium structure is disposed in a second insulating layer, which is disposed above a first insulating layer, wherein the ruthenium structure physically contacts the device-level contacts.

[0063] An air gap separates the sidewalls of the ruthenium structure from the second insulating layer.

[0064] Example 2. The device according to Example 1, wherein the top surface of the ruthenium structure is lower than the top surface of the second insulating layer, such that a distance is defined between the top surface of the ruthenium structure and the second insulating layer.

[0065] Example 3. The device according to Example 1, wherein the ruthenium structure includes an adhesive layer and a ruthenium plug disposed on the adhesive layer, wherein the air gap separates the sidewall of the ruthenium plug from the second insulating layer.

[0066] Example 4. The device according to Example 3, wherein the air gap also separates the sidewalls of the adhesion layer from the second insulating layer.

[0067] Example 5. The device according to Example 1 further includes: the remaining portion of the dummy contact spacer layer, disposed between the first insulating layer and the second insulating layer and separating the first insulating layer and the second insulating layer.

[0068] Example 6. The device according to Example 5, wherein the dummy contact spacer layer is an amorphous silicon layer, a titanium oxide layer, or an amorphous carbon layer.

[0069] Example 7. The device according to Example 1 further includes:

[0070] A back-end process interconnect structure is disposed on top of the mid-end process interconnect structure, the back-end process interconnect structure having:

[0071] A through-hole is disposed in a third insulating layer, which is disposed above the second insulating layer, wherein the through-hole extends below the top surface of the second insulating layer and is in physical contact with the ruthenium structure; and

[0072] A metal wire is arranged in the third insulating layer, wherein the metal wire is in physical contact with the through hole.

[0073] Example 8. The device according to Example 7, wherein the length of the air gap is defined between the bottom surface of the through hole and the top surface of the first insulating layer.

[0074] Example 9. The device according to Example 1, wherein the first insulating layer includes an etch stop layer and the second insulating layer does not have an etch stop layer.

[0075] Example 10. A semiconductor device, comprising:

[0076] A first oxide layer is disposed on the substrate;

[0077] A second oxide layer is disposed on top of the first oxide layer;

[0078] A third oxide layer is disposed on top of the second oxide layer;

[0079] Device-level contacts are disposed in and extend through the first oxide layer and are in physical contact with IC device features formed on the substrate.

[0080] A ruthenium structure disposed within the second oxide layer and in physical contact with the device-level contact, wherein an air gap is provided between the sidewall of the ruthenium structure and the second oxide layer; and

[0081] Through-holes are arranged in the third oxide layer and the second oxide layer, wherein the through-holes are in physical contact with the ruthenium structure.

[0082] Example 11. The device according to Example 10, wherein the second oxide layer is disposed directly on and in physical contact with the first oxide layer, and a metal oxide layer is disposed between the second oxide layer and the third oxide layer and separates the second oxide layer from the third oxide layer.

[0083] Example 12. The device according to Example 10, wherein the remaining portion of the dummy contact spacer layer is disposed between the second oxide layer and the first oxide layer and separates the second oxide layer from the first oxide layer, and a metal oxide layer is disposed between the second oxide layer and the third oxide layer and separates the second oxide layer from the third oxide layer.

[0084] Example 13. The device according to Example 10, wherein the via includes a first via portion disposed in the third oxide layer and a second via portion disposed in the second oxide layer, wherein a first width of the first via portion is greater than a second width of the second via portion, and a third width of the ruthenium structure is less than the second width.

[0085] Example 14. The device according to Example 10, wherein the via is in physical contact with the top surface of the second oxide layer and the sidewall of the second oxide layer.

[0086] Example 15. The device according to Example 10 further includes:

[0087] A fourth oxide layer is disposed between the substrate and the first oxide layer, wherein the device-level contacts are further disposed in the fourth oxide layer; and

[0088] A first etch stop layer and a second etch stop layer, wherein the first etch stop layer is disposed between the third oxide layer and the second oxide layer, and the second etch stop layer is disposed between the fourth oxide layer and the first oxide layer.

[0089] Example 16. A method of manufacturing a semiconductor device, comprising:

[0090] A ruthenium structure is formed on and in physical contact with the device-level contact;

[0091] A layer of dummy contact spacers is formed along the sidewall of the ruthenium structure;

[0092] After forming an insulating layer on top of the dummy contact spacer layer, the dummy contact spacer layer is removed from the sidewall of the ruthenium structure to form an air gap between the sidewall of the ruthenium structure and the insulating layer; and

[0093] A through-hole is formed, which is in physical contact with the ruthenium structure.

[0094] Example 17. The method according to Example 16 further includes: removing the dummy contact spacer layer from the device-level contact layer before forming the insulating layer, the device-level contact layer including the device-level contacts disposed therein.

[0095] Example 18. The method according to Example 16, wherein forming the ruthenium structure comprises:

[0096] A contact adhesion layer is formed on top of a device-level contact layer, the device-level contact layer including the device-level contacts disposed therein;

[0097] A ruthenium layer is formed on top of the contact adhesion layer;

[0098] Patterned mask features are formed on the ruthenium layer; and

[0099] The patterned mask features are used as an etching mask to etch the ruthenium layer and the contact adhesion layer.

[0100] Example 19. The method according to Example 18 further includes: removing the patterned mask features after forming the insulating layer and before removing the dummy contact spacer layer.

[0101] Example 20. The method according to Example 18, wherein the patterned mask feature is a first patterned mask feature, the method further comprising:

[0102] Before forming the first patterned mask feature on the ruthenium layer, a mask layer is formed on the ruthenium layer;

[0103] When the ruthenium structure is formed, the mask layer is etched to form a second patterned mask feature, wherein forming the insulating layer includes: using the second patterned mask feature as a planarization stop layer during the planarization process; and

[0104] The second patterned mask features are removed to form a groove defined between the ruthenium structure and the insulating layer, wherein the via fills the groove.

Claims

1. A semiconductor device, comprising: Mid-stage process interconnect structure, has: Device-level contacts are disposed within a first insulating layer, wherein the device-level contacts physically contact features of an integrated circuit (IC). A ruthenium structure is disposed within a second insulating layer, which is disposed above a first insulating layer, wherein the ruthenium structure physically contacts the device-level contacts. An air gap, which separates the sidewalls of the ruthenium structure from the second insulating layer; and The remaining portion of the dummy contact spacer layer is arranged between the first insulating layer and the second insulating layer, separating the first insulating layer and the second insulating layer, wherein the remaining portion of the dummy contact spacer layer has a higher etching selectivity than the ruthenium structure and the second insulating layer.

2. The semiconductor device according to claim 1, wherein, The top surface of the ruthenium structure is lower than the top surface of the second insulating layer, such that there is a distance defined between the top surface of the ruthenium structure and the second insulating layer.

3. The semiconductor device according to claim 1, wherein, The ruthenium structure includes an adhesive layer and a ruthenium plug disposed on the adhesive layer, wherein the air gap separates the sidewall of the ruthenium plug from the second insulating layer.

4. The semiconductor device according to claim 3, wherein, The air gap also separates the sidewalls of the adhesion layer from the second insulating layer.

5. The semiconductor device according to claim 1, wherein, The dummy contact spacer layer is an amorphous silicon layer, a titanium oxide layer, or an amorphous carbon layer.

6. The semiconductor device according to claim 1, further comprising: A back-end process interconnect structure is disposed on top of the mid-end process interconnect structure, the back-end process interconnect structure having: A through-hole is disposed in a third insulating layer, which is disposed above the second insulating layer, wherein the through-hole extends below the top surface of the second insulating layer and is in physical contact with the ruthenium structure; and A metal wire is arranged in the third insulating layer, wherein the metal wire is in physical contact with the through hole.

7. The semiconductor device according to claim 6, wherein, The length of the air gap is defined between the bottom surface of the through hole and the top surface of the first insulating layer.

8. The semiconductor device according to claim 1, wherein, The first insulating layer includes an etch stop layer, while the second insulating layer does not have an etch stop layer.

9. A semiconductor device, comprising: A first oxide layer is disposed on the substrate; A second oxide layer is disposed on top of the first oxide layer; A third oxide layer is disposed on top of the second oxide layer; Device-level contacts are disposed in and extend through the first oxide layer and are in physical contact with IC device features formed on the substrate. A ruthenium structure is disposed in the second oxide layer and in physical contact with the device-level contact, wherein an air gap is disposed between the sidewall of the ruthenium structure and the second oxide layer; Through-holes are disposed in the third oxide layer and the second oxide layer, wherein the through-holes are in physical contact with the ruthenium structure; and The remaining portion of the dummy contact spacer layer is disposed between the second oxide layer and the first oxide layer, and separates the second oxide layer from the first oxide layer, wherein the remaining portion of the dummy contact spacer layer has higher etching selectivity than the ruthenium structure and the second oxide layer.

10. The semiconductor device according to claim 9, wherein, The second oxide layer is disposed directly on the first oxide layer and in physical contact with the first oxide layer, and the metal oxide layer is disposed between the second oxide layer and the third oxide layer and separates the second oxide layer from the third oxide layer.

11. The semiconductor device according to claim 9, wherein, A metal oxide layer is disposed between the second oxide layer and the third oxide layer, and separates the second oxide layer from the third oxide layer.

12. The semiconductor device according to claim 9, wherein, The via includes a first via portion disposed in the third oxide layer and a second via portion disposed in the second oxide layer, wherein a first width of the first via portion is greater than a second width of the second via portion, and a third width of the ruthenium structure is less than the second width.

13. The semiconductor device according to claim 9, wherein, The through-hole is in physical contact with the top surface of the second oxide layer and the sidewall of the second oxide layer.

14. The semiconductor device according to claim 9, further comprising: A fourth oxide layer is disposed between the substrate and the first oxide layer, wherein the device-level contacts are further disposed in the fourth oxide layer; and A first etch stop layer and a second etch stop layer, wherein the first etch stop layer is disposed between the third oxide layer and the second oxide layer, and the second etch stop layer is disposed between the fourth oxide layer and the first oxide layer.

15. A method for manufacturing a semiconductor device, comprising: A ruthenium structure is formed on and in physical contact with the device-level contact; A layer of dummy contact spacers is formed along the sidewall of the ruthenium structure; After forming an insulating layer on the dummy contact spacer layer, the dummy contact spacer layer is removed from the sidewall of the ruthenium structure to form an air gap between the sidewall of the ruthenium structure and the insulating layer; and A through-hole is formed, which is in physical contact with the ruthenium structure. The dummy contact spacer layer has a higher etching selectivity than the ruthenium structure and the insulating layer.

16. The method of claim 15, further comprising: Before forming the insulating layer, the dummy contact spacer layer, which includes the device-level contacts disposed therein, is removed from the device-level contact layer.

17. The method according to claim 15, wherein, Forming the ruthenium structure includes: A contact adhesion layer is formed on top of a device-level contact layer, the device-level contact layer including the device-level contacts disposed therein; A ruthenium layer is formed on top of the contact adhesion layer; Patterned mask features are formed on the ruthenium layer; and The patterned mask features are used as an etching mask to etch the ruthenium layer and the contact adhesion layer.

18. The method of claim 17, further comprising: The patterned mask features are removed after the insulating layer is formed and before the dummy contact spacer layer is removed.

19. The method of claim 17, wherein, The patterned mask feature is a first patterned mask feature, and the method further includes: Before forming the first patterned mask feature on the ruthenium layer, a mask layer is formed on the ruthenium layer; When the ruthenium structure is formed, the mask layer is etched to form a second patterned mask feature, wherein forming the insulating layer includes: using the second patterned mask feature as a planarization stop layer during the planarization process; and The second patterned mask features are removed to form a groove defined between the ruthenium structure and the insulating layer, wherein the via fills the groove.

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