Array substrate and manufacturing method thereof

Abstract

The present invention discloses an array substrate and a method for manufacturing the same. The method comprises providing a substrate; forming a first metal layer and a first insulating layer on the substrate; covering the first insulating layer with a first positive photoresist layer; exposing the first positive photoresist layer from the top of the substrate using a first half-tone mask to ultimately form scan lines, gate electrodes, and touch leads, and forming a second insulating layer entirely on the gate insulating layer; covering the second insulating layer with a negative photoresist layer; exposing and developing the negative photoresist layer from the bottom of the substrate to ultimately remove the second insulating layer at locations corresponding to the scan lines, gate electrodes, and touch leads, while retaining the second insulating layer in other areas; forming an entire second metal layer on the second insulating layer; and patterning the second metal layer to form a source electrode, a drain electrode, a data line, and a touch bridge portion. The array substrate and method for manufacturing the same not only save costs but also improve the aperture ratio.

Description

Technical Field

[0001] The present invention relates to the technical field of display devices, and in particular to an array substrate and a manufacturing method thereof. Background Art

[0002] At present, metal oxide TFTs have attracted widespread attention due to their advantages over low-temperature polysilicon TFTs and amorphous silicon TFTs, such as higher electron mobility, high transmittance, low leakage current, low deposition temperature, and low manufacturing cost. However, in the metal oxide TFT structure, in order to prevent etching damage to the metal oxide back channel, an etch stop layer (ESL) structure is usually used to prevent back channel etching damage, but an additional photomask is required, and before the S / D (source / drain) electrodes of the TFT are manufactured, a conductor treatment is usually performed to ensure good ohmic contact between the S / D and the semiconductor layer. In this method, the accumulated alignment deviation of the two-step photolithography process limits the accuracy of the active channel size, which is not conducive to the "miniaturization" of the TFT device size. At the same time, the etch stop layer introduced in the etch stop layer (ESL) structure adds a thin film growth and photolithography process, which increases the process complexity and cost, and indirectly reduces the market competitiveness of metal oxides.

[0003] And, as Figure 1 and Figure 2 As shown, the current array architecture of metal oxide semiconductor in-cell touch control, in the case of an OC flat layer 42: the process is 10 masks or above. The specific process includes: forming a pattern including a gate 31 and a scan line 37 through a single patterning process (1Mask); forming a pattern including a gate insulating layer 32 through a single patterning process (2Mask); forming a pattern including a metal oxide semiconductor layer 33 through a single patterning process (3Mask); forming a pattern including an etching stop layer 34 covering the metal oxide semiconductor layer 33 through a single patterning process (4Mask); forming a pattern including a source line, a drain 35, a source 36, a source line (not shown in the figure) and a layer connecting two adjacent scan lines 3 through a single patterning process (5Mask). 7 is used to form a pattern of a bridging layer 38; a first insulating layer pattern is formed; a pattern including an OC flat layer 42 is formed through a single patterning process (6Mask); a pattern including a common electrode 41 is formed through a single patterning process (7Mask); a touch lead is formed above the common electrode 41 through a single patterning process (8Mask); a second insulating layer pattern is formed through a single patterning process (9Mask), and a through-conducting hole 104 is formed above the drain 35; a pattern of a pixel electrode 39 is formed through a single patterning process (10Mask), and the pixel electrode 39 is connected to the drain 35 through the conductive hole 104.

[0004] In addition, without the OC planarization layer 42, the manufacturing process is 8 masks or higher. The touch lines, source electrodes, drain electrodes, and source lines are formed in a single patterning process. Therefore, the design distance between the source lines and touch lines (TP lines) is at least 4-5 μm, resulting in a significant loss in aperture ratio.

[0005] As can be seen from the above, the metal oxide semiconductor in-cell touch array structure manufactured by the above method cannot simultaneously meet the requirements of high transmittance and low TP loading. Summary of the Invention

[0006] In view of this, the present invention provides an array substrate and a manufacturing method thereof, which not only saves costs but also improves the aperture ratio.

[0007] A method for manufacturing an array substrate, the method comprising:

[0008] providing a substrate;

[0009] forming a first metal layer and a first insulating layer on the entire surface of the substrate in sequence;

[0010] covering the first insulating layer with a first positive photoresist layer;

[0011] Exposing the first positive photoresist layer from the top of the substrate using a first half-tone mask, wherein the first half-tone mask includes a first opaque area, a first semi-transparent area, and a first fully transparent area, wherein the first opaque area corresponds to the conductor portions of the scan lines, the gates, and the touch leads, the first semi-transparent area corresponds to the connecting portions of the touch leads, and the first fully transparent area corresponds to other areas;

[0012] developing the first positive photoresist layer, retaining the first positive photoresist layer at positions corresponding to the scan lines, the gates, and the wire portions, and retaining the first positive photoresist layer at positions corresponding to the connecting portions, wherein the thickness of the first positive photoresist layer corresponding to the connecting portions is less than the thickness of the first positive photoresist layer corresponding to the scan lines, the gates, and the wire portions, while removing the first positive photoresist layer from other areas;

[0013] Performing a patterning process on the first insulating layer and the first metal layer so that the first metal layer forms a scan line, a gate, and a touch lead, and the first insulating layer forms a gate insulating layer covering the scan line, the gate, and the touch lead, wherein the touch lead includes a wire portion and a connecting portion, the wire portion is located between two adjacent scan lines, the connecting portions are respectively located at both ends of the wire portion and connected to the wire portion, and the gate is connected to the scan line;

[0014] ashing and thinning the first positive photoresist layer to remove the first positive photoresist layer corresponding to the connection portion, but retaining the first positive photoresist layer corresponding to the scan line, the gate, and the wire portion;

[0015] performing patterning on the first insulating layer again to remove the gate insulating layer covering the connecting portion, thereby exposing the connecting portion;

[0016] stripping the first positive photoresist layer;

[0017] forming a second insulating layer on the entire surface of the gate insulating layer;

[0018] covering the second insulating layer with a negative photoresist layer;

[0019] exposing the negative photoresist layer from the bottom of the substrate;

[0020] Developing the negative photoresist layer, removing the negative photoresist layer at positions corresponding to the scan lines, gates, and touch leads, while retaining the negative photoresist layer in other areas;

[0021] Performing a patterning process on the second insulating layer to remove the second insulating layer corresponding to the scan line, the gate, and the touch lead to expose the gate insulating layer and the connecting portion;

[0022] Stripping the negative photoresist layer;

[0023] forming a second metal layer on the entire surface of the second insulating layer;

[0024] The second metal layer is patterned to form a source electrode, a drain electrode, a data line and a touch bridge portion on the second metal layer, wherein the source electrode and the drain electrode are spaced apart to form a channel region, the data line is connected to the source electrode, the touch bridge portion spans the scan line, and the two ends of the touch bridge portion are respectively in contact with the connecting portions at the ends of two adjacent touch leads, so that the two adjacent touch leads are electrically connected through the touch bridge portion.

[0025] In an embodiment of the present invention, the above-mentioned semiconductor layer includes a first connecting portion, a second connecting portion and a third connecting portion, the first connecting portion and the drain are stacked, the second connecting portion is filled in the through hole and connected between the first connecting portion and the third connecting portion, and the third connecting portion and the source are stacked.

[0026] In an embodiment of the present invention, the above-mentioned manufacturing method further includes:

[0027] forming a metal oxide semiconductor layer entirely on the source electrode, the drain electrode, the data line, and the touch bridge portion;

[0028] covering the metal oxide semiconductor layer with a second positive photoresist layer;

[0029] exposing the second positive photoresist layer using a second half-tone mask, wherein the second half-tone mask includes a second opaque area, a second semi-transparent area, and a second fully transparent area, wherein the second opaque area corresponds to the active layer, the second semi-transparent area corresponds to the source electrode stack, the drain electrode stack, the data line stack, and the bridge stack, and the second fully transparent area corresponds to other areas;

[0030] developing the second positive photoresist layer, retaining the second positive photoresist layer at a position corresponding to the active layer, retaining the second positive photoresist layer at positions corresponding to the source electrode stacking portion, the drain electrode stacking portion, the data line stacking portion, and the bridge stacking portion, wherein the thickness of the second positive photoresist layer corresponding to the source electrode stacking portion, the drain electrode stacking portion, the data line stacking portion, and the bridge stacking portion is less than the thickness of the second positive photoresist layer corresponding to the active layer, and removing the second positive photoresist layer from other regions;

[0031] Performing a patterning process on the metal oxide semiconductor layer so that the metal oxide semiconductor layer forms the active layer, the source electrode stacking portion, the drain electrode stacking portion, the data line stacking portion, and the bridge stacking portion, wherein the active layer is located in the channel region, the source electrode stacking portion is stacked with the source electrode, the drain electrode stacking portion is stacked with the drain electrode, the data line stacking portion is stacked with the data line, and the bridge stacking portion is stacked with the touch bridge portion;

[0032] ashing and thinning the second positive photoresist layer to remove the second positive photoresist layer corresponding to the source electrode stacking portion, the drain electrode stacking portion, the data line stacking portion, and the bridge stacking portion, but retaining the second positive photoresist layer corresponding to the active layer;

[0033] performing a hydrogenation treatment or an ion doping treatment on the source electrode stack, the drain electrode stack, the data line stack, and the bridge stack, so that the source electrode stack, the drain electrode stack, the data line stack, and the bridge stack are transformed from semiconductors to conductors, while the active layer remains a semiconductor;

[0034] The second positive photoresist layer is stripped off.

[0035] In an embodiment of the present invention, the above-mentioned manufacturing method further includes:

[0036] forming a third insulating layer entirely on the source electrode stack, the drain electrode stack, the active layer, the bridge stack, and the data line stack;

[0037] Performing a patterning process on the third insulating layer to form a first conductive hole at a position of the third insulating layer corresponding to the bridge stack portion, and the bridge stack portion is exposed through the first conductive hole;

[0038] forming a first transparent conductive layer on the entire surface of the third insulating layer;

[0039] The first transparent conductive layer is patterned to form a common electrode. The common electrode is filled in the first conductive hole and contacts the bridge stack portion. The common electrode is conductively connected to the touch lead through the bridge stack portion and the touch bridge portion.

[0040] In an embodiment of the present invention, the above-mentioned manufacturing method further includes:

[0041] When the second positive photoresist layer is exposed using a second half-tone mask, the second semi-transparent area also corresponds to the pixel electrode;

[0042] When developing the second positive photoresist layer, the second positive photoresist layer is retained at a position corresponding to the pixel electrode, and a thickness of the second positive photoresist layer corresponding to the pixel electrode is less than a thickness of the second positive photoresist layer corresponding to the active layer;

[0043] When patterning the metal oxide semiconductor layer, the metal oxide semiconductor layer also forms the pixel electrode, wherein the pixel electrode is connected to the drain electrode stacking portion;

[0044] When the second positive photoresist layer is ashed and thinned, the second positive photoresist layer corresponding to the pixel electrode is also removed;

[0045] When the source electrode stack, the drain electrode stack, the data line stack and the bridge stack are subjected to hydrogenation or ion doping, the pixel electrode is also subjected to hydrogenation or ion doping to transform the pixel electrode from a semiconductor into a conductor.

[0046] In an embodiment of the present invention, the above-mentioned manufacturing method further includes:

[0047] forming a third insulating layer entirely on the source electrode stack, the drain electrode stack, the active layer, the bridge stack, and the data line stack;

[0048] forming a flat layer on the entire surface of the third insulating layer;

[0049] Performing a patterning process on the planar layer and the third insulating layer to form second via holes at positions corresponding to the bridge stack portion in the planar layer and the third insulating layer, and the bridge stack portion is exposed through the second via holes;

[0050] forming a second transparent conductive layer on the entire surface of the flat layer;

[0051] Performing a patterning process on the second transparent conductive layer to form a common electrode on the second transparent conductive layer, wherein the common electrode is filled in the second conductive hole and contacts the bridge stack portion, and the common electrode is conductively connected to the touch lead through the bridge stack portion and the touch bridge portion;

[0052] forming a fourth insulating layer on the entire surface of the common electrode;

[0053] performing a patterning process on the fourth insulating layer so as to form a third conductive hole at a position corresponding to the drain electrode stacking portion among the fourth insulating layer, the planar layer, and the third insulating layer, and the drain electrode stacking portion is exposed through the third conductive hole;

[0054] forming a third transparent conductive layer on the entire surface of the fourth insulating layer;

[0055] The third transparent conductive layer is patterned to form a pixel electrode. The pixel electrode is filled in the third conductive hole and contacts the drain electrode stack. The pixel electrode is conductively connected to the drain electrode through the drain electrode stack.

[0056] The present invention further provides an array substrate, comprising:

[0057] substrate;

[0058] Scan lines, gates, and touch leads are formed on the substrate, wherein the touch leads include a wire portion and a connecting portion, the wire portion is located between two adjacent scan lines, the connecting portions are located at both ends of the wire portion and connected to the wire portion, and the gate is connected to the scan line;

[0059] The gate insulating layer corresponding to the gate insulating layer covering the scanning line, the gate and the wire portion, and the connecting portion is not covered with the gate insulating layer;

[0060] a second insulating layer formed on the gate insulating layer, wherein the second insulating layer covers an area except the scan line, the gate, and the touch lead, and the connecting portion is not covered with the second insulating layer;

[0061] A source electrode, a drain electrode, a data line, and a touch bridge portion are formed on the second insulating layer, wherein the source electrode and the drain electrode are spaced apart to form a channel region, the data line is connected to the source electrode, the touch bridge portion spans the scan line, and two ends of the touch bridge portion are respectively in contact with the connecting portions at the ends of two adjacent touch leads, so that the two adjacent touch leads are electrically connected through the touch bridge portion.

[0062] In an embodiment of the present invention, the array substrate further comprises:

[0063] A source electrode stacking portion, a drain electrode stacking portion, an active layer, a data line stacking portion, and a bridge stacking portion are formed on the source electrode, the drain electrode, the data line, and the touch bridge portion, wherein the active layer is located in the channel region, the source electrode stacking portion is stacked with the source electrode, the drain electrode stacking portion is stacked with the drain electrode, the data line stacking portion is stacked with the data line, and the bridge stacking portion is stacked with the touch bridge portion;

[0064] The source electrode stack, the drain electrode stack, the active layer, the data line stack and the bridge stack are made of metal oxide semiconductor materials, wherein the source electrode stack, the drain electrode stack, the data line stack and the bridge stack are transformed from semiconductors to conductors through hydrogenation or ion doping, while the active layer remains as a semiconductor.

[0065] In an embodiment of the present invention, the array substrate further comprises:

[0066] A pixel electrode located in the same layer and made of the same material as the source electrode stack, the drain electrode stack, the active layer, the data line stack, and the bridge stack;

[0067] The pixel electrode is connected to the drain electrode stacking portion, and the pixel electrode is transformed from a semiconductor into a conductor through hydrogenation or ion doping.

[0068] In an embodiment of the present invention, the array substrate further comprises:

[0069] A third insulating layer is formed on the source electrode stack, the drain electrode stack, the active layer, the bridge stack, the data line stack, and the pixel electrode, wherein the third insulating layer has a first conductive hole formed at a position corresponding to the bridge stack;

[0070] A common electrode is formed on the third insulating layer, the common electrode is filled in the first conductive hole and contacts the bridge stacking portion, and the common electrode is conductively connected to the touch lead through the bridge stacking portion and the touch bridge portion.

[0071] In an embodiment of the present invention, the array substrate further comprises:

[0072] a third insulating layer formed on the source electrode stack, the drain electrode stack, the active layer, the bridge stack, and the data line stack;

[0073] A planar layer formed on the third insulating layer, wherein the planar layer and the third insulating layer form a second via hole at a position corresponding to the bridge stack portion;

[0074] a common electrode formed on the planar layer, the common electrode filling the second conductive hole and contacting the bridge laminate portion, the common electrode being conductively connected to the touch lead through the bridge laminate portion and the touch bridge portion;

[0075] A fourth insulating layer is formed on the common electrode, wherein the fourth insulating layer, the planar layer, and the third insulating layer form a third conductive hole at a position corresponding to the drain electrode stacking portion;

[0076] A pixel electrode is formed on the fourth insulating layer, the pixel electrode is filled in the third conductive hole and contacts the drain electrode stacking portion, and the pixel electrode is conductively connected to the drain electrode through the drain electrode stacking portion.

[0077] The array substrate of the present invention first forms a first metal layer and a first insulating layer on the entire surface of the substrate in sequence, and covers the first insulating layer with a first positive photoresist layer; then, the first positive photoresist layer is exposed and developed from the top of the substrate using a first half-tone mask; then, the first metal layer is patterned to form scan lines, gates, and touch leads, and the first insulating layer is formed into a gate insulating layer covering the scan lines, gates, and touch leads. Next, a second insulating layer is formed on the entire surface of the gate insulating layer, and a negative photoresist layer is covered on the second insulating layer; and the negative photoresist layer is exposed and developed from the bottom of the substrate. At this time, by using the patterned first metal layer to replace the function of the mask, there is no need to add an additional mask to expose the negative photoresist layer, and the second insulating layer can still be patterned, ultimately achieving the purpose of removing the second insulating layer corresponding to the scan lines, gates, and touch leads to expose the gate insulating layer and the connecting portion. A mask for making the second insulating layer is eliminated.

[0078] The touch lead includes a conductor portion and a connector portion. The conductor portion is located between two adjacent scan lines, and the connector portions are located at both ends of the conductor portion and connected to the conductor portion. When patterning the first insulating layer, the gate insulating layer covering the connector portion is removed to expose the connector portion. When patterning the second insulating layer, the gate insulating layer covering the connector portion is similarly removed to expose the connector portion. Finally, a second metal layer is formed entirely on the second insulating layer. The second metal layer is patterned to form a source electrode, a drain electrode, a data line, and a touch bridge portion. The ends of the touch bridge portion contact the exposed connector portions at the ends of the two adjacent touch leads, thereby electrically connecting the two adjacent touch leads via the touch bridge portion. Since the connector portions of the touch leads are already exposed during the patterning of the first and second insulating layers, there is no need to add a mask to create a separate bridge hole for electrically connecting the two adjacent touch leads. This eliminates the need for a mask to create the bridge hole.

[0079] The touch lines are formed by patterning the first metal layer, while the data lines are formed by patterning the second metal layer. Therefore, by forming the touch lines and data lines on the same metal layer, the design spacing between the touch lines can be reduced to 0-1 μm, while also increasing the aperture ratio without increasing the TP loading of the touch lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] Figure 1 It is a schematic diagram of a partial cross-sectional structure of an array substrate in the prior art.

[0081] Figure 2 It is a schematic diagram of a partial cross-sectional structure of an array substrate in the prior art.

[0082] Figures 3 to 8 Schematic diagrams S1-S6 of the cross-sectional manufacturing process of the manufacturing method of the array substrate of the present invention.

[0083] Figure 9 yes Figure 8 The planar structural diagram of the array substrate is shown in FIG.

[0084] Figures 10 to 15 Schematic diagram of the cross-sectional manufacturing process S7-S12 of the manufacturing method of the array substrate of the present invention.

[0085] Figure 16 yes Figure 15 The planar structural diagram of the array substrate is shown in FIG.

[0086] Figures 17 to 20 Schematic diagram of the cross-sectional manufacturing process S13-S16 of the manufacturing method of the array substrate of the present invention.

[0087] Figure 21 yes Figure 20 The planar structural diagram of the array substrate is shown in FIG.

[0088] Figure 22 FIG. 1 is a schematic cross-sectional manufacturing process diagram S17 of the manufacturing method of the array substrate of the present invention.

[0089] Figure 23 yes Figure 22 The planar structural diagram of the array substrate is shown in FIG.

[0090] Figures 24 to 25 Schematic diagram of a cross-sectional manufacturing process S18-S19 of the manufacturing method of the array substrate according to the first embodiment of the present invention.

[0091] Figure 26 yes Figure 25 The planar structural diagram of the array substrate is shown in FIG.

[0092] Figures 27 to 29 Schematic diagram of the planar flow chart S18 ′-S20 ′ of the method for manufacturing an array substrate according to the second embodiment of the present invention.

[0093] Figure 30 yes Figure 29 The cross-sectional structural diagram of the array substrate is shown in FIG. DETAILED DESCRIPTION

[0094] To facilitate understanding by those skilled in the art, the present application describes the specific implementation process of the technical solution provided by the present application through the following embodiments.

[0095] First embodiment

[0096] Figures 3 to 8 Schematic diagrams S1-S6 of the cross-sectional manufacturing process of the manufacturing method of the array substrate of the present invention are shown. Figure 9 yes Figure 8 The planar structural diagram of the array substrate shown in FIG. Figures 10 to 15 Schematic diagram of the cross-sectional manufacturing process S7-S12 of the manufacturing method of the array substrate of the present invention, Figure 16 yes Figure 15 The planar structural diagram of the array substrate shown in FIG. Figures 17 to 20 Schematic diagram of the cross-sectional manufacturing process S13-S16 of the manufacturing method of the array substrate of the present invention, Figure 21 yes Figure 20 The planar structural diagram of the array substrate shown in FIG. Figure 22 FIG17 is a cross-sectional manufacturing process diagram of the manufacturing method of the array substrate of the present invention, Figure 23 yes Figure 22 The planar structural diagram of the array substrate shown in FIG. Figures 24 to 25Schematic diagram of the cross-sectional manufacturing process S18-S19 of the manufacturing method of the array substrate according to the first embodiment of the present invention, Figure 26 yes Figure 25 The planar structural diagram of the array substrate is shown in FIG.

[0097] like Figures 1 to 26 As shown, a first embodiment of the present invention provides a method for manufacturing an array substrate, the manufacturing method comprising:

[0098] S1: If Figures 3 to 9 As shown, a substrate 11 is provided, and the substrate 11 can be made of materials such as glass, quartz, acrylic or polycarbonate.

[0099] A first metal layer 12 and a first insulating layer 13 are sequentially formed on the entire surface of the substrate 11. The first metal layer 12 can be made of copper and molybdenum niobium (Cu / MoNb) or copper and molybdenum (Cu / Mo); and the first insulating layer 13 can be made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.

[0100] The first insulating layer 13 is covered with a first positive photoresist layer 14 . Parts of the first positive photoresist layer 14 exposed to light are dissolved in a photoresist developer, while parts not exposed to light are not dissolved in the photoresist developer and remain on the first insulating layer 13 .

[0101] The first positive photoresist layer 14 is exposed from the top of the substrate 11 using a first half-tone mask 15, wherein the first half-tone mask 15 includes a first opaque area 151, a first semi-transparent area 152 and a first fully transparent area 153. The first opaque area 151 corresponds to the scanning line 121, the gate 122 and the wire portion 1231 of the touch lead 123, the first semi-transparent area 152 corresponds to the connecting portion 1232 of the touch lead 123, and the first fully transparent area 153 corresponds to other areas.

[0102] S2: Figure 4 and Figure 9 As shown, the first positive photoresist layer 14 is developed, and the first positive photoresist layer 14 is retained at positions corresponding to the scan line 121, the gate 122 and the wire portion 1231, and the first positive photoresist layer 14 is retained at positions corresponding to the connection portion 1232. The thickness of the first positive photoresist layer 14 corresponding to the connection portion 1232 is less than the thickness of the first positive photoresist layer 14 corresponding to the scan line 121, the gate 122 and the wire portion 1231, while the first positive photoresist layer 14 is removed from other areas.

[0103] S3: Figure 5 and Figure 9As shown, the first insulating layer 13 and the first metal layer 12 are patterned to form a scan line 121, a gate 122, and a touch lead 123 on the first metal layer 12. The first insulating layer 13 forms a gate insulating layer 131 that covers the scan line 121, the gate 122, and the touch lead 123. The touch lead 123 includes a wire portion 1231 and a connecting portion 1232. The wire portion 1231 is located between two adjacent scan lines 121. The connecting portions 1232 are located at both ends of the wire portion 1231 and connected to the wire portion 1231. The gate 122 is connected to the scan line 121. In this embodiment, the patterning of the first insulating layer 13 and the first metal layer 12 is specifically performed by first dry etching the first insulating layer 13 to form the gate insulating layer 131, and then wet etching the first metal layer 12 to form the scan line 121, the gate 122, and the touch lead 123.

[0104] S4: Figure 6 and Figure 9 As shown, the first positive photoresist layer 14 is ashed and thinned to remove the first positive photoresist layer 14 corresponding to the connection portion 1232 , while the first positive photoresist layer 14 corresponding to the scan line 121 , the gate 122 and the wire portion 1231 is retained.

[0105] S5: Figure 7 and Figure 9 As shown, the first insulating layer 13 is patterned again to remove the gate insulating layer 131 covering the connecting portion 1232, thereby exposing the connecting portion 1232. In this embodiment, the patterning of the first insulating layer 13 again includes dry etching the first insulating layer 13 again to expose the connecting portion 1232, while retaining the gate insulating layer 131 on the scan line 121, the gate 122, and the wire portion 1231 to prevent the scan line 121, the gate 122, and the wire portion 1231 from being corroded in subsequent manufacturing processes.

[0106] S6: Figure 8 and Figure 9 As shown, after the first insulating layer 13 is patterned, the first positive photoresist layer 14 is stripped to expose the gate insulating layer 131 .

[0107] S7: Figure 10 and Figure 16 As shown, a second insulating layer 16 is formed entirely on the gate insulating layer 131. A negative photoresist layer 17 is covered on the second insulating layer 16. The negative photoresist layer 17 is exposed from the bottom of the substrate 11. The negative photoresist layer 17 is developed, and the negative photoresist layer 17 is removed at locations corresponding to the scan lines 121, the gates 122, and the touch leads 123, while the negative photoresist layer 17 remains in other areas.

[0108] S8: Figure 11and Figure 16 As shown, in this embodiment, the photoresist layer covering the second insulating layer 16 is a negative photoresist layer 17. The portions of the negative photoresist layer 17 not exposed to light will dissolve in the photoresist developer; the portions exposed to light will not dissolve in the photoresist developer and will remain on the first insulating layer 13. Therefore, when the negative photoresist layer 17 is exposed from the bottom of the substrate 11, the negative photoresist layer 17 located above the scan lines 121, the gate electrode 122, and the touch leads 123 are opaque and block the light from the bottom of the substrate 11. Therefore, the negative photoresist layer 17 located above the scan lines 121, the gate electrode 122, and the touch leads 123 is not exposed to light. Ultimately, the negative photoresist layer 17 corresponding to the scan lines 121, the gate electrode 122, and the touch leads 123 is removed, while the remaining portions of the negative photoresist layer 17 exposed to light remain. Specifically, the scan line 121 , the gate 122 and the touch lead 123 obtained after the patterning process of the first metal layer 12 respectively have at least one section, and the negative photoresist layer 17 adjacent to each section and between each section are all retained.

[0109] S9: Figure 12 and Figure 16 As shown, the second insulating layer 16 is patterned to remove the second insulating layer 16 corresponding to the scan line 121 , the gate 122 and the touch lead 123 to expose the gate insulating layer 131 and the connecting portion 1232 .

[0110] S10: Figure 13 and Figure 16 As shown, after the second insulating layer 16 is patterned, the negative photoresist layer 17 is peeled off. At this point, the patterned second insulating layer 16 not only serves as an insulator, but also protects the cross-sections of the scanning lines 121, the gates 122, and the touch leads 123 from corrosion during subsequent manufacturing processes.

[0111] S11: Figure 14 and Figure 16 As shown, a second metal layer 18 is formed on the entire surface of the second insulating layer 16 , wherein the second metal layer 18 can be made of copper and molybdenum niobium (Cu / MoNb) or copper and molybdenum (Cu / Mo).

[0112] S12: Figure 15 and Figure 16As shown, the second metal layer 18 is patterned to form a source electrode 181, a drain electrode 182, a data line 183 and a touch bridge portion 184 in the second metal layer 18. The source electrode 181 and the drain electrode 182 are spaced apart from each other to form a channel region 185. The data line 183 is connected to the source electrode 181. The touch bridge portion 184 spans the scan line 121. The two ends of the touch bridge portion 184 are respectively in contact with the connecting portions 1232 at the ends of two adjacent touch leads 123, so that the two adjacent touch leads 123 are electrically connected through the touch bridge portion 184.

[0113] The array substrate of the present invention first forms a first metal layer 12 and a first insulating layer 13 on a substrate 11, and covers the first insulating layer 13 with a first positive photoresist layer 14. The first positive photoresist layer 14 is then exposed and developed from the top of the substrate 11 using a first half-tone mask 15. Scan lines 121, gates 122, and touch leads 123 are then formed on the first metal layer 12 through a patterning process, and a gate insulating layer 131 covering the scan lines 121, gates 122, and touch leads 123 is formed on the first insulating layer 13. Next, a second insulating layer 16 is formed on the gate insulating layer 131, and a negative photoresist layer 17 is covered on the second insulating layer 16. The negative photoresist layer 17 is then exposed and developed from the bottom of the substrate 11. At this point, by using the patterned first metal layer 12 to replace the function of the mask, there is no need to add an additional mask to expose the negative photoresist layer 17. The second insulating layer 16 can still be patterned, ultimately removing the second insulating layer 16 corresponding to the scan line 121, gate 122, and touch lead 123 to expose the gate insulating layer 131 and the connecting portion 1232. This eliminates the need for a mask to form the second insulating layer 16.

[0114] Among them, the touch lead 123 includes a wire portion 1231 and a connecting portion 1232. The wire portion 1231 is located between two adjacent scanning lines 121, and the connecting portion 1232 is respectively located at both ends of the wire portion 1231 and is connected to the wire portion 1231. When the first insulating layer 13 is patterned, the gate insulating layer 131 covering the connecting portion 1232 needs to be removed to expose the connecting portion 1232; when the second insulating layer 16 is patterned, the gate insulating layer 131 on the connecting portion 1232 also needs to be removed to expose the connecting portion 1232. Finally, a second metal layer 18 is formed entirely on the second insulating layer 16. The second metal layer 18 is patterned to form a source electrode 181, a drain electrode 182, a data line 183, and a touch bridge 184. The ends of the touch bridge 184 contact the exposed connection portions 1232 at the ends of two adjacent touch leads 123, thereby electrically connecting the two adjacent touch leads 123 via the touch bridge 184. Since the connection portions 1232 of the touch leads 123 are already exposed during the patterning of the first insulating layer 13 and the second insulating layer 16, there is no need to add a separate mask to create a bridge hole for electrically connecting the two adjacent touch leads 123. This eliminates the need for a mask to create the bridge hole.

[0115] Meanwhile, the touch leads 123 are formed by patterning the first metal layer 12, while the data lines 183 are formed by patterning the second metal layer 18. Therefore, by forming the touch leads 123 and data lines 183 on the same metal layer, not only can the design spacing between the touch leads 123 and data lines 183 be reduced to 0-1 μm, but the aperture ratio is also improved without increasing the TP loading of the touch leads 123.

[0116] Further, if Figures 17 to 23 As shown, the method for manufacturing the array substrate further includes:

[0117] S13: Figure 17 and Figure 21 As shown, a metal oxide semiconductor layer 19 is formed entirely on the source electrode 181, the drain electrode 182, the data line 183 and the touch bridge portion 184. The metal oxide semiconductor layer 19 is made of IGZO material.

[0118] The metal oxide semiconductor layer 19 is covered with a second positive photoresist layer 21 .

[0119] The second positive photoresist layer 21 is exposed using a second half-tone mask plate 22, wherein the second half-tone mask plate 22 includes a second opaque area 221, a second semi-transparent area 222 and a second fully transparent area 223, the second opaque area 221 corresponds to the active layer 191, the second semi-transparent area 222 corresponds to the source stack portion 192, the drain stack portion 193, the data line stack portion 194 and the bridge stack portion 195, and the second fully transparent area 223 corresponds to other areas.

[0120] S14: Figure 18 and Figure 21 As shown, the second positive photoresist layer 21 is developed, and the second positive photoresist layer 21 is retained at the position corresponding to the active layer 191, and the second positive photoresist layer 21 is retained at the positions corresponding to the source stack portion 192, the drain stack portion 193, the data line stack portion 194 and the bridge stack portion 195, and the thickness of the second positive photoresist layer 21 corresponding to the source stack portion 192, the drain stack portion 193, the data line stack portion 194 and the bridge stack portion 195 is less than the thickness of the second positive photoresist layer 21 corresponding to the active layer 191, while the second positive photoresist layer 21 is removed from other areas.

[0121] S15: Figure 19 and Figure 21 As shown, the metal oxide semiconductor layer 19 is patterned to form an active layer 191, a source electrode stack 192, a drain electrode stack 193, a data line stack 194, and a bridge stack 195. The active layer 191 is located in the channel region 185, the source electrode stack 192 is stacked with the source electrode 181, the drain electrode stack 193 is stacked with the drain electrode 182, the data line stack 194 is stacked with the data line 183, and the bridge stack 195 is stacked with the touch bridge 184. In this embodiment, the active layer 191, the source electrode stack 192, and the drain electrode stack 193 are formed on the entire surface. Therefore, when the source electrode stacking portion 192 is stacked with the source electrode 181, the source electrode 181 can not only directly achieve ohmic contact with the active layer 191 through the source electrode stacking portion 192, but the source electrode stacking portion 192 can also protect the source electrode 181 from being corroded in subsequent processes; after the drain electrode stacking portion 193 is stacked with the drain electrode 182, the drain electrode 182 can achieve ohmic contact with the active layer 191 through the drain electrode stacking portion 193, and the drain electrode stacking portion 193 can protect the drain electrode 182 from being corroded in subsequent processes.

[0122] S16: Figure 20 and Figure 21 As shown, the second positive photoresist layer 21 is ashed and thinned to remove the second positive photoresist layer 21 corresponding to the source stack 192 , the drain stack 193 , the data line stack 194 and the bridge stack 195 , but the second positive photoresist layer 21 corresponding to the active layer 191 is retained.

[0123] The source electrode stack 192, drain electrode stack 193, data line stack 194, and bridge stack 195 are hydrogenated or ion doped, transforming them from semiconductors to conductors, while the active layer 191 remains a semiconductor. In this embodiment, the second positive photoresist layer 21 corresponding to the active layer 191 is not removed. Therefore, during the hydrogenation or ion doping of the metal oxide semiconductor layer 19, the active layer 191 remains a semiconductor, protected by the second positive photoresist layer 21 above it. Without the protection of the second positive photoresist layer 21, the source electrode stack 192, drain electrode stack 193, data line stack 194, and bridge stack 195 are transformed from semiconductors to conductors.

[0124] S17: Figure 22 and Figure 23 As shown, after the source electrode stack 192 , the drain electrode stack 193 , the data line stack 194 and the bridge stack 195 are hydrogenated or ion doped, the second positive photoresist layer 21 is stripped to expose the active layer 191 .

[0125] Further, if Figure 24 and Figure 26 As shown, the method for manufacturing the array substrate further includes:

[0126] S18: Figure 24 and Figure 26 As shown, a third insulating layer 23 is formed on the entire surface of the source stack 192, the drain stack 193, the active layer 191, the bridge stack 195 and the data line stack 194, wherein the material of the third insulating layer 23 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0127] The third insulating layer 23 is patterned to form first vias 101 at positions of the third insulating layer 23 corresponding to the bridge stacking portions 195 , and the bridge stacking portions 195 are exposed through the first vias 101 .

[0128] S19: Figure 25 and Figure 26 As shown, the metal oxide semiconductor layer 19 is patterned to form an active layer 191, a source electrode stack 192, a drain electrode stack 193, a data line stack 194, and a bridge stack 195. A first transparent conductive layer is formed entirely on the third insulating layer 23. The first transparent conductive layer is made of a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). In this embodiment, the first transparent conductive layer is indium tin oxide (ITO).

[0129] The first transparent conductive layer is patterned to form a common electrode 25. The common electrode 25 is inserted into the first conductive via 101 and contacts the bridge laminate 195. The common electrode 25 is conductively connected to the touch lead 123 via the bridge laminate 195 and the touch bridge 184. In this embodiment, the common electrode 25 can be reused as a touch electrode, and the touch lead 123 can be reused as a common electrode 25 line. Therefore, during the touch phase, the touch lead 123 provides touch drive signals to the common electrode 25 (touch electrode) and receives touch feedback signals. During the display phase, the touch lead 123 provides common signals to the common electrode 25 (touch electrode), providing the signals required by the common electrode 25 for display. When the common electrode 25 can be reused as a touch electrode and the touch lead 123 can be reused as a common electrode 25 line, the thickness of the array substrate is reduced. When the array substrate is used in a touch display panel, the thickness of the touch display panel is reduced.

[0130] Furthermore, for the multiple pixels on the array substrate, each pixel may be provided with a common electrode 25 ; some pixels may share one common electrode 25 , or all pixels may share one entire surface of the common electrode 25 .

[0131] Furthermore, the method for manufacturing the array substrate further includes:

[0132] When the second positive photoresist layer 21 is exposed to light using the second half-tone mask 22 , the second semi-transparent region 222 also corresponds to the pixel electrode 24 .

[0133] When the second positive photoresist layer 21 is developed, the second positive photoresist layer 21 is retained at the position corresponding to the pixel electrode 24 , and the thickness of the second positive photoresist layer 21 corresponding to the pixel electrode 24 is less than the thickness of the second positive photoresist layer 21 corresponding to the active layer 191 .

[0134] When the metal oxide semiconductor layer 19 is patterned, a pixel electrode 24 is formed on the metal oxide semiconductor layer 19 , wherein the pixel electrode 24 is connected to the drain electrode stacking portion 193 .

[0135] When the second positive photoresist layer 21 is ashed and thinned, the second positive photoresist layer 21 corresponding to the pixel electrode 24 is also removed.

[0136] The third insulating layer 23 is formed entirely on the source electrode stack 192 , the drain electrode stack 193 , the active layer 191 , the bridge stack 195 , and the data line stack 194 , and is also formed above the pixel electrode 24 .

[0137] In this embodiment, when the source electrode stack 192, the drain electrode stack 193, the data line stack 194, and the bridge stack 195 are subjected to hydrogenation or ion doping, the pixel electrode 24 is also subjected to hydrogenation or ion doping to convert the pixel electrode 24 from a semiconductor into a conductor. In this embodiment, because the pixel electrode 24, the source electrode stack 192, the drain electrode stack 193, the data line stack 194, and the bridge stack 195 are all integrally formed using the same metal oxide semiconductor layer 19, no additional photomask is required to form the pixel electrode 24. Furthermore, the pixel electrode 24 can be directly electrically connected to the drain electrode 182 through the drain electrode stack 193, and no additional photomask is required to form a contact hole connecting the pixel electrode 24 and the drain electrode 182, thereby significantly saving costs.

[0138] The present invention further provides an array substrate, comprising:

[0139] The substrate 11 can be made of glass, quartz, acrylic acid, polycarbonate or other materials.

[0140] Scan lines 121, gates 122, and touch leads 123 are formed on the substrate 11. The scan lines 121 are electrically connected to the gates 122. The touch leads 123 include a conductor portion 1231 and a connection portion 1232. The conductor portion 1231 is located between two adjacent scan lines 121. The connection portions 1232 are located at both ends of the conductor portion 1231 and connected to the conductor portion 1231. The gates 122 are connected to the scan lines 121. In this embodiment, the scan lines 121, the gates 122, and the touch leads 123 are all formed by patterning the first metal layer 12. The first metal layer 12 can be made of copper and molybdenum niobium (Cu / MoNb) or copper and molybdenum (Cu / Mo).

[0141] Corresponding to the gate insulating layer 131 covering the scan line 121, the gate 122, and the conductive line 1231, the connecting portion 1232 is not covered with the gate insulating layer 131. In this embodiment, the first insulating layer 13 is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. The fact that the connecting portion 1232 is not covered with the gate insulating layer 131 facilitates subsequent electrical connection of the touch lead 123 to other circuits or electrodes.

[0142] A second insulating layer 16 is formed on the gate insulating layer 131. The second insulating layer 16 covers the entire area except for the scan line 121, the gate electrode 122, and the touch lead 123. The connecting portion 1232 is not covered by the second insulating layer 16. Specifically, the second insulating layer 16 is disposed adjacent to the cross-sections of the scan line 121, the gate electrode 122, and the touch lead 123, thereby protecting the cross-sections of the scan line 121, the gate electrode 122, and the touch lead 123 from corrosion during subsequent manufacturing processes. In this embodiment, the second insulating layer 16 is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.

[0143] A source electrode 181, a drain electrode 182, a data line 183, and a touch bridge 184 are formed on the second insulating layer 16. The source electrode 181 and the drain electrode 182 are spaced apart to form a channel region 185. The data line 183 is connected to the source electrode 181. The touch bridge 184 spans the scan line 121. The two ends of the touch bridge 184 respectively contact the connecting portions 1232 at the ends of two adjacent touch leads 123, electrically connecting the two adjacent touch leads 123 through the touch bridge 184. In this embodiment, the source electrode 181, the drain electrode 182, the data line 183, and the touch bridge 184 can be made of copper and molybdenum niobium (Cu / MoNb) or copper and molybdenum (Cu / Mo).

[0144] Furthermore, the array substrate further includes:

[0145] The source electrode stacking portion 192, the drain electrode stacking portion 193, the active layer 191, the data line stacking portion 194 and the bridge stacking portion 195 are formed on the source electrode 181, the drain electrode 182, the data line 183 and the touch bridge portion 184. The active layer 191 is located in the channel region 185, the source electrode stacking portion 192 is stacked with the source electrode 181, the drain electrode stacking portion 193 is stacked with the drain electrode 182, the data line stacking portion 194 is stacked with the data line 183, and the bridge stacking portion 195 is stacked with the touch bridge portion 184. In this embodiment, when the source electrode stacking portion 192 is stacked with the source electrode 181, the source electrode 181 can not only achieve ohmic contact with the active layer 191 through the source electrode stacking portion 192, but also the source electrode stacking portion 192 can protect the source electrode 181 from being corroded in subsequent processes; after the drain electrode stacking portion 193 is stacked with the drain electrode 182, the drain electrode 182 can achieve ohmic contact with the active layer 191 through the drain electrode stacking portion 193, and also the drain electrode stacking portion 193 can protect the drain electrode 182 from being corroded in subsequent processes.

[0146] The source electrode stack 192, the drain electrode stack 193, the active layer 191, the data line stack 194 and the bridge stack 195 are made of metal oxide semiconductor materials, wherein the source electrode stack 192, the drain electrode stack 193, the data line stack 194 and the bridge stack 195 are transformed from semiconductors to conductors through hydrogenation treatment or ion doping treatment, while the active layer 191 remains as a semiconductor.

[0147] Furthermore, the array substrate further includes:

[0148] The pixel electrode 24 is located on the same layer and made of the same material as the source electrode stack 192, the drain electrode stack 193, the active layer 191, the data line stack 194, and the bridge stack 195. In this embodiment, since the pixel electrode 24, the source electrode stack 192, the drain electrode stack 193, the data line stack 194, and the bridge stack 195 are all integrally formed using the same metal oxide semiconductor layer 19, there is no need to separately fabricate the pixel electrode 24. At the same time, the pixel electrode 24 can be directly electrically connected to the drain electrode 182 through the drain electrode stack 193, and there is no need to use an additional mask to form a contact hole connecting the pixel electrode 24 and the drain electrode 182, which greatly saves costs.

[0149] The pixel electrode 24 is connected to the drain electrode stack portion 193 . The pixel electrode 24 is converted from a semiconductor to a conductor through hydrogenation or ion doping.

[0150] Furthermore, the array substrate further includes:

[0151] A third insulating layer 23 is formed on the source electrode stack 192, the drain electrode stack 193, the active layer 191, the bridge stack 195, the data line stack 194, and the pixel electrode 24. The third insulating layer 23 has a first via hole 101 formed at a position corresponding to the bridge stack 195. The bridge stack 195 is exposed through the first via hole 101. The material of the third insulating layer 23 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0152] A common electrode 25 is formed on the third insulating layer 23. The common electrode 25 fills the first conductive hole 101 and contacts the bridge stack 195. The common electrode 25 is electrically connected to the touch lead 123 through the bridge stack 195 and the touch bridge 184. The first transparent conductive layer is made of a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). In this embodiment, the first transparent conductive layer is indium tin oxide (ITO).

[0153] Furthermore, the array substrate of the present invention can be applied to a display panel, wherein the display panel includes a color filter substrate disposed opposite the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. The array substrate and the color filter substrate are bonded together with a sealant, thereby confining the liquid crystal layer within the area enclosed by the sealant.

[0154] Furthermore, the color filter substrate further includes a substrate and a color filter layer disposed on the substrate. The color filter layer includes red, green, and blue photoresist units. The red, green, and blue photoresist units are periodically arranged, with the red, green, and blue photoresist units arranged in columns. Furthermore, the red, green, and blue photoresist units are aligned with each sub-pixel on the array substrate, and their projections on the substrate overlap along the thickness of the display panel.

[0155] Furthermore, to prevent crosstalk between light emitted from adjacent sub-pixels, the color filter substrate may also include a black matrix (BM). For example, the black matrix pattern may include multiple parallel first light-shielding strips and multiple parallel second light-shielding strips. These first and second light-shielding strips form a grid, with each grid enclosing a sub-pixel. In this embodiment, the orthographic projections of the data lines 183 and touch leads 123 on the color filter substrate are located on the first and / or second light-shielding strips.

[0156] Second embodiment

[0157] Figures 3 to 8 Schematic diagrams S1-S6 of the cross-sectional manufacturing process of the manufacturing method of the array substrate of the present invention are shown. Figure 9 yes Figure 8 The planar structural diagram of the array substrate shown in FIG. Figures 10 to 15 Schematic diagram of the cross-sectional manufacturing process S7-S12 of the manufacturing method of the array substrate of the present invention, Figure 16 yes Figure 15 The planar structural diagram of the array substrate shown in FIG. Figures 17 to 20 Schematic diagram of the cross-sectional manufacturing process S13-S16 of the manufacturing method of the array substrate of the present invention, Figure 22 FIG17 is a cross-sectional manufacturing process diagram of the manufacturing method of the array substrate of the present invention, Figures 27 to 29 Schematic diagram S18'-S20' of a planar flow chart of a method for manufacturing an array substrate according to a second embodiment of the present invention, Figure 30 yes Figure 29 The cross-sectional structural diagram of the array substrate is shown in FIG.

[0158] Please refer to Figures 3 to 20 、 Figure 22 as well as Figures 27 to 30 The array substrate and its manufacturing method provided in the second embodiment of the present invention are basically the same as the array substrate and its manufacturing method in the first embodiment. The difference is that, in this embodiment, the manufacturing method and structure of the pixel electrode 24 and the third insulating layer after the entire surface is formed on the source stack part, the drain stack part, the active layer, the bridge stack part and the data line stack part are different.

[0159] Further, if Figures 27 to 30 As shown, the method for manufacturing the array substrate further includes:

[0160] S18': Figure 27 and Figure 30 As shown, the metal oxide semiconductor layer 19 is patterned so that the metal oxide semiconductor layer 19 only forms an active layer 191, a source electrode stack 192, a drain electrode stack 193, a data line stack 194 and a bridge stack 195, and a third insulating layer 23 is formed on the source electrode stack 192, the drain electrode stack 193, the active layer 191, the bridge stack 195 and the data line stack 194. The material of the third insulating layer 23 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0161] A flat layer 26 is formed on the entire surface of the third insulating layer 23 ; the flat layer 26 and the third insulating layer 23 are patterned to form second vias 102 in the flat layer 26 and the third insulating layer 23 at positions corresponding to the bridging laminate portion 195 , and the bridging laminate portion 195 is exposed through the second vias 102 .

[0162] S19': Figure 28 and Figure 30 As shown, a second transparent conductive layer is formed on the entire surface of the flat layer 26. The second transparent conductive layer is made of transparent metal oxides such as indium tin oxide (ITO) or indium zinc oxide (IZO). In this embodiment, the second transparent conductive layer is indium tin oxide (ITO).

[0163] The second transparent conductive layer is patterned to form a common electrode 25 . The common electrode 25 is filled into the second conductive hole 102 and contacts the bridge stack portion 195 . The common electrode 25 is conductively connected to the touch lead 123 via the bridge stack portion 195 and the touch bridge portion 184 .

[0164] A fourth insulating layer 27 is formed on the entire surface of the common electrode 25 , wherein the fourth insulating layer 27 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination thereof.

[0165] The fourth insulating layer 27 is patterned so that the fourth insulating layer 27, the planar layer 26, and the third insulating layer 23 form a third conductive hole 103 at a position corresponding to the drain stack portion 193, and the drain stack portion 193 is exposed through the third conductive hole 103. In this embodiment, the third conductive hole 103 is formed at a position corresponding to the drain stack portion 193 by the fourth insulating layer 27, the planar layer 26, and the third insulating layer 23. The fourth conductive hole is formed at the same time when the planar layer 26 and the third insulating layer 23 are patterned so that the planar layer 26 and the third insulating layer 23 form the second conductive hole 102 at a position corresponding to the bridge stack portion 195. Therefore, when the fourth insulating layer 27 is patterned, it is only necessary to etch the fourth insulating layer 27 at the position corresponding to the fourth conductive hole. The fifth conductive hole is connected to the fifth conductive hole through the fourth conductive hole to form a third conductive hole 103; or, the flat layer 26 and the third insulating layer 23 are patterned so that only the second conductive hole 102 is formed in the flat layer 26 and the third insulating layer 23 at the position corresponding to the bridge stack portion 195, and the fourth insulating layer 27 is patterned and the fourth insulating layer 27, the flat layer 26 and the third insulating layer 23 are etched at the same time using the same mask to form the third conductive hole 103 at the position corresponding to the drain stack portion 193.

[0166] S20': Figure 29 and Figure 30 As shown, a third transparent conductive layer is formed on the entire surface of the fourth insulating layer 27. The third transparent conductive layer is made of transparent metal oxides such as indium tin oxide (ITO) or indium zinc oxide (IZO). In this embodiment, the third transparent conductive layer is indium tin oxide (ITO).

[0167] The third transparent conductive layer is patterned to form a pixel electrode 24. The pixel electrode 24 is inserted into the third conductive hole 103 and contacts the drain electrode stack 193. The pixel electrode 24 is conductively connected to the drain electrode 182 through the drain electrode stack 193. In this embodiment, after forming a metal oxide semiconductor layer 19 entirely on the source electrode 181, the drain electrode 182, the data line 183, and the touch bridge 184, the metal oxide semiconductor layer 19 is patterned to form the source electrode stack 192, the drain electrode stack 193, the data line stack 194, and the bridge stack 195 without forming the pixel electrode 24. Furthermore, the method for manufacturing the array substrate further includes:

[0168] When forming the entire second transparent conductive layer on the flat layer 26, since the flat layer 26 is relatively soft, a third metal layer for supporting the spacer can also be formed on the flat layer 26. The third metal layer can be directly conductively connected to the common electrode 25, thereby increasing the thrust of the common electrode 25 as a common signal.

[0169] The present invention further provides an array substrate, the array substrate further comprising:

[0170] A third insulating layer 23 is formed on the source electrode stack 192 , the drain electrode stack 193 , the active layer 191 , the bridge stack 195 , and the data line stack 194 .

[0171] A planar layer 26 is formed on the third insulating layer 23. The planar layer 26 and the third insulating layer 23 form a second via 102 at a location corresponding to the bridge laminate 195. In this embodiment, since the planar layer 26 is relatively soft, a third metal layer for supporting the spacer can also be formed on the planar layer 26. The third metal layer can be directly conductively connected to the common electrode 25, thereby increasing the thrust of the common electrode 25 as a common signal.

[0172] The common electrode 25 formed on the planar layer 26 is filled in the second conductive hole 102 and contacts the bridge stacking portion 195 . The common electrode 25 is conductively connected to the touch lead 123 via the bridge stacking portion 195 and the touch bridge portion 184 .

[0173] A fourth insulating layer 27 is formed on the common electrode 25. The fourth insulating layer 27, the planarizing layer 26, and the third insulating layer 23 form a third via hole 103 at a position corresponding to the drain electrode stack 193. The fourth insulating layer 27 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.

[0174] The pixel electrode 24 is formed on the fourth insulating layer 27. The pixel electrode 24 fills the third conductive hole 103 and contacts the drain electrode stack 193. The pixel electrode 24 is conductively connected to the drain electrode 182 through the drain electrode stack 193. The pixel electrode 24 is made of a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). In this embodiment, the pixel electrode 24 is made of indium tin oxide (ITO).

[0175] Regarding other structures and manufacturing methods of the array substrate, please refer to the first embodiment and will not be described in detail here.

[0176] In this document, directional terms such as "up," "down," "left," "right," "front," and "back" are defined based on the positions of structures in the accompanying drawings and their relative positions to each other, for the sake of clarity and convenience in presenting the technical solution. It should be understood that the use of directional terms does not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein, are used solely for distinctions and are not intended to limit quantity or order.

[0177] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with this profession can make some changes or modifications to the technical contents disclosed above without departing from the scope of the technical solution of the present invention, which are equivalent embodiments of equivalent changes. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate includes: base (11); A scan line (121), a gate (122) and a touch lead (123) are formed on the substrate (11); the touch lead (123) comprises a wire portion (1231) and a connecting portion (1232); the wire portion (1231) is located between two adjacent scan lines (121); the connecting portion (1232) is located at both ends of the wire portion (1231) and is connected to the wire portion (1231); the gate (122) is connected to the scan line (121); A gate insulating layer (131) corresponding to the gate (121), the gate (122) and the wire portion (1231) is covered, and the connecting portion (1232) is not covered with the gate insulating layer (131); a second insulating layer (16) formed on the gate insulating layer (131), the second insulating layer (16) covering an area other than the scan line (121), the gate (122), and the touch lead (123), and the connecting portion (1232) is not covered with the second insulating layer (16); A source electrode (181), a drain electrode (182), a data line (183) and a touch bridge portion (184) are formed on the second insulating layer (16), wherein the source electrode (181) and the drain electrode (182) are spaced apart from each other to form a channel region (185), the data line (183) is connected to the source electrode (181), the touch bridge portion (184) spans the scan line (121), and the two ends of the touch bridge portion (184) are respectively in contact with the connecting portions (1232) at the ends of two adjacent touch leads (123), so that the two adjacent touch leads (123) are electrically connected through the touch bridge portion (184).

2. The array substrate according to claim 1, wherein: The array substrate further includes: A source electrode stacking portion (192), a drain electrode stacking portion (193), an active layer (191), a data line stacking portion (194) and a bridge stacking portion (195) are formed on the source electrode (181), the drain electrode (182), the data line (183) and the touch bridge portion (184); the active layer (191) is located in the channel region (185); the source electrode stacking portion (192) is stacked with the source electrode (181); the drain electrode stacking portion (193) is stacked with the drain electrode (182); the data line stacking portion (194) is stacked with the data line (183); and the bridge stacking portion (195) is stacked with the touch bridge portion (184); The source electrode stacking portion (192), the drain electrode stacking portion (193), the active layer (191), the data line stacking portion (194) and the bridge stacking portion (195) are made of metal oxide semiconductor materials, wherein the source electrode stacking portion (192), the drain electrode stacking portion (193), the data line stacking portion (194) and the bridge stacking portion (195) are transformed from semiconductors to conductors through hydrogenation treatment or ion doping treatment, while the active layer (191) remains as a semiconductor.

3. The array substrate according to claim 2, wherein: The array substrate further includes: a pixel electrode (24) located in the same layer as the source electrode stacking portion (192), the drain electrode stacking portion (193), the active layer (191), the data line stacking portion (194) and the bridge stacking portion (195) and made of the same material; The pixel electrode (24) is connected to the drain electrode stack (193), and the pixel electrode (24) is transformed from a semiconductor into a conductor through hydrogenation or ion doping.

4. The array substrate according to claim 3, wherein: The array substrate further includes: A third insulating layer (23) is formed on the source electrode stacking portion (192), the drain electrode stacking portion (193), the active layer (191), the bridge stacking portion (195), the data line stacking portion (194) and the pixel electrode (24), wherein the third insulating layer (23) forms a first conductive hole (101) at a position corresponding to the bridge stacking portion (195); A common electrode (25) is formed on the third insulating layer (23), the common electrode (25) is filled in the first conductive hole (101) and contacts the bridge laminate portion (195), and the common electrode (25) is conductively connected to the touch lead (123) through the bridge laminate portion (195) and the touch bridge portion (184).

5. The array substrate according to claim 2, wherein: The array substrate further includes: a third insulating layer (23) formed on the source electrode stacking portion (192), the drain electrode stacking portion (193), the active layer (191), the bridge stacking portion (195) and the data line stacking portion (194); A flat layer (26) is formed on the third insulating layer (23), wherein the flat layer (26) and the third insulating layer (23) form a second via hole (102) at a position corresponding to the bridge laminate portion (195); A common electrode (25) is formed on the flat layer (26), the common electrode (25) is filled in the second conductive hole (102) and contacts the bridge laminate portion (195), and the common electrode (25) is conductively connected to the touch lead (123) through the bridge laminate portion (195) and the touch bridge portion (184); A fourth insulating layer (27) is formed on the common electrode (25), wherein the fourth insulating layer (27), the flat layer (26) and the third insulating layer (23) form a third via hole (103) at a position corresponding to the drain electrode stacking portion (193); A pixel electrode (24) is formed on the fourth insulating layer (27), the pixel electrode (24) is filled in the third conductive hole (103) and is in contact with the drain electrode stacking portion (193), and the pixel electrode (24) is conductively connected to the drain electrode (182) through the drain electrode stacking portion (193).

6. A method for manufacturing an array substrate, characterized in that: The production method comprises: providing a substrate (11); forming a first metal layer (12) and a first insulating layer (13) on the entire surface of the substrate (11) in sequence; Covering the first insulating layer (13) with a first positive photoresist layer (14); The first positive photoresist layer (14) is exposed from the top of the substrate (11) using a first half-tone mask (15), wherein the first half-tone mask (15) comprises a first opaque area (151), a first semi-transparent area (152) and a first fully transparent area (153), the first opaque area (151) corresponding to the scanning line (121), the gate (122) and the wire portion (1231) of the touch lead (123), the first semi-transparent area (152) corresponding to the connecting portion (1232) of the touch lead (123), and the first fully transparent area (153) corresponding to other areas; Developing the first positive photoresist layer (14), retaining the first positive photoresist layer (14) at positions corresponding to the scanning line (121), the gate (122) and the wire portion (1231), retaining the first positive photoresist layer (14) at positions corresponding to the connecting portion (1232), and the thickness of the first positive photoresist layer (14) corresponding to the connecting portion (1232) is smaller than the thickness of the first positive photoresist layer (14) corresponding to the scanning line (121), the gate (122) and the wire portion (1231), while removing the first positive photoresist layer (14) from other areas; The first insulating layer (13) and the first metal layer (12) are patterned so that the first metal layer (12) forms the scan line (121), the gate (122) and the touch lead (123), and the first insulating layer (13) forms a gate insulating layer (131) covering the scan line (121), the gate (122) and the touch lead (123), wherein the touch lead (123) comprises the wire portion (1231) and the connecting portion (1232), the wire portion (1231) is located between two adjacent scan lines (121), the connecting portion (1232) is respectively located at both ends of the wire portion (1231) and connected to the wire portion (1231), and the gate (122) is connected to the scan line (121); ashing and thinning the first positive photoresist layer (14) to remove the first positive photoresist layer (14) corresponding to the connecting portion (1232), but retaining the first positive photoresist layer (14) corresponding to the scanning line (121), the gate (122) and the wire portion (1231); Performing a patterning process on the first insulating layer (13) again to remove the gate insulating layer (131) covering the connecting portion (1232), thereby exposing the connecting portion (1232); stripping the first positive photoresist layer (14); forming a second insulating layer (16) on the entire surface of the gate insulating layer (131); Covering the second insulating layer (16) with a negative photoresist layer (17); exposing the negative photoresist layer (17) from the bottom of the substrate (11); Developing the negative photoresist layer (17), removing the negative photoresist layer (17) at positions corresponding to the scan line (121), the gate (122), and the touch lead (123), while retaining the negative photoresist layer (17) in other areas; Performing a patterning process on the second insulating layer (16), removing the second insulating layer (16) corresponding to the scan line (121), the gate (122), and the touch lead (123), so as to expose the gate insulating layer (131) and the connecting portion (1232); peeling off the negative photoresist layer (17); forming a second metal layer (18) on the entire surface of the second insulating layer (16); The second metal layer (18) is patterned to form a source electrode (181), a drain electrode (182), a data line (183) and a touch bridge portion (184) on the second metal layer (18), wherein the source electrode (181) and the drain electrode (182) are spaced apart from each other to form a channel region (185), the data line (183) is connected to the source electrode (181), the touch bridge portion (184) spans the scan line (121), and the two ends of the touch bridge portion (184) are respectively in contact with the connecting portions (1232) at the ends of two adjacent touch leads (123), so that the two adjacent touch leads (123) are electrically connected through the touch bridge portion (184).

7. The method for manufacturing an array substrate according to claim 6, wherein: The production method further comprises: forming a metal oxide semiconductor layer (19) on the source electrode (181), the drain electrode (182), the data line (183), and the touch bridge portion (184); Covering the metal oxide semiconductor layer (19) with a second positive photoresist layer (21); The second positive photoresist layer (21) is exposed using a second half-tone mask (22), wherein the second half-tone mask (22) comprises a second light-impermeable area (221), a second semi-transparent area (222), and a second fully light-transmitting area (223), the second light-impermeable area (221) corresponds to the active layer (191), the second semi-transparent area (222) corresponds to the source electrode stacking portion (192), the drain electrode stacking portion (193), the data line stacking portion (194), and the bridge stacking portion (195), and the second fully light-transmitting area (223) corresponds to other areas; Developing the second positive photoresist layer (21), retaining the second positive photoresist layer (21) at a position corresponding to the active layer (191), retaining the second positive photoresist layer (21) at a position corresponding to the source electrode stacking portion (192), the drain electrode stacking portion (193), the data line stacking portion (194), and the bridge stacking portion (195), and the thickness of the second positive photoresist layer (21) corresponding to the source electrode stacking portion (192), the drain electrode stacking portion (193), the data line stacking portion (194), and the bridge stacking portion (195) is less than the thickness of the second positive photoresist layer (21) corresponding to the active layer (191), while removing the second positive photoresist layer (21) from other areas; The metal oxide semiconductor layer (19) is patterned to form the active layer (191), the source electrode stacking portion (192), the drain electrode stacking portion (193), the data line stacking portion (194) and the bridge stacking portion (195), wherein the active layer (191) is located in the channel region (185), the source electrode stacking portion (192) is stacked with the source electrode (181), the drain electrode stacking portion (193) is stacked with the drain electrode (182), the data line stacking portion (194) is stacked with the data line (183), and the bridge stacking portion (195) is stacked with the touch bridge portion (184); The second positive photoresist layer (21) is ashed and thinned to remove the second positive photoresist layer (21) corresponding to the source electrode stacking portion (192), the drain electrode stacking portion (193), the data line stacking portion (194) and the bridge stacking portion (195), but the second positive photoresist layer (21) corresponding to the active layer (191) is retained; The source electrode stacking portion (192), the drain electrode stacking portion (193), the data line stacking portion (194) and the bridge stacking portion (195) are subjected to hydrogenation treatment or ion doping treatment, so that the source electrode stacking portion (192), the drain electrode stacking portion (193), the data line stacking portion (194) and the bridge stacking portion (195) are transformed from semiconductors to conductors, while the active layer (191) remains as a semiconductor; The second positive photoresist layer (21) is peeled off.

8. The method for manufacturing an array substrate according to claim 7, wherein: The production method further comprises: forming a third insulating layer (23) on the entire surface of the source electrode stacking portion (192), the drain electrode stacking portion (193), the active layer (191), the bridge stacking portion (195), and the data line stacking portion (194); Performing a patterning process on the third insulating layer (23) so as to form a first conductive hole (101) in the third insulating layer (23) at a position corresponding to the bridge laminate portion (195), and the bridge laminate portion (195) is exposed through the first conductive hole (101); forming a first transparent conductive layer on the entire surface of the third insulating layer (23); The first transparent conductive layer is patterned to form a common electrode (25) on the first transparent conductive layer. The common electrode (25) is filled into the first conductive hole (101) and contacts the bridge stacking portion (195). The common electrode (25) is conductively connected to the touch lead (123) through the bridge stacking portion (195) and the touch bridge portion (184).

9. The method for manufacturing an array substrate according to claim 7, wherein: The production method further comprises: When the second positive photoresist layer (21) is exposed using a second half-tone mask (22), the second semi-transparent area (222) also corresponds to the pixel electrode (24); When the second positive photoresist layer (21) is developed, the second positive photoresist layer (21) is retained at a position corresponding to the pixel electrode (24), and the thickness of the second positive photoresist layer (21) corresponding to the pixel electrode (24) is smaller than the thickness of the second positive photoresist layer (21) corresponding to the active layer (191); When the metal oxide semiconductor layer (19) is patterned, the metal oxide semiconductor layer (19) is further formed into the pixel electrode (24), wherein the pixel electrode (24) is connected to the drain electrode stacking portion (193); When the second positive photoresist layer (21) is ashed and thinned, the second positive photoresist layer (21) corresponding to the pixel electrode (24) is also removed; When the source electrode stacking portion (192), the drain electrode stacking portion (193), the data line stacking portion (194) and the bridge stacking portion (195) are subjected to hydrogenation treatment or ion doping treatment, the pixel electrode (24) is also subjected to hydrogenation treatment or ion doping treatment at the same time, so that the pixel electrode (24) is transformed from a semiconductor into a conductor.

10. The method for manufacturing an array substrate according to claim 7, wherein: The production method further comprises: forming a third insulating layer (23) on the entire surface of the source electrode stacking portion (192), the drain electrode stacking portion (193), the active layer (191), the bridge stacking portion (195), and the data line stacking portion (194); forming a flat layer (26) covering the entire surface of the third insulating layer (23); The flat layer (26) and the third insulating layer (23) are patterned to form a second conductive hole (102) in the flat layer (26) and the third insulating layer (23) at a position corresponding to the bridge laminate portion (195), and the bridge laminate portion (195) is exposed through the second conductive hole (102); forming a second transparent conductive layer on the entire surface of the flat layer (26); The second transparent conductive layer is patterned to form a common electrode (25) on the second transparent conductive layer. The common electrode (25) is filled into the second conductive hole (102) and contacts the bridge laminate portion (195). The common electrode (25) is conductively connected to the touch lead (123) through the bridge laminate portion (195) and the touch bridge portion (184). forming a fourth insulating layer (27) covering the entire surface of the common electrode (25); The fourth insulating layer (27) is patterned to form a third conductive hole (103) at a position corresponding to the drain electrode stacking portion (193) among the fourth insulating layer (27), the flat layer (26) and the third insulating layer (23), and the drain electrode stacking portion (193) is exposed through the third conductive hole (103); forming a third transparent conductive layer on the entire surface of the fourth insulating layer (27); The third transparent conductive layer is patterned to form a pixel electrode (24) on the third transparent conductive layer. The pixel electrode (24) is filled into the third conductive hole (103) and contacts the drain electrode stacking portion (193). The pixel electrode (24) is conductively connected to the drain electrode (182) through the drain electrode stacking portion (193).

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