Display device

Abstract

A display device includes a substrate; an anticorrosion layer over the substrate and including an inorganic material; a first conductive layer over the anticorrosion layer and including aluminum or an aluminum alloy; a first insulating film over the first conductive layer; a semiconductor layer over the first insulating film and including a channel region of a transistor; a second insulating film over the semiconductor layer; and a second conductive layer over the second insulating film and including a barrier layer including titanium and a main conductive layer including aluminum or an aluminum alloy, wherein the semiconductor layer includes an oxide semiconductor, and the barrier layer is between the semiconductor layer and the main conductive layer and overlaps with the channel region of the transistor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0087975, filed on July 16, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device. Background Technology

[0004] With the development of multimedia technology, display devices are becoming increasingly important. Therefore, various display devices, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs), are now in use.

[0005] A typical display device includes multiple pixels representing different colors (e.g., capable of displaying different colors), and thus enables color display. To enable the pixels to operate independently and display different colors, the display device may include drive signal lines for transmitting drive signals and various functional electrodes disposed within the pixels.

[0006] For example, the drive signal lines need to have low resistance, high thermal stability, and ease of processing. Summary of the Invention

[0007] Various aspects of embodiments of this disclosure relate to a display device capable of providing improved display quality by reducing signal delay while achieving high resolution, and to a method of manufacturing the display device.

[0008] However, the aspects of the embodiments of this disclosure are not limited to or restricted to those set forth herein. The above and other aspects of the embodiments of this disclosure will become more apparent to those skilled in the art upon which this disclosure pertains from the following detailed description of the disclosure.

[0009] An embodiment of the display device includes: a substrate; an anti-corrosion layer on the substrate and comprising (e.g., an inorganic material); a first conductive layer on the anti-corrosion layer and comprising (e.g., aluminum or an aluminum alloy); a first insulating film on the first conductive layer; a semiconductor layer on the first insulating film and including a channel region of a transistor; a second insulating film on the semiconductor layer; and a second conductive layer on the second insulating film, comprising a barrier layer comprising (e.g., titanium) and a main conductive layer comprising (e.g., aluminum or an aluminum alloy), wherein the semiconductor layer comprises (e.g., an oxide semiconductor), and the barrier layer is located between the semiconductor layer and the main conductive layer and overlaps with the channel region of the transistor.

[0010] An embodiment of the display device includes: a substrate; a semiconductor layer on the substrate, the semiconductor layer including a channel region of a transistor; a first insulating film on the semiconductor layer; a first conductive layer on the first insulating film, including a barrier layer comprising (e.g.,) titanium, a main conductive layer comprising (e.g.,) aluminum or an aluminum alloy, and a capping layer comprising (e.g.,) titanium; a second insulating film on the first conductive layer; and a second conductive layer on the second insulating film, including a source electrode and a drain electrode of the transistor, wherein the semiconductor layer includes an oxide semiconductor, the first conductive layer includes a gate electrode of the transistor, and the barrier layer is located between the semiconductor layer and the main conductive layer and overlaps with the channel region of the transistor.

[0011] According to the foregoing and other aspects of embodiments of this disclosure, improved display quality can be provided while providing high resolution by reducing signal latency.

[0012] Other features and aspects of embodiments of this disclosure may be apparent from the following detailed description, accompanying drawings, and claims. Attached Figure Description

[0013] The above and other aspects and features of the embodiments of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in more detail:

[0014] Figure 1 This is a plan view of a display device according to an embodiment of the present disclosure;

[0015] Figure 2 yes Figure 1 A block diagram of a display device;

[0016] Figure 3yes Figure 1 The equivalent circuit diagram of the pixels of the display device;

[0017] Figure 4 This is a cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0018] Figure 5 yes Figure 4 An enlarged cross-sectional view of region A;

[0019] Figure 6 yes Figure 4 Enlarged cross-sectional view of region B;

[0020] Figure 7 yes Figure 4 Enlarged cross-sectional view of region C;

[0021] Figure 8 This is a cross-sectional view illustrating how hydrogen diffusion into a semiconductor layer having a barrier layer is prevented or reduced according to embodiments of the present disclosure.

[0022] Figure 9 The diagram is shown according to Figure 8 The curves (a) and (b) show the changes in driving current with or without the presence of the blocking layer.

[0023] Figures 10 to 12 This is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present disclosure;

[0024] Figure 13 This is a cross-sectional view of a display device according to another embodiment of the present disclosure;

[0025] Figure 14 This is a cross-sectional view of a display device according to another embodiment of the present disclosure;

[0026] Figure 15 This is a cross-sectional view of a display device according to another embodiment of the present disclosure; and

[0027] Figure 16 This is a cross-sectional view of a display device according to another embodiment of the present disclosure. Detailed Implementation

[0028] In the following description, the present disclosure will now be described more fully with reference to the accompanying drawings, in which some embodiments of the present disclosure are illustrated. However, the present disclosure may be implemented in many different forms and should not be construed as limiting itself to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be exhaustive and complete, and will fully convey the scope of the disclosure to those skilled in the art. As used herein, when describing embodiments of the present disclosure, the term “may” means “one or more embodiments of the present disclosure”.

[0029] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on said other layer or substrate, or there may be an intermediate layer. Throughout this specification, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Thus, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. Describing an element as a “first” element may not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc. As used herein, the terms “substantially,” “approximately,” “approximately,” and similar terms are used as approximate terms rather than as terms of degree and are intended to explain the inherent biases of measurements or calculations that will be recognized by those skilled in the art.

[0031] Furthermore, any numerical ranges listed herein are intended to include all subranges of the same numerical precision that fall within the listed range. For example, the range “1.0 to 10.0” is intended to include all subranges between (and including) the listed minimum value of 1.0 and the listed maximum value of 10.0, i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit listed herein is intended to include all lower numerical limits therein, and any minimum numerical limit listed in this specification is intended to include all higher numerical limits therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly list any subranges that fall within the scope expressly listed herein.

[0032] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0033] Figure 1 This is a plan view of a display device according to an embodiment of the present disclosure. Figure 2 yes Figure 1 A block diagram of the display device.

[0034] Reference Figure 1 and Figure 2The display device 1, which serves as a means of displaying moving or still images, can be used not only as a display screen for portable electronic devices, but also as a display screen for various other suitable products, such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), and various other suitable products such as televisions (TVs), laptops, monitors, billboards, and Internet of Things (IoT) devices.

[0035] The display device 1 may have a substantially rectangular shape in a plan view. The display device 1 may have a rectangular shape with right-angled corners in a plan view, but this disclosure is not limited thereto. In some embodiments, the display device 1 may have a rectangular shape with rounded corners in a plan view.

[0036] Reference Figure 1 and Figure 2 In the plan view, the first direction DR1 refers to the horizontal direction of the display device 1, the second direction DR2 refers to the vertical direction of the display device 1, and the third direction DR3 refers to the thickness direction of the display device 1. The first direction DR1 and the second direction DR2 may intersect or intersect each other perpendicularly, and the third direction DR3, which is the direction that intersects or intersects the plane containing the first direction DR1 and the second direction DR2, may intersect or intersect the first direction DR1 and the second direction DR2 perpendicularly. However, the first direction DR1, the second direction DR2, and the third direction DR3 are relative directions and are therefore not specifically limited.

[0037] Unless otherwise stated, the terms “above,” “top surface,” and “upper” as used herein may refer to one side of the display surface of display device 1 (e.g., the side of display device 1 where an image is to be displayed), and the terms “below,” “bottom surface,” and “lower” may refer to the opposite side of one side of the display surface of display device 1.

[0038] The display device 1 may include a display panel 10, a timing controller 21, a data driver 22, and a scan driver 30.

[0039] Display panel 10 may be an organic light-emitting diode (OLED) display panel. Hereinafter, display panel 10 will be described as, for example, an OLED display panel, but this disclosure is not limited thereto. That is, various other suitable display panels, such as liquid crystal display (LCD) panels, quantum dot OLED display panels, quantum dot LCD panels, quantum nano-light-emitting diode (QNED) display panels, and micro-light-emitting diode (micro-LED) display panels, may be used as (e.g., serve as) display panel 10.

[0040] Display panel 10 may include a display area DA for displaying images and a non-display area NDA for not displaying images. In a plan view, display panel 10 may be divided into display area DA and non-display area NDA. Non-display area NDA may be configured to surround (e.g., partially or completely surround) display area DA. Non-display area NDA may form a border of display panel 10.

[0041] The display area DA in a planar drawing can have a rectangular shape with right angles or rounded corners. However, the planar shape of the display area DA is not specifically limited. That is, the display area DA in a planar drawing can have various other suitable shapes such as circles or ellipses.

[0042] The display area DA may include multiple pixels PX. The multiple pixels PX may be arranged in a matrix. Each of the multiple pixels PX may include an emissive layer and a circuit layer for controlling the amount of light emitted by the emissive layer. The circuit layer may include wiring, electrodes, and at least one transistor. The emissive layer may include (e.g., is) an organic light-emitting material. The emissive layer may be sealed by an encapsulation film. The structure of the pixel PX will be described in more detail later.

[0043] The non-display area NDA can be configured to be adjacent to the two short sides and two long sides of the display area DA. In this case, the non-display area NDA can surround all the sides of the display area DA to form the edge of the display area DA. However, this disclosure is not limited thereto. In some embodiments, the non-display area NDA can be configured to be adjacent only to the two short sides or the two long sides of the display area DA.

[0044] Multiple scan lines SL1, SL2, ..., SLk (hereinafter referred to as "SL1 to SLk") (where k is an integer of 2 or greater), multiple data lines DL1, DL2, ..., DLj (hereinafter referred to as "DL1 to DLj") (where j is an integer of 2 or greater), and multiple power lines coupled (e.g., connected) to pixel PX can be arranged in the display area DA. Scan lines SL1 to SLk can extend in a first direction DR1 and can be arranged relative to each other along a second direction DR2. Data lines DL1 to DLj can extend in the second direction DR2 and can be arranged relative to each other along the first direction DR1.

[0045] The display panel 10 may include a plurality of pixels PX, which are respectively disposed at the intersections or junctions between scan lines SL1 to SLk and data lines DL1 to DLj, and thus the plurality of pixels PX are arranged in a matrix. Each of the pixels PX may be coupled (e.g., connected) to at least one of the scan lines SL1 to SLk and one of the data lines DL1 to DLj.

[0046] Timing controller 21 receives digital video data RGB and timing signal CS from the host system. In some embodiments, timing controller 21 may (e.g., from the host system) receive digital video data RGB and may generate digital video data DATA and / or transmit digital video data DATA to data driver 22. The host system may be an application processor of a smartphone or tablet PC, or a system-on-chip of a monitor or TV.

[0047] The timing controller 21 can generate control signals for controlling the operating timing of the data driver 22 and the scan driver 30. In some embodiments, the timing controller 21 can receive a timing signal CS (e.g., from a host system). The control signals may include a source control signal CONT2 for controlling the operating timing of the data driver 22 and a scan control signal CONT1 for controlling the operating timing of the scan driver 30.

[0048] The scan driver 30 receives the scan control signal CONT1 from the timing controller 21. The scan driver 30 can generate scan signals S1, S2, ..., Sk (hereinafter referred to as "S1 to Sk") based on the scan control signal CONT1 (where k is an integer of 2 or greater), and can provide the scan signals S1 to Sk to the scan lines SL1 to SLk of the display panel 10. The scan driver 30 can be formed in the non-display area NDA of the display panel 10. The scan driver 30 can be formed as an integrated circuit (IC).

[0049] Data driver 22 receives digital video data DATA and source control signal CONT2 from timing controller 21. Data driver 22 can convert digital video data DATA into analog data voltage according to source control signal CONT2 and provide analog data voltage to data lines DL1 to DLj. Pixel PX can emit light of a specific brightness based on the driving current provided to the light-emitting element according to the data signals D1, D2, ..., Dj (hereinafter referred to as "D1 to Dj") provided to the light-emitting element via data lines DL1 to DLj (where j is an integer of 2 or greater).

[0050] The power supply circuit can generate a voltage from the main power supply to drive the display panel 10, and can supply the generated voltage to the display panel 10. For example, the power supply circuit can generate a first power supply voltage ELVDD and a second power supply voltage ELVSS from the main power supply to drive the display panel 10 (see...). Figure 3 And the first power supply voltage ELVDD and the second power supply voltage ELVSS can be supplied to the first power line ELVDL and the second power line ELVSL of the display panel 10 (see...). Figure 3 Furthermore, the power supply circuit can generate drive voltages from the main power supply to drive the timing controller 21, the data driver 22, and the scan driver 30. The power supply circuit can be formed as an integrated circuit (IC) and can be mounted on a circuit board, but this disclosure is not limited thereto.

[0051] Figure 3 yes Figure 1 The equivalent circuit diagram of the pixels of the display device.

[0052] Reference Figure 3 A pixel PX may include a first transistor TR1, a second transistor TR2, a light-emitting element OLED, and a capacitor Cst. Figure 3 The illustration shows a pixel PX with a "2 transistors-1 capacitor" (2T1C) structure comprising two transistors and one capacitor, but this disclosure is not limited thereto. In some embodiments, the pixel PX may include more than two transistors and more than one capacitor. That is, various other suitable structures (such as 3T1C, 6T1C, 7T1C, and / or 5T2C structures, for example) may also be applied to the pixel PX.

[0053] Each of the first transistor TR1 and the second transistor TR2 may include a first source / drain electrode (e.g., a source electrode or a drain electrode), a second source / drain electrode (e.g., a drain electrode or a source electrode), and a gate electrode. One of the first source / drain electrode and the second source / drain electrode may be a source electrode, and the other of the first source / drain electrode and the second source / drain electrode may be a drain electrode.

[0054] The first transistor TR1 and the second transistor TR2 can be formed as thin-film transistors (TFTs). Figure 3 The first transistor TR1 and the second transistor TR2 are shown to be N-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but this disclosure is not limited thereto. For example, the first transistor TR1 and the second transistor TR2 can be formed as P-type MOSFETs. In this case, the positions of the source and drain electrodes of each of the first transistor TR1 and the second transistor TR2 can be reversed. Hereinafter, the first transistor TR1 and the second transistor TR2 will be described as, for example, N-type MOSFETs.

[0055] The first transistor TR1 can be a driving transistor. For example, the gate electrode of the first transistor TR1 can be coupled (e.g., connected) to both the second source / drain electrode of the second transistor TR2 and the second electrode of the capacitor Cst. The first source / drain electrode of the first transistor TR1 can be coupled (e.g., connected) to the first power line ELVDL. The second source / drain electrode of the first transistor TR1 can be coupled (e.g., connected) to the anode electrode of the light-emitting element OLED. The first transistor TR1 can receive a data signal Dm (where m is an integer of 1 or greater) and provide driving current to the light-emitting element OLED according to the switching operation of the second transistor TR2.

[0056] The gate electrode of the second transistor TR2 can be coupled (e.g., connected) to the scan line SL. The first source / drain electrode of the second transistor TR2 can be coupled (e.g., connected) to the data line DL. The second source / drain electrode of the second transistor TR2 can be coupled (e.g., connected) to the gate electrode of the first transistor TR1 and the second electrode of the capacitor Cst. The second transistor TR2 can be turned on by a scan signal Sn (where n is an integer of 1 or greater) to perform a switching operation that transmits the data signal Dm to the gate electrode of the first transistor TR1.

[0057] The first electrode of capacitor Cst can be coupled (e.g., connected) to the first power line ELVDL and the first source / drain electrode of the first transistor TR1, and the second electrode of capacitor Cst can be coupled (e.g., connected) to the gate electrode of the first transistor TR1 and the second source / drain electrode of the second transistor TR2. Capacitor Cst can uniformly maintain the data voltage applied to the gate electrode of the first transistor TR1.

[0058] The OLED light-emitting element can emit light according to the driving current from the first transistor TR1. The OLED light-emitting element can be an OLED including an anode electrode (or a first electrode), an organic light-emitting layer, and a cathode electrode (or a second electrode). The anode electrode of the OLED light-emitting element can be coupled (e.g., connected) to the second source / drain electrode of the first transistor TR1, and the cathode electrode of the OLED light-emitting element can be coupled (e.g., connected) to the second power line ELVSL, and a power supply voltage lower than the first power supply voltage ELVDD (e.g., the second power supply voltage ELVSS) is applied to the second power line ELVSL.

[0059] The cross-sectional structure of pixel PX will be described below.

[0060] Figure 4 This is a cross-sectional view of a display panel according to an embodiment of the present disclosure. Figure 4 It shows Figure 3Example cross-sectional view of the first transistor TR1 and the second transistor TR2.

[0061] Reference Figure 4 The display panel 10 includes a semiconductor layer SCL, multiple conductive layers, and multiple insulating layers all disposed on a substrate SUB. The conductive layers may include a first conductive layer 100, a second conductive layer 200, a third conductive layer 300, and an anode electrode ANO. The insulating layers may include an anti-corrosion layer CB, a first insulating film IL1, a second insulating film IL2, a third insulating film IL3, and a via layer VIA. The anti-corrosion layer CB, the first conductive layer 100, the first insulating film IL1, the semiconductor layer SCL, the second insulating film IL2, the second conductive layer 200, the third insulating film IL3, the third conductive layer 300, the via layer VIA, the anode electrode ANO, and the pixel defining film PDL can be sequentially arranged on the substrate SUB. One or more of the following components—the anti-corrosion layer CB, the first conductive layer 100, the first insulating film IL1, the semiconductor layer SCL, the second insulating film IL2, the second conductive layer 200, the third insulating film IL3, the third conductive layer 300, the via layer VIA, the anode electrode ANO, and the pixel defining film PDL—may be formed as a single layer or as a stack of multiple films. Other layers may be further disposed between the various components of the anti-corrosion layer CB, the first conductive layer 100, the first insulating film IL1, the semiconductor layer SCL, the second insulating film IL2, the second conductive layer 200, the third insulating film IL3, the third conductive layer 300, the via layer VIA, the anode electrode ANO, and the pixel defining film PDL.

[0062] A substrate SUB supports layers disposed above the substrate SUB. The substrate SUB can be generally (e.g., suitably) transparent and can have a suitably high light transmittance. The substrate SUB can include (e.g., is) inorganic materials such as glass and / or quartz. For example, the inorganic material can include (e.g., is) silicon dioxide (SiO2), but this disclosure is not limited thereto. The substrate SUB can be a transparent plate or film, but this disclosure is not limited thereto.

[0063] The substrate SUB can be a suitably rigid substrate, but this disclosure is not limited thereto. In some embodiments, the substrate SUB can be a suitably flexible substrate that is bendable, foldable, and / or rollable. The substrate SUB can be an ultrathin glass (UTG) substrate with a thickness of 0.1 mm or less. As used herein, the term “mm” can mean equal to 10 mm. -3 The distance is meters. In this case, the thickness and weight of the display device 1 can usually be reduced, and therefore, user convenience can be maximized or improved.

[0064] The anti-corrosion layer CB can be disposed on the substrate SUB. The anti-corrosion layer CB can prevent or inhibit the diffusion of impurity ions and / or the penetration of moisture and / or external air. As described later, even when the first conductive layer 100 disposed on the anti-corrosion layer CB comprises (e.g., is) aluminum (Al) or an Al alloy, the anti-corrosion layer CB can prevent, reduce, or inhibit corrosion of the first conductive layer 100, and therefore, enable smooth operation of the display panel 10. That is, if the main conductive layer 110 comprises (e.g., is) Al (see... Figure 5 If the substrate SUB is in direct contact with the main conductive layer 110, moisture and / or external air can diffuse through the substrate SUB into the substrate SUB or into the main conductive layer 110, and then react with the Al of the main conductive layer 110. Therefore, even if the substrate SUB comprises (e.g., is) glass and / or quartz, the main conductive layer 110 will be oxidized and / or corroded. If the main conductive layer 110 is oxidized and / or corroded, the resistance of the main conductive layer 110 will increase, and therefore, the resistance of the first conductive layer 100 will also increase.

[0065] Therefore, by arranging an anti-corrosion layer CB between the substrate SUB and the main conductive layer 110, the diffusion of moisture and / or external air into the main conductive layer 110 can be suppressed, reduced, or prevented. Consequently, the resistance of the first conductive layer 100 can be kept low, and the display quality and reliability of the display device 1 can be improved. For example, an increase in the resistance of the first conductive layer 100 can be prevented, reduced, or suppressed. The anti-corrosion layer CB can have a thickness tCB of, for example, 1000 angstroms to 2000 angstroms or 500 angstroms to 3000 angstroms (see [link to relevant documentation]). Figure 5 However, this disclosure is not limited thereto. As used herein, the term "E" refers to... "Can be represented as equal to 10" -10 A distance of meters.

[0066] The anti-corrosion layer CB may include (e.g., is) an inorganic material. For example, the anti-corrosion layer CB may include (e.g., is) silicon nitride, silicon oxide, and / or silicon oxynitride, but this disclosure is not limited thereto.

[0067] The first conductive layer 100 is disposed on the anti-corrosion layer CB. The first conductive layer 100 can be disposed below the semiconductor layer SCL, and can perform the functions of a light-shielding pattern and a lower conductive layer for the semiconductor layer SCL.

[0068] The first conductive layer 100 may include a first lower conductive pattern BML1 and a second lower conductive pattern BML2. The first lower conductive pattern BML1 and the second lower conductive pattern BML2 can prevent or block light incident from below the display panel 10 from entering semiconductor patterns ACT1 and ACT2, which are the active layers of the first transistor TR1 and the second transistor TR2, respectively, and are respectively disposed above the first lower conductive pattern BML1 and the second lower conductive pattern BML2. For example, the first lower conductive pattern BML1 and the second lower conductive pattern BML2 can respectively prevent or block light incident from below the display panel 10 from entering the channel regions of semiconductor patterns ACT1 and ACT2.

[0069] In some embodiments, the first lower conductive pattern BML1 may be configured to at least cover the channel region of the semiconductor pattern ACT1 of the first transistor TR1, and the second lower conductive pattern BML2 may be configured to at least cover the channel region of the semiconductor pattern ACT2 of the second transistor TR2. In some embodiments, the first lower conductive pattern BML1 may be configured to cover the entire semiconductor pattern ACT1 of the first transistor TR1, and the second lower conductive pattern BML2 may be configured to cover the entire semiconductor pattern ACT2 of the second transistor TR2.

[0070] A first lower conductive pattern BML1 and a second lower conductive pattern BML2 can be disposed below the semiconductor layer SCL and can be configured as (e.g., can be or can be used as) a lower conductive layer for the semiconductor layer SCL. In some embodiments, the first lower conductive pattern BML1 can be electrically coupled (e.g., electrically connected) to the second source / drain electrode SD2 of the first transistor TR1. Furthermore, the second lower conductive pattern BML2 can be electrically coupled (e.g., electrically connected) to the gate electrode GAT2 of the second transistor TR2. Therefore, the device characteristics of the first transistor TR1 as a driving transistor and the device characteristics of the second transistor TR2 as a switching transistor can be improved. For example, the first transistor TR1 as a driving transistor can easily control the driving current, and the second transistor TR2 as a switching transistor can easily be turned on or off.

[0071] The first conductive layer 100 may include not only the first lower conductive pattern BML1 and the second lower conductive pattern BML2, but also [other components]. Figure 3 The first power line ELVDL corresponds to the first power wiring, and Figure 3 Data cable DL corresponding data cabling and Figure 3 The first electrode of capacitor Cst.

[0072] The first conductive layer 100 may include (for example,) Al. Because Al has a lower resistance than molybdenum (Mo), a conductive layer including (for example,) Al or an Al alloy can conduct electricity sufficiently even at small thicknesses compared to conductive layers including (for example,) Mo, etc.

[0073] The stacked structure of the first conductive layer 100 will be described below.

[0074] A first insulating film IL1 is disposed on the first conductive layer 100. The first insulating film IL1 covers the first conductive layer 100 and may be disposed on the entire surface of the anti-corrosion layer CB. The first insulating film IL1 may include contact holes, for example, contact holes corresponding to contact holes CNT3 and CNT5. The first insulating film IL1 may perform the function of an interlayer insulating film that insulates the first conductive layer 100 and the semiconductor layer SCL. The first insulating film IL1 may include (for example, is) at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0075] A semiconductor layer SCL can be disposed on a first insulating film IL1. The semiconductor layer SCL may include a semiconductor pattern ACT1 of a first transistor TR1 and a semiconductor pattern ACT2 of a second transistor TR2. The semiconductor pattern ACT1 of the first transistor TR1 can be an active layer of the first transistor TR1, and the semiconductor pattern ACT2 of the second transistor TR2 can be an active layer of the second transistor TR2. The semiconductor pattern ACT1 of the first transistor TR1 and the semiconductor pattern ACT2 of the second transistor TR2 can be disposed in each pixel PX.

[0076] The semiconductor pattern ACT1 of the first transistor TR1 may include a channel region of the first transistor TR1 that overlaps with the gate electrode GAT1 of the first transistor TR1 in the thickness direction (e.g., in a planar view), and may also include a first source / drain region and a second source / drain region of the first transistor TR1 disposed on both sides of the channel region of the first transistor TR1. The first source / drain region and the second source / drain region of the first transistor TR1 may be conductive regions, and may be more conductive than the channel region of the first transistor TR1, but with lower resistance.

[0077] The semiconductor pattern ACT2 of the second transistor TR2 may include a channel region of the second transistor TR2 that overlaps with the gate electrode GAT2 of the second transistor TR2 in the thickness direction (e.g., in a planar view), and may also include a first source / drain region and a second source / drain region of the second transistor TR2 disposed on both sides of the channel region of the second transistor TR2. The first source / drain region and the second source / drain region of the second transistor TR2 may be conductive regions, and may be more conductive than the channel region of the second transistor TR2, but with lower resistance.

[0078] The semiconductor layer SCL may include (e.g., is) an oxide semiconductor. For example, the oxide semiconductor may include (e.g., is) a binary compound AB comprising indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), Al, hafnium (Hf), zirconium (Zr), and / or magnesium (Mg). x ternary compound AB x C y Quaternary compound AB x C y D z Or pentagonal compound AB x C y D z E w For example, the semiconductor layer SCL may include (e.g., is) indium gallium zinc oxide (IGZO) or indium tin gallium zinc oxide (ITGZO).

[0079] The second insulating film IL2 may be disposed on the semiconductor layer SCL. The second insulating film IL2 may be disposed only on a portion of the semiconductor layer SCL. In some embodiments, the second insulating film IL2 may overlap with a portion of the semiconductor layer SCL. The second insulating film IL2 may cover the channel region of the first transistor TR1 and may expose the first source / drain region and the second source / drain region of the first transistor TR1 as well as the side surface of the semiconductor layer SCL.

[0080] The second insulating film IL2 may have a planar shape substantially the same as that of the second conductive layer 200 disposed on the second insulating film IL2. The side surfaces of the second insulating film IL2 may be aligned with the side surfaces of the second conductive layer 200. In some embodiments, the second insulating film IL2 may include contact holes, for example, contact holes corresponding to contact holes CNT5.

[0081] The second insulating film IL2 may include (e.g., is) silicon compounds and / or metal oxides. For example, the second insulating film IL2 may include (e.g., is) silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. These materials may be used individually (e.g., used) or in combination with each other (e.g., used).

[0082] A second conductive layer 200 is disposed on the second insulating film IL2. The second conductive layer 200 may include the gate electrode GAT1 of the first transistor TR1 and the gate electrode GAT2 of the second transistor TR2. The gate electrode GAT1 of the first transistor TR1 may be electrically coupled (e.g., electrically connected) to the source electrode of the second transistor TR2. The second conductive layer 200 may further include ( Figure 3 The second electrode (or upper electrode) of the capacitor Cst. The second conductive layer 200 may be formed of Al. In some embodiments, the second conductive layer 200 may include (e.g., is) Al.

[0083] The gate electrode GAT2 of the second transistor TR2 can be electrically coupled (e.g., electrically connected) to the second lower conductive pattern BML2 through a contact hole CNT5 that exposes a portion of the second lower conductive pattern BML2.

[0084] The stacked structure of the second conductive layer 200 will be described later.

[0085] A third insulating film IL3 may be disposed on the second conductive layer 200. The third insulating film IL3 may cover the second conductive layer 200, the second insulating film IL2, and the semiconductor layer SCL, and may be disposed on the entire surface of the first insulating film IL1. In some embodiments, the third insulating film IL3 may include contact holes, for example, contact holes corresponding to contact holes CNT1, CNT2, and CNT3. The third insulating film IL3 may perform the function of an interlayer insulating film that insulates the second conductive layer 200 and the third conductive layer 300. The second insulating film IL2 may include (e.g., is) at least one of silicon nitride, silicon oxide, and silicon oxynitride. In some embodiments, the third insulating film IL3 may include (e.g., is) at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0086] The third conductive layer 300 may be disposed on the third insulating film IL3. The third conductive layer 300 may include the first source / drain electrode SD1 and the second source / drain electrode SD2 of the first transistor TR1. The third conductive layer 300 may include the source electrode and the drain electrode of the second transistor TR2.

[0087] The third conductive layer 300 may also include... Figure 3 The first power line ELVDL corresponds to the first power wiring, and Figure 3Data cable DL corresponding data cabling and Figure 3 The second electrode of capacitor Cst.

[0088] The first source / drain electrode SD1 of the first transistor TR1 can be electrically coupled (e.g., electrically connected) to the first source / drain region of the first transistor TR1 through a contact hole CNT1 that exposes the first source / drain region of the first transistor TR1.

[0089] The second source / drain electrode SD2 of the first transistor TR1 can be electrically coupled (e.g., electrically connected) to the second source / drain region of the first transistor TR1 through a contact hole CNT2 that exposes the second source / drain region of the first transistor TR1. Furthermore, the second source / drain electrode SD2 of the first transistor TR1 can be electrically coupled (e.g., electrically connected) to the first lower conductive pattern BML1 through a contact hole CNT3 that exposes a portion of the first lower conductive pattern BML1.

[0090] The third conductive layer 300 may be formed of a low-resistance material. The third conductive layer 300 may include (for example, is) at least one metal selected from Al, molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), but this disclosure is not limited thereto. The third conductive layer 300 may have the same stacked structure as one of the conductive layers in the first conductive layer 100 and the second conductive layer 200.

[0091] A via layer VIA is disposed on the third conductive layer 300. The via layer VIA can be disposed on the third conductive layer 300 to completely cover the top surface of the third conductive layer 300. In some embodiments, the via layer VIA may include or have contact holes, such as a fourth contact hole CNT4. When the via layer VIA is formed as an organic film, the top surface of the via layer VIA can be substantially flat (e.g., substantially flat) regardless of the presence or absence of a height difference (e.g., thickness difference) beneath the via layer VIA.

[0092] The via layer VIA may include (e.g., is) inorganic insulating materials and / or organic insulating materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, and / or benzocyclobutene (BCB). The via layer VIA may also include (e.g., is) photosensitive materials, but this disclosure is not limited thereto.

[0093] The anode electrode ANO is disposed on the via layer VIA. The anode electrode ANO can be configured to be separated between different pixels PX. The anode electrode ANO can penetrate the via layer VIA and can be electrically coupled (e.g., electrically connected) to the second source / drain electrode SD2 of the first transistor TR1 via the fourth contact hole CNT4. In some embodiments, the anode electrode ANO is disposed in the display area DA, but not in the non-display area NDA.

[0094] The anode electrode ANO can have indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In) stacked therein. x O y The disclosure describes a structure for a high work function material layer and a reflective material layer of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or mixtures thereof, but is not limited thereto. The high work function material layer can be disposed on the reflective material layer, and therefore, the high work function material layer can be positioned closer to the emitter layer EL than the reflective material layer. The anode electrode ANO can have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, and ITO / Ag / ITO, but is not limited thereto.

[0095] A pixel-defining film (PDL) can be disposed on the anode electrode (ANO). For example, the PDL can cover the side (e.g., edge) of the anode electrode (ANO). The PDL may include openings that partially expose the anode electrode (ANO) (e.g., the central portion of the anode electrode). The PDL can be formed of organic and / or inorganic insulating materials. For example, the PDL may include (e.g., is) at least one of polyimide resin, acrylic resin, silicone compound, and polyacrylic resin.

[0096] The emitter layer EL and the cathode electrode CAT can be further disposed on the portion of the anode electrode ANO exposed by the pixel-defined film PDL.

[0097] The emitting layer (EL) may include (e.g., is) an organic material layer. The organic material layer of the emitting layer EL may include an organic light-emitting layer, and may also include a hole injection / transport layer and / or an electron injection / transport layer. In some embodiments, the organic material layer of the emitting layer EL may include an organic light-emitting layer, and may also include at least one selected from a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.

[0098] The cathode electrode (CAT) can be disposed on the emitter layer (EL). The cathode electrode (CAT) can be a common electrode disposed across the entire surface of the substrate (SUB) without considering the differentiation of each pixel (PX). For example, the cathode electrode can be common to multiple pixels (PX). The anode electrode (ANO), the emitter layer (EL), and the cathode electrode (CAT) can form an organic light-emitting element (OLED).

[0099] The cathode electrode CAT may comprise a low work function material layer of Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg). The cathode electrode CAT may also comprise a transparent metal oxide layer disposed on the low work function material layer.

[0100] A thin-film encapsulation layer may be further disposed on the cathode electrode CAT. The thin-film encapsulation layer may include multiple insulating films, and the multiple insulating films may include inorganic insulating films and / or organic insulating films.

[0101] Display device 1 can have a high resolution of up to 460 ppi or greater. The timing controller 21 of display device 1 can output a gate control signal at a frequency of 120 Hz to 240 Hz. The higher the frequency of the output gate control signal and / or the resolution of display device 1, the shorter the gate conduction duration of the TFT. When the resistance of the scan signal line is high, scan signal delay occurs. In this case, sufficient gate conduction duration cannot be ensured, resulting in horizontal stripe patterns or display blemishes.

[0102] When the first conductive layer 100 and the second conductive layer 200 are formed with a conductive pattern comprising (for example,) Al or an Al alloy, the scan signal delay can be reduced compared to the case where materials with relatively high sheet resistance, such as Mo, are used because Al or the Al alloy has a relatively low sheet resistance. Therefore, defects such as horizontal stripe patterns or display blemishes can be reduced.

[0103] Since the first conductive layer 100 and the second conductive layer 200 comprise Al or an Al alloy, an anti-corrosion layer CB can also be provided. Figure 6 The barrier layer 230 and the anti-corrosion layer CB can reduce or prevent corrosion of Al or Al alloy. The barrier layer 230 can prevent the lower part of the main conductive layer 210 of the second conductive layer 200 from being exposed (or reduce the exposure of the lower part of the main conductive layer 210 of the second conductive layer 200) and prevent or stop hydrogen (H) from diffusing into the channel region of the TFT.

[0104] In the following text, reference will be made to Figures 5 to 7The stacked structure of the first conductive layer 100 and the second conductive layer 200 and the contact relationship between the first conductive layer 100 and the second conductive layer 200 are described.

[0105] Figure 5 yes Figure 4 An enlarged cross-sectional view of region A. Figure 6 yes Figure 4 An enlarged cross-sectional view of region B, and Figure 7 yes Figure 4 Enlarged cross-sectional view of region C. Figure 5 A cross-sectional view of the first lower conductive pattern BML1 and its surrounding area, as an example of the first conductive layer 100, is shown. Figure 6 A cross-sectional view of the gate electrode GAT1, which serves as an example of the second conductive layer 200, is shown. Figure 7 A cross-sectional view of the interface IF between the second lower conductive pattern BML2 of the first conductive layer 100 and the gate electrode GAT2 of the second transistor TR2 of the second conductive layer 200, and the surrounding area, is shown.

[0106] In the following text, reference will be made to Figure 5 Describe the first conductive layer 100.

[0107] The first conductive layer 100 may include a main conductive layer 110 and a cover layer 120 disposed on the main conductive layer 110.

[0108] The main conductive layer 110 imparts conductivity to the first conductive layer 100. The main conductive layer 110 may be formed of a low-resistance material. The main conductive layer 110 may include (e.g., is) Al or an Al alloy. The Al alloy may include (e.g., is) Al and additives. The additives may include (e.g., is) at least one of Ni, lanthanum (La), Nd, and germanium (Ge). The additives may be included in any suitable amount (e.g., 2 at% or 1 at% as examples) based on the total amount of the Al alloy, but this disclosure is not limited thereto.

[0109] The thickness t110 of the main conductive layer 110 can be, for example, 2,500 angstroms to 4,000 angstroms or 2,000 angstroms to 5,000 angstroms, but this disclosure is not limited thereto.

[0110] The main conductive layer 110 can be a single-layer film or a multilayer film. In the case that the main conductive layer 110 is a multilayer film, at least one of the multiple films forming the main conductive layer 110 may include (for example) Al or an Al alloy.

[0111] A capping layer 120 is disposed on the top surface of the main conductive layer 110. The capping layer 120 can cover the top surface of the main conductive layer 110 to protect it. Even when Al (or an Al alloy) is coated onto the main conductive layer 110, Al hillocks can be suppressed, reduced, or prevented, and damage to the main conductive layer 110 and / or defects in the main conductive layer 110 that may occur during the process of forming other components on the main conductive layer 110 can be suppressed, reduced, or prevented. Therefore, damage to the surface of the first conductive layer 100 and / or defects on the surface of the first conductive layer 100 or an increase in the resistance of the first conductive layer 100 can be suppressed, reduced, or prevented, and the reliability of the first conductive layer 100 can be improved.

[0112] The capping layer 120 can be formed as a multilayer structure having layers of heterogeneous materials stacked therein. In some embodiments, the capping layer 120 may include multiple stacked layers. For example, the capping layer 120 may include a first capping layer 121 and a second capping layer 122. The first capping layer 121 and the second capping layer 122 may be formed of different materials.

[0113] The first cover layer 121 may be disposed on the main conductive layer 110, and the second cover layer 122 may be disposed on the first cover layer 121. For example, the first cover layer 121 may be disposed between the main conductive layer 110 and the second cover layer 122.

[0114] The first capping layer 121 and the second capping layer 122 forming the multilayer structure of capping layer 120 can be formed of a conductive material. The total conductivity of capping layer 120 can be less than the conductivity of the main conductive layer 110. For example, each of the first capping layer 121 and the second capping layer 122 may include (e.g., is) Ti or titanium nitride (TiN). For example, capping layer 120 may have a structure in which TiN layers and Ti layers are alternately stacked. In some embodiments, the first capping layer 121 may be a TiN layer including (e.g., is) TiN, and the second capping layer 122 may be a Ti layer including (e.g., is) Ti. The TiN layer and the Ti layer are heterogeneous materials with different physical properties, but because the TiN layer and the Ti layer both share (e.g., include) Ti, the TiN layer and the Ti layer can be formed by a continuous process. This will be described in more detail later.

[0115] The capping layer 120 may have sufficient thickness to effectively protect the main conductive layer 110, but the thickness t120 of the capping layer 120 may be less than the thickness t110 of the main conductive layer 110. For example, the thickness t120 of the capping layer 120 may be half or less than half the thickness t110 of the main conductive layer 110.

[0116] The thickness t120 of the cover layer 120 can be in the range of 400 angstroms to 2000 angstroms. The thickness t121 of the first cover layer 121 can be in the range of 100 angstroms to 500 angstroms or 250 angstroms to 350 angstroms. The thickness t122 ​​of the second cover layer 122 can be in the range of 1000 angstroms to 1500 angstroms or 1100 angstroms to 1300 angstroms.

[0117] As described later, the main conductive layer 110 and the capping layer 120 of the first conductive layer 100 can be formed by a single mask process. The side surfaces of the main conductive layer 110, the first capping layer 121, and the second capping layer 122 can all be aligned, but this disclosure is not limited thereto. In some embodiments, only two of the main conductive layer 110, the first capping layer 121, and the second capping layer 122 may have their side surfaces aligned, or none of the main conductive layer 110, the first capping layer 121, and the second capping layer 122 may have their side surfaces not aligned.

[0118] The capping layer 120 has been described above as having a multilayer structure including a first capping layer 121 and a second capping layer 122, but this disclosure is not limited thereto. In some embodiments, the capping layer 120 may have a single-layer structure. In this case, the capping layer 120 may include one of the first capping layer 121 and the second capping layer 122, which respectively include (e.g., TiN and Ti). Even if the capping layer 120 includes only (e.g., only) one of the first capping layer 121 and the second capping layer 122, the capping layer 120 may have a thickness substantially the same as the thickness t120. For example, in this case, the capping layer 120 may have the same composition as the first capping layer 121 or the second capping layer 122, and therefore, the capping layer 120 may include (e.g., TiN or Ti).

[0119] In the following text, reference will be made to Figure 6 and Figure 7 The stacking structure of the second conductive layer 200 and the contact relationship between the first conductive layer 100 and the second conductive layer 200 are described.

[0120] The second conductive layer 200 may include a main conductive layer 210, a capping layer 220, and a barrier layer 230. The capping layer 220 and the barrier layer 230 may be disposed on the main conductive layer 210. The capping layer 220 may be disposed on (e.g., above) the main conductive layer 210, and the barrier layer 230 may be disposed below the main conductive layer 210. For example, the main conductive layer 210 may be disposed between the capping layer 220 and the barrier layer 230. The capping layer 220 may be disposed between the main conductive layer 210 and the third insulating film IL3, and the barrier layer 230 may be disposed between the main conductive layer 210 and the semiconductor layer SCL. In some embodiments, the barrier layer 230 may be disposed between the main conductive layer 210 and the second insulating film IL2.

[0121] The main conductive layer 210 of the second conductive layer 200 may be substantially the same as the main conductive layer 110 of the first conductive layer 100 (e.g., it may have substantially the same composition as the main conductive layer 110 of the first conductive layer 100), and the capping layer 220 of the second conductive layer 200 may be substantially the same as the capping layer 120 of the first conductive layer 100 (e.g., it may have substantially the same composition as the capping layer 120 of the first conductive layer 100). For example, the material (e.g., composition), thickness t210, and stacking structure of the main conductive layer 210 of the second conductive layer 200 may be substantially the same as the material (e.g., composition), thickness t110, and stacking structure of the main conductive layer 110 of the first conductive layer 100, respectively. The material, thickness t220 (t221 and t222), and stacking structure of the capping layer 220 of the second conductive layer 200 may be substantially the same as the material, thickness t120 (t121 and t122), and stacking structure of the capping layer 120 of the first conductive layer 100, respectively. Therefore, a detailed description of the main conductive layer 210 and the cover layer 220 of the second conductive layer 200 is not required.

[0122] The second conductive layer 200 may have the same stacked structure as the first conductive layer 100, and may further include a barrier layer 230 disposed below the corresponding stacked structure. The barrier layer 230 may include (e.g., be) the same material as one of the first and second capping layers 221 and 222 of the capping layer 220. For example, the barrier layer 230 may be a Ti layer including (e.g., is) Ti, but this disclosure is not limited thereto. For example, the thickness t230 of the barrier layer 230 may be in the range of 100 angstroms to 300 angstroms or 10 angstroms to 500 angstroms.

[0123] Since the first conductive layer 100 and the second conductive layer 200 can be in direct contact with each other, and a barrier layer 230 including (e.g., is) Ti is disposed at the bottom of the second conductive layer 200, the contact resistance in the contact area of ​​the first conductive layer 100 and the second conductive layer 200 can be reduced, and the bonding of the first conductive layer 100 and the second conductive layer 200 in the contact area of ​​the first conductive layer 100 and the second conductive layer 200 can be promoted.

[0124] In some embodiments, since the first conductive layer 100 includes a second capping layer 122 comprising (e.g., is) Ti located above the first conductive layer 100 (e.g., as the uppermost layer of the first conductive layer 100), and the second conductive layer 200 includes a barrier layer 230 comprising (e.g., is) Ti located below the second conductive layer 200 (e.g., as the lowermost layer of the second conductive layer 200), homogeneous materials (i.e., Ti) from the first conductive layer 100 and the second conductive layer 200 can directly contact each other when the first conductive layer 100 and the second conductive layer 200 are in direct contact with each other. In some embodiments, the second capping layer 122 of the first conductive layer 100 and the barrier layer 230 of the second conductive layer 200 can directly contact each other. Therefore, the contact resistance between the first conductive layer 100 and the second conductive layer 200 can become lower than the contact resistance between the first conductive layer 100 and the second conductive layer 200 when heterogeneous materials contact each other at the interface IF where the first conductive layer 100 and the second conductive layer 200 are in direct contact with each other. For example, compared to when the material at the upper surface of the first conductive layer 100 is different from the material at the lower surface of the second conductive layer 200, when the material at the upper surface of the first conductive layer 100 (e.g., Ti) and the material at the lower surface of the second conductive layer 200 (e.g., Ti) are substantially the same, the contact resistance between the first conductive layer 100 and the second conductive layer 200 can be relatively low. Furthermore, when the first conductive layer 100 and the second conductive layer 200 are in direct contact with each other and thus coupled to each other, the bonding force between the first conductive layer 100 and the second conductive layer 200 can be improved because the homogeneous materials (e.g., Ti) from the first conductive layer 100 and the second conductive layer 200 are bonded together.

[0125] However, this disclosure is not limited thereto. In some embodiments, during the formation of the contact hole CNT5, a portion of the second capping layer 122 of the first conductive layer 100 may be over-etched, such that the barrier layer 230 of the second conductive layer 200 can directly contact the first capping layer 121 of the first conductive layer 100. Even though the barrier layer 230 of the second conductive layer 200 and the first capping layer 121 of the first conductive layer 100 are in direct contact with each other, the same advantages as described above can still be achieved because the first capping layer 121 of the first conductive layer 100 comprises (e.g., is) TiN.

[0126] For example, when the gate electrode GAT2 and the lower conductive pattern BML2 of the second transistor TR2 are in direct contact with each other through the contact hole CNT5, the contact resistance between the gate electrode GAT2 and the lower conductive pattern BML2 of the second transistor TR2 can be reduced, the bonding force between the gate electrode GAT2 and the lower conductive pattern BML2 of the second transistor TR2 can be improved, and the device characteristics and reliability of the second transistor TR2 as a switching transistor can be further improved.

[0127] The barrier layer 230 prevents the bottom surface of the main conductive layer 210 of the second conductive layer 200 from being exposed to external air and / or moisture. In some embodiments, the barrier layer 230 can reduce the exposure of the bottom surface of the main conductive layer 210 of the second conductive layer 200 to external air and / or moisture. The barrier layer 230 covers the top surface of the semiconductor layer SCL and thus can suppress, block, or prevent hydrogen from diffusing from the semiconductor layer SCL into the channel region of the first transistor TR1. Referring below... Figure 8 This will be described.

[0128] Figure 8 This is a cross-sectional view illustrating how hydrogen diffusion into a semiconductor layer having a barrier layer is prevented or blocked according to embodiments of the present disclosure. Figure 8 A cross-sectional view of the gate electrode GAT1 and its surrounding area of ​​the first transistor TR1 is shown.

[0129] Reference Figure 8 The barrier layer 230 can prevent hydrogen (H) from potentially traveling towards the semiconductor layer SCL. In other words, hydrogen (H) can diffuse through the main conductive layer 210 and the second insulating film IL2 towards the semiconductor layer SCL, but may not be able to penetrate the barrier layer 230. The barrier layer 230 can allow hydrogen (H) to permeate into and remain within the barrier layer 230 without being released. Therefore, the barrier layer 230 can suppress, reduce, or prevent the diffusion of hydrogen (H).

[0130] The barrier layer 230 can be disposed above the portion of the semiconductor layer SCL corresponding to the channel region of the first transistor TR1, and can overlap with the channel region of the first transistor TR1. Therefore, the barrier layer 230 can reduce, suppress, or prevent hydrogen (H) diffusion into the channel region of the first transistor TR1. For example, even if the main conductive layer 210 of the gate electrode GAT1 of the first transistor TR1 includes (e.g., is) Al, the amount of hydrogen (H) penetrating into the channel region of the first transistor TR1 can still be reduced or minimized due to the presence of the barrier layer 230 below the main conductive layer 210 (e.g., between the main conductive layer 210 and the semiconductor layer SCL), and thus the reliability of the first transistor TR1 can be ensured (e.g., improved).

[0131] In the following text, reference will be made to Figure 9 Describe how to utilize (e.g., use) barrier layer 230 to ensure transistor reliability.

[0132] Figure 9 The illustration is shown according to Figure 8 The curves (a) and (b) show the changes in driving current with or without the presence of the blocking layer. Figure 9 The graph (a) shows the drive current I when the second conductive layer 200 does not include the barrier layer 230. DS According to the transistor's gate voltage V GS The changes, and Figure 9 Graph (b) shows the drive current I when the second conductive layer 200 includes the barrier layer 230. DS According to the transistor's gate voltage V GS The change. Here, the transistor includes a gate electrode containing Al.

[0133] Reference Figure 9 The curve (a) shows that when the barrier layer 230 is not provided, even if the gate voltage V of the transistor is... GS Change, drive current I DS This also doesn't change the situation. That is, when the barrier layer 230 is not provided, regardless of whether the gate electrode of the transistor includes (e.g., whether or not) Al to achieve low resistance, a large amount of hydrogen will permeate into the channel region of the transistor, causing the resistance of the channel region of the transistor to decrease. Therefore, it is difficult to control the conduction or cutoff of the transistor, and thus, the reliability of the transistor may not be guaranteed.

[0134] Reference Figure 9 The curve (b) shows the change in transistor gate voltage V. GS Change, drive current I DS This change allows the transistor to have a threshold voltage of approximately 0.24V. In some embodiments, when the gate electrode of the transistor includes a barrier layer 230, such as Figure 8 As shown, the barrier layer 230 can prevent hydrogen from traveling towards the channel region of the transistor, and thus can minimize or reduce the change in resistance of the transistor's channel region. Therefore, it can facilitate the transistor's turn-on or turn-off, and thus ensure the transistor's reliability.

[0135] In other words, such as Figure 8 As shown, even if the gate electrode of the transistor comprises (e.g., is) Al, hydrogen diffusion into the channel region of the transistor can still be reduced, suppressed, or prevented due to the presence of the barrier layer 230. Therefore, the gate electrode of the transistor can be kept at a low resistance, and the transistor's on / off state can be easily controlled, thereby ensuring transistor reliability.

[0136] Hereinafter, a method for manufacturing a display device according to embodiments of the present disclosure will be described.

[0137] Figures 10 to 12 This is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present disclosure. Figures 10 to 12 It shows how to manufacture Figure 6 The second conductive layer 200. Figure 1 The manufacture of the other components of the display device 1 is already generally available, and therefore, a detailed description thereof is not required.

[0138] Reference Figure 10 A barrier layer material layer 230a comprising (e.g., Ti), a main conductive layer material layer 210a comprising (e.g., Al or an Al alloy), a first capping layer material layer 221a, and a second capping layer material layer 222a are sequentially formed on a semiconductor layer SCL. In some embodiments, a second insulating film material layer IL2a is formed on the semiconductor layer SCL, and then the barrier layer material layer 230a is formed on the second insulating film material layer IL2a. The barrier layer material layer 230a, the main conductive layer material layer 210a, the first capping layer material layer 221a, and the second capping layer material layer 222a can be formed on (…). Figure 4 (substrate) SUB or ( Figure 4 The entire surface of the first insulating film IL1 is covered to cover the semiconductor layer SCL.

[0139] The barrier layer material layer 230a, the main conductive layer material layer 210a, the first capping layer material layer 221a, and the second capping layer material layer 222a can be formed by sputtering using a sputtering apparatus (e.g., by performing sputtering in a sputtering apparatus). The barrier layer material layer 230a, the main conductive layer material layer 210a, the first capping layer material layer 221a, and the second capping layer material layer 222a can be formed in different sputtering apparatuses, or at least some of the barrier layer material layer 230a, the main conductive layer material layer 210a, the first capping layer material layer 221a, and the second capping layer material layer 222a can be formed by continuous sputtering.

[0140] For example, the first capping material layer 221a and the second capping material layer 222a can be formed by continuous sputtering.

[0141] In some embodiments, a substrate SUB on which the main conductive layer material layer 210a is formed may be placed in a sputtering apparatus including a Ti target. Thereafter, a first capping layer material layer 221a comprising (e.g., TiN) is formed by reactive sputtering using (e.g., using) nitrogen as the sputtering gas.

[0142] Then, nitrogen is replaced with argon in the sputtering apparatus, and sputtering continues to form a second capping material layer 222a comprising (e.g.,) Ti.

[0143] Reference Figure 11 and Figure 12 A photoresist pattern PR is formed on the second cover layer material layer 222a, and the photoresist pattern PR is used as an etching mask to etch the barrier layer material layer 230a, the main conductive layer material layer 210a, the first cover layer material layer 221a, and the second cover layer material layer 222a.

[0144] Etching of the barrier layer material layer 230a, the main conductive layer material layer 210a, the first capping layer material layer 221a, and the second capping layer material layer 222a is performed using a photoresist pattern PR as an etching mask. The barrier layer material layer 230a, the main conductive layer material layer 210a, the first capping layer material layer 221a, and the second capping layer material layer 222a can be etched by dry etching. The barrier layer material layer 230a, the main conductive layer material layer 210a, the first capping layer material layer 221a, and the second capping layer material layer 222a can be etched sequentially in the same batch or in different batches using different etching processes with different sets of etching conditions. In some embodiments, the second capping layer material layer 222a can be etched first, then the first capping layer material layer 221a can be etched, then the main conductive layer material layer 210a can be etched, and then the barrier layer material layer 230a can be etched.

[0145] Therefore, the barrier layer 230, the main conductive layer 210, and the capping layer 220 are etched using a single mask process, and the number of mask processes does not increase even with the barrier layer 230. As a result, the process efficiency is not reduced even with the barrier layer 230.

[0146] The second insulating film IL2 can be etched together with the second conductive layer 200 using (e.g., by using) a single mask. In some embodiments, the second insulating film material layer IL2a can be etched using (e.g., by using) a photoresist pattern PR to form the second insulating film IL2.

[0147] Subsequently, the residual photoresist pattern (PR) can be obtained by removing it through ashing or stripping. Figure 6 The second conductive layer 200.

[0148] In the following description, the display devices according to other embodiments of the present disclosure will focus primarily on the differences from display device 1. Descriptions of already described elements or features may be simplified or omitted.

[0149] Figure 13This is a cross-sectional view of a display device according to another embodiment of the present disclosure.

[0150] Reference Figure 13 , Figure 13 Implementation examples and Figure 4 The difference in the embodiment is that the anti-corrosion layer CB_1 of the display panel 10_1 has the same pattern as the first conductive layer 100.

[0151] In some embodiments, the display panel 10_1 includes an anti-corrosion layer CB_1 disposed on a substrate SUB and a first conductive layer 100 disposed on the anti-corrosion layer CB_1. The anti-corrosion layer CB_1 and the first conductive layer 100 may be formed in a plan view with substantially the same pattern and may overlap each other. The side surface of the anti-corrosion layer CB_1 is aligned with the side surface of the first conductive layer 100, but this disclosure is not limited thereto.

[0152] In this configuration, the anti-corrosion layer CB_1 can cover the entire bottom surface of the first conductive layer 100. Because the anti-corrosion layer CB_1 is disposed beneath the first conductive layer 100, corrosion of the first conductive layer 100 can be prevented or reduced even if the first conductive layer 100 comprises (e.g., is) Al or an Al alloy, and this ensures... Figure 13 The display quality and reliability of the display device.

[0153] Figure 14 This is a cross-sectional view of a display device according to another embodiment of the present disclosure. Figure 14 A cross-sectional view of the first lower conductive pattern BML1_2 and its surroundings is shown as an example of the first conductive layer 100_2.

[0154] Reference Figure 14 , Figure 14 Implementation examples and Figure 5 The difference in the embodiment is that the first conductive layer 100_2 has the same Figure 6 The second conductive layer 200 has essentially the same stacked structure.

[0155] For example, the first conductive layer 100_2 may include a main conductive layer 110 and a cover layer 120 disposed on the main conductive layer 110, and may also include a sub-blocking layer 130_2 disposed below the main conductive layer 110.

[0156] The sub-blocking layer 130_2 of the first conductive layer 100_2 can interact with Figure 6The second conductive layer 200 has a barrier layer 230 that is substantially the same. For example, the sub-barrier layer 130_2 of the first conductive layer 100_2 may include (e.g., is) Ti and may be disposed below the main conductive layer 110 of the first conductive layer 100_2. The sub-barrier layer 130_2 of the first conductive layer 100_2 may be disposed between the main conductive layer 110 of the first conductive layer 100_2 and the substrate SUB and / or between the main conductive layer 110 and the anti-corrosion layer CB. The main conductive layer 110 of the first conductive layer 100_2 may be disposed between the sub-barrier layer 130_2 of the first conductive layer 100_2 and the cover layer 120 of the first conductive layer 100_2.

[0157] In this configuration, not only the anti-corrosion layer CB, but also the sub-barrier layer 130_2 is further disposed below the main conductive layer 110 of the first conductive layer 100_2, and thus, moisture and / or external air can be appropriately prevented from diffusing into the main conductive layer 110 of the first conductive layer 100_2. Therefore, oxidation and / or corrosion of the main conductive layer 110 can be further suppressed, reduced, or prevented.

[0158] Figure 15 This is a cross-sectional view of a display device according to another embodiment of the present disclosure. Figure 15 The first transistor TR1 is shown as an example of the second conductive layer 200_3 (see Figure 3 and Figure 4 A cross-sectional view of the gate electrode GAT1_3 and its surrounding area.

[0159] Reference Figure 15 , Figure 15 Implementation examples and Figure 6 The difference in the embodiment is that the barrier layer 230_3 and the main conductive layer 210 of the second conductive layer 200_3 have different cone angles, namely, cone angles θ2 and θ1.

[0160] In some embodiments, the second conductive layer 200_3 may include a main conductive layer 210, a cover layer 220 disposed on the main conductive layer 210, and a barrier layer 230_3 disposed below the main conductive layer 210. The cone angle θ2 of the barrier layer 230_3 of the second conductive layer 200_3 may be different from the cone angle θ1 of the main conductive layer 210. In some embodiments, the cone angle θ1 of the main conductive layer 210 is an acute angle of one side (e.g., a sidewall or side surface) of the main conductive layer 210 relative to its lower surface, and the cone angle θ2 of the barrier layer 230_3 is an acute angle of one side (e.g., a sidewall or side surface) of the barrier layer 230_3 relative to its lower surface. The cone angle θ2 of the barrier layer 230_3 of the second conductive layer 200_3 may be smaller than the cone angle θ1 of the main conductive layer 210 of the second conductive layer 200_3.

[0161] Even under these conditions, the barrier layer 230_3 of the second conductive layer 200_3 can minimize or reduce hydrogen diffusion into the channel region of the TFT, and thus ensure the reliability of the TFT.

[0162] Figure 16 This is a cross-sectional view of a display device according to another embodiment of the present disclosure. Figure 16 The first transistor TR1 is shown as an example of the second conductive layer 200_4 (see Figure 3 and Figure 4 A cross-sectional view of the gate electrode GAT1_4 and its surrounding area.

[0163] Reference Figure 16 , Figure 16 Implementation examples and Figure 6 The difference in the embodiment is that the side surface of the barrier layer 230_4 of the second conductive layer 200_4 is not aligned with the side surface of the main conductive layer 210 of the second conductive layer 200_4.

[0164] In some embodiments, the side surface of the barrier layer 230_4 of the second conductive layer 200_4 may protrude outward relative to the side surface of the main conductive layer 210 of the second conductive layer 200_4. For example, in a plan view, the side surface of the barrier layer 230_4 may extend beyond the side surface of the main conductive layer 210, such that a portion of the barrier layer 230_4 is suspended below the main conductive layer 210. However, this disclosure is not limited thereto. In some embodiments, the side surface of the main conductive layer 210 of the second conductive layer 200_4 may protrude outward relative to the side surface of the barrier layer 230_4 of the second conductive layer 200_4. For example, in a plan view, the side surface of the main conductive layer 210 may extend beyond the side surface of the barrier layer 230_4, such that a portion of the main conductive layer 210 is suspended above the barrier layer 230_4.

[0165] Even under these conditions, the barrier layer 230_4 of the second conductive layer 200_4 can minimize or reduce hydrogen diffusion into the channel region of the TFT, and thus ensure the reliability of the TFT.

[0166] In concluding this detailed description, those skilled in the art will understand that many variations and appropriate modifications can be made to the disclosed embodiments without substantially departing from the principles and scope of this disclosure as defined by the claims and their equivalents. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A display device, wherein, The display device includes: Base; An anti-corrosion layer, said anti-corrosion layer being on the substrate and comprising inorganic materials; A first conductive layer is placed on the anti-corrosion layer and comprises aluminum or an aluminum alloy. A first insulating film, wherein the first insulating film is on the first conductive layer; A semiconductor layer, the semiconductor layer being on the first insulating film, and including the channel region of a transistor; A second insulating film, the second insulating film being on the semiconductor layer; and The second conductive layer is on the second insulating film and includes a barrier layer comprising titanium and a main conductive layer comprising aluminum or an aluminum alloy. in, The semiconductor layer comprises an oxide semiconductor, and The barrier layer lies between the semiconductor layer and the main conductive layer, and overlaps with the channel region of the transistor. The second conductive layer is electrically connected to the first conductive layer through contact holes that expose the first conductive layer. The first conductive layer further includes a metallic pattern containing titanium as the top layer of the first conductive layer. The metal pattern and the barrier layer are in direct contact with each other.

2. The display device according to claim 1, wherein, The second conductive layer includes the gate electrode of the transistor.

3. The display device according to claim 2, wherein, The display device further includes: A third insulating film, said third insulating film being on the second conductive layer; and A third conductive layer is formed on the third insulating film. The third conductive layer includes the source electrode and the drain electrode of the transistor.

4. The display device according to claim 3, wherein, The source electrode of the transistor is electrically connected to both the semiconductor layer and the first conductive layer.

5. The display device according to claim 4, wherein, The third conductive layer includes a first power line.

6. The display device according to claim 1, wherein, The second conductive layer is in direct contact with the first conductive layer.

7. The display device according to claim 1, wherein, The barrier layer has the same shape as the main conductive layer in the plan view.

8. The display device according to claim 7, wherein, The barrier layer has the same shape as the second insulating film in the plan view.

9. The display device according to claim 8, wherein, The side surfaces of the barrier layer, the main conductive layer, and the second insulating film are aligned.

10. The display device according to claim 1, wherein, The thickness of the barrier layer is in the range of 100 angstroms to 300 angstroms.

11. The display device according to claim 10, wherein, The thickness of the main conductive layer is in the range of 2,500 angstroms to 4,000 angstroms.

12. The display device according to claim 11, wherein, The display device further includes: A capping layer is placed on the main conductive layer and includes at least one of titanium and titanium compounds.

13. A display device, wherein, The display device includes: Base; A semiconductor layer, said semiconductor layer on said substrate, and including a channel region for a transistor; A first insulating film is placed on the semiconductor layer; A first conductive layer is on the first insulating film and includes a barrier layer containing titanium, a main conductive layer containing aluminum or an aluminum alloy, and a cover layer containing titanium. A second insulating film, the second insulating film being disposed on the first conductive layer; and A second conductive layer is formed on the second insulating film and includes the source and drain electrodes of the transistor. in, The semiconductor layer includes an oxide semiconductor. The first conductive layer includes the gate electrode of the transistor, and The barrier layer lies between the semiconductor layer and the main conductive layer, and overlaps with the channel region of the transistor. The display device further includes a third conductive layer disposed on the substrate and comprising aluminum or an aluminum alloy, wherein the third conductive layer includes a metallic pattern comprising titanium as the top layer of the third conductive layer. The first conductive layer is electrically connected to the third conductive layer through a contact hole that exposes the third conductive layer. The metal pattern and the barrier layer are in direct contact with each other.

14. The display device according to claim 13, wherein, The display device further includes: An anti-corrosion layer, said anti-corrosion layer on the substrate, and comprising an inorganic material; and A third insulating film is provided on the third conductive layer. The third conductive layer is located on the anti-corrosion layer, and the anti-corrosion layer, the third conductive layer, and the third insulating film are located between the substrate and the semiconductor layer.

15. The display device according to claim 14, wherein, The third conductive layer includes a lower conductive pattern that overlaps with the channel region of the transistor.

16. The display device according to claim 15, wherein, The lower conductive pattern is electrically connected to the gate electrode of the transistor.

17. The display device according to claim 13, wherein, The barrier layer has the same shape as the main conductive layer in the plan view.

18. The display device according to claim 17, wherein, The barrier layer has the same shape as the first insulating film in the plan view.

19. The display device according to claim 18, wherein, The side surfaces of the barrier layer, the main conductive layer, and the first insulating film are aligned.

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