High voltage semiconductor device and method of forming the same

Abstract

A high voltage semiconductor device and a method of forming the same. The high voltage semiconductor device includes a substrate, a gate structure, a drain, a first insulating structure, and a drain doped region. The gate structure is disposed on the substrate. The drain is disposed within the substrate and is located on one side of the gate structure. The first insulating structure is disposed on the substrate and is located below the gate structure and partially overlaps the gate structure. The drain doped region is disposed within the substrate and is located below the drain and the first insulating structure and has a discontinuous bottom surface.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device and a method for forming the same, and more particularly to a high-voltage semiconductor device and a method for forming the same. [Existing Technology]

[0002] With advancements in semiconductor technology, the industry can now integrate control circuits, memory, low-voltage operating circuits, and high-voltage operating circuits and related components onto a single chip, reducing costs and improving operational performance. Transistors, commonly used in amplifying current or voltage signals in circuits, as oscillators, or as switching components controlling circuit switching, are increasingly being used as high-power or high-voltage components due to advancements in semiconductor manufacturing processes. For example, high-voltage transistors are positioned between the chip's internal circuitry and input / output (I / O) pins to prevent large amounts of charge from entering the internal circuitry via the I / O pins in a very short time and causing damage.

[0003] Currently, transistors used as high-voltage components primarily improve breakdown voltage by reducing the lateral electric field. Structurally, these components generally include double-diffuse MOS (DDDMOS) and laterally diffused drain MOS (LDMOS) devices with introduced drift regions. However, further improving the breakdown voltage of high-voltage semiconductor devices to meet practical requirements remains a challenge for the industry. [Summary of the Invention]

[0004] One objective of this invention is to provide a high-voltage semiconductor device and a method for forming the same. The high-voltage semiconductor device has a doped region at the high-voltage end. The doped region has a discontinuous bottom surface, which has the effects of improving the hot carrier injection problem and avoiding the collapse voltage drop, thereby improving the component reliability of the high-voltage semiconductor device.

[0005] To achieve the above objectives, a preferred embodiment of the present invention provides a high-voltage semiconductor device, comprising a substrate, a gate structure, a drain, a first insulating structure, and a drain-doped region. The gate structure is disposed on the substrate, and the drain is disposed within the substrate and located on one side of the gate structure. The first insulating structure is disposed on the substrate, located below the gate structure, and partially overlaps the gate structure. The drain-doped region is disposed within the substrate, located below the drain and the first insulating structure, and the drain-doped region has a discontinuous bottom surface.

[0006] To achieve the above objectives, a preferred embodiment of the present invention provides a method for forming a high-voltage semiconductor device, comprising the following steps: First, a substrate is provided, and an insulating structure is formed on the substrate. Next, a drain-doped region is formed within the substrate, the drain-doped region having a discontinuous bottom surface below the insulating structure. Then, a gate structure is formed on the substrate. [Attached Image Description]

[0007] Figure 1 A cross-sectional schematic diagram of a high-voltage semiconductor device in a comparative embodiment of the present invention is shown.

[0008] Figure 2 A cross-sectional schematic diagram of a high-voltage semiconductor device according to the first embodiment of the present invention is shown.

[0009] Figure 3 The diagram illustrates the curves of the simulated substrate current (Isub) or gate current (Ig) of the high-voltage semiconductor device relative to the gate voltage (Vg) in the comparative embodiment and the first embodiment of the present invention.

[0010] Figures 4 to 5 A cross-sectional schematic diagram illustrating the stages of the method for forming a high-voltage semiconductor device in the first embodiment of the present invention is shown.

[0011] Figure 6 A cross-sectional schematic diagram of a high-voltage semiconductor device according to a second embodiment of the present invention is shown.

Detailed Implementation Methods

[0012] To enable those skilled in the art to further understand the present invention, several preferred embodiments of the present invention are listed below, and the composition and desired effects of the present invention are described in detail with reference to the accompanying drawings.

[0013] In this invention, the description of "a first component being formed on or above a second component" can refer to either "the first component and the second component being in direct contact" or "other components existing between the first component and the second component," resulting in the first component and the second component not being in direct contact. Furthermore, various embodiments of this invention may use repeated component symbols and / or textual annotations. The use of these repeated component symbols and textual annotations is for the purpose of making the description more concise and clear, rather than to indicate the relationship between different embodiments and / or configurations. Additionally, regarding spatially related descriptive terms mentioned in this invention, such as "below," "above," "low," "high," "below," "above," "under," "above," "bottom," "top," and similar terms, for ease of description, their usage is to describe the relative relationship between one component or feature and another (or more) components or features in the drawings. Besides the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientation of semiconductor devices during fabrication, use, and operation. For example, when a semiconductor device is rotated 180 degrees, a component that was originally positioned "above" other components will now be positioned "below" them. Therefore, as the orientation of a semiconductor device changes (rotating 90 degrees or other angles), the spatial descriptions used to describe its orientation should also be interpreted accordingly.

[0014] Although the present invention uses terms such as first, second, and third to describe various components, parts, regions, layers, and / or sections, it should be understood that such components, parts, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one component, part, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the component, nor do they represent the arrangement order of one component with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present invention, the first component, part, region, layer, or section discussed below may also be referred to as the second component, part, region, layer, or section, etc.

[0015] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0016] Please refer to Figure 1The diagram illustrates a cross-sectional view of a high-voltage semiconductor device 100 in a comparative embodiment of the present invention. In this invention, the high-voltage semiconductor device 100 refers to a semiconductor device whose operating voltage can exceed 20 volts (V) (e.g., 30 volts). The high-voltage semiconductor device 100 includes a substrate 110, a gate structure 130, a drain 150, a source 170, and at least one insulating structure 190. In one embodiment, the substrate 110 may include a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The substrate 110, for example, has a first conductivity type (e.g., P-type). The gate structure 130 is disposed on the substrate 110, while the drain 150 and source 170 are disposed within the substrate 110 and are respectively located on opposite sides of the gate structure 130 in a horizontal direction (not shown, e.g., the X direction). In one embodiment, the gate structure 130 may include a polysilicon gate, a metal gate, or a gate structure formed of other suitable materials, while the drain 150 and source 170 may each be a doped region having a second conductivity type (e.g., N-type), which is complementary to the first conductivity type (e.g., P-type). In another embodiment, the first conductivity type may be N-type, and the second conductivity type may be P-type, forming a P-type doped region as the drain and source, to obtain different types of high-voltage semiconductor devices.

[0017] At least one insulating structure 190 is also disposed on the substrate 110, wherein the insulating structure 190 is, for example, a field oxide (FOX) layer formed by the local oxidation of silicon (LOCOS) method, such as... Figure 1 As shown, or, alternatively, insulating cells (such as shallow trench isolation) can be fabricated through deposition processes or other suitable processes, but are not limited thereto. In this embodiment, two insulating structures 191 and 192 can be formed on opposite sides of the gate structure 130, such that the source 170 is located between the insulating structure 192 and the gate structure 130, while the drain 150 is located between the insulating structure 191 and the gate structure 130, but does not directly contact the insulating structure 191 and / or the gate structure 130, as shown. Figure 1 As shown. However, those skilled in the art will readily understand that the number and location of the aforementioned insulation structures 190 are merely illustrative, and their specific number and location can be further adjusted according to the actual component requirements.

[0018] The high-voltage semiconductor device 100 further includes a drain-doped region 160 and a source-doped region 180 disposed within the substrate 100, respectively located below the drain 150 and the source 170. The drain-doped region 160 and the source-doped region 180 may also be doped regions having the second conductivity type (e.g., N-type), and their doping concentration is less than that of the drain 150 and the source 170. In this embodiment, the drain-doped region 160 and the source-doped region 180 may have a mutually asymmetrical structure, for example, along the horizontal direction, the width w1 of the drain-doped region 160 may be greater than the width w2 of the source-doped region 180. Figure 1 As shown. In this embodiment, the source doped region 180 is also disposed between the gate structure 130 and the insulating structure 192, such that the sidewall of the source doped region 180 and the sidewall of the source 170 are both flush with the sidewall of the gate structure 130 on the same side. The drain doped region 160 extends further from one side of the insulating structure 191 to the bottom of the gate structure 130, and its sidewall is not flush with the drain 150 or the sidewall of the gate structure 130. That is, in this embodiment, the drain 150 is located within and surrounded by the drain doped region 160 in the horizontal direction, so that the drain doped region 160 can serve as the drift region of the high-voltage semiconductor device 100. However, the structural arrangement of the drain doped region 150 and the source doped region 170 is not limited to the above. In another embodiment, the structures of the source doped region and the drain doped region can also be made symmetrical to each other. For example, the source doped region and the drain doped region can have the same width in the horizontal direction.

[0019] Specifically, the drain doped region 160 may further include a first drain doped region 161, a second drain doped region 162, and a third drain doped region 163 arranged sequentially from bottom to top. The first drain doped region 161, the second drain doped region 162, and the third drain doped region 163 may each contain the same or different dopants, such as pentavalent atoms like phosphorus (P), arsenic (As), or tellurium (Ti), but are not limited thereto. The first drain doped region 161 may have a relatively deep depth d1 and a relatively low doping concentration within the substrate 110, for example, a doping concentration of approximately 5 × 10⁻⁶ ions per cubic centimeter. 13 Up to 2.0×10 14 (5×10 13 -2.0×10 14 ions / cm 3 The third drain doped region 163 within the substrate 110 can have a relatively shallow depth d3 and a relatively large doping concentration, for example, approximately 3.0 × 10⁻⁶ ions per cubic centimeter. 14 Up to 9.0×10 14(3.0-9.0×10 14 ions / cm 3 The depth d2 and doping concentration of the second drain doped region 162 are respectively between the depths d1 and d3 and the doping concentration of the first drain doped region 161 and the third drain doped region 163, and the doping concentration is, for example, approximately 1.0 × 10⁻⁶ ions per cubic centimeter. 14 Up to 5.0×10 14 (1.0-5.0×10 14 ions / cm 3 However, this is not a limitation. In one embodiment, the depth d1 of the first drain doped region 161 is, for example, 0.8 micrometers (μm) to 1.2 micrometers, the depth d2 of the second drain doped region 162 is, for example, 0.4 micrometers to 0.8 micrometers, and the depth d3 of the third drain doped region 163 is, for example, 0.1 micrometers to 0.3 micrometers, but is not a limitation. In other words, the overall doping concentration within the drain doped region 160 gradually decreases with increasing depth within the substrate 110.

[0020] On the other hand, the source doped region 180 may also include a first source doped region 181, a second source doped region 182, and a third source doped region 183 arranged sequentially from bottom to top. The first source doped region 181, the second source doped region 182, and the third source doped region 183 may each contain doped regions with the same or different dopants, which may also contain pentavalent atoms such as phosphorus, arsenic, or tellurium. Furthermore, the depths d1, d2, d3, and doping concentrations of the first source doped region 181, the second source doped region 182, and the third source doped region 183 are the same as those of the first drain doped region 161, the second drain doped region 162, and the third drain doped region 163, respectively. This allows the source doped region 180 and the drain doped region 160 to be formed simultaneously through the same shielding and doping process during the fabrication of the high-voltage semiconductor device 100, but this is not a limitation.

[0021] Therefore, in the comparative embodiment of the present invention, the high-voltage semiconductor device 100 achieves sufficient breakdown voltage capability by gradually decreasing the doping concentration from top to bottom in the drain doping region 160. However, in some cases, the high-voltage semiconductor device 100 is still prone to hot carrier injection, resulting in excessively high substrate current (Isub) through its substrate 110 or gate current (Ig) through the gate structure 130, leading to poor device reliability. Generally, although the hot carrier injection problem can be improved by further reducing the overall doping concentration of the drain doping region 160, this may also cause the Kirk effect, resulting in a decrease in the breakdown voltage (Vth), which is still not conducive to improving the device reliability of the high-voltage semiconductor device 100.

[0022] Therefore, those skilled in the art will readily understand that, to meet actual product requirements, the high-voltage semiconductor device of the present invention may also have other forms, and is not limited to those described above. Other embodiments or variations of the high-voltage semiconductor device will be further described below. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments.

[0023] Please refer to Figure 2 The diagram shown illustrates a cross-sectional view of the high-voltage semiconductor device 200 according to the first embodiment of the present invention. The structure of the high-voltage semiconductor device 200 in this embodiment is generally similar to that described above. Figure 1 The illustrated embodiment is the same, also including a substrate 110, a drain 150, a source 170, a source doped region 180, and an insulating structure 190, etc., and the similarities will not be repeated. The main difference between this embodiment and the aforementioned comparative embodiment is that an additional insulating structure 290 is provided below the side of the gate structure 230 near the drain 150, so that the portion of the drain doped region 260 extending below the insulating structure 290 and the gate structure 230 can have a discontinuous bottom surface 260a.

[0024] In detail, the insulating structure 290 is also disposed on the substrate 110, and preferably it is formed together with the insulating structure 190 as a single oxide layer (e.g., Figure 2(as shown) or other suitable insulating units, but not limited thereto. In this embodiment, the drain doped region 260 also extends further from one side of the insulating structure 191 to below the gate structure 230, so that the drain 150 can be located within the drain doped region 260 in the horizontal direction and surrounded by the drain doped region 260. In this embodiment, the drain 150 does not directly contact the gate structure 230 or the insulating structure 290 below the gate structure 230, and the drain 150 and the insulating structure 290 are separated by a portion of the drain doped region 260 (i.e., a portion of the third drain doped region 263), such that the distance g between the drain 150 and the insulating structure 290 is, for example, about 1 micrometer to 2.5 micrometers, preferably 1.5 micrometers to 2 micrometers, but not limited thereto.

[0025] In one embodiment, the drain doped region 260 may further include a first drain doped region 261, a second drain doped region 262, and a third drain doped region 263 arranged sequentially from bottom to top. The first drain doped region 261, the second drain doped region 262, and the third drain doped region 263 may also be doped regions containing the same or different dopants. These dopants may contain pentavalent atoms such as phosphorus, arsenic, or tellurium, but are not limited thereto. The doping concentrations of the first drain doped region 261, the second drain doped region 262, and the third drain doped region 263 are generally the same as those of the first drain doped region 161, the second drain doped region 162, and the third drain doped region 163 in the aforementioned comparative embodiment, and will not be repeated here. Therefore, the overall doping concentration within the drain doped region 260 of this embodiment also gradually decreases with increasing depth within the substrate 110. However, in another embodiment, the drain doped region may also include other numbers of doped regions, or may consist of a single doped region with doping concentration gradually increasing from bottom to top.

[0026] It should be noted that in this embodiment, a portion of the first drain doped region 261 (e.g., the portion located below the drain 150), a portion of the second drain doped region 262 (e.g., the portion located below the drain 150), and the third drain doped region 263 may generally have the same depths d1, d2, and d3 as the first drain doped region 161, the second drain doped region 162, and the third drain doped region 163 in the aforementioned comparative embodiment. For example, the depth d1 of the first drain doped region 161 is, for example, 0.8 micrometers to 1.2 micrometers, the depth d2 of the second drain doped region 162 is, for example, 0.4 micrometers to 0.8 micrometers, and the depth d3 of the third drain doped region 163 is, for example, 0.1 micrometers to 0.3 micrometers, but is not limited thereto. The other part of the first drain doped region 261 (e.g., the part located below the insulating structure 290) and the other part of the second drain doped region 262 (e.g., the part located below the insulating structure 290) have shallower depths d1' and d2', respectively. Meanwhile, due to the shielding effect of the insulating structure 290, the vertical doping range a2' of the second drain doped region 262 located below the insulating structure 290 is significantly smaller than the vertical doping range a2 of the second drain doped region 262 located below the drain 150, such as... Figure 2 As shown. On the other hand, also due to the shielding of the insulating structure 290, the third drain doped region 263 is only formed below the drain 150 and part of the gate structure 230, and not below the insulating structure 290. Due to the difference in depth or vertical doping range between the portions of the first drain doped region 261 and the second drain doped region 262 located below the insulating structure 290 and other portions, the portion of the drain doped region 260 below the insulating structure 290 has a relatively shallow depth d1', resulting in the drain doped region 260 having a discontinuous bottom surface 260a overall, as shown. Figure 2 As shown. Furthermore, a portion of the drain doped region 260 can be disposed below the gate structure 230 (located only below the gate structure 230 and not simultaneously below the insulating structure 290), and generally has the same depths d1, d2, d3 and doping range as the aforementioned drain doped region 160 (i.e., the bottom surface of the drain doped region 260 located below the gate structure 230 is deeper than the bottom surface of the drain doped region 260 located below the insulating structure 290). In other words, the bottom surface of the drain doped region 260 is not always at the same horizontal plane; its bottom surface near the insulating structure 290 has discontinuous steep rises or falls, resulting in the drain doped region 260 having a discontinuous bottom surface 260a overall. Figure 2 The arrow indicates a junction where the portion of the drain doped region 260 below the adjacent insulating structure 290 can exhibit a clear misalignment with other portions.

[0027] Therefore, in the first embodiment of the present invention, the high-voltage semiconductor device 200 can possess sufficient withstand voltage capability due to the gradually decreasing doping concentration of the drain doped region 260 and its discontinuous bottom surface 260a. Simultaneously, the discontinuous bottom surface 260a of the drain doped region 260 effectively mitigates the problem of hot carrier injection. Please refer to... Figure 3 As shown, the solid curves C and E1 depict the relationship between the gate voltage (Vg, X-axis) and the substrate current (Isub, Y-axis), while the dashed curves C' and E1' depict the relationship between the gate voltage (X-axis) and the gate current (Ig, Y-axis). At the point where the substrate current is at its maximum (approximately 10 volts), the current indicated by the substrate current curve E1 of the first embodiment is lower than the current indicated by the substrate current curve C of the comparative embodiment. Furthermore, at the point where the gate current is at its maximum (approximately 30 volts), the current indicated by the gate current curve E1' of the first embodiment is lower than the gate current curve C' of the comparative embodiment. Thus, the high-voltage semiconductor device 200 can indeed have better component reliability.

[0028] Please refer to Figures 4 to 5 As shown, it illustrates a stage cross-sectional schematic diagram of a method for forming a high-voltage semiconductor device 200 according to an embodiment of the present invention. First, as... Figure 4 As shown, a substrate 110 is first provided, and insulating structures 190 and 290 are simultaneously formed on the substrate 110. Next, a shield 400 is formed on the substrate 110, exposing a portion of the substrate 110 and the insulating structure 290, and at least one doping process is performed through the shield 400 to form a drain doped region 260 and a source doped region 180 within the substrate 110.

[0029] It is particularly important to note that the formation location of the drain doped region 260 partially overlaps with the insulating structure 290. This means that the thickness of the insulating structure 290 affects the degree of energy penetration during the doping process, thereby influencing the depth and / or vertical doping range of the drain doped region 260 located below the insulating structure 290. For example, if ion implantation is performed at a higher doping voltage (e.g., 700-800 keV), the shielding effect of the insulating structure 290 will affect the depth of ion implantation, resulting in a shallower doped region (e.g., below the insulating structure 290) Figure 2 The first drain doped region 261 is shown. If ion implantation is performed at a lower doping voltage (e.g., 450 to 550 keV), the shielding of the insulating structure 290 may prevent at least some ions from implanting successfully, thus forming a shallower doped region with a smaller vertical extent below the insulating structure 290 (e.g., ...). Figure 2The second drain doped region 262 shown. This allows for a clearly misaligned interface between the drain doped region 260 formed below the insulating structure 290 and other drain doped regions 260, resulting in a discontinuous bottom surface 260a overall. Figure 4 As shown. Furthermore, if ion implantation is performed at a lower doping voltage (e.g., 100 to 200 keV), the shielding effect of the insulating structure 290 may even affect the ion implantation process, preventing the formation of a doped region (e.g., below the insulating structure 290). Figure 2 The third drain doped region 263 is shown.

[0030] In this embodiment, for example, a first doping process is first performed, such as ion implantation at an energy of about 700 to 800 keV (preferably 750 keV), to form a first drain doped region 261 and a first source doped region 181. Then, a second doping process is performed, such as ion implantation at an energy of about 450 to 550 keV (preferably 500 keV), to form a second drain doped region 262 and a second source doped region 182. Finally, a third doping process is performed, such as ion implantation at an energy of about 100 to 200 keV (preferably 120 keV), to form a third drain doped region 263 and a third source doped region 183. Thus, a first drain doped region 261, a second drain doped region 262, and a third drain doped region 263 are sequentially formed to constitute a drain doped region 260, and a first source doped region 181, a second source doped region 182, and a third source doped region 183 are sequentially formed to constitute a source doped region 180. However, those skilled in the art will readily understand that in actual manufacturing processes, the number and order of doping operations are not limited to the foregoing and can be further adjusted according to product requirements. For example, although the aforementioned embodiment selects to operate the doping process with higher doping energy first to form a deeper doped region, in other embodiments, it is also possible to select to operate the doping process with lower doping energy first to form a shallower doped region, or to perform a single or other number of doping processes to form the drain doped region or the source doped region.

[0031] Then, as Figure 5 As shown, a gate structure 230, a drain 150, and a source 170 are formed sequentially. The gate structure 230 is formed on a portion of the insulating structure 290 and partially overlaps the drain doped region 260 below. The drain 150 and the source 170 are formed within the drain doped region 260 and the source doped region 180 on either side of the gate structure 230, respectively. Thus, the high-voltage semiconductor device 200 of the first embodiment described above can be formed, and the same components in this process have already been described above. Figure 2The illustrations and descriptions are omitted here. The high-voltage semiconductor device 200 effectively mitigates the hot carrier injection problem and avoids a drop in breakdown voltage by using a discontinuous bottom surface 260a at the bottom of its drain doped region 260. Therefore, the formation method of this embodiment is advantageous for obtaining a high-voltage semiconductor device with better component reliability. Furthermore, it can be further... Figure 5 As shown, at least one dielectric layer 410 and a plurality of plugs 431, 432, and 433 are then formed on the substrate 110, which are respectively connected to the gate structure 230, the drain 150, and the source 170 to electrically connect the high-voltage semiconductor device 200 to an external circuit.

[0032] It should be noted that although the high-voltage semiconductor device formation method in this embodiment is illustrated by the process sequence of first forming the drain doped region 260 and the source doped region 180, and then forming the gate structure 230, the actual process is not limited to this. In another embodiment, after forming the insulating structure 290, a gate structure (not shown) that partially covers the insulating structure 290 can be formed on the substrate 110, and then a drain doped region (not shown) and a source doped region (not shown) can be formed through a shield (not shown). Thus, the formation of the drain doped region can be doubly shielded by the insulating structure 290 and the gate structure, allowing the drain doped region to have a more complex discontinuous bottom surface (not shown). In this way, the formed high-voltage semiconductor device should also have the effect of improving the hot carrier injection problem and avoiding the breakdown voltage drop. Furthermore, although the doping range of the aforementioned doped regions (such as drain doped region 260, source doped region 180, etc.) is described as being flush with the sidewalls of the shield 400 or the side components (such as insulating structure 190, etc.) as an embodiment, in actual manufacturing processes, the doping range of each doped region may further diffuse to the area below the side components (not shown) during subsequent drive-in processes. Therefore, the other process embodiments described above should still fall within the scope of this invention.

[0033] Please refer to Figure 6 The diagram shown illustrates a cross-sectional view of the high-voltage semiconductor device 300 according to a second embodiment of the present invention. The structure of the high-voltage semiconductor device 300 in this embodiment is generally similar to that described above. Figure 2 The first embodiment shown is the same, and the similarities will not be repeated. The main difference between this embodiment and the first embodiment is that the drain doped region 260 and the source doped region 380 in this embodiment can have a mutually symmetrical structure, for example, having the same width.

[0034] Specifically, the source doped region 380 is also disposed between the gate structure 230 and the insulating structure 192, and the width w3 of the source doped region 380 is, for example, equal to the width w1 of the drain doped region 260. In this embodiment, the source doped region 380 extends further from one side of the insulating structure 192 to below the gate structure 230, so that the source 170 can be located within the source doped region 380 in the horizontal direction and surrounded by the source doped region 380. Thus, the source 170 and the insulating structure 390 can be separated by a portion of the source doped region 380 (i.e., a portion of the third source doped region 383), such that the distance g between the source 170 and the insulating structure 390 is, for example, about 1 micrometer to 2.5 micrometers, preferably 1.5 micrometers to 2 micrometers, but not limited thereto. Under this configuration, the source 170 of this embodiment can also serve as the drift region of the high-voltage semiconductor device 300.

[0035] Furthermore, it should be noted that an additional insulating structure 390 is provided below the gate structure 230 near the source 170, allowing the portion of the source doped region 380 extending below the insulating structure 390 and the gate structure 230 to have a discontinuous bottom surface 380a. The fabrication process and structure of the insulating structure 390 are largely the same as those of the insulating structure 290, and will not be described in detail here. The source doped region 380 may also include a first source doped region 381, a second source doped region 382, ​​and a third source doped region 383 arranged sequentially from bottom to top. Similar to the drain doped region 260 on the left, a portion of the source doped region 380 is also shielded by the insulating structure 390 during its formation, thereby affecting the depth or doping range of the first source doped region 381 and the second source doped region 382 below the insulating structure 390. Thus, the bottom surface of the source doped region 380 is not always at the same horizontal plane, but exhibits discontinuous steep rises or falls in some areas below the adjacent insulating structure 390, resulting in a discontinuous bottom surface 360a for the source doped region 380 as a whole. Figure 6 As shown. The depths of the first source doped region 381, the second source doped region 382, ​​and the third source doped region 383 below the source 170 are roughly the same as the depths d1, d2, and d3 of the first drain doped region 261, the second drain doped region 262, and the third drain doped region 263 below the drain 150. The depths of the first source doped region 381 and the second source doped region 382 below the insulating structure 390 are roughly the same as the depths d1' and d2' of the first drain doped region 261 and the second drain doped region 262 below the insulating structure 290, and will not be described again here.

[0036] Therefore, the source 170 and drain 150 of the high-voltage semiconductor device 300 in this embodiment can have sufficient withstand voltage by means of the gradually decreasing doping concentration of the source doping region 380 and the drain doping region 260 and their discontinuous bottom surfaces 380a and 260a, respectively. This effectively improves the problem of hot carrier injection and avoids the drop in breakdown voltage, thereby achieving better component reliability.

[0037] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included within the scope of the present invention.

[0038] [Symbol Explanation]

[0039] 100, 200, 300: High-voltage semiconductor devices

[0040] 110: Base

[0041] 130: Gate structure

[0042] 150: Drain

[0043] 170: Source Extreme

[0044] 160: Drain doped region

[0045] 161: First drain doped region

[0046] 162: Second drain doped region

[0047] 163: Third drain doped region

[0048] 180: Source doped region

[0049] 181: First source doped region

[0050] 182: Second source doped region

[0051] 183: Third source doped region

[0052] 190, 191, 192: Insulation structure

[0053] 230: Gate structure

[0054] 260: Drain doped region

[0055] 260a: bottom surface

[0056] 261: First drain doped region

[0057] 262: Second drain doped region

[0058] 263: Third drain doped region

[0059] 290: Insulation structure

[0060] 380: Source doped region

[0061] 380a: Bottom surface

[0062] 381: First source doped region

[0063] 382: Second source doped region

[0064] 383: Third source doped region

[0065] 390: Insulation structure

[0066] 400: Block

[0067] 410: Dielectric layer

[0068] 431, 432, 433: Plugs

[0069] a2, a2': Vertical doping range

[0070] C: Substrate current curves of the comparative embodiment

[0071] C': Gate current curve of the comparative embodiment

[0072] d1, d2, d3, d1', d2': Depth

[0073] E1: Substrate current curve of the first embodiment

[0074] E1': Gate current curve of the first embodiment

[0075] g: Spacing

[0076] w1, w2, w3: Width

Claims

1. A high-voltage semiconductor device, comprising: One base; A gate structure is disposed on the substrate; A drain electrode is disposed within the substrate and located on one side of the gate structure; A first insulating structure is disposed on the substrate, wherein the first insulating structure is located below the gate structure and partially overlaps the gate structure; as well as A drain-doped region is disposed within the substrate, located below the drain and the first insulating structure, and the drain-doped region has a discontinuous bottom surface extending horizontally between the two sides of the first insulating structure. The drain-doped region further includes a first drain-doped region and a second drain-doped region, both located below the drain and the first insulating structure. The depth of the portion of the bottom surface of the second drain-doped region below the drain within the substrate is less than the depth of the portion of the bottom surface of the first drain-doped region below the drain within the substrate, but greater than the depth of the portion of the bottom surface of the first drain-doped region below the first insulating structure within the substrate.

2. The high-voltage semiconductor device as described in claim 1, wherein, The depth of the drain doped region located below the first insulating structure is less than the depth of other parts of the drain doped region.

3. The high-voltage semiconductor device as described in claim 1, wherein, The doping concentration of the first drain doped region is less than that of the second drain doped region.

4. The high-voltage semiconductor device as described in claim 1, further comprising: A third drain doped region is disposed within the substrate, above the first drain doped region and the second drain doped region, and a portion of the third drain doped region is located between the drain and the first insulating structure.

5. A high-voltage semiconductor device as described in claim 4, wherein, The doping concentration of the third drain doped region is greater than the doping concentration of the first drain doped region and the doping concentration of the second drain doped region.

6. A high-voltage semiconductor device as described in claim 5, wherein, The third drain doped region is located only below the drain and surrounds the drain.

7. The high-voltage semiconductor device as described in claim 1, further comprising: A source electrode, disposed within the substrate, located on the other side of the gate structure; and A source doped region is disposed within the substrate and located below the source.

8. A high-voltage semiconductor device as described in claim 7, wherein, The source doped region is symmetrical to the drain doped region.

9. A high-voltage semiconductor device as described in claim 7, wherein, The source doped region is asymmetric to the drain doped region.

10. The high-voltage semiconductor device as described in claim 7, further comprising: A second insulating structure is disposed on the substrate, wherein the first insulating structure and the second insulating structure are respectively located on two opposite sides of the source electrode.

11. The high-voltage semiconductor device as described in claim 1, further comprising: A third insulating structure is disposed on the substrate, wherein the first insulating structure and the third insulating structure are respectively located on two opposite sides of the drain electrode.

12. A method for forming a high-voltage semiconductor device, comprising: Provide a base; An insulating structure is formed on the substrate; A drain electrode is formed within the substrate; A drain-doped region is formed within the substrate. The drain-doped region has a discontinuous bottom surface below the insulating structure, extending horizontally between the two sides of the insulating structure. The drain-doped region further includes a first drain-doped region and a second drain-doped region, both located below the drain and the first insulating structure. The depth of the bottom surface of the second drain doped region located below the drain in the substrate is less than the depth of the bottom surface of the first drain doped region located below the drain in the substrate, but greater than the depth of the bottom surface of the first drain doped region located below the first insulating structure in the substrate. as well as A gate structure is formed on the substrate.

13. The method for forming a high-voltage semiconductor device as described in claim 12, wherein, The gate structure is formed on a portion of the insulating structure.

14. The method for forming a high-voltage semiconductor device as described in claim 12, wherein, The step of forming the drain doped region includes: A doping process is performed, wherein the doping voltage of the doping process is 700 to 800 kiloelectron volts.

15. The method for forming a high-voltage semiconductor device as described in claim 12, wherein, The vertical doping range of the drain doped region formed below the insulating structure is smaller than the vertical doping range of other parts of the drain doped region.

16. The method for forming a high-voltage semiconductor device as described in claim 12, wherein a portion of the drain doped region is disposed between the drain and the insulating structure.

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