Ldo free wireless power receiver with rectifier regulator

Abstract

Disclosed herein are LDO free wireless power receivers with rectification regulators, in which a bridge rectifier and associated control circuitry that collectively form a "rectification regulator" are capable of rectifying an input time-varying voltage and regulating the resulting rectified output voltage. To accomplish this, the gate voltages of the transistors of the bridge rectifier that are turned on during a given phase can be modulated via analog control (to increase the on-resistance of those transistors) or via pulse width modulation (to turn off those transistors before the end of the phase). Alternatively or additionally, transistors of the bridge rectifier that would otherwise be turned off during a given phase can be turned on to help dissipate excess power, and thereby regulate the output voltage. No conventional voltage regulator (such as a low-dropout amplifier) is used in this design.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of wireless power transfer, and in particular to hardware, techniques for operation of the hardware, and methods for causing a bridge rectifier to perform a rectification function and a regulation function. BACKGROUND

[0002] Portable electronic devices, such as smartphones, smartwatches, audio output devices (earbuds, headphones), and wearable devices, rely on batteries for power, rather than wired power sources transmitted to them through wired transmission lines and electrical distribution systems. Batteries for such devices are typically rechargeable, and thus methods for recharging the batteries are needed.

[0003] Most portable electronic devices include a charging port, typically conforming to the Micro USB or USB-C standards, into which a power cord connected to a power source can be plugged to provide recharging for their batteries. However, such charging ports can be difficult to improve the water resistance of the electronic devices, and are prone to damage from repeated use. In addition, some smaller portable electronic devices (e.g., earbuds and smartwatches) can lack the available space to provide a charging port. Furthermore, some users can find it cumbersome to plug a power cord into the charging port of an electronic device to charge the battery of the device.

[0004] Accordingly, to address these issues, wireless power transfer has been developed. As Figure 1 shown, a typical prior art wireless power transfer system 10 utilizes a transmitter 11 including a transmission coil Lp and a series capacitor Cp to form a series resonant L,C network driven by electrical power from a power source 12 (typically a wired connection, but in some cases a battery), to generate a time-varying electric field, and a receiver 15 including a reception coil Ls and a series capacitor Cs to form a similar series resonant L,C network in which the time-varying electric field induces an AC current. Other possible configurations exist in which the L,C are parallel on the primary side and / or the secondary side, providing four possible schemes— series-series, series-parallel, parallel-series, and parallel-parallel. Depending on the application, each scheme can present some advantages and / or disadvantages, and the series-series configuration is most widely used in recent developments targeting the mobile device market. The receiver 15 includes a bridge rectifier 16 (composed of the illustrated diodes D1-D4) that rectifies the AC current to produce a DC current that charges a tank capacitor Ctank connected to an input node Nin of a regulator 17 to a regulator input voltage. The regulator 17 (typically a low-dropout amplifier) produces a regulated output voltage at its output node Nout, which is provided to a load (represented by a load resistance Rl and a load capacitance Cl).

[0005] Although this prior art wireless power transfer system 10 is functional and is widely used, the use of the regulator 17 consumes a large amount of integrated circuit area due to the use of high power MOS devices by the regulator 17. Since this wireless power transfer system 10 is mainly used in portable electronic devices, this area consumption is undesirable. Therefore, there is a need for further development of wireless power transfer systems. SUMMARY

[0006] Disclosed herein are bridge rectifiers and associated control circuitry that together form a "rectifier regulator" capable of rectifying an input time-varying voltage and regulating the resulting rectified output voltage. To accomplish this, the gate voltages of the transistors of the bridge rectifier that are turned on during a given phase can be modulated via analog control (to increase the on-circuit of those transistors) or via pulse width modulation (to turn off those transistors before the end of the phase). Alternatively or additionally, transistors of the bridge rectifier that would otherwise be turned off during a given phase can be turned on to help dissipate excess power and thereby regulate the output voltage. No conventional voltage regulator, such as a low-dropout amplifier, is used in this design. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic block diagram of a prior art wireless power transfer system.

[0008] Figure 2 is a schematic block diagram of a wireless power transfer system disclosed herein, in which the bridge rectifier also performs the regulation function, enabling the absence of additional voltage regulation circuitry.

[0009] Figure 3 is a schematic block diagram of a wireless power transfer system Figure 2 in operation (when the feedback loop is controlling the bridge rectifier to perform in-phase serial voltage regulation).

[0010] Figure 4 is a schematic block diagram of a wireless power transfer system Figure 2 of FIG. 1 in operation during phase A of the in-phase serial voltage regulation of FIG. 1. Figure 3

[0011] is a schematic block diagram of a wireless power transfer system Figure 5 of FIG. 1 in operation during phase B of the in-phase serial voltage regulation of FIG. 1. Figure 2 Figure 3

[0012] Figure 6 is a schematic block diagram of a wireless power transfer system​​Figure 2 Timing diagram of the voltage of the wireless power transmission system during operation (when the feedback loop is controlling the bridge rectifier to perform inverse parallel voltage regulation).

[0013] Figure 7 yes Figure 2 A schematic block diagram of a wireless power transmission system, illustrating the use of... Figure 6 The operation of the wireless power transmission system during phase A of the inverse parallel voltage regulation.

[0014] Figure 8 yes Figure 2 A schematic block diagram of a wireless power transmission system, illustrating the use of... Figure 6 The operation of the wireless power transmission system during phase B of the inverse parallel voltage regulation.

[0015] Figure 9 It shows Figure 2 A timing diagram of the voltage of the wireless power transmission system during operation (when the feedback loop is controlling the bridge rectifier to perform low-side in-phase serial voltage regulation). In this example, regulation is applied only on the low side to allow for a better understanding of the material difference between the drive signal applied to the low side according to the wireless power transmission system disclosed herein and the conventional drive signal applied to the high side according to the prior art.

[0016] Figure 10 It shows Figure 2 Timing diagram of the voltage of the wireless power transmission system during operation (when the feedback loop is controlling the bridge rectifier to perform low-side inverse parallel voltage regulation).

[0017] Figure 11 It shows Figure 2 The timing diagram of the voltage in operation of the wireless power transmission system, wherein the feedback loop switches between controlling the bridge rectifier to perform in-phase serial voltage regulation and controlling the bridge rectifier to perform in-phase parallel voltage regulation of the FSK symbols transmitted during power transmission.

[0018] Figure 12 This is a timing diagram showing the feedback signal FB and the PWM control of the modulated transistor when operating using PWM-based in-phase serial voltage regulation.

[0019] Figure 13 It shows Figure 2 Timing diagram of the voltage of the wireless power transmission system during operation (when the feedback loop is controlling the bridge rectifier to perform low-side PWM-based in-phase serial voltage regulation).

[0020] Figure 14is a timing diagram showing the three different PWM control techniques available when the feedback loop is controlling the bridge rectifier to perform low-side PWM-based in-phase serial voltage regulation.

[0021] Figure 15 is a schematic diagram of an alternative configuration of the rectifier regulator of Figure 2

[0022] Figure 16 is a timing diagram showing one of the PWM control techniques available when the feedback loop is controlling the bridge rectifier to perform low-side PWM-based in-phase serial voltage regulation using the rectifier regulator of Figure 16

[0023] Figure 17a is a timing diagram of the AC1 and AC2 signals and the associated generated GA and GB signals within the controller of Figure 2

[0024] Figure 17b is the output / input transfer function of the hysteresis comparator used within the controller of Figure 2

[0025] is a schematic diagram of the hysteresis comparator used to generate the GA signal. Figure 17c

[0026] is a schematic diagram of the hysteresis comparator used to generate the GB signal. Figure 17d

[0027] Figure 18a is a schematic diagram illustrating the mode selection circuitry within the controller of Figure 2 Figure 2

[0028] Figure 18b is a schematic diagram illustrating the mode selection circuit within the controller of Figure 2 Figure 2

[0029] Figure 18c is a schematic diagram illustrating the presence of an amplifier and a comparator as a feedback loop.

[0030] Figure 19 is a timing diagram showing the voltages in operation of the wireless power transfer system of Figure 2 ​​​​​​​​​

[0031] Figure 20 is a block diagram illustrating components of a controller for performing fly mode switching between in-phase serial voltage regulation and anti-phase parallel voltage regulation.

[0032] Figure 21 is a method of operating Figure 20 a mode switching circuit arrangement to switch a rectifier regulator between performing in-phase serial voltage regulation and anti-phase parallel voltage regulation.

[0033] Figure 22 is a timing diagram illustrating Figure 2 voltages in operation of the wireless power transfer system of when the feedback loop is controlling the bridge rectifier to perform low-side anti-phase parallel voltage regulation. Note that here, the feedback generation of the feedback signal is filtered, so the gates of the transistors of the bridge rectifier are driven pseudo-statically.

[0034] Figure 23 is a timing diagram illustrating Figure 2 voltages in operation of the wireless power transfer system of when the feedback loop is controlling the bridge rectifier to perform low-side anti-phase parallel voltage regulation. Note that here, the feedback generation of the feedback signal is filtered, so the gates of the transistors of the bridge rectifier are driven pseudo-statically.

[0035] Figure 24 is a timing diagram illustrating Figure 2 voltages in operation of the wireless power transfer system of when the feedback loop is controlling the bridge rectifier to perform low-side in-phase serial voltage regulation. Note that here, the feedback generation of the feedback signal is filtered, so the gates of the transistors of the bridge rectifier are driven pseudo-statically.

[0036] Figure 25 is a timing diagram illustrating Figure 2 voltages in operation of the wireless power transfer system of when the feedback loop is controlling the bridge rectifier to perform low-side in-phase serial voltage regulation. Note that here, the feedback generation of the feedback signal is filtered, so the gates of the transistors of the bridge rectifier are driven pseudo-statically. DETAILED DESCRIPTION

[0037] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein. It should be noted that when transistors are described below as “on,” this means that those transistors are operating in the linear or saturation region, not in the cutoff region.

[0038] A. Hardware Description

[0039] Now for reference Figure 2 The description includes a wireless power transmission system 20 comprising a transmitter 21 and a receiver 22. The transmitter 21 includes an AC voltage source 12 coupled to a serial resonant reflector coil Lp and a capacitor Cp. The receiver 22 includes a serial resonant receiver coil Ls and a capacitor Cs coupled between nodes Ac1 and Ac2, and a “rectifier regulator” 25 (a bridge rectifier capable of voltage regulation when controlled using the techniques described below) formed by transistors M1 to M4 coupled between node N1 and ground.

[0040] The rectifier regulator is formed by: an n-channel transistor M1 having a drain connected to node N1, a source connected to node Ac1, and a gate coupled to receive a control signal G1; an n-channel transistor M4 having a drain connected to node Ac1, a source connected to ground, and a gate coupled to receive a control signal G4; an n-channel transistor M3 having a drain connected to node N1, a source connected to node Ac2, and a gate coupled to receive a control signal G3; and an n-channel transistor M2 having a drain connected to node Ac2, a source connected to ground, and a gate coupled to receive a control signal G2.

[0041] Amplifier 23 has an inverting input terminal coupled to receive a reference voltage Vref (which is set to be equal to the desired output voltage Vrect at node N1), a non-inverting input terminal coupled to node N1, and an output coupled to control circuitry 24 and generating a feedback signal FB. A load is connected between node N1 and ground, and is represented by resistor R1 and capacitor C1. Control circuitry 24 itself receives the input from the feedback signal FB and generates control signals G1 to G4 for transistors M1 to M4 based on this input.

[0042] As will be explained in detail below, the control circuitry 24 generates control signals G1 through G4 to cause the rectifier regulator 25 to rectify the AC current induced in the receiver coil Ls to produce a rectified output voltage Vrect, and at the same time to appropriately modulate one or more of the control signals G1 through G4 to dissipate excess power to thereby regulate the output voltage Vrect. By dissipating excess power, the power delivered by the rectifier regulator 25 to the load can be controlled and maintained within a desired level without the need to use a separate discrete voltage regulation circuit.

[0043] Thus, the amplifier 23 and the control circuitry 24 form a feedback loop.

[0044] B. Operation using in-phase serial voltage regulation

[0045] The operation of the wireless power transmission system 20 under the in-phase serial voltage regulation scheme controlled by the control circuit 24 will now be described.

[0046] In Figure 3 Shown in the graph of FIG. 3 are the waveform traces of the signals at node Ac1 and node Ac2. Note that when the signal at Ac1 is positive, it is labeled as phase A, when the signal at Ac2 is positive, it is labeled as phase B, and the signals at Ac1 and Ac2 are 180° out of phase with each other.

[0047] During phase A, corresponding to the positive phase of Ac1 and the negative phase of Ac2, the control signal GA is generated and driven by the controller 24 to a high voltage (a level sufficient to fully turn on transistors M1-M2), and the control signal GB is generated and pulled by the controller 24 to a low voltage (a level to fully turn off transistors M3-M4). Conversely, during phase B, the control signal GB is driven by the controller 24 to a high voltage and the control signal GA is pulled by the controller 24 to a low voltage. The controller 24 generates the gate voltages G1 through G4 for the transistors M1 through M4, and the values of G1 through G4 depend on the voltage values of the control signals GA and GB, the voltage of the feedback signal FB, and the current phase.

[0048] When the incoming power delivered to the load by the rectifier regulator 25 exceeds the power consumed by the load, the voltage Vrect at node N1 rises above the reference voltage Vref, causing the feedback signal FB to rise. As the feedback signal FB rises, the control circuitry 24 modulates appropriate gate voltages from G1 to G4 to place the associated transistors M1 to M4 into the linear region (ohmic region) of operation and increases the drain-to-source resistance of those transistors, causing the excess incoming power to be dissipated within the activated transistors M1 to M4 of the rectifier regulator 25. This modulation continues throughout operation, resulting in the voltage Vrect remaining close to the reference voltage Vref.

[0049] When the modulation of gate voltages G1 to G4 does not occur, the gate voltages G1-G2 are equal to the voltage of the control signal GA.

[0050] 1. Analog control of transistor gate

[0051] More in detail, such as Figure 3 As shown, gate voltages G1 and G2 are modulated during stage A, preventing transistors M1 and M2 from being fully turned on. This increases the drain-to-source resistance of transistors M1 and M2, resulting in additional power dissipation in transistors M1 and M2 beyond normal operation. Gate voltages G3 and G4 remain pulled low, keeping transistors M3 and M4 off. Figure 4 The configuration of transistors M1 to M4 can be seen in the image.

[0052] During phase B, such as Figure 3 As shown, gate voltages G3 and G4 are modulated, preventing transistors M3 and M4 from fully conducting and increasing the drain-to-source resistance of transistors M3 and M4, resulting in additional power dissipation in transistors M3 and M4 beyond normal operation; gate voltages G1 and G2 remain pulled low, keeping transistors M1 and M2 off. This can be achieved... Figure 5 The configuration of transistors M1 to M4 can be seen in the image.

[0053] This operating scheme is called in-phase serial modulation because transistors M1 to M4, which are normally fully conducting during a given phase, are switched to conductivity modulation, thus... Figure 4 and Figure 5 As shown, during this method, power dissipation is achieved by increasing the conductivity and voltage drop within the components connected in series in the main current path to the load.

[0054] It should be noted that during phase A, the voltage levels of gate voltages G1 and G2 need not both be modulated to increase the drain-to-source resistance of their respective transistors M1 and M2, but rather only one of gate voltages G1 or G2 can be modulated to increase the drain-to-source resistance of its respective transistor M1 or M2, and the other control signal can remain high to maintain its respective transistor M1 or M2 fully on.

[0055] Similarly, during phase B, the voltage levels of gate voltages G3 and G4 need not both be modulated to increase the drain-to-source resistance of their respective transistors M3 and M4, but rather only one of gate voltages G3 or G4 can be modulated to increase the drain-to-source resistance of its respective transistor M3 or M4, and the other control signal can remain high to maintain its respective transistor M3 or M4 fully on.

[0056] The selection of techniques to apply to one or more elements will be understood / considered in comparison to the maximum excess power amount to be dissipated by the system.

[0057] As an example of this form of operation where one transistor M1-M4 is modulated at a time and the modulation is not flat over each pulse of the gate voltage, Figure 9 Additional waveforms are shown for wireless power transfer system 20 operating using in-phase serial regulation. Here, it can be seen that during phase A, the gate voltage G2 of transistor M2, which turns on transistor M2, is pulled from a steady high voltage of 5.0V to less than 4V, and the gate voltage G1 of transistor M1, which turns on transistor M1, remains high and the gate voltage G3 of transistor M3 and the gate voltage G4 of transistor M4 remain low. Here, it can also be seen that during phase B, the gate voltage G4 of transistor M4, which turns on transistor M4, is pulled from a steady high voltage of 5.0V to less than 4V, and the gate voltage G3 of transistor M3, which turns on transistor G3, remains high and the gate voltage G1 of transistor M1 and the gate voltage G2 of transistor M2 remain low.

[0058] It should be noted that when gate voltages G2 and G4 are pulled down from full high to modulate the on-resistance of transistors M2 and M4, this is performed for about half of the pulse of those gate voltages. However, if additional power needs to be dissipated by the arrangement, then gate voltages G2 and G4 can be pulled down from full high for more than half of the pulse of those gate voltages in order to modulate the on-resistance of transistors M2 and M4 for a longer period of time. These techniques are clearly applicable to the case where two transistors are modulated at a time.

[0059] The in-phase serial voltage regulation scheme described above is particularly suitable for use cases where the voltage output Vrect of the rectification regulator 25 is relatively low and the expected excess power to be dissipated is relatively low.

[0060] It should be noted that the feedback loop formed by the amplifier 23 and the control circuitry 24 can operate at a sufficient speed so that it acts on a cycle-to-cycle basis, enabling the control circuitry 24 to alter the generation of the gate voltages G1 to G4 on a cycle-to-cycle basis when performing in-phase serial voltage regulation (meaning that the gate voltages G1 to G4 can be adjusted to have different flat amplitudes during each cycle, or the gate voltages G1 to G4 can be modified on-the-fly during each cycle so that the gate voltages G1 to G4 can start a cycle with one amplitude, but that amplitude can be changed during part of the cycle). This feedback technique can be observed in the graph of Figure 9 where the feedback signal FB is generated during each phase, enabling the control signals G1 to G4 to be altered on a cycle-to-cycle basis.

[0061] However, in some cases, the feedback loop formed by the amplifier 23 and the control circuitry 24 can operate slowly compared to the frequency of the signal being transmitted by the transmitter 21. In this way, the generation of the feedback signal FB is not on a cycle-to-cycle basis, instead the generation of the feedback signal FB is filtered, allowing the gates of the transistors M1 to M4 to be driven pseudo-statically. When operating using inverting parallel regulation, the waveforms showing this mode of operation can be seen in Figures 22-23 and when operating using in-phase serial regulation, the waveforms showing this mode of operation can be seen in Figures 24-25 .

[0062] 2. PWM control of transistor gates

[0063] In the description given above, the gate voltages G1 to G4 of the transistors M1 to M4 were modulated in an analog fashion by the control circuitry 24 to perform in-phase serial voltage regulation. Now, techniques for modulating the gate voltages G1 to G4 of the transistors M1 to M4 using pulse width modulation (PWM) to perform in-phase serial voltage regulation are described.

[0064] The first way in which the gates of transistors from M1 to M4 to be regulated are operated involves simple switching PWM. Here, the amplifier is configured as a comparator to provide the feedback signal FB as a digital output, resulting in a pulse FB during which the output voltage Vrect exceeds the reference voltage Vref. During this pulse, the respective gate voltages of M1 to M4 are pulled to ground, the transistors from M1 to M4 that are fully on during the current phase are fully turned off in response to the rise of FB, in turn increasing power dissipation. Thus, through feedback, the duration of the gate voltages G1 to G4 driving the transistors M1 to M4 is regulated so that the output pulse duration of the rectifier regulator 25 is just long enough to provide the required power but just short enough to dissipate excess power.

[0065] A simple example of this technique can be seen in the trace of Figures 12-13 where it can be seen that here the feedback signal FB is digitized, the gate voltage G1 is maintained as a full high during phase A, and the gate voltage G2 is pulled low through about half of phase A to increase the resistance of the drain to source of transistor M2 to increase power dissipation. Note that as shown, spikes can appear in the gate voltage G2 being modulated, and these spikes can be filtered by the control circuitry 24, such as by using a de-bouncing function.

[0066] In the example of Figure 13 , the gate voltages G2 and G4 of the low side transistors (M2 and M4) are modulated, while the gate voltages G1 and G3 of the high side transistors (M1 and M3) are not modulated. However, both the low side transistors and the high side transistors can be modulated. As shown in Figure 14 , during phase A, to provide voltage regulation, the gate voltages G1 and G2 (in response to the feedback signal FB rising, which can be seen to occur when Vrect exceeds Vref) are turned off fully earlier than they would otherwise be using a conventional wireless power transmission system, maintaining the output voltage Vrect at the desired level and dissipating excess power. Similarly, during phase B, to provide voltage regulation, the gate voltages G3 and G4 (in response to the feedback signal FB rising) are turned off fully earlier than they would otherwise be using a conventional wireless power transmission system, maintaining the output voltage Vrect at the desired level and dissipating excess power.

[0067] The second way in which the gates of transistors from M1 to M4 to be regulated are operated involves modifying the rectifier regulator itself to produce a modified rectifier regulator 25'. From Figure 15As can be seen, each transistor of the rectifier regulator 25' is split into two parallel coupled transistors having different W / L ratios from one another to provide different resistivities when individually controlled, where the sum of the width and length of each parallel coupled pair of transistors is equal to the width and length of the corresponding transistor of the rectifier regulator 25 to provide exactly the same resistivity as the rectifier regulator 25 when fully on. Thus, the rectifier regulator 25 includes: parallel coupled n-channel transistors Ml and Mlb, where their drains are coupled to node Nl, their sources are coupled to node Acl, and their gates are coupled to receive gate voltages Gl and Gla, respectively; parallel coupled n-channel transistors M4 and M4b, where their drains are coupled to node Acl, their sources are coupled to ground, and their gates are coupled to receive control signals M4 and M4a, respectively; parallel coupled n-channel transistors M3 and M3b, where their drains are coupled to node Nl, their sources are coupled to node Ac2, and their gates are coupled to receive gate voltages G3 and G3a, respectively; and parallel coupled n-channel transistors M2 and M2a, where their drains are coupled to node Ac2, their sources are coupled to ground, and their gates are coupled to receive gate voltages G2 and G2a, respectively.

[0068] The area of transistor Ml in the rectifier regulator 25' is 90% of the area of transistor Ml in the rectifier regulator 25, and the area of transistor Mla in the rectifier regulator 25' is 10% of the area of transistor Ml in the rectifier regulator 25; the area of transistor M2 in the rectifier regulator 25' is 90% of the area of transistor M2 in the rectifier regulator 25, and the area of transistor M2a in the rectifier regulator 25' is 10% of the area of transistor M2 in the rectifier regulator 25; the area of transistor M3 in the rectifier regulator 25' is 90% of the area of transistor M3 in the rectifier regulator 25, and the area of transistor M3a in the rectifier regulator 25' is 10% of the area of transistor M3 in the rectifier regulator 25; and the area of transistor M4 in the rectifier regulator 25' is 90% of the area of transistor M4 in the rectifier regulator 25, and the area of transistor M4a in the rectifier regulator 25' is 10% of the area of transistor M4 in the rectifier regulator 25. It should be noted that the relative sizes of the above transistors Ml to M4 can vary, and for example, the transistors Ml to M4 of the rectifier regulator 25' can be 80% of the area of the transistors Ml to M4 of the rectifier regulator 25, while the transistors Mla-M4a of the rectifier regulator 25' can be 20% of the area of the transistors Ml to M4 of the rectifier regulator 25.

[0069] With this, the control circuitry 24' is also modified to output gate voltages Gla to G4a in addition to gate voltages Gl to G4, as shown. Figure 15

[0070] With this modified rectifier regulator 25', during phase A, gate voltages Gla and G2a are fully high for the entire phase, while gate voltages Gl and G2 are fully high for a first portion of the phase and then decrease for an excess portion of the phase, as shown in FIG. 6A. Similarly, during phase B, gate voltages G3a and G4a are fully high for the entire phase, while gate voltages G3 and G4 are fully high for a first portion of the phase and then decrease for an excess portion of the phase, as shown in FIG. 6B. Using this technique helps avoid the induction of noise that can result when fully on transistors are turned off, because when transistors Gl and G2 are turned off, transistors Gla and G2a remain on for the excess portion of phase A, and because when transistors G3 and G4 are turned off, transistors G3a and G4a remain on for the excess portion of phase B. Figure 14 Figure 16

[0071] A third way of operating the gates from the transistors Ml to M4 to be regulated involves switching the gate voltages Gl to G4 between a first predetermined constant drive voltage and a second predetermined constant drive voltage. During phase A, gate voltages Gl and G2 are fully high (first constant drive voltage) for a first portion of the phase and then decrease to the second constant drive voltage for an excess portion of the phase, as shown in FIG. 5A. Similarly, during phase B, gate voltages G3 and G4 are fully high (first constant drive voltage) for a first portion of the phase and then decrease to the second constant drive voltage for an excess portion of the phase, as shown in FIG. 5B. The first portion of phases A and B can be about 90% of the total elapsed time of those phases, while the second portion of phases A and B can be an excess portion of the total elapsed time of those phases. Figure 14

[0072] It should be noted that while Figure 14 the first way of operating the gates can induce noise that can result when the transistors are turned off, the second way can result in high current density in small devices (10%) during repeated time elapses, the third way has the benefit of being simple in digital method, as it uses only two drive levels, and will allow, as the analog method, minimization of current density in the devices.

[0073] ​​​​It should be noted that the feedback loop formed by the amplifier 23 and the control circuitry 24 can operate at a sufficient speed so that it acts on a cycle-to-cycle basis, enabling the control circuitry 24 to alter the generation of the gate voltages G1 to G4 on a cycle-to-cycle basis when performing in-phase serial voltage regulation. This feedback technique can be observed in the graph of Figure 9 where the feedback signal FB is generated during each phase, enabling the gate voltages G1 to G4 to be altered on a cycle-to-cycle basis.

[0074] However, in some cases, the feedback loop formed by the amplifier 23 and the control circuitry 24 can operate slowly compared to the frequency of the signal being transmitted by the transmitter 21. In this way, the generation of the feedback signal FB is not on a cycle-to-cycle basis, instead the generation of the feedback signal FB is filtered, allowing the gates of the transistors M1 to M4 to be driven pseudo-statically.

[0075] C. Operation using anti-phase parallel voltage regulation

[0076] The operation of the wireless power transfer system 20 under the out-of-phase parallel voltage regulation scheme controlled by the control circuitry 24 will now be described.

[0077] Figure 6 The graph of

[0078] During phase A, the gate voltages G1 and G2 are driven, fully turning on the transistors M1 and M2, while during phase B, the gate voltages G3 and G4 are driven, not fully turning on the transistors M3 and M4. Typically, the transistors in M1 to M4 that are not turned on during a given phase are fully turned off.

[0079] However, with the out-of-phase parallel voltage regulation scheme, when the amount of incoming power delivered by the rectifier regulator 25 to the load is greater than the amount of power consumed by the load, the voltage Vrect at the node N1 rises above the reference voltage Vref, causing the feedback signal FB to rise. When the feedback signal FB rises, the control circuitry 24 modulates the appropriate gate voltages from G1 to G4 to turn on one or more of the transistors M1 and M2, or M3 and M4 that are typically turned off during the current phase, and places those transistors in the saturation region of operation. The result is that these transistors M1 and M2, or M3 and M4 that are additionally turned on draw a modest current but have a large drain-to-source voltage, thus inducing enough power loss to consume the excess incoming power.

[0080] More in detail, such as Figure 6 As shown, in stage A, gate voltages G1 and G2 are at high levels to fully turn on transistors M1 and M2, and those transistors remain fully turned on during stage A. However, here, although at voltage amplitudes smaller than gate voltages G1 and G2, gate voltages G3 and G4 are also driven to thereby fully turn on transistors M3 and M4, which have drain-to-source voltages and associated impedances sufficient to dissipate additional power in normal operation. Similarly, in stage B, gate voltages G3 and G4 are at high levels to fully turn on transistors M3 and M4, and those transistors remain fully turned on during stage B. However, here, although at voltage amplitudes smaller than gate voltages G3 and G4, gate voltages G1 and G2 are also driven to thereby fully turn on transistors M1 and M2, which have drain-to-source voltages and associated impedances sufficient to dissipate additional power in normal operation.

[0081] This operating scheme is called inverse parallel regulation because transistors M1 to M4, which are normally fully on during a given phase, remain fully on, while transistors from M1 to M4, which are normally off during a given phase, are sufficiently turned on to dissipate excess power not consumed by the load, and because, as Figures 7-8 As shown, power dissipation is achieved by increasing the conductivity of the components and creating an additional current path in the device, which is off during normal operation when the method described is used, and which is actually parallel to the main current path when on.

[0082] It should be noted that during stage B, gate voltages G1 and G2 do not need to be modulated to turn on their respective transistors M1 and M2 in linear operation mode, while gate voltages G3 and G4 remain high to keep their respective transistors M3 and M4 fully turned on. Instead, only one of the gate voltages G1 or G2 can be modulated while the other gate voltage can remain off to keep its respective transistor M1 or M2 fully turned off.

[0083] Similarly, during phase A, gate voltages G3 and G4 do not need to be modulated while gate voltages G1 and G2 remain high to keep their respective transistors M1 and M2 fully turned on. Instead, only one of the gate voltages G3 or G4 can be modulated while the other gate voltage can remain off to keep its respective transistor M3 or M4 fully turned off.

[0084] As an example of this mode of operation in which one of the transistors M1 to M4 is modulated during the phase when it would normally be completely turned off, Figure 10Additional waveforms are shown for the wireless power transfer system 20 operating using inverse parallel regulation. Here, it can be seen that the feedback signal FB is generated during each phase, and that during phase A the gate voltages G1 and G2 are fully high to turn on transistors M1 and M2, and the gate voltage G4 is raised to approximately 1 V to turn on transistor M4, which has a drain-to-source resistance sufficient to dissipate additional power above regular operation. It can also be seen that during phase B the gate voltages G3 and G4 are fully high to turn on transistors M3 and M4, and the gate voltage G2 is raised to approximately 1 V to turn on transistor M2, which has a drain-to-source resistance sufficient to dissipate additional power above regular operation.

[0085] The inverse parallel voltage regulation scheme described above is particularly suitable for use cases in which the voltage output Vrect of the rectification regulator 25 is not relatively low and the expected excess power to be dissipated is also not relatively low. Thus, when operating using the inverse parallel voltage regulation scheme, the rectification regulator 25 is able to dissipate a large amount of excess power and maintain the transistors of the rectification regulator 25 within their safe operating limits.

[0086] It should be noted that the feedback loop formed by the amplifier 23 and the control circuitry 24 can operate at a speed sufficient that it acts on a cycle-to-cycle basis, enabling the control circuitry 24 to alter the generation of the gate voltages G1 to G4 on a cycle-to-cycle basis when performing inverse parallel voltage regulation. This feedback technique can be observed in the graph of FIG. 4, in which the feedback signal FB is generated during each phase, enabling the gate voltages G1 to G4 to be altered on a cycle-to-cycle basis. Figure 10 It should be noted that the feedback loop formed by the amplifier 23 and the control circuitry 24 can operate at a speed sufficient that it acts on a cycle-to-cycle basis, enabling the control circuitry 24 to alter the generation of the gate voltages G1 to G4 on a cycle-to-cycle basis when performing inverse parallel voltage regulation. This feedback technique can be observed in the graph of FIG. 4, in which the feedback signal FB is generated during each phase, enabling the gate voltages G1 to G4 to be altered on a cycle-to-cycle basis.

[0087] However, in some cases the feedback loop formed by the amplifier 23 and the control circuit 24 can operate slowly compared to the frequency of the signal being transmitted by the transmitter 21. In this way, the generation of the feedback signal FB is not on a cycle-to-cycle basis, instead the generation of the feedback signal FB is filtered, allowing the gates of the transistors M1 to M4 to be driven pseudo-statically.

[0088] D. Combination of in-phase serial voltage regulation and anti-phase parallel voltage regulation

[0089] Since the above-described in-phase serial voltage regulation involves modulating the gate voltage of one or both of the transistors that are normally on during a given phase, and since the above-described anti-phase parallel voltage regulation involves modulating the gate voltage of one or both of the transistors that are normally off during a given phase, it should be understood that both techniques can be utilized simultaneously. Thus, the gate voltage of one or both of the transistors of rectifier regulator 25 can be modulated according to the in-phase serial regulation scheme, while the gate voltage of one or both of the other transistors of rectifier regulator 25 can be modulated according to the anti-phase parallel regulation scheme, and simultaneously the non-modulated transistors of rectifier regulator 25 are operated conventionally.

[0090] Furthermore, in some cases, the in-phase serial voltage regulation scheme and the anti-phase parallel voltage regulation scheme can be used separately. For example, the in-phase serial voltage regulation scheme can be used during one phase, and the anti-phase parallel voltage regulation scheme can be used during the next phase.

[0091] As another example of a combination of in-phase serial voltage regulation and anti-phase parallel voltage regulation, the in-phase serial voltage regulation scheme can be used for a given number of phases (e.g., for one phase A and the subsequent phase B), and then the anti-phase parallel voltage regulation scheme can be used for a given number of phases (e.g., for the next phase A and the subsequent phase B).

[0092] As another example of a combination of in-phase serial voltage regulation and anti-phase parallel voltage regulation, the in-phase serial voltage regulation scheme can be used on one or both of the high-side transistors (transistors Ml and M3), while the anti-phase parallel voltage regulation scheme can be used on one or both of the low-side transistors (transistors M2 and M4), or vice versa.

[0093] As yet another example, which of the in-phase serial voltage regulation scheme and the anti-phase parallel voltage regulation scheme is used can depend on the additional power to be dissipated to switch. When the additional power to be dissipated is below a certain threshold, the gate voltages G1 through G4 can be generated so as to operate rectifier regulator 25 using the in-phase serial voltage regulation scheme, and the gate voltages G1 through G4 can then switch to being generated so as to operate rectifier regulator 25 using the anti-phase parallel voltage regulation scheme.

[0094] E. Control signal generation and feedback loop

[0095] Reference is now made to FIG. 17 and Figure 19 Control circuitry 24 is described. First, the generation of control signals GA and GB will be described, after which the generation of gate voltages for transistors Ml through M4 from gate voltages GA and GB will be described.

[0096] The control circuitry 24 includes a hysteretic comparator 51 having a non-inverting terminal coupled to the node Ac1, an inverting terminal coupled to ground, and an output that produces GA.

[0097] The control circuitry 24 includes a hysteretic comparator 54 having a non-inverting terminal coupled to the node Ac2, an inverting terminal coupled to ground, and an output that produces GB.

[0098] Reference is made to Figure 17a When generating the control voltages GA and GB, the operation of the control circuitry 24 is thus that when the AC signal at the node Ac1 rises to become greater than a first threshold of the hysteretic comparator 51 (in this example, 0 mV) (reference Figure 17c ), the output GA of the comparator 51 is pulled low. Similarly, when the AC signal at the node Ac2 falls (which occurs when the AC signal at the node Ac1 rises) and is less than a second threshold of the hysteretic comparator 54 (in this example, -200 mV) (reference Figure 17d ), the output GB of the comparator 54 is pulled high.

[0099] Conversely, when the AC signal at the node Ac1 falls and as a result is less than the second threshold of the hysteretic comparator 51, the output GA of the comparator 51 is pulled high. Similarly, when the AC signal at the node Ac2 rises to become greater than the first threshold of the hysteretic comparator 54, the output of the comparator 54 is pulled low.

[0100] Reference is now made to Figures 18a to 19 The excess portion of the control circuitry 24 is described for the case of PWM control without the use of transistor gates.

[0101] It is noted that as a general practice for low-side drive techniques, the signals used to drive the gates of M2 and M4 are buffered. Further, it is noted that as a general practice for high-side drive techniques, the signals used to drive the gates of M1 and M3 are level-shifted and buffered. For simplicity, the following description will assume that GA, GB, and any composite signals derived from GA, GB, FB are coupled directly to the gates, and in actual implementation, buffers and level-shifting techniques will be used in keeping with the techniques mentioned above for low-side and high-side drive techniques.

[0102] When switch ml is closed, indicating that rectifier regulator 25 is to operate as a standard rectifier, control signal GA is coupled to the gates of transistors Ml and M2 as gate voltages Gl and G2, regardless of phase, and control signal GB is coupled to the gates of transistors M3 and M4 as gate voltages G3 and G4, regardless of phase. Thus, during phase A, transistors Ml and M2 are fully on while transistors M3 and M4 are fully off, and during phase B, transistors M3 and M4 are fully on while transistors Ml and M2 are fully off.

[0103] When switch ml is closed, indicating that rectifier regulator 25 is to operate as a standard rectifier, control signal GA is coupled to the gates of transistors Ml and M2 as gate voltages Gl and G2, regardless of phase, and control signal GB is coupled to the gates of transistors M3 and M4 as gate voltages G3 and G4, regardless of phase. Thus, during phase A, transistors Ml and M2 are fully on while transistors M3 and M4 are fully off, and during phase B, transistors M3 and M4 are fully on while transistors Ml and M2 are fully off.

[0104] When switch m2 is closed, the rectifier regulator 25 is instructed to operate so as to perform anti-phase parallel voltage regulation, in phase A: voltage FB is applied to control signal GB, and the result is then coupled to the gate of transistor M3 as gate voltage G3; voltage FB is applied to control signal GB, and the result is then coupled to the gate of transistor M4 as gate voltage G4; control signal GA is coupled to the gate of transistor Ml as gate voltage Gl; and control signal GA is coupled to the gate of transistor T2 as gate voltage G2. In phase B: voltage FB is applied to control signal GA, and the result is coupled to the gate of transistor Ml as gate voltage Gl; voltage FB is applied to control signal GA, and the result is coupled to the gate of transistor M2 as gate voltage G2; control signal GB is coupled to the gate of transistor M3 as gate voltage G3; and control signal GB is coupled to the gate of transistor M4 as gate voltage G4. Thus, during phase A, transistors Ml and M2 are fully on, while the gates of transistors M3 and M4 are driven sufficiently to cause dissipation of excess power through transistors M3 and M4 but not enough to prevent rectification. Similarly, during phase B, transistors M3 and M4 are fully on, while the gates of transistors Ml and M2 are driven sufficiently to cause dissipation of excess power through transistors Ml and M2 but not enough to prevent rectification.

[0105] Reference is now made to Figure 18b and Figure 18c , the excess part of the control circuitry 24 is described for PWM control of the transistor gates in accordance with the first and second ways of operating the gates in Figure 14 . The feedback signal FB in accordance with Figure 18a has been split into two parts, where FBA is the output of the feedback amplifier 23 (named FB in Figure 2 ) and FBD is the output of the digitized feedback provided by the comparator 23', and accordingly generates the signals to the timing diagrams in accordance with Figure 12 . During operation, FBD can take two levels, labeled FBD_H and FBD_L. Now assuming that the drive strength of GA, GB is VDD, the signal GA-FBD (respectively GB-FBD) will provide two levels of drive strength, VDD-VGH and VDD-VGL. Thus, in the case of using VGH = VDD and VGL = 0, the signal GA-FBD (respectively GB-FBD) will provide two levels of drive strength, 0 and VDD, so as to drive in accordance with the first way of operating the gates on Figure 14 .

[0106] Now, in the case of using VGH = VDD-V1 and VGH = 0, the signal GA-FBD (respectively GB-FBD) will provide two levels of drive strength, V1 and VDD, so as to drive in accordance with the second way of operating the gates on Figure 14 .Figure 14 the third way of driving the gate on the rectifier regulator 25'.

[0107] It should be noted that when the rectifier regulator 25' is in the series mode controlled by ml, or in the parallel mode controlled by m2, and if the FB signal (FBA and FBD respectively) is gated to zero, the rectifier regulator 25' behaves exactly like the regulator 25' in the normal mode controlled by m0, because when FBA and FBD are gated to zero, GA+FBD, GB+FBD, GA-FBA, GB-FBA are equal to GA, GB, which can happen for example when Vrect is much lower than the target.

[0108] The skilled person will understand from Figure 15 how to generalize Figure 18b the third way of driving the gate on the rectifier regulator 25'.

[0109] The hardware and techniques for automatically switching the rectifier regulator 25' between in-phase series voltage regulation using PWM and anti-phase parallel voltage regulation are now described.

[0110] Reference is now made to Figure 20The illustration shows hardware included within controller 24 for automatically switching rectifier regulator 25' between in-phase serial voltage regulation and in-phase parallel voltage regulation using PWM. Serial monitoring circuit 50 includes a duty cycle determination circuit that uses counters to determine the duty cycles of control signals GA and GB during the execution of PWM in-phase serial voltage regulation (thereby determining gate voltages G1 to G4), and thus the duty cycle of the output of rectifier regulator 25' is determined by counting the number of pulses of the high-frequency counter clock HFClk within each pulse of control signals GA and GB, counting the number of pulses of the high-frequency counter clock within each pulse of control signals GA' and GB' (thereby determining gate voltages G1a to G4a), and dividing the number of pulses of the high-frequency clock HFClk within each pulse of control signals GA and GB by the number of pulses of the high-frequency clock within each pulse of control signals GA' and GB'. The duty cycle will be referred to as Duty_Ser_SH below: for example, if the duty cycle of rectifier regulator 25' is found to be 90%, then Duty_Ser_SH will be 90%. The serial monitoring circuit 50 also includes a digital comparator 52 that compares each occurrence of Duty_Ser_SH with an established duty cycle limit, Duty_Ser_limit, and the latch then asserts the Duty_Ser_limit_latch_B signal when the current occurrence of Duty_Ser_SH is greater than Duty_Ser_limit. When the current occurrence of Duty_Ser_SH is less than the duty cycle limit, Duty_Ser_limit, the digital comparator 52 cancels the assertion of the Duty_Ser_limit_latch_B signal. It should be noted that during the inverting parallel mode, the Duty_Ser_limit_latch_B signal is always asserted as high.

[0111] The controller 24 also includes a parallel monitoring circuit 60 comprising an n-channel transistor M5, which is a copy (illustratively a copy of G1 or G2) of one of the transistors in the rectifier regulator 25', receiving the corresponding gate voltage G1 or G2 at its gate, having its source coupled to node Ac1, and its drain coupled to a first current mirror 61. During inverting parallel voltage regulation, the first current mirror 61 mirrors the current Ipar flowing through the copy transistor M5 to a second current mirror 62, which in turn mirrors the current to the inverting terminal of an amplifier 63 configured as an integrator of IinHS (if transistor M5 is a copy of transistor M1 or M3) or IinLS (if transistor M5 is a copy of transistor M2 or M4). It should be noted that the current mirror 61 can advantageously be supplied from the Vrect node, and the power consumption of the current mirror is not significant, as it functions as part of the overall target of consuming excessive input power in any case. Thus, it should be understood that the ratio K1 does not need to be very high and good mirror matching performance is feasible. The inverting terminal of integrator 63 is coupled to ground, and capacitor C and reset switch are coupled in parallel between the output and the inverting terminal of integrator 63. The output of integrator 63 is the Int_charge_par signal, which is compared with the current limit Ipar_limit by latchable comparator 64, and the result is latched by comparator 64 and then inverted by inverter 65 to generate the Ipar_limit_latch_B signal. It should be noted that the Ipar_limit_latch_B signal is designed to always be asserted high during in-phase serial mode because no current flows in the inverting parallel regulation HW.

[0112] The mode switching control circuit device 80 includes an AND gate 81 that receives the Duty_Ser_limit_latch_B signal and the Ipar_limit_latch_B signal, performs a logical AND operation, and generates a signal 103 as an output. Since the Duty_Ser_limit_latch_B signal is always asserted as high during the inverted parallel mode, and the Ipar_limit_latch_B signal is designed to always be asserted as high during the non-inverted serial mode, the AND gate 81 does indeed always have one of its two inputs at logic one. Therefore, the AND gate 81 is the entry point for automatic switching between the two modes.

[0113] AND gate 82 receives signal 104 and initialization signal Reset_Init as inputs, performs a logical AND operation, and generates ULP_Auto_Pre signal as output. OR gate 84 receives ULP_Auto_Pre signal from AND gate 82 as input, and receives ULP_Auto_0_latch signal from non-retriggerable monostable 83 as input, performs a logical OR operation, and generates ULP_Auto_0 signal as output. Monostable 83 receives ULP_Auto_0 signal as input and generates ULP_Auto_0_latch signal as output.

[0114] Comparator 86 receives output voltage Vrect at its non-inverting terminal and reference voltage Vref+200mv at its inverting terminal, and generates Vgate_over signal as output. AND gate 87 receives Vgate_over signal and ULP_Auto_0 signal as inputs, performs a logical AND operation, and generates signal 101 as output, which in turn is inverted by inverter 88 to generate ULP_Auto_En signal as output. AND gate 85 receives ULP_Auto_0 signal and ULP_Auto_En signal as inputs, performs a logical AND operation, and generates ULP_Auto_1 signal as output. AND gate 89 receives ULP_Auto_1 signal from AND gate 85 as input, and signal 110 as output of inverter gate 92, which receives its input from output 111 of non-retriggerable monostable 91. AND gate 89 performs a logical AND operation to generate ULP_Auto signal as output, which is inverted by inverter 90 and passed to the input of monostable 91.

[0115] Non-retriggerable monostables 83 and 91 receive initialization signal Reset_Init, which is asserted when it is desired to reset monostables 83 and 91 to be retriggerable once more.

[0116] As will be explained, controller 24 generates gate voltages G1 to G4 and G1a to G4a of transistors M1 to M4 and M1a to M4a to cause rectifier regulator 25' to perform in-phase serial voltage regulation when ULP_Auto signal is logic one, and to generate gate voltages G1 to G4 and G1a to G4a of transistors M1 to M4 and M1a to M4a to cause rectifier regulator 25' to perform anti-phase parallel voltage regulation when ULP_Auto signal is logic zero.

[0117] The operation of mode switching control circuitry 80 will now be described with additional reference to Figure 21 to FIG. 4.

[0118] At power-up and / or reset, the Reset_Init signal is set to a logic zero, which resets monostables 83 and 91 and integrator 63 by closing its switch (block 201). As a result, the AND gate 82 outputs the ULP_Auto_Pre signal as a logic zero and the monostable 83 outputs the ULP_Auto_0_latch as a logic zero, causing the OR gate 84 to output the ULP_Auto_0 signal as a logic zero. Since the ULP_Auto_0 signal is a logic zero, the AND gate 85 will output the ULP_Auto_1 signal as a logic zero, and in turn the AND gate 89 will output the ULP_Auto signal as a logic zero. It should be noted that at this time the input 110 has no influence, because the ULP_Auto_1 is a logic 0. However, if the ULP_Auto_1 has just transitioned from a logic one to a logic zero, the input 110 would keep ULP_Auto to logic 0 for a while.

[0119] Next, to exit the reset, the Reset_Init signal is set to a logic one (block 202). At this time, the power delivery has not yet started, so the control signals GA, GB, GA’ and GB’ are zero. As a result of the control signals GA, GB, GA’ and GB’ being zero, the gate voltages G1 to G4 and G1a to G4a are generated to be zero.

[0120] As a result of G1 to G4, G1a to G4b being zero: the rectifier regulator 25’ operates in asynchronous mode as a regular 4-diode rectifier, and Vrect is free to rise under the influence of incoming power, which in turn supplies the controller 24’, which in turn generates the signals G1 to G4, G1a to G4b.

[0121] At this time, because the Vrect voltage is still low and below the target, the rectifier regulator 25’ operates as a regular rectifier as previously emphasized, and as a first result the Duty_Ser_SH signal is high and the comparator 52 outputs the Duty_Ser_limit_latch_B signal as a logic one.

[0122] As a second effect of the rectifier regulator 25’ operating as a regular rectifier, the currents Ipar and IinHS / IinLS are zero because no commutation occurs, with the result that the amplifier 63 outputs the Int_charge_par signal to be zero. As a result of the Int_charge_par signal being zero, the Ipar_limit is greater than Int_charge_par, and the comparator 64 latches and outputs a logic zero, which is inverted by the inverter 65 to produce the Ipar_limit_latch_B signal at a logic one.

[0123] Since both Duty_Ser_limit_latch and Ipar_limit_latch_B are at logic one, the signal 103 output by AND gate 81 is logic one, and since the Reset_Init signal is at logic one, the ULP_Auto_Pre signal output by AND gate 82 is logic one. As a result of the ULP_Auto_Pre signal being logic one, the ULP_Auto_0 signal is output by OR gate 84 as logic one, in turn causing the ULP_Auto_0_latch signal to rise to logic one, in turn triggering monostable 83, in turn applying logic one to the ULP_Auto_0_latch, which remains at logic one during the duration of the monostable 83 pulse, which guarantees a logic one on ULP_Auto_0 during the duration of the pulse generated by monostable 83. Thus, each time ULP_Auto_0 transitions from logic zero to logic one, the system is able to latch ULP_Auto_0 logic one for the minimum duration set by the monostable pulse duration.

[0124] Since the output voltage Vrect will be lower than Vref, the reference voltage Vref + 200mV is greater than Vrect, causing the Vgate_over signal output by comparator 86 to be logic zero, and in turn, the signal 101 output by AND gate 87 to be logic zero and inverted by inverter 88 to produce the ULP_Auto_En signal as logic one. In other words, the Vgate_over signal has no effect during this phase. The relevance of the function will be further explained.

[0125] Note that since ULP_Auto is produced as logic zero during the reset, inverter 90 outputs logic one, causing monostable 91 to produce logic one at its output as signal 110. Since ULP_Auto_0 is logic one and since the ULP_Auto_En signal is logic one, the ULP_Auto_1 signal output by AND gate 85 is produced as logic one. Since the ULP_Auto_1 signal is logic one and since signal 110 is logic one, the ULP_Auto signal will at this time be output by AND gate 89 as logic one.

[0126] The ULP_Auto signal at logic one causes the controller 23 to generate GA, GB, GA’ and GB’, whereby it performs in-phase serial regulation (block 203) on top of the regular operation of rectifying the current induced in the secondary coil Ls. Initially, the output voltage Vrect will be significantly less than Vref, so the comparator 23 will constantly speak the feedback signal FB.

[0127] Operation continues in this open loop fashion with the output voltage Vrect remaining less than the reference voltage Vref (block 204). As operation continues, the output voltage Vrect will rise. Once the output voltage Vrect becomes higher than or equal to the reference voltage Vref (block 204), the feedback signal FB is asserted by the comparator 23 and closed loop serial phase-locked regulation begins (block 205). At this point, closed loop serial phase-locked regulation using PWM continues as described in detail above and continues until the Duty_ser_limit_latch_B signal is pulled to logic low (block 206). This occurs when the duty cycle Duty_Ser_SH of the rectifier regulator 25' falls below 10% (meaning the Duty_Ser_SH signal falls below 10% to become less than Duty_Ser_limit, which is set to 10%, causing the comparator 52 to output Duty_Ser_limit_latch_B as a logic zero).

[0128] Duty_Ser_limit_latch_B being output as a logic zero in turn causes the signal 103 output by the AND gate 81 to become a logic zero, causing ULP_Auto_Pre output by the AND gate 82 to become a logic zero, causing the OR gate 84 to output the ULP_Auto_0 signal as a logic zero (because ULP_Auto_0 is a logic zero), in turn causing ULP_Auto_1 output by the AND gate 85 to be a logic zero, and thus ULP_Auto signal output by the AND gate 89 to be a logic zero.

[0129] The ULP_Auto signal being output as a logic zero causes the controller 23 to generate GA, GB, GA' and GB' in order to rectify the current induced in the secondary winding Ls when performing inverted parallel regulation (block 207).

[0130] It should be noted that the transition of ULP_Auto from a logic one to a logic zero does indeed trigger the monostable 91 after being inverted by the inverter 90, the output of which once inverted by the inverter gate 92 results in a logic zero on the input 110 and ensures that a logic zero on the AND gate 89 is maintained during the duration of the non-retriggerable monostable 91.

[0131] Thus, until the time elapsed since the start of the anti-parallel regulation becomes greater than the minimum time (block 208), the anti-parallel regulation continues. If the time elapsed becomes greater than the minimum time (block 208), but neither the Ipar_limit_latch_B signal nor the Duty_Ser_limit_latch_B signal are both logic ones, then ULP_Auto continues to be output as a logic zero and the anti-parallel regulation continues. However, if both the Ipar_limit_latch_B signal and the Duty_Ser_limit_latch_B signal become equal to logic ones (block 209), then the controller 23 again generates GA, GB, GA' and GB' in order to rectify the current induced in the secondary winding Ls when performing the in-phase serial regulation (block 210).

[0132] The system remains in serial in-phase regulation until the time elapsed becomes greater than the minimum time (block 211). Once this occurs, the system continues to check whether both the Ipar_limit_latch_B signal and the Duty_Ser_limit_latch_B signal are both at logic ones, and if these two conditions are still true, then the in-phase serial regulation continues.

[0133] However, if the time has not yet elapsed while the output exceeds the reference voltage plus the tolerance (set at 200 mV in the example block 212), the signal 101 rises to a logic one and ULP_Auto_En falls to zero, then the controller 23 returns to generating the control signals G1 to G4 and Gla to G4a in order to cause the transistors M1 to M4 and Mla to M4a of the rectifier regulator 25' to perform the anti-parallel regulation. Thus, the system also has the ability to self-exit the in-phase serial loop with the highest priority in the event of a Vrect overvoltage, which helps to guarantee that if the system enters in-phase serial regulation for less time than the time elapsed, but the coincident entering power becomes too high, the system is still able to exit the in-phase serial mode and enter the anti-parallel mode.

[0134] As such, the rectifier 24' switches instantaneously between in-phase serial voltage regulation and anti-phase parallel voltage regulation, where in-phase serial voltage regulation is used from power-up / reset and until the closed loop in-phase serial regulation causes the rectifier regulator 24' to operate at a duty cycle less than 10% (indicated by the Duty_Ser_SH signal falling below the Duty_Ser_Limit signal), at which time anti-phase parallel voltage regulation is used. This continues until the anti-phase parallel voltage regulation has been used for a given time period and until the anti-phase parallel current falls below a current threshold (the duty cycle limit detection Duty_Ser_Limit_latch_B is asserted by default during parallel regulation), at which time it returns to serial regulation. Then, if serial regulation has not been used for a given time period, but the output voltage Vrect becomes greater than the reference voltage Vref + 200mv, then it returns to parallel voltage regulation. Otherwise, serial regulation remains and cycles until the duty cycle falls too low.

[0135] Thus, in summary, in-phase serial voltage regulation is used until the duty cycle of the rectifier regulator 25' falls below 10%, which means that 90% of the power dissipation capability of the rectifier regulator 25' is being utilized. At this point, anti-phase parallel voltage regulation is used for its additional power dissipation capability. Should the regulated voltage become too high during a given time window, the parallel voltage regulation has the ability to stop the serial regulation, and uses anti-phase voltage regulation until the current it draws falls below a defined limit. This advantageously allows the appropriate voltage regulation scheme to be used given the current operating conditions.

[0136] G. Advantages

[0137] The in-phase serial voltage regulation scheme and the anti-phase parallel voltage regulation scheme have a variety of advantages, including: a significant area saving provided by eliminating separate discrete voltage regulators (including power transistors and tank capacitors) such as low dropout amplifiers, and a power saving when the wireless power transfer system 20 is operating at equilibrium. Furthermore, these schemes spread the excess power dissipation over four devices (transistors M1-M4) rather than all of the excess power dissipation being absorbed by a single power transistor within an additional voltage regulator. Still further, these schemes allow the receiver 22 to be easily used as a transmitter, since node N1 (at which the voltage Vrect is generated) can be directly accessed.

[0138] The efficiency difference between the prior art wireless power transfer system and the wireless power transfer system 20 is shown in the following table:

[0139]

[0140] Among other advantages, it is noted that the system efficiency is improved by nearly 3%.

[0141] Another advantage offered is that when the operation of the wireless power transmission system 20 includes both data communication and power transmission, such as when data transmission occurs from receiver 22 to transmitter 21, the data symbols (ASK symbols) received by transmitter 21 are cleaner due to the use of amplitude shift keying (ASK). This can... Figure 11 As can be seen, the signal received by the transmitter 21 of the wireless power transmission system 20 using the prior art (labeled Vcoil LDO primary) contains reduced amplitude peaks in its pulse, but the signal received by the transmitter 21 (labeled Vcoil_3Regtifier) ​​uses the wireless data transmission system 20 to contain flat amplitude peaks in its pulse, which makes symbol extraction at the primary side easier.

[0142] Furthermore, when performing ASK data transmission using existing power transmission systems, the modulation depth varies depending on the magnitude of the input power and the output voltage Vrect because the drain-to-source resistance of the power transistors in a discrete voltage regulator varies significantly with the magnitude of the input power and the output voltage Vrect. However, when using the wireless data transmission system 20 described herein, the drain-to-source resistance variation of the four transistors M1 to M4 of the rectifier regulator is much smaller than that of a single power transistor in a discrete voltage regulator, maintaining the modulation depth at a generally constant level.

[0143] While this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments can be conceived without departing from the scope of this disclosure. Therefore, the scope of this disclosure should be limited only by the appended claims.

Claims

1. A wireless power receiving system, comprising: The transistor bridge rectifier arrangement receives the input time-varying power signal and is coupled between the ground and the output node; A feedback device receives input from the output node and generates a feedback signal based on the input; A control circuit, coupled to receive the input time-varying power signal and the feedback signal, and based on the input time-varying power signal and the feedback signal, generates the gate voltage of the transistors for the bridge rectifier arrangement to cause: During the first phase, two transistors of the bridge rectifier arrangement are turned on, and during the second phase, two other transistors of the bridge rectifier arrangement are turned on, thereby causing the rectification of the input time-varying power signal to generate an output voltage at the output node. as well as During the first phase, the gate voltage of at least one transistor in the bridge rectifier arrangement is modulated, and during the second phase, the gate voltage of at least one other transistor in the bridge rectifier arrangement is modulated, thereby causing dissipation of excess power transmitted by the input time-varying power signal, and thus performing output voltage regulation on rectification. The control circuit wherein, during the first phase, turns on the two transistors by generating the respective gate voltages of the two transistors arranged in the bridge rectifier to have a first constant amplitude. The at least one transistor having a gate voltage modulated during the first phase is one of the two transistors that are turned on during the first phase; The control circuit modulates the gate voltage of the at least one transistor during the first stage by reducing the gate voltage of the at least one transistor, such that the magnitude of the gate voltage of the at least one transistor decreases from the first constant magnitude to a second constant magnitude that is less than the first constant magnitude. The control circuit wherein, during the second phase, turns on the two other transistors by generating the respective gate voltages of the two other transistors arranged in the bridge rectifier to have the first constant amplitude. The at least one transistor having a gate voltage modulated during the second phase is one of the two transistors that are turned on during the second phase; and The control circuit modulates the gate voltage of the at least one transistor during the second phase by reducing the gate voltage of the at least one transistor, such that the amplitude of the gate voltage of the at least one transistor decreases from the first constant amplitude to the second constant amplitude.

2. The wireless power receiving system according to claim 1, The at least one transistor having a gate voltage modulated during the first phase is one of the two transistors that are turned on during the first phase; The at least one other transistor having a gate voltage modulated during the second phase is one of the two transistors that are turned on during the second phase; The modulation of the gate voltage of the at least one transistor during the first stage and the modulation of the gate voltage of the at least one other transistor during the second stage are used to modulate the drain-to-source resistance of the at least one transistor and the at least one other transistor, such that the excess power transmitted by the input time-varying power signal is dissipated.

3. The wireless power receiving system of claim 2, wherein the at least one transistor having a gate voltage modulated during the first phase is a high-side transistor; and wherein the at least one other transistor having a gate voltage modulated during the second phase is a high-side transistor.

4. The wireless power receiving system of claim 2, wherein the at least one transistor having a gate voltage modulated during the first phase is a low-side transistor; and wherein the at least one other transistor having a gate voltage modulated during the second phase is a low-side transistor.

5. The wireless power receiving system according to claim 1, The at least one transistor having a gate that is modulated during the first phase is not one of the two transistors that are turned on during the first phase; The at least one other transistor having a gate that is modulated during the second phase is not one of the two transistors that are turned on during the second phase; The modulation of the gate voltage of the at least one transistor during the first stage and the modulation of the gate voltage of the at least one other transistor during the second stage are used to fully turn on the at least one transistor and the at least one other transistor, such that the excess power transmitted by the input time-varying power signal is dissipated.

6. The wireless power receiving system of claim 5, wherein the at least one transistor having a gate voltage modulated during the first phase is a high-side transistor; and wherein the at least one other transistor having a gate voltage modulated during the second phase is a high-side transistor.

7. The wireless power receiving system of claim 5, wherein the at least one transistor having a gate voltage modulated during the first phase is a low-side transistor; and wherein the at least one other transistor having a gate voltage modulated during the second phase is a low-side transistor.

8. The wireless power receiving system of claim 1, wherein the feedback device comprises an amplifier having a non-inverting terminal coupled to the output node, an inverting terminal coupled to a reference voltage, and an output, wherein the feedback signal is generated at the output.

9. The wireless power receiving system of claim 8, wherein the reference voltage is a desired output voltage; wherein if the output voltage at the output node exceeds the reference voltage, the amplifier amplifies the feedback signal, and the control circuitry adjusts the modulation of the gate voltage of at least one transistor of the bridge rectifier arrangement during the first phase and adjusts the modulation of the gate voltage of at least one other transistor of the bridge rectifier arrangement during the second phase to cause sufficient dissipation of excess power transmitted by the input time-varying signal, such that the output voltage at the output node remains close to the reference voltage.

10. The wireless power receiving system according to claim 1, The bridge rectifier arrangement of the transistors includes: A second and a third transistor are connected in series between the output node and ground, and a first and a fourth transistor are connected in series between the output and ground; The two transistors turned on during the first phase are the first transistor and the second transistor, and the two transistors turned on during the second phase are the third transistor and the fourth transistor; The at least one transistor having a gate voltage modulated during the first phase is the first transistor; and The at least one transistor having a gate voltage modulated during the second phase is the third transistor.

11. The wireless power receiving system according to claim 1, The bridge rectifier arrangement of the transistors includes: A second and a third transistor are connected in series between the output node and ground, and a first and a fourth transistor are connected in series between the output and ground; The two transistors turned on during the first phase are the first transistor and the second transistor, and the two transistors turned on during the second phase are the third transistor and the fourth transistor; The at least one transistor having a gate voltage modulated during the first phase is the second transistor; and The at least one transistor having a gate voltage modulated during the second phase is the fourth transistor.

12. The wireless power receiving system according to claim 1, The bridge rectifier arrangement of the transistors includes: A second and a third transistor are connected in series between the output node and ground, and a first and a fourth transistor are connected in series between the output and ground; The two transistors turned on during the first phase are the first transistor and the second transistor, and the two transistors turned on during the second phase are the third transistor and the fourth transistor; The at least one transistor having a gate voltage modulated during the first phase is the first transistor and the second transistor; and The at least one transistor having a gate voltage modulated during the second phase is the third transistor and the fourth transistor.

13. The wireless power receiving system according to claim 1, The bridge rectifier arrangement of the transistors includes: A second and a third transistor are connected in series between the output node and ground, and a first and a fourth transistor are connected in series between the output and ground; The two transistors turned on during the first phase are the first transistor and the second transistor, and the two transistors turned on during the second phase are the third transistor and the fourth transistor; The at least one transistor having a gate voltage modulated during the first phase is the third transistor; and The first transistor is the one having at least one gate voltage that is modulated during the second phase.

14. The wireless power receiving system according to claim 1, The bridge rectifier arrangement of the transistors includes: A second and a third transistor are connected in series between the output node and ground, and a first and a fourth transistor are connected in series between the output and ground; The two transistors turned on during the first phase are the first transistor and the second transistor, and the two transistors turned on during the second phase are the third transistor and the fourth transistor; The at least one transistor having a gate voltage modulated during the first phase is the fourth transistor; and The at least one transistor having a gate voltage modulated during the second phase is the second transistor.

15. The wireless power receiving system according to claim 1, The bridge rectifier arrangement of the transistors includes: A second and a third transistor are connected in series between the output node and ground, and a first and a fourth transistor are connected in series between the output and ground; The two transistors turned on during the first phase are the first transistor and the second transistor, and the two transistors turned on during the second phase are the third transistor and the fourth transistor; The at least one transistor having a gate voltage modulated during the first phase is the third transistor and the fourth transistor; and The at least one transistor having a gate voltage modulated during the second phase is the first transistor and the second transistor.

16. The wireless power receiving system according to claim 1, wherein the control circuit comprises: The control signal generator is configured as follows: During the first stage, a first control signal is generated having a voltage amplitude sufficient to fully turn on the transistors of the bridge rectifier arrangement, and a second control signal is generated having a voltage amplitude sufficiently low to completely turn off the transistors of the bridge rectifier arrangement. During the second phase, the second control signal is generated to have a voltage amplitude sufficient to fully turn on the transistors of the bridge rectifier arrangement, and the first control signal is generated to have a voltage amplitude low enough to completely turn off the transistors of the bridge rectifier arrangement. The first switching circuit is configured as follows: During the first stage, the gate voltage for the at least one transistor is generated by generating a gate voltage equal to the voltage of the first control signal minus the voltage of the feedback signal; and During the second stage, the gate voltage for the at least one transistor is generated by generating a gate voltage equal to the voltage of the first control signal; as well as The second switching circuit is configured as follows: During the first stage, the gate voltage for the at least one other transistor is generated by generating a gate voltage equal to the voltage of the second control signal; and During the second stage, the gate voltage for the at least one other transistor is generated by generating a gate voltage equal to the voltage of the second control signal minus the voltage of the feedback signal.

17. The wireless power receiving system according to claim 1, wherein the control circuit comprises: The control signal generator is configured as follows: During the first stage, a first control signal is generated having a voltage amplitude sufficient to fully turn on the transistors arranged in the bridge rectifier, and a second control signal is generated having a voltage amplitude sufficiently low to completely turn off the transistors arranged in the bridge rectifier; and During the second phase, the second control signal is generated to have a voltage amplitude sufficient to fully turn on the transistors of the bridge rectifier arrangement, and the first control signal is generated to have a voltage amplitude low enough to completely turn off the transistors of the bridge rectifier arrangement. The first switching circuit is configured as follows: During the first phase, the gate voltage for the at least one transistor is generated to be equal to the voltage of the first control signal; and During the second stage, the gate voltage for the at least one transistor is generated to be equal to the sum of the voltage of the first control signal and the voltage of the feedback signal; as well as The second switching circuit is configured as follows: During the first phase, the gate voltage for the at least one other transistor is generated to be equal to the sum of the voltage of the second control signal and the voltage of the feedback signal; and During the first phase, the gate voltage for the at least one other transistor is generated to be equal to the voltage of the second control signal.

18. The wireless power receiving system according to claim 1, The at least one transistor having a gate voltage modulated during the first phase is one of the two transistors that are turned on during the first phase; The at least one other transistor having a gate voltage modulated during the second phase is one of the two transistors that are turned on during the second phase; The modulation of the gate voltage of the at least one transistor during the first phase and the modulation of the gate voltage of the at least one other transistor during the second phase are performed via pulse width modulation.

19. The wireless power receiving system of claim 18, wherein the at least one transistor having a gate voltage modulated during the first phase is a high-side transistor; and wherein the at least one transistor having a gate voltage modulated during the second phase is a high-side transistor.

20. The wireless power receiving system of claim 18, wherein the at least one transistor having a gate voltage modulated during the first phase is a low-side transistor; and wherein the at least one transistor having a gate voltage modulated during the second phase is a low-side transistor.

21. The wireless power receiving system according to claim 18, The feedback device is a comparator having a non-inverting terminal coupled to the output node, an inverting terminal coupled to a reference voltage equal to the desired output voltage, and an output that generates the feedback signal in digital form. When the output voltage exceeds the reference voltage, the comparator asserts the feedback signal; When the feedback signal is asserted, the control circuit modulates the gate voltage of the at least one transistor by pulling down the gate voltage of the at least one transistor during the first stage, and when the feedback signal is asserted, the control circuit modulates the gate voltage of the at least one other transistor by pulling down the gate voltage of the at least one other transistor during the second stage.

22. The wireless power receiving system of claim 1, wherein the at least one transistor having a gate voltage modulated during the first phase is a high-side transistor; and wherein the at least one transistor having a gate voltage modulated during the second phase is a high-side transistor.

23. The wireless power receiving system of claim 1, wherein the at least one transistor having a gate voltage modulated during the first phase is a low-side transistor; and wherein the at least one transistor having a gate voltage modulated during the second phase is a low-side transistor.

24. The wireless power receiving system according to claim 1, The bridge rectifier arrangement of the transistors includes: A first transistor and a fourth transistor are coupled in series between the output node and ground, and a third transistor and a second transistor are coupled in series between the output node and ground; The feedback device is a comparator having a non-inverting terminal coupled to the output node, an inverting terminal coupled to a reference voltage equal to the desired output voltage, and an output that generates the feedback signal in digital form. When the output voltage exceeds the reference voltage, the comparator asserts the feedback signal; The control circuit, during the first stage, turns on the first transistor and the second transistor of the bridge rectifier by generating the corresponding gate voltages of the first transistor and the second transistor of the bridge rectifier to have a first constant amplitude, and the control circuit, during the second stage, turns on the third transistor and the fourth transistor of the bridge rectifier by generating the corresponding gate voltages of the third transistor and the fourth transistor of the bridge rectifier to have the first constant amplitude. The control circuit modulates the gate voltage during the first phase by reducing the gate voltage of at least one of the first transistor and the second transistor in response to the assertion of the feedback signal, such that the amplitude of the gate voltage of at least one of the first transistor and the second transistor drops from the first constant amplitude to a second constant amplitude that is less than the first constant amplitude. The control circuit modulates the gate voltage of at least one of the third and fourth transistors in response to an assertion of the feedback signal during the second phase; and The control circuit modulates the gate voltage during the second phase by reducing the gate voltage of at least one of the third and fourth transistors in response to the assertion of the feedback signal, such that the amplitude of the gate voltage of at least one of the third and fourth transistors drops from the first constant amplitude to the second constant amplitude.

25. The wireless power receiving system of claim 24, wherein the control circuit modulates only the gate voltage of the first transistor in response to an assertion of the feedback signal during the first phase; and wherein the control circuit modulates only the gate voltage of the third transistor in response to an assertion of the feedback signal during the second phase.

26. The wireless power receiving system of claim 24, wherein the control circuit modulates only the gate voltage of the second transistor in response to an assertion of the feedback signal during the first phase; and wherein the control circuit modulates only the gate voltage of the fourth transistor in response to an assertion of the feedback signal during the second phase.

27. The wireless power receiving system according to claim 1, The bridge rectifier arrangement of the transistors includes: A first transistor and a first accompanying transistor are coupled in parallel between the output node and the first node, wherein the gate of the first transistor is coupled to receive a first gate voltage, and the gate of the first accompanying transistor is coupled to receive a first accompanying gate voltage. A fourth transistor and a fourth accompanying transistor are coupled in parallel between the first node and ground, wherein the gate of the fourth transistor is coupled to receive a fourth gate voltage, and the gate of the fourth accompanying transistor is coupled to receive a fourth accompanying gate voltage. A third transistor and a third accompanying transistor are coupled in parallel between the output node and the second node, wherein the gate of the third transistor is coupled to receive a third gate voltage, and the gate of the third accompanying transistor is coupled to receive a third accompanying gate voltage. A second transistor and a second accompanying transistor are coupled in parallel between the second node and ground, wherein the gate of the second transistor is coupled to receive a second gate voltage, and the gate of the second accompanying transistor is coupled to receive a second accompanying gate voltage. The control circuit is configured as follows: During the first phase, the first transistor, the first accompanying transistor, the second transistor, and the second accompanying transistor are turned on, and during the second phase, the third transistor, the third accompanying transistor, the fourth transistor, and the fourth accompanying transistor are turned on, thereby causing the rectification of the input time-varying power signal to generate an output voltage at the output node; as well as At least one of the first transistor and the second transistor is turned off before the end of the first phase, and at least one of the third transistor and the fourth transistor is turned off before the end of the second phase, thereby causing dissipation of excess power transmitted by the input time-varying power signal.

28. The wireless power receiving system of claim 27, wherein the first transistor and the first accompanying transistor have the same length but different aspect ratios; wherein the second transistor and the second accompanying transistor have the same length but different aspect ratios; wherein the third transistor and the third accompanying transistor have the same length but different aspect ratios; and wherein the fourth transistor and the fourth accompanying transistor have the same length but different aspect ratios.

29. The wireless power receiving system of claim 28, wherein the aspect ratio of the first transistor is greater than that of the first accompanying transistor; wherein the aspect ratio of the second transistor is greater than that of the second accompanying transistor; wherein the aspect ratio of the third transistor is greater than that of the third accompanying transistor; and wherein the aspect ratio of the fourth transistor is greater than that of the fourth accompanying transistor.

30. The wireless power receiving system of claim 27, wherein the control circuit generates gate voltages for the transistors in the bridge arrangement to cause the first and second transistors to turn off before the end of the first phase, and the third and fourth transistors to turn off before the end of the second phase.

31. The wireless power receiving system of claim 27, wherein the control circuit generates gate voltages for the transistors in the bridge arrangement to cause the first transistor to turn off before the end of the first phase and the third transistor to turn off before the end of the second phase.

32. The wireless power receiving system of claim 27, wherein the control circuit generates gate voltages for the transistors in the bridge arrangement to cause the second transistor to turn off before the end of the first phase and the fourth transistor to turn off before the end of the second phase.

33. The wireless power receiving system according to claim 27, The feedback device is a comparator having a non-inverting terminal coupled to the output node, an inverting terminal coupled to a reference voltage equal to the desired output voltage, and an output that generates the feedback signal in digital form. When the output voltage exceeds the reference voltage, the comparator asserts the feedback signal; The control circuit wherein at least one of the first and second transistors is turned off before the end of the first stage by pulling down the corresponding gate voltage in response to an assertion of the feedback signal; and The control circuit wherein at least one of the third and fourth transistors is turned off before the end of the first phase by pulling down the corresponding gate voltage in response to an assertion of the feedback signal.

34. A wireless power receiving system, comprising: The transistor bridge rectifier arrangement receives the input time-varying power signal and is coupled between the ground and the output node; A feedback device receives input from the output node and generates a feedback signal based on the input; A control circuit, coupled to receive the input time-varying power signal and the feedback signal, and based on the input time-varying power signal and the feedback signal, generates the gate voltage of the transistors for the bridge rectifier arrangement to cause: During the first phase, two transistors of the bridge rectifier arrangement are turned on, and during the second phase, two other transistors of the bridge rectifier arrangement are turned on, thereby causing the rectification of the input time-varying power signal to generate an output voltage at the output node. as well as During the first phase, the gate voltage of at least one transistor in the bridge rectifier arrangement is modulated, and during the second phase, the gate voltage of at least one other transistor in the bridge rectifier arrangement is modulated, thereby causing dissipation of excess power transmitted by the input time-varying power signal. Based on the operating conditions of wireless power reception, the control circuit operates the bridge rectifier arrangement in a non-in-phase serial configuration and / or in an out-of-phase parallel configuration. One of the two transistors turned on during the first phase is a high-side transistor, and the other of the two transistors turned on during the first phase is a low-side transistor. In the second phase, one of the two transistors turned on is a low-side transistor, and the other of the two transistors turned on during the second phase is a high-side transistor; and the control circuit operates the bridge rectifier arrangement in the in-phase serial configuration by modulating the gate voltage of the high-side transistor, and in the first phase by modulating the gate voltage of the low-side transistor that is not turned on during the first phase, and in the second phase by modulating the gate voltage of the low-side transistor that is not turned on during the second phase, in the in-phase parallel configuration. or One of the two transistors turned on during the first phase is a high-side transistor, and the other of the two transistors turned on during the first phase is a low-side transistor. In the second phase, one of the two transistors turned on is a low-side transistor, and the other of the two transistors turned on during the second phase is a high-side transistor; and the control circuit operates the bridge rectifier arrangement in the in-phase serial configuration by modulating the gate voltage of the low-side transistor, and in the first phase by modulating the gate voltage of the high-side transistor that is not turned on during the first phase, and in the second phase by modulating the gate voltage of the high-side transistor that is not turned on during the second phase, in the out-of-phase parallel configuration.

35. The wireless power receiving system of claim 34, wherein the modulation of the gate voltage in the in-phase serial configuration is performed via pulse width modulation.

36. The wireless power receiving system according to claim 34, wherein, Based on the operating conditions of the wireless power reception, the control circuit switches between generating a gate voltage to operate the bridge rectifier arrangement in an in-phase serial configuration and generating a gate voltage to operate the bridge rectifier arrangement in an out-of-phase parallel configuration.

37. The wireless power receiving system of claim 34, wherein the operating condition is the amount of excess power to be dissipated.

38. The wireless power receiving system of claim 37, wherein when the excess power to be dissipated is below a threshold, the control circuit switches to generating a gate voltage to operate the bridge rectifier arrangement in the in-phase serial configuration, but when the excess power to be dissipated is above the threshold, the control circuit switches to generating a gate voltage to operate the bridge rectifier arrangement in the out-of-phase parallel configuration.

39. The wireless power receiving system of claim 34, wherein the control circuitry switches between operating the bridge rectifier in the in-phase serial configuration and operating the bridge rectifier in the out-of-phase parallel configuration, depending on whether the current phase is the first phase or the second phase.

40. The wireless power receiving system of claim 34, wherein the control circuitry switches between operating the bridge rectifier in the in-phase serial configuration and operating the bridge rectifier in the out-of-phase parallel configuration, depending on the passage of a given number of stages.

41. The wireless power receiving system of claim 34, wherein in the in-phase serial configuration: The at least one transistor having a gate voltage modulated during the first phase is one of the two transistors that are turned on during the first phase; The at least one other transistor having a gate voltage modulated during the second phase is one of the two transistors that are turned on during the second phase; as well as The modulation of the gate voltage of the at least one transistor during the first phase and the modulation of the gate voltage of the at least one other transistor during the second phase are used to modulate the drain-to-source resistance of the at least one transistor and the at least one other transistor, such that the excess power transmitted by the input time-varying power signal is dissipated.

42. The wireless power receiving system of claim 34, wherein in the in-phase serial configuration: The at least one transistor having a gate voltage modulated during the first phase is one of the two transistors that are turned on during the first phase; The at least one other transistor having a gate voltage modulated during the second phase is one of the two transistors that are turned on during the second phase; as well as The modulation of the gate voltage of the at least one transistor during the first phase and the modulation of the gate voltage of the at least one other transistor during the second phase are performed via pulse width modulation.

43. The wireless power receiving system according to claim 34, wherein, When in the aforementioned anti-parallel configuration: The at least one transistor having a gate that is modulated during the first phase is not one of the two transistors that are turned on during the first phase; The at least one other transistor having a gate that is modulated during the second phase is not one of the two transistors that are turned on during the second phase; as well as The modulation of the gate voltage of the at least one transistor during the first phase and the modulation of the gate voltage of the at least one other transistor during the second phase are used to fully turn on the at least one transistor and the at least one other transistor, such that the excess power transmitted by the input time-varying power signal is dissipated.

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