A general software online maintenance control device

Abstract

The present invention discloses a general software online maintenance control device, which can perform online maintenance, upgrading, error detection, error correction, APP loading, FPGA refresh, etc. of various CPU and FPGA software stored in the memory during the ground test and on-orbit operation of the spacecraft. The general software on-orbit maintenance control device includes an interface communication unit, a memory interface unit, a register unit, a SEFI detection unit, an FPGA loading configuration unit, an FPGA dynamic refresh unit, an FPGA timing readback unit, and a CPU interface unit.

Description

Technical Field

[0001] The invention belongs to the technical field of software maintenance, and relates to a general software online maintenance control device. Background Art

[0002] Software is an important component of the spacecraft's electronic system, and is also the control carrier and information processing center for realizing spacecraft functions and human-machine interaction.

[0003] Software is usually stored in non-volatile memory. After power-on or reset, the CPU or FPGA reads the executable software program data from the memory to start and run the software. The non-volatile memory used to store software can be divided into two types: one-time programmable memory (such as PROM) and reprogrammable memory (such as EEPROM or FLASH):

[0004] When one-time programmable memory is used, the memory on the circuit board must be desoldered once the software needs to be repaired or upgraded, and there is a risk that the software cannot be changed when the spacecraft is in orbit. When reprogrammable memory is used, it is easy to repair and upgrade the software, but it also faces the situation that the software program data stored in the memory is rewritten due to the influence of the space radiation environment, which in turn causes the software to be unable to start and run normally. At the same time, during the on-orbit operation of the spacecraft, although the memory is reprogrammable, there is still a lack of supporting circuits or devices for rewriting the software program data in the memory, which brings difficulties to the on-orbit maintenance and upgrade of the software.

[0005] In addition, when the CPU or FPGA reads and loads software program data from the memory, it can only load software program data from a fixed address, and cannot load different versions of software program data stored at different addresses, which makes it impossible to achieve the selective operation of different software APPs and the reconstruction of system functions, and cannot meet the time-sharing multiplexing of the spacecraft's electronic system for different payloads or functions, which is not conducive to achieving high integration and refined design of spacecraft. In addition, due to the unique configurable structure of FPGA, it may still be affected by the space radiation environment during operation, resulting in abnormal operation of FPGA, which has an adverse impact on the functional stability and continuity of the spacecraft's electronic system.

[0006] To this end, there is an urgent need for a universal spacecraft software on-orbit maintenance control device that can realize the seamless maintenance and loading management of software program data while the spacecraft is on-orbit and during the normal operation of the software, and realize software version control and refresh and error correction management of FPGA, so as to improve the efficiency and reliability of on-orbit maintenance of spacecraft electronic system software. Summary of the invention

[0007] The present invention discloses a general software online maintenance control device, which can perform online maintenance, upgrading, error detection, error correction, APP loading, FPGA refreshing, etc. of various CPU and FPGA software stored in a memory during ground testing and on-orbit operation of a spacecraft.

[0008] The present invention is achieved through the following technical solutions.

[0009] A general software on-orbit maintenance control device comprises: an interface communication unit, a memory interface unit, a register unit, a SEFI detection unit, an FPGA loading configuration unit, an FPGA dynamic refresh unit, an FPGA timing readback unit, and a CPU interface unit; wherein:

[0010] The interface communication unit is used to respond to the instruction interface control signal, obtain the control information in the command frame data field, parse and decode it, and generate a control signal according to the instruction type for reading and writing the register unit or the memory interface unit;

[0011] The memory interface unit is used to implement read and write access control of the non-volatile memory, including address management, patrol control, and encoding and decoding verification;

[0012] The register unit is used to classify and organize the control signal and the status signal to form a control register and a status register, realize the operation control of other units according to the content of the control register, and collect them into the status register in real time;

[0013] The CPU interface unit is used for read and write interface operations and reset control with the CPU;

[0014] The FPGA loading configuration unit is used to load the configuration after the FPGA is powered on or reset;

[0015] The FPGA timing readback unit is used to determine the software configuration data interval that can be read back inside the FPGA according to the control in the register unit, and the working state is controlled by the register unit to be enabled or disabled;

[0016] The FPGA dynamic refresh unit is used to dynamically write repeatedly writable software configuration data inside the FPGA;

[0017] The SEFI detection unit is used to detect single-particle function interruption of the FPGA loading configuration interface.

[0018] Beneficial effects of the present invention:

[0019] (1) The general software online maintenance control device of the present invention realizes unified maintenance management of FPGA and CPU software, which overcomes the disadvantage that traditional spacecraft can only perform online software upgrade and maintenance on some CPUs but cannot perform online upgrade and maintenance on FPGAs, and enhances the on-orbit repair and function reconstruction capabilities of spacecraft software;

[0020] (2) The general software online maintenance control device of the present invention has the ability to dynamically manage the storage addresses of FPGA and CPU software in the non-volatile memory, thereby realizing software version management and loading and starting different versions of software programs as independent software APPs. On the one hand, it can realize the time-sharing multiplexing and functional reconstruction of hardware resources by software, and on the other hand, it can also avoid the migration of software storage intervals in the event of a failure in a certain address interval of the non-volatile memory, thereby enhancing the flexibility and reliability of the spacecraft electronic system;

[0021] (3) The general software online maintenance control device of the present invention can simultaneously realize the online maintenance management of multiple FPGAs and CPUs. For the application of multiple FPGAs and CPUs in coordination, it can save the system resources occupied by software online maintenance and enhance the intensiveness and functional density of spacecraft electronic system design.

[0022] (4) The universal software online maintenance control device of the present invention has the ability to adapt to a variety of different series of FPGAs and CPUs, avoiding the disadvantage that traditional spacecraft need to design special maintenance circuits for each type of FPGA and CPU, and enhancing the versatility and convenience of spacecraft electronic system design;

[0023] (5) The general software online maintenance control device of the present invention has the ability to identify the FPGA loading configuration interface SEFI, and can reload the configuration of the FPGA when the SEFI is detected, thereby timely eliminating the influence of SEFI on the FPGA and enhancing the reliability of the spacecraft FPGA in the space radiation environment;

[0024] (6) The general software online maintenance control device of the present invention supports a read-back refresh mode for FPGA. Compared with the mode in which the traditional spacecraft only refreshes the FPGA, it can effectively avoid the probability of introducing errors by frequently writing software configuration data to the FPGA, thereby improving the fault tolerance capability of the spacecraft FPGA.

[0025] (7) The timed readback and timed refresh functions of the online maintenance control device of the general software of the present invention have the ability to configure the timing time. Compared with the traditional fixed interval mode, it can adapt to the scenarios of error rates in different orbits and different radiation environments, thereby improving the adaptability of the online maintenance control device;

[0026] (8) The general software online maintenance control device of the present invention has the ability to perform error correction and detection coding and inspection on the software data stored in the non-volatile memory. Compared with the mechanism of storing software data in traditional spacecraft, it can timely discover software data errors in the non-volatile memory, avoid the accumulation of errors caused by the non-volatile memory being affected by the radiation environment, and enhance the on-orbit reliability and robustness of the spacecraft software.

[0027] (9) The general software online maintenance control device of the present invention supports the capabilities of out-of-order injection and breakpoint resumption in the process of receiving software maintenance or update data. Compared with the design that traditional spacecraft must transmit software maintenance data in sequence and must retransmit all software data that has been transmitted after an error occurs, it can significantly enhance the efficiency of software injection. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a structural block diagram of an interface communication unit according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described below in conjunction with the accompanying drawings.

[0030] A general software on-orbit maintenance control device of this specific implementation method includes:

[0031] Interface communication unit, memory interface unit, register unit, FPGA model detection unit, SEFI detection unit, FPGA loading configuration unit, FPGA dynamic refresh unit, FPGA timing readback unit, CPU interface unit, serial data acquisition interface processing unit, telemetry status framing processing unit; Among them:

[0032] like Figure 1 As shown, the interface communication unit: responds to the instruction interface control signal, obtains the control information in the command frame data field, parses and decodes it, and generates a control signal according to the instruction type for reading and writing operations on the register unit or the memory interface unit;

[0033] When a write operation is performed on the register unit, the change in the register content further generates a control signal to realize the operation control of other units inside the software on-orbit maintenance control device; when a write operation is performed on the memory interface unit, the data information in the command frame data field is written into the memory for storage, and when it is a read operation, the data in the read register or memory is output through the interface communication unit.

[0034] In specific implementation, the interface communication unit supports the use of UART, SPI, and SpaceWire interfaces as command interfaces, receives software upgrade or maintenance data, stores it in the address space specified by the non-volatile memory, or receives control command data, and performs read and write operations on the registers inside the software online maintenance control device. When the software online maintenance control device is connected through the UART or SPI interface, multiple software online maintenance control devices can be connected in the form of a bus. When the software online maintenance control device is connected through the SpaceWire interface, multiple software online maintenance control devices can be connected in a point-to-point manner through a SpaceWire switch. When the UART or SPI interface is used as the command interface, the frame header in the data packet is a fixed "0xEB90". When the SpaceWire interface is used as the command interface, the frame header in the data packet is the destination end (such as the SpaceWire routing address of the software online maintenance control device itself in the command data packet) plus the remote end (such as the SpaceWire routing address of the controller in the command data packet).

[0035] When the spacecraft general software online maintenance control device receives the command data packet and completes the frame header detection, it determines whether the ID in the data packet is consistent with the set ID (set by the pin). If not, the command data packet is directly discarded. If they are consistent, a fixed-length data packet is received according to the length field, and after completing the reception of the data packet, the correctness of the check field is judged. The check field is the XOR of the 16-bit data in the entire data packet. When the check field is incorrect, the command data packet is discarded, and a response data packet is returned to reflect that the received command data packet has an error. When the check field is correct, the corresponding operation will be performed according to the command field, address field, and data field content in the command data packet. The content in the command field is shown in Table 1. The address field represents the address to be read and written. The registers in the software online maintenance control device and the external non-volatile memory adopt a unified addressing form. The lower 4k address space is the register address space, and the remaining address space is the non-volatile memory address space. For the data field, when it is a write operation command, it represents the data to be written into the register or memory, when it is a read operation, it represents the length of the data to be read, and when it is a response operation, it represents the returned read data or operation result data.

[0036] Table 1 Command field content description

[0037] Command domain illustrate 0x0 Reserve 0x1 Write register command 0x2 Read register command 0x3 Reserve 0x4 Reserve 0x5 Write non-volatile memory command 0x6 Read Non-Volatile Memory Command 0x7 Answer Flag

[0038] The memory interface unit is used to implement read and write access control of the non-volatile memory, including address management, patrol control, and encoding and decoding verification;

[0039] In this embodiment, during the address management, the address is automatically accumulated according to the starting address sent by the interface communication unit; during the inspection control, according to the inspection cycle set in the register unit, the data in the non-volatile memory is automatically error checked and corrected, wherein the error detection and correction are realized by encoding and decoding the data stored in the non-volatile memory, the data stored in the non-volatile memory is firstly error-corrected and encoded, and error-corrected and decoded after reading the stored data during the inspection, and when an error is detected, it is corrected and written back to the non-volatile memory.

[0040] In the specific implementation, in order to adapt to the error rate differences caused by the radiation environment of spacecraft in different orbits, the inspection cycle and inspection address interval are controlled by the control information in the register unit, and the inspection cycle is set using The form of n is 0~15, f clk The software online maintenance controller controls the working clock frequency of the device. If an error is found in the data of the non-volatile memory during the inspection process, if it is a correctable error, the software online maintenance controller will automatically correct it and write it back to the non-volatile memory. If it is an uncorrectable error, a fault flag will be generated and written into the status register in the register unit.

[0041] The register unit is used to classify and organize control signals and status signals to form control registers and status registers, implement operation control of other units according to the content of the control register, and collect them into the status register in real time.

[0042] In specific implementation, the default value of the control register comes from the pin level setting of the maintenance control device, or from the low-order address space in the non-volatile memory, and is selected through an independent pin level. In order to adapt the software online maintenance control device to work according to the previously predetermined mode or action after power-on or reset, a mutual mapping between the non-volatile memory and the control register in the register unit is established. During initial operation, the software online maintenance control device can obtain the pre-stored control information from the non-volatile memory, so that the software online maintenance control device can work according to the default mode. At the same time, when the control register information in the register unit is rewritten through the instruction interface unit, the rewritten information will also be updated to the non-volatile memory, ensuring that the software online maintenance control device works according to the latest control information after the next reset or power-on. When the software online maintenance control device is connected to multiple CPUs or FPGAs, the register unit is also responsible for controlling the software loading sequence of the multiple CPUs and FPGAs. The specific measure is to set the lowest bit of the control signal to 1, and AND it with the value in the sequence control register corresponding to each CPU and FPGA. The device whose result of the AND is not 0 is the first software loading device. Then the control signal is shifted left bit by bit, and ANDed with the value in the sequence control register corresponding to each CPU and FPGA again, and so on, until the software loading of all CPUs or FPGAs is completed.

[0043] The CPU interface unit is used for read-write interface operation and reset control between the CPU and the CPU; the CPU software is loaded in an active loading manner, so when the software is loaded, the software online maintenance controller only needs to release the reset signal of the CPU, and then XOR the CPU address with the starting address set in the register unit as the access address of the non-volatile memory. After the CPU software is loaded, by writing to the fixed control register address, it means that the CPU software is loaded and the subsequent CPU or FPGA software can be loaded. In order to improve the reliability of the design, when the access non-volatile memory address reaches the maximum address of the address interval corresponding to the CPU device, the CPU still does not show that the loading is successful, then the CPU will be automatically reset again, and the software loading operation will be executed again. If the CPU fails to load successfully for three consecutive times, the CPU will no longer be loaded, and an error flag signal will be set in the status register of the register unit, and the subsequent CPU and FPGA software loading operations will continue to be executed. In addition, in order to support the interface with the CPU watchdog circuit, the CPU interface unit sets an independent asynchronous trigger signal between each CPU connected to it. When the asynchronous trigger signal is valid, the CPU will be reset again and the software loading operation will be executed.

[0044] In specific implementation, when multiple CPUs are connected, the time-sharing sharing of the CPU interface unit is achieved by releasing the reset signals of multiple CPUs in a time-sharing manner. Through the CPU interface unit, the CPU actively reads the data in the non-volatile memory connected to the memory interface unit to realize the startup loading of the software. The memory start address read by different CPUs is controlled by the control register in the register unit.

[0045] FPGA loading configuration unit: used to load configuration after power-on or reset of FPGA;

[0046] In specific implementation, the FPGA loading configuration unit can realize the reconfiguration of the FPGA according to the control signal distributed by the register unit, or realize the reconfiguration of the FPGA according to the FPGA failure detected by the SEFI detection unit. During the loading configuration process, if the address of the non-volatile memory is read to reach the maximum value of the address interval corresponding to the FPGA, and the FPGA still does not display the successful loading configuration, it is considered that the FPGA loading fails, and then the loading configuration operation of the FPGA is performed again until the FPGA loading configuration is successful, or after three consecutive loading configuration failures, the loading configuration of the FPGA is no longer performed, and the error flag signal is set in the status register of the register unit, and the subsequent CPU and FPGA software loading operations are continued. In addition, the FPGA loading configuration unit can respond to the instruction configuration, that is, after the instruction interface unit receives the command data packet for configuring the FPGA, the register unit parses the data packet content and outputs a control signal to the FPGA loading configuration unit to realize the reloading configuration operation of the FPGA. At the same time, the FPGA loading configuration unit supports the dynamic configuration function, that is, under the premise of enabling the control register in the register unit, when the DONE signal of the FPGA is detected to be low, or when the SEFI detection unit detects the SEFI of the FPGA loading configuration interface, the FPGA can be actively reloaded. The configuration operation.

[0047] In this embodiment, the FPGA loading configuration unit can manage the loading configuration of multiple FPGAs, specifically: by controlling the chip select and read-write signals of the FPGA loading configuration interface, the time-sharing multiplexing of the FPGA loading configuration unit is realized, wherein the starting address of different FPGA loading configuration software program data is controlled by the control register in the register unit, and the FPGA loading configuration unit outputs a reset signal to the FPGA during the FPGA loading configuration process, and releases the reset signal after detecting that the FPGA loading configuration is successfully completed.

[0048] The FPGA timing readback unit is used to determine the software configuration data interval that can be read back inside the FPGA according to the control in the register unit. The working state of the FPGA timing readback unit is controlled by the register unit to be enabled or disabled; wherein the setting of the readback cycle adopts The form of n is 0~15, f clk It is the working clock frequency of the software online maintenance control device.

[0049] In the specific implementation, the timing time interval is set by the register unit; when the FPGA timing readback unit is enabled, when the FPGA loading configuration is successful, the readable software configuration data intervals inside multiple FPGAs will be read immediately in sequence, and the check code will be calculated for the read data, and the check code will be stored in the register unit. After that, the check code will be recalculated for the regular reading of the FPGA internal software configuration data, and the calculated check code will be compared with the check code stored in the register unit. In the case of inconsistency, it is considered that an error has occurred in the FPGA internal software configuration data, and an error status signal is output.

[0050] FPGA dynamic refresh unit: used to dynamically write repeatedly writable software configuration data inside the FPGA. The FPGA dynamic refresh unit determines the refreshable software configuration data interval inside the FPGA according to the control of the register unit. The working state of the FPGA dynamic refresh unit is controlled by the register unit to be enabled or disabled, and in the enabled state, the register unit can be set to two working modes: read-back dynamic refresh and timed dynamic refresh. In the read-back dynamic refresh mode, when the FPGA timed read-back unit outputs an FPGA internal software configuration data error status signal, the FPGA dynamic refresh unit starts and executes a dynamic write of the FPGA internal software configuration data. In the timed dynamic refresh mode, the dynamic write of the FPGA internal software configuration data is executed unconditionally and regularly according to the timed time interval set by the register unit; the refresh cycle is set using The form of n is 0~15, f clk It is the working clock frequency of the software online maintenance control device.

[0051] The SEFI detection unit is used to detect single-particle function interruption of the FPGA loading configuration interface. Before the FPGA dynamic refresh unit and the FPGA timing readback unit work, SEFI detection will be performed first. When SEFI is detected, the FPGA will be reloaded with software configuration data according to the register unit control register to allow reconfiguration. Otherwise, the SEFI status signal is output and the operation of the FPGA dynamic refresh unit and the FPGA timing readback unit is stopped. In summary,

[0052] In this embodiment, detection is divided into two types, one is to continuously detect the DONE signal of the FPGA loading configuration interface, and the other is to periodically detect the FAR, STAUS registers and BUSY signals of the FPGA loading configuration interface when performing readback or refresh on the FPGA. When a fault is detected in the FPGA loading configuration interface, if it is a DONE signal fault, the FPGA will be dynamically reconfigured unconditionally. If it is other faults, the dynamic reconfiguration operation of the FPGA will be performed when the register in the register unit is controlled to enable dynamic configuration. Otherwise, the fault information is only written to the status register in the register unit.

[0053] The above are only preferred examples of the present invention and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A spacecraft general software on-orbit maintenance control device, characterized in that: include: Interface communication unit, memory interface unit, register unit, SEFI detection unit, FPGA loading configuration unit, FPGA dynamic refresh unit, FPGA timing readback unit, CPU interface unit; Among them: 2.7.11.12 The interface communication unit is used to respond to the instruction interface control signal, obtain the control information in the command frame data field, parse and decode it, and generate a control signal according to the instruction type for reading and writing the register unit or the memory interface unit; The memory interface unit is used to implement read and write access control of the non-volatile memory, including address management, patrol control, and encoding and decoding verification; The register unit is used to classify and organize the control signal and the status signal to form a control register and a status register, realize the operation control of other units according to the content of the control register, and collect them into the status register in real time; The CPU interface unit is used for read and write interface operations and reset control with the CPU; The FPGA loading configuration unit is used to load the configuration after the FPGA is powered on or reset; The FPGA timing readback unit is used to determine the software configuration data interval that can be read back inside the FPGA according to the control in the register unit, and the working state is controlled by the register unit to be enabled or disabled; The FPGA dynamic refresh unit is used to dynamically write repeatedly writable software configuration data inside the FPGA; The SEFI detection unit is used to detect single-particle function interruption of the FPGA loading configuration interface; When a write operation is performed on the register unit, the change in the register content generates a control signal to realize the operation control of other units inside the software on-orbit maintenance control device; when a write operation is performed on the memory interface unit, the data information in the command frame data field is written into the memory for storage, and when it is a read operation, the data in the register or memory is output through the interface communication unit; During patrol control of the memory interface unit, the data in the non-volatile memory is automatically error checked and corrected according to the patrol cycle set in the register unit, wherein the error check and correction are realized by encoding and decoding the data stored in the non-volatile memory, the data stored in the non-volatile memory is firstly error-corrected and decoded after reading the stored data during patrol, and when an error is detected, it is corrected and then written back to the non-volatile memory; The timing time interval of the FPGA timing readback unit is set by the register unit; When the FPGA timing readback unit is enabled, the FPGA timing readback unit immediately reads the readable software configuration data intervals inside the multiple FPGAs in sequence when the FPGA loading configuration is successful, calculates the check code for the read data, and stores the check code in the register unit. Thereafter, the check code will be recalculated for the regular reading of the software configuration data inside the FPGA, and the calculated check code is compared with the check code stored in the register unit. In the case of inconsistency, it is considered that an error has occurred in the software configuration data inside the FPGA, and an error status signal is output.

2. A spacecraft general software on-orbit maintenance control device as claimed in claim 1, characterized in that: The interface communication unit supports the use of UART, SPI, and SpaceWire interfaces as command interfaces.

3. A spacecraft general software on-orbit maintenance control device as claimed in claim 2, characterized in that: When the interface communication unit supports the use of UART and SPI, multiple software online maintenance control devices are connected in the form of a bus.

4. A spacecraft general software on-orbit maintenance control device as claimed in claim 2, characterized in that: When the interface communication unit supports the use of a SpaceWire interface, multiple software online maintenance control devices are connected in a point-to-point manner through a SpaceWire switch.

5. A spacecraft general software on-orbit maintenance control device as claimed in claim 1, 2, 3 or 4, characterized in that: When the memory interface unit manages the address, the address is automatically accumulated according to the starting address sent by the interface communication unit.

6. A spacecraft general software on-orbit maintenance control device as claimed in claim 1, 2, 3 or 4, characterized in that: The default value of the control register comes from the pin level setting of the maintenance control device, or comes from the low-order address space in the non-volatile memory, and is selected through an independent pin level.

7. A spacecraft general software on-orbit maintenance control device as claimed in claim 1, 2, 3 or 4, characterized in that: When the CPU interface unit is connected to multiple CPUs, the time-sharing sharing of the CPU interface unit is achieved by releasing the reset signals of multiple CPUs in a time-sharing manner. Through the CPU interface unit, the CPU actively reads the data in the non-volatile memory connected to the memory interface unit to realize the startup loading of the software. The memory start address read by different CPUs is controlled by the control register in the register unit.

8. A spacecraft general software on-orbit maintenance control device as claimed in claim 1, 2, 3 or 4, characterized in that: The FPGA loading configuration unit can manage the loading configuration of multiple FPGAs, specifically: time-sharing multiplexing of the FPGA loading configuration unit is achieved by controlling the chip selection and read-write signals of the FPGA loading configuration interface, wherein the starting addresses of different FPGA loading configuration software program data are controlled by the control register in the register unit, and the FPGA loading configuration unit outputs a reset signal to the FPGA during the FPGA loading configuration process, and releases the reset signal after detecting that the FPGA loading configuration is successfully completed.

9. A spacecraft general software on-orbit maintenance control device as claimed in claim 1, 2, 3 or 4, characterized in that: The FPGA dynamic refresh unit determines the software configuration data interval that can be refreshed inside the FPGA according to the control of the register unit. The working state of the FPGA dynamic refresh unit is controlled by the register unit to be enabled or disabled, and in the enabled state, the register unit can be set to two working modes: read-back dynamic refresh and timed dynamic refresh.

10. A spacecraft general software on-orbit maintenance control device as claimed in claim 9, characterized in that: In the readback dynamic refresh mode, when the FPGA timing readback unit outputs an FPGA internal software configuration data error status signal, the FPGA dynamic refresh unit starts and executes a dynamic write of the FPGA internal software configuration data. In the timing dynamic refresh mode, the dynamic write of the FPGA internal software configuration data is unconditionally executed regularly according to the timing time interval set by the register unit.

11. A spacecraft general software on-orbit maintenance control device as claimed in claim 1, 2, 3 or 4, characterized in that: When the SEFI detection unit detects the presence of SEFI, it will reload the software configuration data operation on the FPGA according to the register unit control register to allow reconfiguration, otherwise it will output a SEFI state signal and stop the FPGA dynamic refresh unit and the FPGA timing readback unit from working.

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