Method and system for binary search

Abstract

The application provides a binary search method and system. The method comprises the following steps: providing a storage device with M entries, each of which stores a value; providing index register registers including N registers, wherein the N registers divide the storage device into N-1, N or N+1 search areas; wherein M and N are integers and N

Description

TECHNICAL FIELD

[0001] The present invention relates to a method and system for binary search, and more particularly, to a method and system for scalable hardware binary search design with constant maximum response time. BACKGROUND

[0002] Binary search, also known as half-interval search, logarithmic search or dichotomic search, is a search algorithm that finds the position of a target value within a sorted array. Binary search compares the target value to the middle element of the array. If the middle element is exactly the element being searched for, the search is over. If the target value is greater or less than the middle element, the search continues in the half of the array that is greater or less than the middle element. The search continues in the remaining half, again taking the middle element and comparing it to the target value, and repeating this until the target value is found. If the search range ends, the target is not in the array.

[0003] Reference is made to FIG. 1A and FIG. 1B which illustrate a conventional binary search.

[0004] As can be seen from FIG. 1A , the binary search table is stored in memory, i.e. the binary search is to be performed. The memory includes several addresses, from #0, #1 to #15. Each address stores an s value. For example, #0 stores the value 3, #4 stores the value 20, and #13 stores the value 87. Now a search query is requested. The search query requests a search for the value 75 in the memory.

[0005] Referring to FIG. 1A , the conventional binary search method performs step 1, which includes the following sub-steps: (1) read the value stored in memory address #7; (2) find the value 47 in #7, determine that 47 < 75; (3) then determine that the target value is not in the range of #0-#6, and no search is needed because the values are stored in order, as shown in FIG. 1A .

[0006] The conventional binary search proceeds to step 2, which also includes the following sub-steps: (1) read the value stored in memory address #11; (2) find the value 72 in #11, determine that 72 < 75; (3) then determine that there is no need to search #8-#10 because the values are stored in order.

[0007] Referring to FIG. 1B , the conventional binary search method performs step 3, which also includes the following sub-steps: (1) read the value stored in memory address #13; (2) find the value 87 in #13, determine that 87 > 75; (3) then determine that there is no need to search #14-#15 because the values are stored in order.

[0008] The conventional binary search ends at step 4, which further includes the following sub-steps: (1) reading the value stored in memory location #12; (2) finding that the value 80 is stored in memory location #12; (3) concluding that 75 does not exist in the memory.

[0009] Therefore, the conventional hardware binary search design has certain drawbacks, such as the need for complex logic circuit design and more execution time for sorting and inserting table entries by hardware. In addition, for a table with M entries, the maximum response time of the binary search is log2M. Moreover, a larger table size results in a larger maximum response time.

[0010] Furthermore, for another conventional BCAM, it provides shorter search time, but requires larger circuit area, which results in higher cost. SUMMARY

[0011] The present invention relates to a method of binary search, comprising: providing a storage device having M entries, each entry storing a value; providing an index register comprising N registers, wherein the N registers divide the storage device into N-1, N or N+1 search regions; wherein M and N are integers and N < M; wherein, when searching for a target value in the storage device, it is determined that the target value falls between two adjacent registers, leaving only the addresses of the storage device between the two registers to search.

[0012] Preferably, the registers are extracted from the M entries of the storage device.

[0013] Preferably, the values stored in the storage device are arranged in ascending order.

[0014] Preferably, the values stored in the storage device are arranged in descending order.

[0015] Preferably, the sorting is performed by software.

[0016] The present invention relates to a binary search system, comprising: a storage device comprising M entries, each entry storing a value; and an index register comprising N registers, wherein the N registers divide the storage device into N-1, N or N+1 search regions; wherein M and N are integers and N < M; wherein, when searching for a target value in the storage device, it is determined that the target value falls between two adjacent registers, leaving only the addresses of the storage device between the two registers to search.

[0017] Preferably, the registers are extracted from the M entries of the storage device.

[0018] Preferably, the values stored in the storage device are arranged in order from smallest to largest.

[0019] Preferably, the values stored in the storage device are arranged in order from largest to smallest.

[0020] Preferably, the sorting is performed by software. BRIEF DESCRIPTION OF DRAWINGS

[0021] FIG. 1A-1B A conventional binary search is described;

[0022] FIG. 2A-2C An improved binary search method of the present invention is described; and

[0023] FIG. 3 A general description of the improved binary search method of the present invention is provided. DETAILED DESCRIPTION

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0026] Reference is made to FIG. 2A-2C . FIG. 2A-2C A schematic diagram of the improved binary search method of the present invention is shown. In addition, the present invention can be understood as an improved binary search with an additional binary search table in the memory and the temporary register.

[0027] As FIG. 2A shown, a plurality of values are stored in a memory 201. The memory 201 includes 16 addresses, numbered from #0 to #15. However, the number of addresses in the memory is not limited. One of ordinary skill in the art can apply the disclosure of the present invention to other memories with more addresses.

[0028] Returning to FIG. 2AEach address of the memory 201 stores a value. For example, address #0 stores the value 3, address #6 stores the value 43, and address #14 stores the value 94. The values described and shown are for example purposes only and should not limit the scope of the present invention.

[0029] Each value is stored in ascending order. The values can be sorted by software when they enter the memory 201. However, the method of sorting is well known to those of ordinary skill in the art and will not be described herein.

[0030] The sorting can be modified accordingly. That is, each value can be arranged in descending order and the present invention would still apply.

[0031] As further shown in FIG. 2A An index register 202 is also provided. The index register 202 includes four addresses, namely #0, #5, #10, and #15. For each address, the value 3, the value 31, the value 67, and the value 98 are stored in addresses #0, #5, #10, and #15, respectively. Next, a request comes in. The request asks whether the value 75 exists in the memory 201. The index register 202 can be in any form. That is, the index register 202 can be implemented as software or hardware.

[0032] Referring next to FIG. 2B , the steps after the request comes in are further described. For step 1, based on the information recorded in the index register 202, it can be found that 75 is greater than 67 and less than 98. That is, 67 < 75 < 98. Therefore, addresses #0 through #9 and addresses #10 and #15 can be excluded from searching because the target value 75 falls between 67 (stored in #10) and 98 (stored in #15), and the search is performed from address #11 to address #14. As can be seen from the figure, this index register 202 helps to exclude more than half of the addresses without reading the memory.

[0033] Referring next to FIG. 2C , steps 2 and 3 are shown. In step 2, the value stored in address #12 is read. It is found that the value 80 is stored in address #80. Since the value 80 is greater than the target value 75, and under the premise that each stored value is arranged in order, it is quickly found that there is no need to search from address #13 to #14 because the values stored in the two addresses must be greater than the value 75.

[0034] The present invention further proceeds to step 3, where the value stored in memory address #11 is next read. It is then found that the value stored in address #11 is 72. Such value 72 is the last value that has not been excluded. However, since 72 is not equal to 75, it can be concluded that the value 75 does not exist in the memory 201.

[0035] Returning to step 2 of FIG. 2C , one of ordinary skill in the art can adjust the reading of the value stored in other addresses accordingly (e.g., instead of reading the value in #12, one can read the value stored in #13)

[0036] Reference is next made to FIG. 3 , which provides a general description of the improved binary search method of the present application.

[0037] Suppose memory 301 includes M entries, numbered Entry 1, Entry 2,..., to Entry M. Each entry stores a value, and all values are arranged in ascending order. The sorting can be done with the aid of software, and since the relevant technology for sorting is conventional in the art, it will not be described in detail.

[0038] The sorting can be modified accordingly. That is, each value can be arranged in descending order, and the present application can still be applied.

[0039] Reference is again made to FIG. 3 , which provides index registers 302. Index registers 302 include N regions, numbered Reg 1, Reg 2,..., to Reg N. The N regions divide the binary search table into N+1 binary search areas, labeled Binary Search Area 1, Binary Search Area 2,..., to Binary Search Area N+1.

[0040] Applying the above steps, the improved binary search of the present application can further reduce the computational resources.

[0041] Thus, the table entries are sorted by software. In setting the contents of a hardware binary search table having M entries in a memory, the software also sets N additional index registers (N

[0042] It is noted that the N regions are extracted from the addresses of the memory. For example, in the figure. As shown in FIG. 2A , index register 202 has four regions, which are extracted from addresses #0, #5, #10, and #15, respectively.

[0043] It is further noted that if both the first and last addresses of the memory are extracted, then the number of search areas divided will be N-1. If one of the first and last addresses of the memory is extracted, then the number of search areas divided will be N. If neither of the first and last addresses of the memory is extracted, then the number of search areas divided will be N+1.

[0044] Applying the above steps, the improved binary search of the present application can further reduce the computing resources.

[0045] Therefore, the table entries are sorted by software. When setting the contents of a hardware binary search table having M entries in a memory, the software also sets up N additional index registers (N

[0046] It is noted that the N regions are extracted from the addresses of the memory. For example, in the figure. As shown in FIG. 2A the index register 202 has four regions extracted from the addresses #0, #5, #10 and #15, respectively.

[0047] It is further noted that if the first and last addresses of the memory are both extracted, the number of search regions will be reduced to N-1. If one of the first and last addresses of the memory is extracted, the number of search regions is N. If neither of the first and last addresses of the memory is extracted, the number of search regions is N+1.

[0048] By the information stored in the index registers, the target binary search region in the memory is significantly reduced, and the size of the search region is fixed regardless of the size of the table. The maximum binary search time limit is log2((M-N) / (N+1)).

[0049] In summary, for the present application, it can be further understood that with the assistance of software, the maximum search time limit of the binary search of the present application on the memory can be fixed regardless of the size of the hardware table.

[0050] In summary, one of the objectives of the present application is to control the maximum search time limit of the binary search to meet the performance requirements.

[0051] In addition, the present application can be applied to various environments, such as all hardware binary search table designs, regardless of the size of the table, to limit the maximum search response time with the assistance of software.

[0052] In summary, according to the present application, the sorting of the table entries by software and the insertion of additional index registers. This design reduces the hardware complexity.

[0053] Further, by increasing the appropriate number of index registers, the maximum binary search response time can be controlled to meet the performance requirements. It is not necessary to use a high-cost BCAM as a solution.

[0054] In summary, the present application has certain potential applications and markets. For example, for all hardware binary search table designs, regardless of the size of the table, a limited maximum response time is required.

[0055] In summary, the present application provides a scalable hardware binary search design with a fixed maximum response time, in which the table entry ordering and insertion are handled by software. In addition, a certain amount of index registers are added to record the contents of the memory. Using the index registers, the target binary search region is only a small portion of the table, the search region size remains constant, but the entire search table size can be increased.

[0056] It can be seen that the present application has achieved the desired improved efficiency, and is not easily thought of by those skilled in the art, and has progressiveness and practicality, and has met the requirements for patent application. Therefore, a patent application is submitted in accordance with the law.

[0057] The above is only an example for illustration, and is not a limiting one. Any equivalent modification or change made to the present application without departing from the spirit and scope thereof should be included in the scope of the patent application.

[0058] Symbol explanation

[0059] 201, 301 memory

[0060] 202, 302 index register

Claims

1. A method of binary search, characterized by, Comprising: providing a storage device having M entries, each entry storing a value; and providing an index register comprising N registers, wherein the N registers divide the storage device into N-1, N or N+1 search regions; wherein M and N are integers and N < M; wherein when searching for a target value in the storage device, it is determined that the target value falls between two adjacent registers, searching is only performed between the storage device addresses left marked by the two registers, and the maximum response time of the binary search is fixed.

2. The method of binary search according to claim 1, wherein: wherein the registers are extracted from the M entries of the storage device.

3. The method of binary search according to claim 1, wherein: wherein the values stored in the storage device are arranged in ascending order.

4. The method of binary search according to claim 1, wherein: wherein the values stored in the storage device are arranged in descending order.

5. The method of binary search according to claim 2, wherein: wherein the sorting is performed by software.

6. A binary search system characterized by Comprising: a storage device comprising M entries, each entry storing a value; and an index register, the index register comprising N registers, the N registers dividing the storage device into N-1, N or N+1 search regions; wherein M and N are integers and N < M; wherein when searching for a target value in the storage device, it is determined that the target value falls between two adjacent registers, searching is only performed between the storage device addresses left marked by the two registers, and the maximum response time of the binary search is fixed.

7. The binary search system of claim 6, wherein: wherein the registers are extracted from the M entries of the storage device.

8. The binary search system of claim 6, wherein: wherein the values stored in the storage device are arranged in ascending order.

9. The binary search system of claim 6, wherein: wherein the values stored in the storage device are arranged in descending order.

10. The binary search system of claim 7, wherein: wherein the sorting is performed by software.

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