Enhanced duplicate write data tracking for cache memory

Abstract

The present application relates to enhanced duplicate write data tracking for cache memory. A request is received to perform a write operation to write data at a memory subsystem. In response to the request to perform the write operation, the data is stored at a cache portion of a cache memory of the memory subsystem. A duplicate copy of the data is stored at a write buffer portion of the cache memory. An entry of a write buffer record is recorded, the entry mapping a location of the duplicate copy of the data stored at the write buffer portion to a location of the data stored at the cache portion of the cache memory. A memory operation is performed at the memory subsystem based at least in part on the write buffer record.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to duplicate data tracking of cache memories in memory subsystems. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, a host system may utilize a memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure provides a method comprising: receiving a request to perform a write operation to write data at a memory subsystem; in response to the request to perform the write operation, storing the data at a cache portion of a cache memory of the memory subsystem; storing a duplicate copy of the data at a write buffer portion of the cache memory; recording an entry in a write buffer record that maps a location of the duplicate copy of the data stored at the write buffer portion to a location of the data stored at the cache portion of the cache memory; and performing a memory operation at the memory subsystem based at least in part on the write buffer record.

[0004] In another aspect, the present disclosure also provides a non-transitory computer-readable medium comprising instructions, which, in response to execution of a processing device, causes the processing device to perform operations including the following: receiving a request to perform a write operation to write data at a memory subsystem; in response to the request to perform the write operation, storing the data at a first cache line of a cache portion of a cache memory of the memory subsystem, wherein the first cache line of the cache portion is accessible by a first channel; allocating a second cache line of the cache portion of the cache memory to a write buffer portion of the cache memory, wherein the second cache line of the write buffer portion is accessible by a second channel; storing a duplicate copy of the data at the second cache line of the write buffer portion of the cache memory; and recording an entry in a write buffer record, wherein the entry maps the location of the duplicate copy of the data stored at the write buffer portion to the location of the data stored at the cache portion of the cache memory.

[0005] In yet another aspect, the present disclosure also provides a system comprising: a cache memory; and a processing device operatively coupled to the cache memory to perform operations comprising: receiving a request to perform a write operation to write data at a memory subsystem; storing the data at a cache portion of the cache memory of the memory subsystem in response to the request to perform the write operation; storing a duplicate copy of the data at a write buffer portion of the cache memory; recording an entry in a write buffer record that maps the location of the duplicate copy of the data stored at the write buffer portion to the location of the data stored at the cache portion of the cache memory; and performing a memory operation at the memory subsystem based at least in part on the write buffer record. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 An example computing environment including a host system and a memory subsystem is depicted according to an embodiment of the present disclosure.

[0009] Figure 3 Cache memory, write buffer logging, and tag metadata according to embodiments of the present disclosure are described.

[0010] Figure 4 is a flow chart of an example method of tracking duplicate copies of data stored by a cache memory of a memory subsystem according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart of an example method of tracking duplicate copies of data stored by a cache memory of a memory subsystem according to some embodiments of the present disclosure.

[0012] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to duplicate data tracking of cache memory in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1Examples of storage devices and memory modules are described. In general, a host system can utilize a memory subsystem that includes one or more components (e.g., a memory device that stores data). The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may include a high-density non-volatile memory device where data retention is required when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. The memory subsystem may further include a volatile memory device that can be used as a cache memory. The cache memory is typically accessed more quickly than the non-volatile memory devices in the memory subsystem. Typically, frequently or recently accessed data can be retrieved from a back-end memory (e.g., a non-volatile memory) and stored at the cache memory to take advantage of the low latency of the cache memory. Data stored at the cache memory may undergo many state changes before the data is (re)written to the back-end memory. Therefore, data stored at the cache memory may become data that is referred to as "dirty" data because it does not match corresponding data stored at the back-end memory.

[0015] Some memory subsystems are configured with a high-reliability cache memory having the ability to recover data lost from a failure of a cache memory device. Some conventional memory subsystems implement conventional techniques to achieve a high-reliability cache memory. For example, a conventional memory system may have a cache memory including a large number of discrete cache memory devices. A large-sized data segment may be divided into smaller data segments (e.g., 64 bytes) and written on a large number of discrete cache memory devices. Each of the smaller data segments written to a specific cache memory device may include an error correction code (ECC). If a discrete cache memory device fails, the data segment stored at the failed cache memory device can be reconstructed using the ECC stored at the remaining cache memory devices. However, some memory subsystems with a specific architecture, such as a memory subsystem with a smaller number of cache memory devices, may not be able to support conventional high-reliability cache memory technology. For example, some memory subsystems with a smaller number of cache memory devices may not have enough cache memory devices to effectively allocate smaller data segments on the cache memory devices, so that the data on the failed cache memory device can be reconstructed using the ECC stored at the remaining cache memory devices.

[0016] Aspects of the present disclosure address the above and other deficiencies by dividing a cache memory into a cache portion and a write buffer portion. In response to receiving a request to perform a write operation to write data at a memory subsystem, the write data is stored at the cache portion of the cache memory. A duplicate copy of the data may be stored at the write buffer portion of the cache memory. The entries recorded in the write buffer may be used to map the location of the duplicate copy of the data to the location of the corresponding write data. In some embodiments, the write data is stored at a cache line that can be accessed using a channel, and the duplicate copy of the data is stored at a cache line that can be accessed using a different channel. By storing the write data and the corresponding duplicate copy of the data on a cache line that can be accessed by different channels, the memory subsystem can recover the data stored at the cache memory in the event of a channel failure.

[0017] A channel may refer to a physical coupling for transferring data. In some embodiments, a channel may be used to perform parallel operations on a cache memory. In some embodiments, two or more channels may be coupled to, for example, different dual in-line memory modules (DIMMs), different discrete memory devices, or different dies of a discrete memory device (e.g., packaged in its own device package).

[0018] In some embodiments, the write buffer record may be used to recover otherwise unrecoverable data stored at a cache portion of a cache memory after a failure (e.g., a failure of a memory cell of a cache line, an entire cache line of a discrete cache memory device, a die of a discrete memory device, a discrete memory device, a dual in-line memory module, etc.). In response to receiving a request to perform a read operation to read data, the data being stored at the cache portion of the cache memory, the memory subsystem may attempt to read the data from a cache line of the cache portion of the cache memory. The memory subsystem may detect an unrecoverable error at a cache line of the cache portion. The memory subsystem may access the write buffer record to determine the location of a corresponding duplicate copy of the data stored at the write buffer portion of the cache memory. The duplicate copy of the data may be accessed using a channel different from a channel used to access write data stored at the cache line of the cache portion. In response to the read request, the memory subsystem may send the duplicate copy of the data to the host system. In some embodiments, after an unrecoverable error is detected at the cache portion, the duplicate copy of the data stored at the write buffer may be written to a backend memory so that the backend memory has an up-to-date copy of the data and ensures that the data has been duplicated. In some embodiments, the write buffer record may also be stored at the same channel as the duplicate copy of the data. By storing the write data and the corresponding write buffer record on different channels, the memory subsystem may also recover the write buffer record in the event of a failure of a particular channel.

[0019] The memory subsystem can efficiently implement a high reliability cache memory by storing write data at cache lines (accessed using a channel) in the cache portion of the cache memory, and storing duplicate copies of the data at cache lines (accessed using a different channel) in the buffer portion of the cache memory, and using write buffer records to map the location of the write data to the location of the duplicate copies of the data. This reduces the likelihood that data will be lost in the event of a memory failure, and allows high reliability without requiring a large number of sophisticated memory devices.

[0020] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0024] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0025] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), and the like. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120. As an example, Figure 1 Memory subsystem 110 is illustrated. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages that may refer to logical units of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (or, for simplicity, controller 115) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0036] In some embodiments, the memory subsystem 110 includes a cache duplication manager 113 that performs aspects of the present disclosure. In some embodiments, the cache duplication manager 113 receives a request to perform a write operation to write data at the memory subsystem. In response to the request to perform the write operation, the cache duplication manager 113 stores the data at a cache portion of a cache memory of the memory subsystem. The cache duplication manager 113 stores a duplicate copy of the data at a write buffer portion of the cache memory. The cache duplication manager 113 records an entry in a write buffer record that maps a location of the duplicate copy of the data stored at the write buffer portion to a location of the data stored at the cache portion of the cache memory. The cache duplication manager 113 performs a memory operation at the memory subsystem based at least in part on the write buffer record.

[0037] In some embodiments, the cache duplication manager 113 receives a request to perform a write operation to write data at the memory subsystem. In response to the request to perform the write operation, the cache duplication manager 113 stores the data at a first cache line of a cache portion of the cache memory. The first cache line of the cache portion is accessible by a first channel. The cache duplication manager 113 allocates a second cache line of the cache portion of the cache memory to a write buffer portion of the cache memory. The second cache line of the write buffer portion is accessible by a second channel. The cache duplication manager 113 stores a duplicate copy of the data at the second cache line of the write buffer portion of the cache memory. The cache duplication manager 113 records an entry in a write buffer record that maps a location of the duplicate copy of the data stored at the write buffer portion to a location of the data stored at the cache portion of the cache memory.

[0038] Figure 2An example computing environment including a host system 120 and a memory subsystem 110 is depicted according to an embodiment of the present disclosure. Unless otherwise described, Figure 1 The components and descriptions can be applied to Figure 2 System 200 shows a host system 120 and a memory subsystem 110 .

[0039] In some embodiments, the host system 120 includes one or more processing devices, such as a central processing unit (CPU) 212 or a graphics processing unit (GPU). The memory controller 220 of the host system 120 may send memory operations including requests to perform read operations or write operations to the memory subsystem 110. In some embodiments, the memory operations from the CPU 212 may request data of a specific size (e.g., 64 bytes).

[0040] The memory subsystem controller 115 of the memory subsystem 110 may include a cache controller 232 and a local memory 119. The local memory 119 may include a cache memory 238. The cache memory 238 may be integrated with the cache controller 232 or a discrete device. In some embodiments, the cache memory 238 includes an SRAM. In some embodiments, the cache memory 238 may be a higher level cache memory than the cache memory 234 relative to the memory subsystem controller 115 and, in particular, relative to the cache controller 115. For example, the cache memory 238 may be a level 1 cache memory, while the cache memory 234 may be a level 2 cache memory. For example, a higher level cache memory allows faster data access to frequently accessed or recently accessed data compared to a lower level cache memory.

[0041] The cache memory 238 of the memory subsystem controller 115 may be used to store tag metadata records 244. A record such as a tag metadata record 244 may refer to a specific data structure for storing one or more pieces of data as entries. A record may include one or more entries. In some embodiments, each entry of the tag metadata record 244 may correspond to specific tag metadata (also referred to herein as a "tag"). A tag may be associated with a specific cache line (described below) and may identify information about the associated cache line. For example, each tag may include a specific number of bits (e.g., 79 bits) and stored information about whether clean or dirty data is included on a sector of the cache line (described below). Dirty data may refer to data stored in the cache memory 234 but does not match corresponding data stored at the back-end memory 236. Clean data may refer to data stored in the cache memory 234 and matching corresponding data stored at the back-end memory 236. In other embodiments, one or more of the tag metadata record 244 or the data stored therein (e.g., the data itself or what the data indicates) may be stored at a different component of the memory subsystem 110 or the host system 120. In some embodiments, the data stored at the tag metadata record 244 may indicate other aspects of the memory subsystem 110, and in particular different aspects of data written to a cache line of the cache memory 234 (as further described below).

[0042] In some embodiments, the cache controller 232, and in particular the cache duplication manager 113, may perform the operations described herein. The cache controller 232 may perform eviction operations to evict data from one or more cache lines of the cache portion 240 of the cache memory 234. The cache controller 232 may perform flush operations to flush one or more cache lines of the write buffer portion 242 of the cache memory 234. The cache controller 232 may manage the write data at the cache portion 240 of the cache memory 234 and the duplicate copies of the write data at the write buffer portion 242 of the cache memory 234. The cache controller 232 may manage the tag metadata record 244 and the write buffer record 246. The cache controller 232 may also manage the data of the cache memory 234 in response to detecting an unrecoverable error in the data stored at the cache memory 234. The cache controller 232 may include a cache policy to determine that data from the backend memory 236A-N is to be cached at the cache memory 234 so that the data is quickly accessed by the host system 120. The cache controller 232 may write dirty cache lines of the cache memory 234 back to the backend memories 236A-N to ensure that the data maintained at the backend memories 236A-N is valid data.

[0043] The memory subsystem controller 115, and in particular the cache controller 232, may be coupled to the cache memory 234 using one or more channels illustrated by channel 0 (CH0) and channel 1 (CH1). A channel may refer to a physical coupling for transferring data. In some embodiments, a channel may be used to perform parallel operations on the cache memory 234. In some embodiments, for example, two channels may be coupled to different DIMMs, different discrete memory devices (e.g., memory device 140), or different dies of a discrete memory device (e.g., packaged in its own device package).

[0044] The memory subsystem 110 may include a cache memory 234. In some embodiments, the cache memory 234 may include volatile memory, such as Figure 1 Memory device 140. In some embodiments, cache memory 234 may include DRAM. In some embodiments, cache memory 234 may include one or more discrete memory devices.

[0045] In some embodiments, cache memory 234 may be partitioned into different portions, such as a cache portion 240 and a write buffer portion 242. Cache portion 240 may store data for read operations or from write operations. Data in cache portion 240 may be retained for a relatively long period of time before being (re)written to back-end memory 236A-N (generally referred to as "back-end memory 236"). Write buffer portion 242 may be used to store duplicate copies of data stored at cache portion 240, and in particular duplicate copies of write data (e.g., data written to cache portion 240 as a result of a write operation or data retrieved from back-end memory 236 and rewritten at cache memory 234).

[0046] In some embodiments, the write buffer portion 242 may be split dynamically and from a pool of cache lines of the cache portion 240. For example, when duplicate copies of write data are to be stored at the write buffer portion, the cache controller 232 may determine whether the write buffer portion 242 has sufficient storage space to store the duplicate copies of the data. If the cache controller 232 determines that there is not sufficient storage space at the write buffer portion 242 of the cache memory 234, the cache controller 232 may allocate cells (e.g., cache lines) of the cache memory from the cache portion 240 of the cache memory 234 to the write buffer portion 242. In some embodiments, the cache controller 232 may determine that one or more cells of the cache memory of the write buffer portion 242 are no longer used (e.g., cleared), and in response to the determination, the unused cells of the cache memory may be allocated back to the cache portion 240 of the cache memory 234.

[0047] In some embodiments, data written to cache portion 240 may be written using a first channel (e.g., CH0). A duplicate copy of the data written to write buffer portion 242 may be written on a second channel (CH1) that is different from the first channel. If the channels are associated with different discrete devices or even different dies of the same discrete device, then data that is damaged (e.g., uncorrectable) on the first channel may be recovered using the duplicate copy of the data accessible via the second channel.

[0048] In some embodiments, cache memory 234 may be divided into different units. In some cases, the units may correspond to the operating specifications of cache memory 234 or the operating specifications of the processing device of host system 120. A cache line may refer to a unit of cache memory and contain multiple bytes and / or data words. In an exemplary embodiment, a cache line may include 4,096 bytes of data, or may correspond to a page size of cache memory, a DRAM row, or a byte logical unit in DRAM allocated by a virtual memory manager. In some embodiments, a cache line may be subdivided into smaller memory units, such as sectors. For example, a sector may include 64 bytes. A cache line may include a group of sectors.

[0049] In some embodiments, the write buffer record 246 may be stored at the cache memory 234, and in particular, at the write buffer portion 242 of the cache memory 234. In some embodiments, the write buffer record 246 may include one or more entries. An entry of the write buffer record 246 may map the location of the duplicate copy of the data (e.g., the sector and / or cache line of the write buffer portion 242 storing the duplicate copy of the data) to the location of the write data (e.g., the sector and / or cache line of the cache portion 240 storing the write data). For example, an entry may store an identifier of the sector of the write buffer portion 242 and an identifier of the cache line of the write buffer portion 242 storing the duplicate copy of the data, as well as an identifier of the cache line (e.g., a cache line address) and an identifier of the sector of the cache portion 240 storing the corresponding write data (e.g., a sector address).

[0050] In some embodiments, one or more write buffer records 246 may be stored at the cache memory 234. For example, one or more write buffer records may be associated with each channel of the cache memory 234. In some embodiments, a single write buffer record 246 may track one or more cache lines of data stored at the cache portion 240 of the cache memory 234. In some embodiments, the write buffer record 246 may be stored at sectors of cache lines at the write buffer portion 242 of the cache memory 234. In other embodiments, one or more of the write buffer records 246 or the data stored therein (e.g., the data itself or what the data indicates) may be stored at different components of the memory subsystem 110 or the host system 120. For example, data stored at the write buffer record 246 may also (alternatively or additionally) be stored at the tag metadata record 244, and vice versa.

[0051] In some embodiments, one or more write buffer records may be used for write data written to a particular channel. For example, write buffer record A may be used to map (e.g., map data or location data) write data (written to channel 0). Write buffer record B may be used to map write data written to channel 1. Duplicate copies of data may be stored at different channels corresponding to the write data, so that if one channel fails, duplicate copies of data may be retrieved at another channel. In some embodiments, write buffer records may be stored at write buffer portion 242 of cache memory 234. In some embodiments, write buffer records may be stored at a channel different from the channel used to store the write data mapped by the write buffer record. For example, write data is stored at channel 1. Duplicate copies of data are stored at channel 0. Write buffer records that map write data stored at channel 1 to duplicate copies of data stored at channel 0 may also be stored at channel 0. If channel 1 fails, write buffer records may still be accessible at channel 1, so that all data lost on channel 1 may be mapped to corresponding duplicate copies of data stored at channel 0 using write buffer records also stored at channel 0.

[0052] In some embodiments, the memory subsystem 110 may include back-end memory 236A to 236N. In some embodiments, the back-end memory 236A to 236 may include Figure 1 Memory device 130 is described. In some embodiments, backend memory 236 may include non-volatile memory, such as, but not limited to, 3D crosspoint or NAND memory. In some embodiments, backend memory 236A-N may be a type of memory having a larger capacity and higher access latency than cache memory 234.

[0053] Figure 3 The following describes a cache memory, write buffer record and tag metadata according to an embodiment of the present disclosure. Figure 1 and Figure 2 300. It is understood that a number of elements (e.g., cache lines, sectors, channels, tags, etc.) and locations of elements (e.g., locations of cache lines of write buffer portion 242 or cache portion 240) are provided for purposes of illustration and not limitation. Aspects of the present disclosure may be applied to memory subsystems, and in particular, to cache memories of memory subsystems having any number of elements (e.g., any number of cache lines, channels, sectors, etc.). It is understood that one or more of the operations described as being performed by cache controller 232 may be performed by cache duplication manager 113 of cache controller 232.

[0054] Diagram 300 illustrates a cache memory 234 according to some embodiments. Cache memory 234 is illustrated having cache lines 312 illustrated as cache lines 0 through 7. One or more of cache lines 312 may be divided into sectors represented by sectors 310. Diagram 300 illustrates sectors 0 through 15 for each of cache lines 312. Each of cache lines 312 is associated with a particular one of channels 314. Diagram 300 illustrates channel 0 and channel 1. One or more of cache lines 312 may be associated with tag metadata 316. Diagram 300 illustrates tag metadata associated with each of cache lines 312. Cache memory 234 is illustrated as being divided into a write buffer portion 242 and a cache portion 240. Write buffer portion 242 includes cache lines 6 and 7. Cache portion 240 includes cache lines 0 through 5.

[0055] In some embodiments, the host system may send a request to the memory subsystem 110 to perform a write operation to write data at the memory subsystem 110. In some embodiments, the cache controller 232 may store the data (WD1) at a sector (e.g., sector 12) of a cache line (e.g., cache line 1) of a cache portion 240 of a cache memory 234 of the memory subsystem 110. The write data is represented as WD1 in sector 12 of cache line 1. In some embodiments, cache line 1 is associated with a particular channel illustrated as channel 1.

[0056] In some embodiments, the cache controller 232 may determine that a duplicate copy of the data stored at sector 12 of cache line 1 is to be stored at the write buffer portion 242, and specifically, a cache line stored at the write buffer portion 242 that is associated with a different channel (e.g., channel 0) than the cache line (e.g., channel 1) storing the write data (WD1). If the cache line at the appropriate channel (e.g., channel 0) of the write buffer portion 242 has not been allocated or is full, the cache controller 232 allocates the cache line at the appropriate channel to the write buffer portion 242 of the cache memory 234. For example, the cache controller 232 allocates cache line 6 associated with channel 0 to the write buffer portion 242 of the cache memory 234. In response to determining that the appropriate cache line at the write buffer portion 242 of the cache memory 234 has been allocated, the cache controller 232 stores a duplicate copy of the data (DWD1) at a sector (sector 0) of a cache line (cache line 6) of the write buffer portion 242 of the cache memory 234. As illustrated, the duplicate copy of the data (represented by DWD1) is stored at sector 0 of cache line 6 of the write buffer portion 242 of the cache memory 234.

[0057] In some embodiments, in response to storing a duplicate copy of data (DWD1) at the write buffer portion 242 of the cache memory 234, the cache controller 232 records an entry in the write buffer record 322 that maps the sector (e.g., sector 1) and cache line (cache line 6) storing the duplicate copy of the data (DWD1) to cache line 1 and sector 12 of cache line 1 storing the write data (WD1).

[0058] In some embodiments, a write buffer record may be used to store one or more cache lines worth of data. For example, a write buffer record 320 may be used to store information for all cache lines (e.g., cache lines 0, 2, and 4) of a cache portion 240 of a cache memory 234 associated with channel 0. A write buffer record 322 may be used to store data for all cache lines (e.g., cache lines 1, 3, and 5) of a cache portion 240 of a cache memory 234 associated with channel 1. In another example, multiple write buffer records may be used to store information for all cache lines of a cache portion 240 associated with a particular channel. In some embodiments, a write buffer record may be associated with a particular channel of a memory subsystem.

[0059] In some embodiments, in response to writing data WD1 to sector 12 of cache line 1, cache controller 232 may update tag metadata associated with cache line 1 to indicate that the data stored at sector 12 of cache line 1 contains dirty data. In response to writing a duplicate copy of write data DWD1 to sector 0 of cache line 6, cache controller 232 may repurpose tag metadata associated with a cache line (e.g., cache line 6) of write buffer portion 242. Rather than recording whether the data of the cache line is clean or dirty, the tag metadata associated with the cache line of write buffer portion 242 may be used to indicate whether the duplicate copy of the data stored at the cache line is valid or invalid. For example, cache line 6 associated with tag metadata may indicate that the duplicate copy of the data (DWD1) stored at sector 0 of cache line 6 is valid data because it has just been written and is the most recent version of the data.

[0060] Diagram 300 also illustrates additional write data stored at cache portion 240 of cache memory 234. For example, the host system may request the memory subsystem to perform a write operation to store data (WD2) at memory subsystem 110. Cache controller 232 may store the data at cache line 2 sector 3 on channel 0. Cache controller 232 may determine whether the cache line has been allocated to a write buffer portion 242 of cache memory 234 on a different channel (e.g., channel 1). If cache controller 232 determines that the cache line on channel 1 has not been allocated to write buffer portion 242, cache controller 232 allocates a cache line, such as cache line 7, to write buffer portion 242. Cache controller 232 stores a duplicate copy of the data (DWD2) at sector 0 of cache line 7 on channel 1. The write buffer record 320 associated with channel 1 of cache memory 234 is updated by mapping the data, updating the tag metadata associated with cache line 2 to indicate that the write data stored at sector 3 of cache line 2 is dirty data, and repurposing the tag metadata associated with cache line 7 to indicate that the duplicate copy of the data (stored at sector 0 of cache line 7) is valid data.

[0061] Diagram 300 also illustrates yet another additional write data (WD3) stored at region 3 of cache line 3. The cache controller 232 may perform similar operations as described above with respect to storing a duplicate copy of the data (DWD3) and updating the write buffer record 322, the tag metadata associated with cache line 3, and the tag metadata associated with cache line 6. For the sake of brevity, similar operations will not be repeated herein. It may be noted that since the write data (WD3) is written to channel 1 and the write buffer portion 242 has free space associated with channel 0, the cache controller 232 does not need to allocate a new cache line to the write buffer portion 242 of the cache memory 234, and may use cache line 6 to store the new duplicate copy of the data.

[0062] The write buffer record 322 associated with channel 0 and the write buffer record 320 associated with channel 1 may be used to assist in performing one or more memory operations, including but not limited to a data recovery operation, an eviction operation, or a clear operation. In some embodiments, the write buffer record 322 or the write buffer record 320 may be used alone or in conjunction with a tag metadata record to perform a memory operation.

[0063] In some embodiments, the memory subsystem 110 (e.g., the cache controller 232) receives a request to perform a read operation to read data stored at a cache portion 240 of the cache memory 234 (e.g., at a sector of a cache line of the cache portion 240). For example, the host system 120 requests to perform a read operation to read data WD2 stored at cache line 2. Cache line 2 of the cache portion 240 may be associated with a specific channel (e.g., channel 0). The cache controller 232 may detect that the data from cache line 2 of the cache portion 240 is unrecoverable (e.g., detect an unrecoverable error at cache line 2 of the cache portion 240). For example, a specific sector 3 of cache line 2, the entire cache line 2, or the entire channel 0 may fail, making the requested data unrecoverable. In response to detecting the unrecoverable error, the cache controller 232 identifies a duplicate copy of the data (DWD2) stored at sector 0 of cache line 7 of the write buffer portion 242 of the cache memory 234. The duplicate copy of the data (DWD2) is stored at a different channel from the original write data. The duplicate copy of the data (DWD2) can be identified using a corresponding entry of the write buffer record 320 also stored at channel 1. The cache controller 232 can search the write buffer record 320 for the sector identifier and cache line identifier of the write data (WD2) requested by the host system 120. The write buffer record 320 maps the sector identifier and cache line identifier of the write data (WD2) to the cache line identifier and sector identifier of the corresponding duplicate copy of the data (e.g., cache line 7, sector 0). The cache controller 232 can use the duplicate copy of the data in response to a request to perform a read operation. In some embodiments, the cache controller 232 can write the duplicate copy of the data to the back-end memory 236. In some embodiments, if the entire channel (e.g., channel 0) fails, the cache controller 232 can read all entries of the write buffer record 320 associated with channel 1, locate the duplicate copy of the data (the duplicate of the write data stored at channel 0), and write the duplicate copy of the data to the back-end memory 236.

[0064] In some embodiments, the cache controller 232 may perform an eviction operation to remove data from one or more cache lines of the cache portion 240 of the cache memory 234. In response to performing the eviction operation, the cache controller 232 erases the corresponding entry in the write buffer record that maps to the cache line of the evicted cache portion 240. For example, data from cache line 1 of the cache portion 240 may be evicted. The cache controller 232 may identify the write buffer record 322 and identify the entry pointing to WD1 and erase the entry from the write buffer record 322.

[0065] In some embodiments, the cache controller 232 may perform a flush operation to erase data from one or more cache lines of the write buffer portion 242 of the cache memory 234. For example, to perform the flush operation, the cache controller 232 erases cache line 7 and removes a duplicate copy of the data (DWD2) from sector 0 of cache line 7. The flush operation may be performed when the write buffer portion 242 reaches a data capacity threshold or the data of the cache line of the write buffer portion 242 meets a data age threshold. The cache controller 232 may identify a corresponding write buffer record, such as the write buffer record 320, and identify the location of the corresponding write data (e.g., WD2) stored in the cache portion 240 of the cache memory 234 using the mapping data of the write buffer record 320. The cache controller 232 may store the corresponding write data at the backend memory 236 so that the duplicate copy of the write data is stored at the memory subsystem 110. The cache controller 232 may erase the corresponding entry of the write buffer record 320.

[0066] In some embodiments, metadata tags associated with cache lines of write buffer portion 242 may be used to store additional data. For example, bits of the metadata tag may be used as mapping data to map (at least in part) the location of a duplicate copy of data to the location of write data stored at cache portion 240 of cache memory 234. The metadata tag may be encoded to identify one or more of a sector of a duplicate copy of data, a cache line corresponding to the write data, or a sector corresponding to the write data. Because the metadata tag is associated with a particular cache line of write buffer portion 242, the cache line of the duplicate copy of data need not be encoded into the metadata tag (but may be inferred by association).

[0067] In the illustrative example, the metadata tag may have 79 bits. The metadata tag is associated with cache line 6. The cache lines associated with channel 0 may be identified by numbers 0 to 3, and the cache lines associated with channel 1 may be identified by numbers 0 to 3. For example, cache lines 0, 2, 4, and 6 of channel 0 may be associated with numbers 0 to 3, respectively, and cache lines 1, 3, 5, and 7 of channel 1 may be associated with numbers 0 to 3, respectively. Therefore, any cache line associated with a particular channel may be represented by 2 bits. A 32-bit metadata tag may be used to represent mapping data that identifies cache lines of all 16 sectors of duplicate copies of data stored at cache line 6 of write buffer portion 242, where write data is stored. For example, the tag metadata of cache line 6 of channel 1 corresponds to write data stored on the cache line of channel 0. 2 bits (e.g., the most significant bits) of tag metadata may correspond to a duplicate copy of the data, DWD1, based on the encoded position. The 2 bits may identify cache line 1 (which has been renumbered as cache line 0 to reduce the number of encoded bits). The next two bits of tag metadata may correspond to a duplicate copy of the data, DWD3, based on the encoded position. The bits may identify cache line 3 (which has been renumbered as cache line 1), and so on. In some embodiments, the cache controller 232 may store the tag metadata at a higher level of cache memory (e.g., cache memory 238) than the write buffer record to allow quick access to such information. For example, the cache controller 232 may quickly read the tag metadata record 244 and determine which cache lines of the cache portion 240 of the cache memory 234 have duplicate copies of the data stored at the write buffer portion 242. The cache controller 232 may then use the write buffer record 322 to determine the specific sectors of the cache lines of the cache portion 240 that store the write data. In other embodiments, the metadata tag may be used to represent mapping data that identifies the cache lines and sectors where the write data is stored for all 16 sectors of the duplicate copy of the data stored at cache line 6 of the write buffer portion 242. The cache controller 232 may use the tag metadata to perform the operations described herein.

[0068] In some embodiments, the type of mapping data stored at the metadata tag may depend on the number of channels, the number of sectors, the number of cache lines in the cache memory 234, and the available bits of tag metadata. For example, for a cache memory with 2 channels, 16 cache lines, and 16 sectors per cache line, 3 bits are used to encode each cache line, and 4 bits are used to encode each sector. 112 bits of tag metadata (if available) will be used to map sectors (64 bits) and cache lines of the cache portion 240 (48 bits). For a cache memory with 4 channels, 16 cache lines, and 16 sectors per cache line, 2 bits are used to encode each cache line, and 4 bits are used to encode each sector. 96 bits of tag metadata will be used to map sectors (64 bits) and cache lines (32 bits). For a cache memory with 8 channels, 16 cache lines, and 16 sectors per cache line, 1 bit is used to encode each cache line and 4 bits are used to encode each sector. 80 bits of tag metadata will be used to map sectors (64 bits) and cache lines (16 bits).

[0069] The following can be described Figures 1 to 3 components to help illustrate Figure 4 Method 400 and Figure 5 Methods 400 and 500 may be performed as one or more operations. It may be noted that methods 400 or 500 may be performed in any order and may include the same, different, more or fewer operations.

[0070] Method 400 or 500 may be performed by processing logic that may include hardware (circuitry, dedicated logic, etc.), software (e.g., instructions running on a processing device), or a combination thereof. In some embodiments, some or all of the operations of method 400 or method 500 may be performed by Figure 1 System 100 or Figure 2 In other embodiments, one or more operations of method 400 or 500 may be performed by, for example, Figures 1 to 3 The described cache duplication manager 113 performs.

[0071] Figure 4 is a flow chart of an example method of tracking duplicate copies of data stored by a cache memory of a memory subsystem according to some embodiments of the present disclosure.

[0072] At operation 405, processing logic receives a request to perform a write operation to write data at a memory subsystem.

[0073] At operation 410, processing logic stores data at a cache portion of a cache memory of a memory subsystem. In some embodiments, in response to a request to perform a write operation, processing logic stores data at a first sector of a first cache line of a cache portion of a cache memory of a memory subsystem.

[0074] At operation 415, processing logic stores the duplicate copy of the data at a write buffer portion of the cache memory. In some embodiments, processing logic stores the duplicate copy of the data at a second sector of a second cache line of the write buffer portion of the cache memory.

[0075] In some embodiments, data is stored at a first cache line of a cache portion, the first cache line being accessible using a first channel associated with a first memory device of the cache memory. A duplicate copy of the data is stored at a second cache line of a write buffer portion, the second cache line being accessible using a second channel associated with a second memory device of the cache memory.

[0076] At operation 420, processing logic records an entry in a write buffer record that maps the location of the duplicate copy of the data stored at the write buffer portion to the location of the data stored at the cache memory portion.

[0077] At operation 425, processing logic stores the write buffer record at the write buffer portion of the cache memory. In some embodiments, processing logic stores the write buffer record at a third sector of a third cache line of the write buffer portion of the cache memory. The third cache line may be accessed using a second channel associated with a second memory device.

[0078] In some embodiments, processing logic records, at first tag metadata associated with a first cache line of the cache portion, an indication that data stored at a first sector of a first cache line of the cache portion of the cache memory is dirty data. Processing logic records, at second tag metadata associated with a second cache line of the write buffer portion, an indication that a duplicate copy of data stored at a second sector of a second cache line of the write buffer portion of the cache memory is valid data.

[0079] In some embodiments, the cache memory is a first cache memory. Processing logic records, at a third tag metadata associated with a second cache line of the write buffer portion, an indication that the first cache memory has duplicated and stored data at the second cache line of the write buffer portion. Processing logic stores the second tag metadata at the second cache memory. The level of the second cache memory is a higher level than the level of the first cache memory.

[0080] At operation 430, processing logic performs a memory operation at the memory subsystem based at least in part on the write buffer record.

[0081] In some embodiments, to perform a memory operation, processing logic receives a request to perform a read operation to read data stored at a first sector of a first cache line of a cache portion of a cache memory. Processing logic detects an unrecoverable error at the first cache line. Based on an entry of a write buffer record, processing logic identifies a duplicate copy of the data stored at a second sector of a second cache line of the write buffer portion of the cache memory. In response to the request to perform the read operation, processing logic sends the duplicate copy of the data stored at the second sector of the second cache line.

[0082] In some embodiments, to perform the memory operation, the processing logic performs an eviction operation to remove data from a first cache line of the cache portion of the cache memory. In response to performing the eviction operation, the processing logic erases the entry in the write buffer record.

[0083] In some embodiments, to perform a memory operation, processing logic performs a flush operation to remove a duplicate copy of data from a second cache line of a write buffer portion of a cache memory. Processing logic identifies an entry in a write buffer record that maps a location of the duplicate copy of data stored at the write buffer portion to a location of data stored at the cache portion. Based on the entry of the write buffer record, processing logic locates data stored at a first sector of a first cache line of the cache portion of the cache memory. Processing logic stores the data at the first sector of the first cache line at the non-volatile memory device.

[0084] Figure 5 is a flowchart of an example method for tracking duplicate copies of data stored in a cache memory of a memory subsystem according to some embodiments of the present disclosure. It can be noted that Figure 4 Any of the operations (and embodiments) of method 400 may be applied to method 500 and will not be repeated for the sake of brevity.

[0085] At operation 505, processing logic receives a request to perform a write operation to write data at a memory subsystem.

[0086] At operation 510, processing logic stores data at a first cache line of a cache portion of a cache memory of a memory subsystem. In some embodiments, in response to a request to perform a write operation, processing logic stores data at a first sector of a first cache line of a cache portion of a cache memory of a memory subsystem. The first cache line of the cache portion is accessible by a first channel.

[0087] At operation 515, processing logic allocates a second cache line of the cache portion to a write buffer portion of the cache memory. In some embodiments, the second cache line of the write buffer portion is accessible by a second channel.

[0088] At operation 520, processing logic stores the duplicate copy of the data at a second cache line of the write buffer portion of the cache memory. In some embodiments, the duplicate copy of the data is stored at a second sector of the second cache line.

[0089] At operation 525, processing logic records an entry in the write buffer record that maps the location of the duplicate copy of the data stored at the write buffer portion to the location of the data stored at the cache memory portion.

[0090] At operation 530, processing logic stores the write buffer record at the write buffer portion of the cache memory.

[0091] At operation 535 , processing logic performs a memory operation at the memory subsystem based at least in part on the write buffer record.

[0092] Figure 6 An example machine of a computer system 600 is illustrated in which a set of instructions may be executed for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 600 may be coupled to, include, or utilize a memory subsystem (e.g., Figure 1 or Figure 2 A host system (eg, a memory subsystem 110) of Figure 1 or Figure 2 The host system 120 corresponds to or can be used to perform the operation of the controller (for example, execute the operating system to perform the operation with Figure 1 or Figure 2In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a cloud computing infrastructure or environment.

[0093] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0094] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618 that communicate with each other via a bus 630.

[0095] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 602 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 can further include a network interface device 608 to communicate via a network 620.

[0096] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 or Figure 2 Memory subsystem 110.

[0097] In one embodiment, instructions 626 include instructions for implementing Figure 1 or Figure 2 The machine-readable storage medium 624 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0098] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that leads to a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. At times, it has proven convenient, primarily for common sense reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0099] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0100] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0101] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0102] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0103] The words "example" or "exemplary" are used herein to mean serving as an example, instance or illustration. Any aspect or design described herein as an "example" or "exemplary" should not necessarily be interpreted as being superior or superior to other aspects or designs. In fact, the use of the words "example" or "exemplary" is intended to present concepts in a specific way. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clearly visible from the context, "X includes A or B" is intended to mean any natural inclusive arrangement. That is, if X includes A; X includes B; or X includes A and B, then "X includes A or B" is satisfied under any of the aforementioned examples. In addition, the article "a / an" as used in this application and the appended claims can generally be interpreted as meaning "one or more", unless otherwise specified or clearly visible from the context to represent a singular form. In addition, the use of the terms "one embodiment" or "one embodiment" or "implementation" or "one implementation" etc. throughout the article may not mean the same embodiment or implementation. One or more embodiments or implementations described herein may be combined in a specific embodiment or implementation. As used herein, the terms "first", "second", "third", "fourth", etc. are meant to be used as marks to distinguish different elements, and may not necessarily have an ordinal meaning according to their numerical names.

[0104] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the disclosed embodiments as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: receiving a request to perform a write operation to write data at a memory subsystem; storing the data at a cache portion of a cache memory of the memory subsystem in response to the request to perform the write operation; storing a duplicate copy of the data at a write buffer portion of the cache memory; recording an entry in a write buffer record, the entry mapping a location of the duplicate copy of the data stored at the write buffer portion to a location of the data stored at the cache portion of the cache memory, wherein the cache memory is partitioned into the cache portion and the write buffer portion; as well as A memory operation is performed at the memory subsystem based at least in part on the write buffer record.

2. The method of claim 1 , wherein performing the memory operation at the memory subsystem based at least in part on the write buffer record comprises: receiving a request to perform a read operation to read the data, the data being stored at a first sector of a first cache line of the cache portion of the cache memory; detecting an unrecoverable error at the first cache line; identifying the duplicate copy of the data stored at a second sector of a second cache line of the write buffer portion of the cache memory based on the entry of the write buffer record; as well as In response to the request to perform the read operation, the duplicate copy of the data stored at the second sector of the second cache line is sent.

3. The method of claim 1 , wherein performing the memory operation at the memory subsystem based at least in part on the write buffer record comprises: performing an eviction operation to remove the data from the cache portion of the cache memory; as well as In response to performing the eviction operation, the entry in the write buffer record is erased.

4. The method of claim 1 , wherein performing the memory operation at the memory subsystem based at least in part on the write buffer record comprises: performing a flush operation to remove the duplicate copy of the data from the write buffer portion of the cache memory; identifying the entry in the write buffer record, the entry mapping the location of the duplicate copy of the data stored at the write buffer portion to the location of the data stored at the cache portion; locating the data stored at the cache portion of the cache memory based on the entry of the write buffer record; as well as The data is stored at a non-volatile memory device.

5. The method of claim 1 , wherein the data is stored at a first cache line of the cache portion, the first cache line being accessible using a first channel associated with a first memory device of the cache memory, and wherein the duplicate copy of the data is stored at a second cache line of the write buffer portion, the second cache line being accessible using a second channel associated with a second memory device of the cache memory.

6. The method according to claim 5, further comprising: The write buffer record is stored at a third sector of a third cache line of the write buffer portion of the cache memory, wherein the third cache line is accessible using the second channel associated with the second memory device.

7. The method according to claim 1, further comprising: recording, at first tag metadata associated with a first cache line of the cache portion, an indication that the data stored at the first cache line of the cache portion of the cache memory is dirty data; as well as An indication that the duplicate copy of the data stored at the second cache line of the write buffer portion of the cache memory is valid data is recorded at second tag metadata associated with the second cache line of the write buffer portion.

8. The method of claim 1 , wherein the cache memory is a first cache memory, the method further comprising: recording, at third tag metadata associated with a second cache line of the write buffer portion, an indication that a first cache line of the cache memory stores data that has been duplicated and stored at the second cache line of the write buffer portion; as well as The second tag metadata is stored at a second cache memory, wherein the second cache memory is at a higher level than the first cache memory.

9. A non-transitory computer-readable medium comprising instructions that, in response to execution by a processing device, cause the processing device to perform operations comprising: receiving a request to perform a write operation to write data at a memory subsystem; responsive to the request to perform the write operation, storing the data at a first cache line of a cache portion of a cache memory of the memory subsystem, wherein the first cache line of the cache portion is accessible by a first channel; allocating a second cache line of the cache portion of the cache memory to a write buffer portion of the cache memory, wherein the second cache line of the write buffer portion is accessible by a second channel; storing a duplicate copy of the data at a second cache line of the write buffer portion of the cache memory; as well as An entry is recorded in a write buffer record, the entry mapping the location of the duplicate copy of the data stored at the write buffer portion to the location of the data stored at the cache portion of the cache memory, wherein the cache memory is divided into the cache portion and the write buffer portion.

10. The non-transitory computer-readable medium of claim 9, wherein the first channel is associated with a first memory device of the cache memory, and wherein the second channel is associated with a second memory device of the cache memory.

11. The non-transitory computer-readable medium of claim 10, the operations further comprising: The write buffer record is stored at a third sector of a third cache line of the write buffer portion of the cache memory, wherein the third cache line is accessible using the second channel associated with the second memory device.

12. The non-transitory computer-readable medium of claim 9, the operations further comprising: A memory operation is performed at the memory subsystem based at least in part on the write buffer record.

13. The non-transitory computer-readable medium of claim 12, wherein performing the memory operation at the memory subsystem based at least in part on the write buffer record further comprises: receiving a request to perform a read operation to read the data, the data being stored at the first cache line of the cache portion of the cache memory; detecting an unrecoverable error at the first cache line; identifying the duplicate copy of the data stored at the second cache line of the write buffer portion of the cache memory based on the entry of the write buffer record; as well as In response to the request to perform the read operation, the duplicate copy of the data stored at the second cache line is sent.

14. The non-transitory computer-readable medium of claim 12, wherein performing the memory operation at the memory subsystem based at least in part on the write buffer record further comprises: performing an eviction operation to remove the data from the first cache line of the cache portion of the cache memory; as well as In response to performing the eviction operation, the entry in the write buffer record is erased.

15. The non-transitory computer-readable medium of claim 12, wherein performing the memory operation at the memory subsystem based at least in part on the write buffer record further comprises: performing a flush operation to remove the duplicate copy of the data from the second cache line of the write buffer portion of the cache memory; identifying the entry in the write buffer record, the entry mapping the location of the duplicate copy of the data stored at the write buffer portion to the location of the data stored at the cache portion; locating the data stored at the first cache line of the cache portion of the cache memory based on the entry of the write buffer record; as well as The data of the first cache line is stored at a non-volatile memory device.

16. A system comprising: Cache memory; as well as a processing device operatively coupled to the cache memory to perform operations comprising: receiving a request to perform a write operation to write data at a memory subsystem; storing the data at a cache portion of a cache memory of the memory subsystem in response to the request to perform the write operation; storing a duplicate copy of the data at a write buffer portion of a cache memory; recording an entry in a write buffer record, the entry mapping a location of the duplicate copy of the data stored at the write buffer portion to a location of the data stored at the cache portion of the cache memory, wherein the cache memory is partitioned into the cache portion and the write buffer portion; as well as A memory operation is performed at the memory subsystem based at least in part on the write buffer record.

17. The system of claim 16, wherein the memory operation is performed at the memory subsystem based at least in part on the write buffer record, the operation comprising: receiving a request to perform a read operation to read the data, the data being stored at a first sector of a first cache line of the cache portion of the cache memory; detecting an unrecoverable error at the first cache line; identifying the duplicate copy of the data stored at a second sector of a second cache line of the write buffer portion of the cache memory based on the entry of the write buffer record; as well as In response to the request to perform the read operation, the duplicate copy of the data stored at the second sector of the second cache line is sent.

18. The system of claim 16, wherein the memory operation is performed at the memory subsystem based at least in part on the write buffer record, the operation comprising: performing an eviction operation to remove the data from the cache portion of the cache memory; as well as In response to performing the eviction operation, the entry in the write buffer record is erased.

19. The system of claim 16, wherein the memory operation is performed at the memory subsystem based at least in part on the write buffer record, the operation comprising: performing a flush operation to remove the duplicate copy of the data from the write buffer portion of the cache memory; identifying the entry in the write buffer record, the entry mapping the location of the duplicate copy of the data stored at the write buffer portion to the location of the data stored at the cache portion; locating the data stored at the cache portion of the cache memory based on the entry of the write buffer record; as well as The data is stored at a non-volatile memory device.

20. The system of claim 16, wherein the data is stored at a first cache line of the cache portion, the first cache line being accessible using a first channel associated with a first memory device of the cache memory, and wherein the duplicate copy of the data is stored at a second cache line of the write buffer portion, the second cache line being accessible using a second channel associated with a second memory device of the cache memory.

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