A transconductance variable field effect transistor array and applications

Abstract

The application discloses a transconductance variable field effect transistor array suitable for a dendritic network hardware and application, and belongs to the technical field of semiconductor integrated circuits.The application realizes three-element multiplication of a storage variable and two input variables based on a single transconductance variable field effect transistor, and realizes mapping of a dendritic network core algorithm based on a complementary device array.Compared with a traditional neural network hardware which realizes nonlinear transformation by using a neuron activation circuit, the application realizes nonlinear transformation by using intrinsic nonlinearity of a device, effectively reduces design complexity, optimizes area and power consumption of a system peripheral circuit, and has important significance for design of a high-performance artificial intelligence computing system.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor, artificial intelligence and complementary metal-oxide-semiconductor (CMOS) hybrid integrated circuit, and particularly relates to a transconductance variable field effect transistor array suitable for a dendritic network hardware and application. BACKGROUND

[0002] The concept of artificial intelligence originated in the 1950s. After more than half a century of development, in the 21st century, artificial intelligence has achieved great success in the fields of machine vision, speech recognition, etc. The explosive growth of information brought about by the rapid development of the Internet has promoted the development of artificial intelligence, but also put forward new requirements for the computing power of hardware. In recent years, memory array-based in-memory computing systems have received extensive attention. Memory arrays not only realize the function of storing information, but also process information to a certain extent, overcoming the "memory wall" problem existing in traditional von Neumann computing systems.

[0003] Neuromorphic computing systems based on two-terminal device arrays have been reported. Since the conductance value of the device can be continuously adjusted, two-terminal resistive switching devices based on metal-dielectric layer-metal structure are widely used to simulate the function of synapses. In artificial neural networks (ANN), the synaptic network realizes linear transformation function, while the nonlinear activation function is realized by neurons. Therefore, resistive memory arrays must be matched with corresponding neuron activation circuits to realize the nonlinear transformation function of the network. Since each layer of the network requires an activation circuit, when the network depth increases, the implementation of the neuron activation circuit will consume a large amount of peripheral circuit, not only increasing the system power consumption and area, but also increasing the system design difficulty, hindering the development of large-scale computing systems. In addition, the existing single device cannot realize the multiplication of multiple variables, and CMOS circuits composed of multiple transistors are needed to realize multiple multiplication, which has a large hardware overhead. SUMMARY

[0004] To overcome the problems of excessive peripheral activation function circuit area and large multi-element calculation hardware overhead in existing neuromorphic computing systems, the application provides a transconductance variable field effect transistor array suitable for dendritic network hardware, which realizes three-element multiplication calculation by using the intrinsic equation of the device, finally realizes the nonlinear transformation from input to output, eliminates the additional nonlinear activation circuit between layers, and reduces the complexity of system design. At the same time, the device has the potential for low-temperature integration in the back end and three-dimensional high-density integration.

[0005] To solve the above technical problems, the technical scheme adopted by the application is as follows:

[0006] A transconductance variable field effect transistor array is characterized by being formed by connecting a plurality of transconductance variable field effect transistor devices, the transconductance variable field effect transistor including a metal gate electrode, a metal oxide material dielectric layer, a compound semiconductor active layer, a metal source electrode, a drain electrode, and a passivation layer, a ternary multiplication implementation method of the transconductance variable field effect transistor mainly including an input-output mapping mode, an information storage mode, and a method of implementing calculation by using a device intrinsic equation. The transconductance g m of the field effect transistor is represented by multiplication of two factors, i.e., g m = w x V d , where the coefficient w represents a control ability of the gate on the channel, V d represents a potential difference between the drain and the source, and w and V d are controlled, respectively, so that the transconductance of the device can be controlled. By changing the number of charges stored at the interface between the metal oxide dielectric layer and the channel active region, the control ability w of the gate on the channel can be changed, thereby changing the transconductance g m of the device. The channel current of the device is ultimately determined by the product of the gate voltage (V g ) and the transconductance (g m ), i.e., by the product of w, V d , and V g . Therefore, a single device can complete ternary multiplication calculation (I d = w x V g x V d ) between its stored information (w) and two input information (V d , V g ). Since the output (I d ) is a quadratic function of the input (V d , V g ), a single device realizes a nonlinear transformation from input to output; in an array, the drain electrodes of the devices in the same row are connected by a word line (WL) and the source electrodes are connected by a source line (SL), and the gate electrodes of the devices in the same column are connected by a bit line (BL). A single device completes ternary multiplication calculation between its stored information (w ij ) and two input information (V WL j , V BL i ), and the currents are summed at the source line. When the source line potential is clamped to 0 V, the current on each source line can be represented by the following formula.

[0007]

[0008] It can be seen that the storage matrix W first does an inner product with the input vector V BL , and the result is multiplied with another input vector VWL The element product is taken, and finally the current vector I of the source line is obtained SL The matrix form of the above operation is as follows:

[0009] I SL = WV BL ⊙V WL

[0010] The core iteration formula of the dendritic network is as follows:

[0011] A i+1 = WA i ⊙A0

[0012] Therefore, only I SL , W, V BL and V WL are mapped to A i+1 , W, A i and A0 in the network one by one, the operation of the single-layer dendritic network can be realized. When multiple arrays are cascaded through an interface circuit, the entire dendritic network can be mapped to hardware to accelerate its operation. The positive and negative weights are realized by complementary transconductance variable field effect transistor arrays, the positive weight array and the negative weight array share the input, and respectively obtain the source line currents I SL + and I SL - , and the final source line current I SL is obtained by subtracting the two. Through the mode of complementary array current subtraction, the first-order phase and zero-order term components in the device currents corresponding to the positive and negative weight arrays will be offset, effectively alleviating the influence of device non-ideal effects on the output result.

[0013] Preferably, the metal electrode (including the gate electrode, the source electrode and the drain electrode) is a conductor material, including Ti, TiN, TaN, Ta, Al, AlN, W, Cu, Pt, etc.

[0014] Preferably, the metal oxide dielectric layer is composed of a single layer or a multi-layer composite material film, including a composite material of metal tantalum and metal oxide, including a composite material of tantalum and oxide of tantalum (Ta / TaO x ), a composite material of tantalum and oxide of hafnium (Ta / HfO x ), or a composite material of metal tantalum, other metal and metal oxide, including a composite material of tantalum, titanium and oxide of tantalum (Ta / Ti / TaO x ), a composite material of tantalum, titanium and oxide of hafnium (Ta / Ti / HfO x ), a composite material of tantalum, iridium and oxide of tantalum (Ta / Ir / TaO x ), a composite material of tantalum, tungsten and oxide of tantalum (Ta / W / TaO x ), a composite material of tantalum, iridium and titanium oxide (Ta / Ir / TiOx ), the metal oxide end of the above composite material of metal tantalum and metal oxide can be a variety of metal materials, including Cu, Ti, Ta, W, Pt, TiN, TaN, TiO x , TaO x , WO x , HfO x , AlO x , ZrO x , etc., forming a metal / N layer transition metal oxide / metal structure, N >= 1

[0015] Preferably, the compound semiconductor active layer is composed of a single layer or multi-layer composite material thin film, including ZnO, InGaZnO, ITO, VO x , NbO x , etc.

[0016] Preferably, the metal oxide dielectric layer thin film and the compound semiconductor active layer material thin film have a thickness of 5nm-1000nm.

[0017] The application provides a transconductance variable field effect transistor array for a dendritic network hardware. A three-element multiplication of a storage variable and two input variables is realized based on a single transconductance variable field effect transistor, and a mapping of a dendritic network core algorithm is realized based on a complementary device array. Compared with a traditional neural network hardware using a neuron activation circuit to realize a nonlinear transformation, the application realizes the nonlinear transformation using an intrinsic nonlinearity of the device, effectively reduces design complexity, optimizes the area and power consumption of a system peripheral circuit, and has important significance for the design of a high-performance artificial intelligence computing system. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a structural schematic diagram of the transconductance variable field effect transistor of the application;

[0019] Figure 2 is a schematic diagram of the transconductance variable field effect transistor of the application adjusting the transconductance by adjusting w;

[0020] Figure 3 is a schematic diagram of the transconductance variable field effect transistor of the application changing the drain voltage to adjust the transconductance of the device;

[0021] Figure 4 is a structural schematic diagram of the transconductance variable field effect transistor array of the application;

[0022] Figure 5 is a schematic diagram of the application in which the positive weight array and the negative weight array share an input;

[0023] Figure 6is a schematic diagram of a dendritic network hardware of the transconductance variable field effect transistor array of the present application; the 4x4 circles in the figure represent Figure 4 the transconductance variable field effect transistor array shown in the figure;

[0024] Figure 7 is a schematic diagram of the recognition accuracy of the dendritic network of the embodiment of the present application on the MNIST data set with the number of weight quantization states. DETAILED DESCRIPTION

[0025] In order to make the above features and advantages of the present application more obvious and easy to understand, the present application will be further described below in combination with the drawings and specific embodiments.

[0026] The present application provides a dendritic network hardware based on a transconductance variable field effect transistor array, which utilizes the nonlinearity of the three-terminal device itself to realize nonlinear transformation from input to output, and eliminates the additional nonlinear activation circuit between layers, specifically as follows:

[0027] The present application is based on a transconductance variable field effect transistor with trap charges, which includes a metal gate electrode, a metal oxide material dielectric layer, a compound semiconductor active layer, a metal source electrode, a drain electrode and a passivation layer.

[0028] The preparation method comprises the following steps:

[0029] 1) Forming a metal gate electrode material by physical vapor deposition (PVD), electron beam evaporation and the like;

[0030] 2) Patterning the metal gate electrode by photolithography and etching;

[0031] 3) Forming a metal oxide dielectric material layer as a back gate dielectric by physical vapor deposition (PVD) method;

[0032] 4) Forming a compound semiconductor channel active layer by physical vapor deposition (PVD) method;

[0033] 5) Patterning the device active area by photolithography and etching;

[0034] 6) Annealing to adjust the composition of the channel active area;

[0035] 7) Forming a metal source electrode and a drain electrode material by physical vapor deposition (PVD), electron beam evaporation and the like;

[0036] 8) Patterning the metal source electrode and the drain electrode by photolithography and etching;

[0037] 9) Forming a passivation layer by physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD) and the like;

[0038] 10) Patterning the contact hole by photolithography and etching.

[0039] The electrode is Ti / Pt, the metal oxide gate dielectric layer and the compound semiconductor channel active layer are TaO x For example, the three-terminal nonlinear device with the metal oxide dielectric layer and the channel active layer of InGaZnO, the control ability w of the gate to the channel can be changed by adjusting the number of stored charges at the interface between the metal oxide dielectric layer and the channel active layer, thereby changing the transconductance of the device. The process of adjusting the transconductance by adjusting w is shown in FIG. 2; the process of adjusting the transconductance by changing the drain voltage is shown in FIG. 3; the transconductance variable field effect transistor array is shown in FIG. 4; the array structure is shown in FIG. 5; the positive and negative weights are realized by complementary device arrays, the positive weight array and the negative weight array share the input, and the source line currents I Figure 2 Figure 3 Figure 4 SL + SL - SL Figure 5 Figure 6 Figure 7

[0040] It should be noted that the purpose of the embodiments is to help further understand the present application, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present application and the appended claims. Therefore, the present application should not be limited to the disclosed embodiments, and the scope of the present application is defined by the scope of the claims.​​​​​​​​​

Claims

1. A method of operating an array of transconductance variable field effect transistors, characterized by, The transconductance variable field effect transistor array is formed by connecting a plurality of transconductance variable field effect transistors, the transconductance variable field effect transistor comprising a metal gate electrode, a metal oxide material dielectric layer, a compound semiconductor active layer, a metal source electrode, a metal drain electrode and a passivation layer, the drain electrodes of the transconductance variable field effect transistors in the same row being connected by a word line; The source electrodes of the transconductance variable field effect transistors in the same row are connected by a source line, and the gate electrodes of the transconductance variable field effect transistors in the same column are connected by a bit line; a single transconductance variable field effect transistor completes a ternary product calculation between its stored information and two input information, and the current is added in the source line, wherein: When the source line potential is clamped to 0V, the current on each source line is shown by formula (1); （1） The stored matrix W is first multiplied by the input vector V BL The result is then multiplied by another input vector V WL The result is then multiplied by another input vector V SL The matrix form of the above operation is shown in equation (2): （2） The tree network core iteration is shown by formula (3): （3） I SL , W, V BL and V WL are one-to-one mapped with A i+1 , W, A i and A0 in the network, the operation of single-layer tree-dendritic network can be realized.

2. The method of claim 1, wherein the array of transconductance variable field effect transistors is a differential array of transconductance variable field effect transistors. The two arrays of transconductance variable field effect transistors share the input as positive and negative weight arrays, respectively, to obtain source line current I SL + and I SL - , both of which are subtracted to obtain the final source line current I SL .

3. The method of claim 1, wherein the array of transconductance variable field effect transistors is a differential array of transconductance variable field effect transistors. The metal gate electrode, the metal source electrode and the metal drain electrode adopt Ti, Ta, Al, W, Cu or Pt.

4. The method of claim 1, wherein the transconductance variable field effect transistor array is a differential pair of transconductance variable field effect transistors. The metal oxide material dielectric layer is composed of a single layer or a multi-layer composite material film, and the composite material is metal tantalum and metal oxide, or metal tantalum, other metal and metal oxide.

5. The method of claim 1, wherein the array of transconductance variable field effect transistors is a field programmable gate array. The compound semiconductor active layer is a single layer or a multi-layer of ZnO, InGaZnO, ITO, VO x or NbO x .

6. The method of claim 1, wherein the array of transconductance variable field effect transistors is a field programmable gate array. The thickness of the metal oxide material dielectric layer and the compound semiconductor active layer is 5nm-1000nm respectively.

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