Image sensing device including a protection device

Abstract

The present application relates to an image sensing device including a protection device. An image sensing device includes a plurality of unit photosensitive pixels configured to convert light into an electrical signal, each unit photosensitive pixel including a photoelectric sensor and a plurality of transistors configured to perform an operation associated with the photoelectric sensor; and a plurality of protection devices, each protection device coupled to any one of the plurality of transistors, wherein each of the plurality of protection devices includes a first region doped with a first type of conductive impurity; a second region doped with a second type of conductive impurity and surrounding the first region; and a third region doped with the first type of conductive impurity and surrounding the second region, wherein the first region includes a contact portion and a first well located below the contact portion, and wherein the contact portion has a higher doping density than the first well, and the contact portion is coupled to any one of the plurality of transistors.

Description

Technical Field

[0001] The technology and implementation methods disclosed in this patent document generally relate to an image sensing device. Background Technology

[0002] Image sensors are used in electronic devices to convert the light from an optical image into an electrical signal. Image sensing devices can be broadly classified into CCD (charge-coupled device) based image sensing devices and CMOS (complementary metal-oxide-semiconductor) based image sensing devices.

[0003] Compared to CCD image sensors, CMOS image sensors, manufactured using CMOS technology, are smaller and consume less power. As a result, CMOS image sensors dominate the consumer market for electronic devices with optical and video cameras. Summary of the Invention

[0004] Various embodiments of the disclosed technology relate to a protective device in a unit pixel of an image sensing device, which is configured to effectively remove charge from the gate of a transistor in the unit pixel during a plasma process.

[0005] Various embodiments of the disclosed technology relate to a protection device in a unit pixel of an image sensing device, which is configured to have a high breakdown voltage such that the protection device does not affect the operation of the protected transistor.

[0006] According to an embodiment of the disclosed technology, an image sensing device includes: a plurality of unit photosensitive pixels configured to convert light into electrical signals, each unit photosensitive pixel including a photosensitive sensor and a plurality of transistors configured to perform operations associated with the photosensitive sensor; and a plurality of protection devices, each protection device being coupled to any one of the plurality of transistors, wherein each of the plurality of protection devices includes: a first region doped with a first type of conductive impurity; a second region doped with a second type of conductive impurity and surrounding the first region; and a third region doped with a first type of conductive impurity and surrounding the second region, wherein the first region includes a contact portion and a first well located below the contact portion, and wherein the contact portion has a higher doping density than the first well, and is coupled to any one of the plurality of transistors.

[0007] In some implementations, the first type of conductive impurity is a P-type impurity, and the second type of conductive impurity is an N-type impurity.

[0008] In some implementations, the second region includes a floating portion, a second well located below the floating portion, and a first deep well located below the second well, wherein the floating portion has a higher doping density than the second well.

[0009] In some implementations, the image sensing device may also include a shallow trench isolation (STI) structure disposed between the contact portion and the floating portion and configured to isolate the contact portion and the floating portion from each other.

[0010] In some implementations, the third region includes a ground voltage terminal portion, a third well located below the ground voltage terminal portion, and a second deep well located below the third well, wherein the ground voltage terminal portion has a higher doping density than the third well.

[0011] In some implementations, the third well is arranged to contact the second well, and the contact portion has a higher doping density than the third well.

[0012] In some implementations, the image sensing device may also include a shallow trench isolation (STI) structure through which the floating portion and the contact portion are isolated from each other.

[0013] In some implementations, each of the plurality of transistors is any one of a transfer transistor, a select transistor, and a reset transistor.

[0014] In some implementations, the image sensing device may further include an isolation region disposed between the region where the plurality of protective devices are disposed and the region where the unit pixels are disposed.

[0015] In some implementations, the isolation region includes a first isolation portion doped with a first type of conductive impurity, wherein the first isolation portion is grounded.

[0016] In some implementations, the isolation region may further include a second isolation portion doped with a second type of conductive impurity, wherein the second isolation portion is disposed between the region where the first isolation portion is disposed and the region where the plurality of protective devices are disposed.

[0017] In some implementations, the second isolation section is grounded.

[0018] In some implementations, the second isolation section can be configured to receive a positive (+) voltage.

[0019] According to another embodiment of the disclosed technology, an image sensing device may include: a plurality of photosensitive sensors configured to convert light into electrical signals; a plurality of transistors configured to perform operations associated with the plurality of photosensitive sensors; and a plurality of protection devices configured to carry charge accumulated in the transistors via a gate connected to the transistor, wherein the protection devices include: a contact portion doped with a P-type impurity; a first well doped with a P-type impurity and formed below the contact portion; a second well doped with an N-type impurity and formed to contact the first well by surrounding the first well; and a first deep well doped with an N-type impurity and formed below the second well, wherein the first deep well is formed between a semiconductor substrate and the first well, and each of the first and second wells is doped at a lower density than the contact portion.

[0020] In some implementations, the protection device includes: a third well doped with a P-type impurity and formed to contact the second well by surrounding it; and a second deep well doped with a P-type impurity and formed below the third well.

[0021] According to another embodiment of the disclosed technology, an image sensing device may include: a plurality of photosensitive sensors configured to convert light into electrical charge; a plurality of first devices configured to accumulate the charge generated by the plurality of photosensitive sensors; and a plurality of second devices configured to transport the charge accumulated in the plurality of first devices, wherein each of the plurality of second devices includes: a first region doped with a first type of conductive impurity; a second region doped with a second type of conductive impurity and surrounding the first region; and a third region doped with a first type of conductive impurity and surrounding the second region, wherein the first region includes a contact portion and a first well located below the contact portion, and wherein the contact portion has a higher doping density than the first well, and the contact portion is coupled to any one of the plurality of first devices.

[0022] In some implementations, the first type of conductive impurity is a P-type impurity, and the second type of conductive impurity is an N-type impurity.

[0023] In some implementations, the second region includes a floating portion, a second well located below the floating portion, and a first deep well located below the second well, wherein the floating portion has a higher doping density than the second well.

[0024] In some implementations, the second well is arranged to contact the first well, and the contact portion has a higher doping density than the second well.

[0025] It will be understood that the above general description and the following detailed description of the disclosed technology are both illustrative and explanatory, intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0026] Figure 1 This is a schematic diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0027] Figure 2 This is a schematic diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0028] Figure 3 This is a cross-sectional view illustrating an example of a first protective device based on some implementations of the disclosed technology.

[0029] Figure 4 This is a schematic diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0030] Figure 5 This is a cross-sectional view illustrating an example of a first protective device based on some implementations of the disclosed technology.

[0031] Figure 6 This is a circuit diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0032] Figure 7 This is a cross-sectional view showing an example of an isolated region based on some implementations of the disclosed technology.

[0033] Figure 8 This is a cross-sectional view showing an example of an isolated region based on some implementations of the disclosed technology.

[0034] Figure 9 This is a cross-sectional view showing an example of an isolated region based on some implementations of the disclosed technology. Detailed Implementation

[0035] This patent document provides implementations and examples of image sensing devices including protective devices, and the disclosed features can be implemented to substantially solve one or more problems caused by the limitations and disadvantages of various image sensing devices, each including a protective device. Some implementations of the disclosed technology relate to a protective device configured to effectively remove charge stored in the gate of a protected transistor during a plasma process and configured to have a high breakdown voltage to avoid affecting the operation of the protected transistor. The disclosed technology provides various implementations of image sensing devices equipped with protective devices that can effectively protect the protected transistor during a plasma process without affecting its operation.

[0036] Reference will now be made in detail to embodiments of the disclosed technology, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. While this disclosure is readily adaptable to various modifications and alternatives, specific embodiments are shown in the drawings by way of example. However, this disclosure should not be construed as limiting itself to the embodiments set forth herein; rather, it is intended to cover all modifications, equivalents, and substitutions falling within the spirit and scope of the embodiments.

[0037] Plasma processes are frequently used in the manufacture of semiconductor devices such as CMOS image sensors. For example, plasma processes can be used in a variety of processes such as dielectric deposition, dielectric etching, metal etching, photoresist removal, and metal deposition by sputtering.

[0038] However, the charge generated by plasma can accumulate in confined regions of semiconductor devices, such as the gate of a transistor, and the high electric field caused by the accumulated charge can alter the electrical characteristics of the device.

[0039] Specifically, during the back-end of the production line (BEOL) process, the interconnects between transistors in the CMOS image sensing device are not properly connected, causing charge to accumulate in the transistor gates and flow to the gate oxide film.

[0040] In some implementations, protection devices such as diodes or bipolar junction transistors (BJTs) can be used to protect the transistor gate during plasma processing.

[0041] However, due to the breakdown voltage characteristics, the protection device may affect the sensing operation of the image sensing device. For example, if the breakdown voltage range is small, it may limit the operating voltage of the transistor to be protected by the protection device, and the sensitivity of the protection device to the amount of photocharge generated by the photodiode of the image sensing device can affect the operating characteristics of the image sensing device.

[0042] Figure 1 This is a schematic diagram illustrating an example of an image sensing device 10 based on some implementations of the disclosed technology.

[0043] Reference Figure 1An image sensing device 10 based on some implementations of the disclosed technology may include: a pixel array 100, wherein unit pixels 400-1 to 400-m (where "m" is an integer of 2 or greater), each comprising a plurality of protected transistors PTR1-PTRn, are arranged in a matrix array; a protection device region 200, wherein protection devices (500-1, 500-2, ... 500-n) for protecting the protected transistors PTR1-PTRn from damage caused by plasma are arranged in a matrix array; and an isolation region 300 configured to isolate the pixel array 100 and the protection device region 200 from each other. In this patent document, the term "protected transistor" may be used to refer to any transistor disposed in a unit pixel of the image sensing device 10 protected by the protection device region during a device manufacturing process including a plasma process. In some implementations, the term "protected transistor" may be used to refer to any structure and device disposed in a unit pixel, such as a transistor, diode, junction, charge storage device, etc.

[0044] Unit pixels 400-1 to 400-m can be arranged in a matrix array on pixel array 100. Unit pixels 400-1 to 400-m included in pixel array 100 can be configured as a shared pixel structure. For example, each of unit pixels 400-1 to 400-m can be formed as a shared pixel structure, wherein four photodiodes (not shown) are connected to a single floating diffusion (FD) region (not shown) via first to fourth transfer transistors (not shown). In some implementations, the first photodiode of the four photodiodes can be connected to the single floating diffusion (FD) region via a first transfer transistor, the second photodiode of the four photodiodes can be connected to the single floating diffusion (FD) region via a second transfer transistor, the third photodiode of the four photodiodes can be connected to the single floating diffusion (FD) region via a third transfer transistor, and the fourth photodiode of the four photodiodes can be connected to the single floating diffusion (FD) region via a fourth transfer transistor.

[0045] For ease of description, the protected transistors included in each unit pixel 400 will be referred to as PTR1 to PTRn respectively. Protected transistors PTR1 to PTRn can be connected to protection devices 500-1 to 500-n via metal lines M1 to Mn respectively. In some implementations, protected transistor PTR1 can be connected to protection device 500-1 via metal line M1, protected transistor PTR2 can be connected to protection device 500-2 via metal line M2, and protected transistor PTRn can be connected to protection device 500-n via metal line Mn.

[0046] The protection devices 500-1 to 500-n can be arranged in a matrix array in the protection device region 200. Among the protected transistors PTR1 to PTRn included in each of the unit pixels 400-1 to 400-m, the same type of protected transistor (i.e., any one of PTR1 to PTRn) in the unit pixels 400-1 to 400-m in the same row can be connected to any one of the protection devices 500-1 to 500-n.

[0047] Protected transistors of the same type (i.e., any one of PTR1 to PTRn) may refer to transistors PTR1 to PTRn included in different unit pixels 400-1 to 400-m and performing the same function when receiving the same control signal through a single signal line.

[0048] For example, the first protected transistor (PTR1) disposed in different unit pixels 400-1 to 400-m can be electrically connected to the first protection device 500-1 via the first metal wire M1. Each first protected transistor (PTR1) can be any of the transmission transistors included in the unit pixels 400-1 to 400-m.

[0049] In this case, the first protected transistor (PTR1) disposed in different unit pixels 400-1 to 400-m can refer to a transistor that performs the same function when receiving the same signal through only one signal line. Here, the transistor can transfer the charge stored in each photodiode (not shown) at a corresponding position in each of the unit pixels 400-1 to 400-m to the floating diffusion (FD) region.

[0050] Each of the protected transistors PTR1 to PTRn can be any transistor included in unit pixels 400-1 to 400-m. For example, unit pixels 400-1 to 400-m included in pixel array 100 may include a transfer transistor, a selection transistor, a reset transistor, etc. The aforementioned transistors can be used as protected transistors PTR1 to PTRn of protection devices 500-1 to 500-n.

[0051] In the protection device region 200, the number of protection devices 500-1 to 500-n arranged in a row can be the same as the number of protected transistors PTR1 to PTRn included in each of the unit pixels 400-1 to 400-m. Therefore, the total number of protection devices 500-1 to 500-n provided in the protection device region 200 can be represented by the product of the number of rows on the pixel array 100 and the number of protected transistors PTR1 to PTRn included in each unit pixel.

[0052] In some implementations, protection devices 500-1 to 500-n can be used to prevent voltages higher than the reverse internal voltage of each of the protection devices 500-1 to 500-n from being applied to the gates of the protected transistors PTR1 to PTRn during the plasma process.

[0053] Because high-energy ions are generated in the plasma process, excess charge may accumulate in the gates of the protected transistors PTR1 to PTRn.

[0054] Each of the protected transistors PTR1 to PTRn may include a source / drain region and a channel region formed in a semiconductor substrate or epitaxial layer. An oxide film (e.g., silicon oxide) may be formed on top of the channel region, and a gate formed of metal may be formed on top of the oxide film.

[0055] If charge accumulates in the gates of protected transistors PTR1 to PTRn or in the interconnects or signal lines connected to the gates of protected transistors PTR1 to PTRn, the charge accumulated in the gates can flow through the oxide film to the semiconductor substrate or epitaxial layer.

[0056] In this situation, the oxide film may be damaged by the charge passing through it, thereby undesirably altering the voltage characteristics of the protected transistors PTR1 to PTRn and causing a degradation in their reliability.

[0057] In some implementations, protection devices 500-1 to 500-n, respectively connected to the gates of the protected transistors PTR1 to PTRn, protect the protected transistors PTR1 to PTRn from damage that may occur during plasma processing. In one example, protection devices 500-1 to 500-n can provide protection by allowing excess charge applied to the protected transistors PTR1 to PTRn to flow into the protection devices 500-1 to 500-n rather than into the oxide film, thereby discharging the charge through the protection devices 500-1 to 500-n toward the semiconductor substrate.

[0058] Each of the protection devices 500-1 to 500-n can be arranged such that regions doped with a first conductive impurity and regions doped with a second conductive impurity are arranged alternately. Additionally, a region doped with one type of conductive impurity can be arranged to surround another region doped with another type of conductive impurity, as will be referred to below. Figures 2 to 5 Discussed.

[0059] During operation of the image sensing device 10, a signal voltage having an enable level (e.g., a voltage level for enabling transistors) or a signal voltage having a disable level (e.g., a voltage level for disabling transistors) can be applied to the gates of the protected transistors PTR1 to PTRn, such that a voltage equal to the voltage applied to the gates of the protected transistors PTR1 to PTRn can be applied to the protection devices 500-1 to 500-n, which are respectively connected to the gates of the protected transistors PTR1 to PTRn.

[0060] In this situation, if the breakdown voltage of the protection devices 500-1 to 500-n is not high enough, excessive leakage current may unexpectedly occur between the protection devices 500-1 to 500-n and the gates of the protected transistors PTR1 to PTRn during sensing operation, resulting in noise during sensing operation. When a voltage higher than the breakdown voltage range is applied to the protection devices 500-1 to 500-n, the breakdown of the protection devices 500-1 to 500-n can lead to excessive leakage current.

[0061] In addition, the characteristics of the protection devices 500-1 to 500-n can affect the doping distribution of each photodiode.

[0062] The doping profile of each photodiode can include the structural and physical properties associated with the doping of the photodiode. The doping density and doping layout of the epitaxial layer constituting the photodiode can be examples of the doping profile.

[0063] When the transfer transistor is used to transport charge, the signal voltage applied to the gate of the transfer transistor can be affected by the doping density and doping layout of the photodiode. Additionally, the doping distribution of the photodiode can be limited when each of the protection devices 500-1 to 500-n fails to provide a sufficiently wide constant current voltage range (i.e., a voltage range falling within the breakdown voltage range) to maintain a constant current.

[0064] The characteristics of the protection devices 500-1 to 500-n can vary depending on the doping density of the doped regions included in the protection devices 500-1 to 500-n and the presence or absence of shallow trench isolation (STI) structures in the doped regions, as will be referred to below. Figures 2 to 5 Discussed.

[0065] The isolation region 300 can isolate the pixel array 100 and the protection device region 200 from each other. In order to isolate the pixel array 100 and the protection device region 200 from each other, the isolation region 300 can be disposed between the protection device region 200 and the pixel array 100.

[0066] The protection device region 200 can serve as a region through which charge accumulated in the gates of the protected transistors PTR1 to PTRn during plasma processing moves, thus a high voltage created by the accumulated charge can be applied to the protection device region 200. If the pixel array 100 and the protection device region 200 are not sufficiently separated from each other, this high voltage can lead to leakage current, resulting in damage to the devices and / or metal lines in the image sensing device 10.

[0067] Therefore, the pixel array 100 and the protection device region 200 need to be properly isolated from each other by the isolation region 300. In some implementations, the distance between the pixel array 100 and the protection device region 200 can be set to, for example, 10 μm or more.

[0068] Although the isolation region 300 may be doped with the same conductive impurities as the semiconductor substrate, the scope of the disclosed technology is not limited thereto. The isolation region 300 may, as needed, include isolation portions doped with different types of conductive impurities. The following will refer to... Figures 7 to 9 Let's discuss an example of an isolation zone of 300.

[0069] Figure 2 This is a schematic diagram illustrating an example of an image sensing device 10 based on some implementations of the disclosed technology.

[0070] Figure 2 The diagram shows unit pixels 400-1 to 400-m for use in pixel array 100. For ease of description, details regarding other constituent elements included in unit pixels 400-1 to 400-m will not be discussed, and the discussion here will focus on... Figure 2 The diagram briefly illustrates the first protected transistor PTR1 to the fourth protected transistor PTR4 among the protected transistors PTR1 to PTRn included in each unit pixel. In some implementations, the first protected transistor PTR1 to the fourth protected transistor PTR4 may be implemented as transmission transistors.

[0071] Although a transistor includes a gate, source, drain, oxide film, and channel region, for ease of description, the following discussion will refer to the gates of the first protection device PTR1 to the fourth protection device PTR4 as the first protected transistor PTR1 to the fourth protected transistor PTR4.

[0072] in addition, Figure 2 The diagram shows a first metal line M1 connected to the gate of the first protected transistor PTR1, a second metal line M2 connected to the gate of the second protected transistor PTR2, a third metal line M3 connected to the gate of the third protected transistor PTR3, and a fourth metal line M4 connected to the gate of the fourth protected transistor PTR4.

[0073] The first metal line M1 to the fourth metal line M4 may be located in the signal line layer or interconnect layer of the image sensing device 10.

[0074] The first gate contact C1 connects the first metal line M1 to the gate of the first protected transistor PTR1. The second gate contact C2 connects the second metal line M2 to the gate of the second protected transistor PTR2. The third gate contact C3 connects the third metal line M3 to the gate of the third protected transistor PTR3. The fourth gate contact C4 connects the fourth metal line M4 to the gate of the fourth protected transistor PTR4.

[0075] The first metal line M1 to the fourth metal line M4 can extend into the protection device region 200 in the row direction of unit pixels 400-1 to 400-m after sequentially passing through the pixel array 100 and the isolation region 300. Although for the sake of description, Figure 2 Only the first metal lines M1 to the fourth metal lines M4, which are respectively connected to the first protected transistor PTR1 to the fourth protected transistor PTR4, are shown. However, the scope of the disclosed technology is not limited to this. The image sensing device 10 may also include metal lines (not shown) as needed, depending on the number of protected transistors.

[0076] As described above, the first metal line M1 to the fourth metal line M4 can be connected together to the same type of protected transistor (i.e., any one of PTR1 to PTR4) among the protected transistors PTR1 to PTR4 included in the unit pixels 400-1 to 400-m that are adjacent to each other in the row direction in the protection device region 200.

[0077] For example, the first protected transistor (PTR1) included in the unit pixels 400-1 to 400-m can be commonly connected to the first metal line M1.

[0078] The first metal wire M1 can be connected to the first protection device 500-1 via the first device contact C11. The second metal wire M2 can be connected to the second protection device 500-2 via the second device contact C21. The third metal wire M3 can be connected to the third protection device 500-3 via the third device contact C31. The fourth metal wire M4 can be connected to the fourth protection device 500-4 via the fourth device contact C41.

[0079] The first protected transistor PTR1 to the fourth protected transistor PTR4 are respectively connected to the first protection device 500-1 to the fourth protection device 500-4 via the first metal line M1 to the fourth metal line M4. Although each of the first metal line M1 to the fourth metal line M4 is formed by two metal layers, the scope of the disclosed technology is not limited thereto, and each of the first metal line M1 to the fourth metal line M4 may be formed by at least two metal layers. In addition, the shape of the first metal line M1 to the fourth metal line M4 may vary according to the layout structure of the image sensing device 20.

[0080] In some implementations, the first protection device 500-1 to the fourth protection device 500-4 disposed in the protection device area 200 may be substantially identical in structure to each other.

[0081] When viewed from a direction perpendicular to one surface of the substrate, each of the first protection device 500-1 to the fourth protection device 500-4 may include a first region 510 doped with a first type of conductive impurity (i.e., the first conductive impurity), a second region 520 surrounding the first region 510 and doped with a second type of conductive impurity (i.e., the second conductive impurity), and a third region 530 surrounding the second region 520 and doped with the first conductive impurity.

[0082] The first regions 510 of the first protection device 500-1 to the fourth protection device 500-4 can be connected to the first metal wire M1 to the fourth metal wire M4 respectively through device contacts C11 to C41. In some implementations, the first region 510 of the first protection device 500-1 can be connected to the first metal wire M1 through device contact C11, the first region 510 of the second protection device 500-2 can be connected to the second metal wire M2 through device contact C21, the first region 510 of the third protection device 500-3 can be connected to the third metal wire M3 through device contact C31, and the first region 510 of the fourth protection device 500-4 can be connected to the fourth metal wire M4 through device contact C41.

[0083] The second area 520 of the first protection device 500-1 to the fourth protection device 500-4 can be floated.

[0084] The third area 530 of the first protection device 500-1 to the fourth protection device 500-4 can be grounded through the first to fourth grounding contacts C12, C22, C32 and C42 respectively.

[0085] When viewed from a direction perpendicular to one surface of the substrate, the doping distributions of the first protection device 500-1 to the fourth protection device 500-4 can be substantially the same as each other. Therefore, for the sake of convenience, the following discussion will focus on the first protection device 500-1.

[0086] The first region 510 may be doped with P-type impurities, the second region 520 may be doped with N-type impurities, and the third region 530 may be doped with P-type impurities. Therefore, the first protection device 500-1 may have a PNP type BJT (bipolar junction transistor) structure.

[0087] The first region 510 of the first protection device 500-1 can be used as the emitter of the BJT, the second region 520 of the first protection device 500-1 can be used as the base of the BJT, and the third region 530 of the first protection device 500-1 can be used as the collector of the BJT. (Refer to the following...) Figure 3 Discuss the detailed shape and function of the protective device.

[0088] Therefore, the first protection device 500-1 to the fourth protection device 500-4, each having a BJT structure and respectively connected to the first protected transistor PTR1 to the fourth protected transistor PTR4, can prevent potential damage to the protected transistors during plasma processing by forming a bypass path for charge movement.

[0089] The isolation region 300, located between the pixel array 100 and the protection device region 200, may be doped with a first conductive impurity, and the first conductive impurity may be a P-type impurity. The cross-sectional shape of the isolation region 300 will be described later. Figures 7 to 9 describe.

[0090] Figure 3 This is a cross-sectional view 30 showing an example of a first protective device 500-1 based on some implementations of the disclosed technology.

[0091] Figure 3 It shows along Figure 2 Figure 30 shows a cross-sectional view of an example of the first protective device 500-1 taken by the first cutting line A-A'. Although the following description focuses on the first protective device 500-1 for ease of description, the scope of the disclosed technology is not limited thereto, and in some implementations, other protective devices 500-2 to 500-n may be structurally identical or similar.

[0092] Reference Figure 3 The first protection device 500-1 may include a first region 510 doped with P-type impurities, a second region 520 doped with N-type impurities, and a third region 530 doped with P-type impurities. The second region 520 may be formed around the first region 510. The third region 530 may be formed around the second region 520.

[0093] The first region 510 may include a contact portion 511 and a first well 512.

[0094] The contact portion 511 can be connected to the gate of the first protected transistor PTR1 via the first metal line M1. The contact portion 511 may be doped with high-density impurities to reduce the resistance between the contact portion 511 and the first metal line M1. In some implementations, the contact portion 511 may be doped with P-type impurities that form a shallow junction structure.

[0095] The first well 512 may have a lower doping density than the contact portion 511.

[0096] The contact portion 511 and the first well 512 may be doped with the same type of impurities, so that the entire first region 510 can be used as the emitter of the BJT.

[0097] The second region 520 may include a floating portion 521, a second well 522, and a first deep well 523. The floating portion 521 may have a higher doping density than the second well 522. In some implementations, the floating portion 521 may be doped with N-type impurities that constitute a shallow junction structure. The floating diffusion region 521 may be floating in a manner where the potential is not fixed.

[0098] The second well 522 may have a lower doping density than the contact portion 511. The first well 512 and the second well 522 may have similar doping densities.

[0099] A first well 512 having a doping density relatively lower than that of the contact portion 511 can be arranged to contact a second well 522 having a doping density relatively lower than that of the floating portion 521, thereby increasing the breakdown voltage range of the first protection device 500-1.

[0100] In some implementations, the first well 512 can be a P-type region with a low doping density, and the second well 522 can be an N-type region with a low doping density. The second region 520, formed around the first region 510, can be used as the base of the BJT.

[0101] The first deep well 523, located below the second well 522, may be doped with N-type impurities and may have a lower doping density than the second well 522.

[0102] The third region 530 may include a ground voltage terminal portion 531, a third well 532, and a second deep well 533. The ground voltage terminal portion 531 may have a higher doping density than the third well 532. The third region 530 may be used as the collector of a BJT. In some implementations, the ground voltage terminal portion 531 may be doped with P-type impurities forming a shallow junction structure. The second deep well 533, located below the third well 532, may be doped with P-type impurities and may have a lower doping density than the third well 532.

[0103] The grounding voltage terminal portion 531 can be grounded by connecting to the grounding contact C21, so that the holes generated by the first protection device 500-1 can be captured.

[0104] The semiconductor substrate 540 may be disposed below the first deep well 523 and the second deep well 533. The semiconductor substrate 540 may be a silicon substrate doped with a first conductive impurity. In some implementations, the semiconductor substrate 540 may be a silicon substrate doped with a p-type impurity.

[0105] Figure 4 This is a schematic diagram illustrating an example of an image sensing device 40 based on some implementations of the disclosed technology.

[0106] Reference Figure 4 Regarding the image sensing device 40 and Figure 2 Details of the remaining components other than the different first protection device 500-1 to the fourth protection device 500-4 can be structurally similar to Figure 2 Those of the image sensing devices 20 shown are the same or similar.

[0107] When viewed from a direction perpendicular to one surface of the substrate, Figure 4 Each of the first protection device 500-1 to the fourth protection device 500-4 shown may include a first region 510 doped with a first conductive impurity, a second region 520 surrounding the first region 510 and doped with a second conductive impurity, and a third region 530 surrounding the second region 520 and doped with the first conductive impurity.

[0108] The first region 510 may include a contact portion 511 doped with a high density of first conductive impurities and a first well 512 doped with a low density of first conductive impurities.

[0109] The second region 520 may include a floating portion 521 doped with a high density of second conductive impurities and a second well 522 doped with a low density of second conductive impurities.

[0110] The third region 530 may include a ground voltage terminal portion 531 doped with a high density of first conductive impurities and a third well 532 doped with a low density of first conductive impurities.

[0111] and Figure 2 Different, such as Figure 4 As shown, a first shallow trench isolation (STI) structure may be formed between a first region 510 and a second region 520, and a second shallow trench isolation (STI) structure may be formed between the second region 520 and a third region 530. Each of the first STI structure and the second STI structure may be filled with an insulating material (e.g., silicon oxide, silicon nitride, etc.).

[0112] In some implementations, the characteristics of the protection device can be affected by the first STI structure and the second STI structure, as will be referred to below. Figure 5 Discussed.

[0113] Figure 5 This is a cross-sectional view illustrating an example of a first protective device 500-1 based on some implementations of the disclosed technology.

[0114] Figure 5 It shows along Figure 4 Figure 50 shows a cross-sectional view of an example of the first protective device cut by the second cutting line B-B'.

[0115] Cross-sectional view of the first protective device, Figure 50 Figure 5 The remaining components, other than the first STI (STI1) structure and the second STI (STI2) structure shown, can be structurally integrated with... Figure 3 The cross-sectional view of the first protective device shown in Figure 30 is the same as or similar to that shown in the figure. Therefore, for the sake of brevity, its redundant description will be omitted in this document. The following will refer to it as... Figure 3 The characteristics of the first protective device shown are described with a focus on different features. Figure 5 The first protective device shown.

[0116] The first STI (STI1) structure isolates the contact portion 511 and the floating portion 521 from each other. The second STI (STI2) structure isolates the floating portion 521 and the ground voltage terminal portion 531 from each other.

[0117] The depth of the first STI (STI1) structure and the depth of the second STI (STI2) structure can be changed according to the characteristics required by the protection device. Each of the first STI (STI1) structure and the second STI (STI2) structure can be formed to have at least a specific depth such that the contact portion 511 and the floating portion 521 can be isolated from each other and the floating portion 521 and the ground voltage terminal portion 531 can be isolated from each other.

[0118] Since the contact portion 511, floating portion 521 and ground voltage terminal portion 531, which are used as high-density doped regions respectively, are isolated from each other by the first STI (STI1) structure and the second STI (STI2) structure, the breakdown voltage reduction caused by the junction between the high-density doped regions can be prevented.

[0119] Furthermore, the first STI (STI1) structure prevents punch-through between the contact portion 511 and the second well 522 in the image sensing device. When a voltage is applied to the contact portion 511, the width of the space charge region located below the contact portion 511 can increase, allowing the space charge region to extend and penetrate the second well 522. To prevent punch-through that could lead to current leakage through the BJTs (or diodes) of each protection device, the contact portion 511 and the second well 522 can be spaced apart from each other by a predetermined distance using the first STI (STI1) structure.

[0120] Figure 6 This is a circuit diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0121] In some implementations, an example of a unit pixel 400-k (where "k" is a positive integer) included in a pixel array can be implemented as described below. In one example, the first protected transistor PTR1 to the sixth protected transistor PTR6, which act as protected transistors included in each unit pixel, the control signals TS1, TS2, TS3, TS4, RS, and SEL respectively applied to the first protected transistor PTR1 to the sixth protected transistor PTR6, and the first photodiode PD1 to the fourth photodiode PD4 included in the unit pixel 400-k can be implemented as follows: Figure 6 The implementation is shown. In some implementations, the example of unit pixel 400-k may also include one or more transistors (e.g., transistors for dual conversion gain, etc.).

[0122] although Figure 6 A unit pixel 400-k is shown, comprising first photodiodes PD1 to fourth photodiodes PD4. The first photodiodes PD1 to fourth photodiodes PD4 are configured to share a floating diffusion (FD) region via first protected transistors PTR1 to fourth protected transistors PTR4. However, the scope of the disclosed technology is not limited to this. It should be noted that a shared pixel structure including two photodiodes configured to share a floating diffusion (FD) region or a unit pixel including photodiodes that do not share a floating diffusion (FD) region can also be implemented. In some implementations, when photogenerated electrons are transferred to the floating diffusion (FD) region via a transfer transistor as a result of a voltage difference existing between the photodiodes and the floating diffusion (FD) region, the floating diffusion (FD) region can be used to retain the photogenerated electrons.

[0123] The first protected transistor PTR1 to the fourth protected transistor PTR4, which are respectively connected to the first photodiode PD1 to the fourth photodiode PD4, can be transmission transistors. The first protected transistor PTR1 to the fourth protected transistor PTR4 can respectively receive the first transmission transistor control signal TS1 to the fourth transmission transistor control signal TS4.

[0124] The first protected transistor PTR1 to the fourth protected transistor PTR4 can transfer the photocharge generated by the first photodiode PD1 to the fourth photodiode PD4 to the floating diffusion (FD) region according to the logic level (e.g., logic high level and / or logic low level) of the first transmission transistor control signal TS1 to the fourth transmission transistor control signal TS4.

[0125] The fifth protected transistor, PTR5, can be a reset transistor. PTR5 can reset each connected device (or component) to the power supply voltage (VDD) level according to the logic level of the received reset transistor control signal (RS). By turning on the reset transistor, the amount of photocharge generated by the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 can be accurately measured.

[0126] The sixth protected transistor, PTR6, can be a select transistor. The sixth protected transistor, PTR6, can generate the output voltage (V) of the drive transistor (DX) based on the logic level of the received select transistor control signal (SEL). pixel (out). In addition, the protection device region 200 may include a first protection device 500-1 to a sixth protection device 500-6 corresponding to the first protected transistor PTR1 to the sixth protected transistor PTR6, respectively.

[0127] The gates of the first protected transistor PTR1 to the sixth protected transistor PTR6 can be connected to the first metal line M1 to the sixth metal line M6, which are independent of the signal lines for receiving control signals TS1, TS2, TS3, TS4, RS, and SEL. The first metal line M1 to the sixth metal line M6 can be connected to the first protection device 500-1 to the sixth protection device 500-6, respectively.

[0128] For example, a first transfer control signal (TS1) can be applied to the gate of a first protected transistor PTR1, and the gate of the first protected transistor PTR1 can be connected to a first protection device 500-1 via a first metal line M1.

[0129] Each of the first protection device 500-1 to the sixth protection device 500-6 can be implemented as a BJT element having an emitter, a base, and a collector. The emitters of the first protection device 500-1 to the sixth protection device 500-6 can be connected to the gates of the first protected transistor PTR1 to the sixth protected transistor PTR6, respectively. In addition, the bases of the first protection device 500-1 to the sixth protection device 500-6 can be floating, and the collectors of the first protection device 500-1 to the sixth protection device 500-6 can be grounded.

[0130] During the sensing operation of the image sensing device, control signals TS1, TS2, TS3, TS4, RS and SEL can be applied to the gates of the first protected transistor PTR1 to the sixth protected transistor PTR6, respectively.

[0131] Each of the control signals TS1, TS2, TS3, TS4, RS, and SEL can have two logic levels (i.e., a logic high level and a logic low level). If a control signal with a logic high level is applied to the gate of the respective transistor, the corresponding transistor can be enabled (or turned on). If a control signal with a logic low level is applied to the gate of the respective transistor, the corresponding transistor can be disabled (or turned off).

[0132] Each of the control signals TS1, TS2, TS3, TS4, RS, and SEL can be a voltage signal. Therefore, the control signals TS1, TS2, TS3, TS4, RS, and SEL applied to the gates of the first protected transistor PTR1 to the sixth protected transistor PTR6 can affect the first protection device 500-1 to the sixth protection device 500-6 respectively connected to the first protected transistor PTR1 to the sixth protected transistor PTR6.

[0133] If the breakdown voltage of the first protection device 500-1 to the sixth protection device 500-6 is not high enough, leakage current can flow from the first protection device 500-1 to the sixth protection device 500-6 to the protected transistors PTR1 to PTR6 by applying voltage to the gate of the protected transistors PTR1 to PTR6, thereby causing noise in the image sensing device 10 due to such leakage current.

[0134] Based on some implementations of the disclosed technology, the first protection device 500-1 to the sixth protection device 500-6 can maintain the breakdown voltage range within the desired range, thereby increasing the voltage range applied to the gates of the protected transistors PTR1 to PTR6, thus providing the necessary characteristics to the protection devices in the image sensing device 10.

[0135] Figure 7This is a cross-sectional view 70 showing an example of an isolation region 300 based on some implementations of the disclosed technology.

[0136] For ease of description, Figure 7 The pixel array 100 and the protection device area 200 are briefly shown in the figure.

[0137] Reference Figure 7 The isolation region 300 may be disposed between the pixel array 100 and the protection device region 200. As described above, since the isolation region 300 is disposed between the pixel array 100 and the protection device region 200, the charge flowing through the protection device region 200 into the semiconductor substrate 540 during the plasma process does not affect the unit pixels disposed in the pixel array 100.

[0138] The isolation region 300 may include a first isolation portion 600-1 doped with a first conductive impurity. Here, the first conductive impurity may be a p-type impurity. The first isolation portion 600-1 may include multiple regions with different doping densities.

[0139] The first isolation portion 600-1 may include a first surface isolation portion 610, a first well isolation portion 611, and a first deep well isolation portion 612.

[0140] The first surface isolation portion 610 may be located at the uppermost end of the first isolation portion 600-1 and may be grounded.

[0141] The first well isolation portion 611 may be disposed below the first surface isolation portion 610. The first deep well isolation portion 612 may be disposed below the first well isolation portion 611. The semiconductor substrate 540 may be disposed below the first deep well isolation portion 612.

[0142] The first conductive impurity may be the same as the conductive impurity of the semiconductor substrate 540.

[0143] The first surface isolation portion 610 can be doped at a higher density than the first well isolation portion 611. Because the first surface isolation portion 610 is doped at a higher density, the resistance between the wire to which the ground voltage is applied and the first surface isolation portion 610 can be reduced.

[0144] Because the first isolation portion 600-1 is doped with a first conductive impurity, holes generated by the protection device region 200 can be easily captured.

[0145] Figure 8 This is a cross-sectional view 80 showing an example of an isolation region 300 based on some implementations of the disclosed technology.

[0146] Reference Figure 8The isolation region 300 may include a first isolation portion 600-1 and a second isolation portion 600-2. In some implementations, Figure 8 The first isolation section 600-1 shown can be connected with Figure 7 The first isolation section 600-1 is the same as or similar to the second isolation section 600-2, which will be discussed below as an example.

[0147] In some implementations, the first isolation portion 600-1 may be formed between the pixel array 100 and the second isolation portion 600-2 due to the formation of the second isolation portion 600-2.

[0148] The isolation region 300 may include a first isolation portion 600-1 doped with a first conductive impurity and a second isolation portion 600-2 doped with a second conductive impurity. The second conductive impurity may be an N-type impurity. The second isolation portion 600-2 may include multiple regions with different doping densities.

[0149] The second isolation portion 600-2 may include a second surface isolation portion 620, a second well isolation portion 621, and a second deep well isolation portion 622. The second surface isolation portion 620 may be located at the uppermost end of the second isolation portion 600-2 and may be grounded.

[0150] The second well isolation portion 621 may be disposed below the second surface isolation portion 620. The second deep well isolation portion 622 may be disposed below the second well isolation portion 621. The semiconductor substrate 540 may be disposed below the second deep well isolation portion 622.

[0151] The second conductive impurity can be an impurity of the opposite type to that of the semiconductor substrate 540.

[0152] The second surface isolation portion 620 may be doped at a higher density than the second well isolation portion 621. Because the second surface isolation portion 620 is doped at a higher density, the resistance between the wire and the second surface isolation portion 620 can be reduced during the connection between the second surface isolation portion 620 and the ground voltage terminal.

[0153] Because the second isolation portion 600-2 is doped with a second conductive impurity, electrons generated by the various protection devices can be easily captured. Since the first isolation portion 600-1 is positioned closer to the pixel array 100 than the second isolation portion 600-2, holes generated from the protection device region 200 can be captured through the first isolation portion 600-1 after electrons are captured by the second isolation portion 600-2.

[0154] The isolation region 300 may include a first isolation portion 600-1 and a second isolation portion 600-2, such that the isolation region 300 can trap electrons and holes. As a result, devices or elements included in the pixel array 100 can be electrically protected.

[0155] Figure 9 This is a cross-sectional view illustrating an example of an isolation region 300 based on some implementations of the disclosed technology.

[0156] Reference Figure 9 The isolation area 300 may include a first isolation section 600-1 and a second isolation section 600-2. Figure 9 The first isolation portion 600-1 and the second isolation portion 600-2 shown are structurally similar to... Figure 8 The first isolation section 600-1 and the second isolation section 600-2 are the same or similar. The voltage applied to the second isolation section 600-2 will be discussed below.

[0157] Since a positive (+) voltage is applied to the second surface isolation portion 620 of the second isolation portion 600-2, the electron trapping capability of the second isolation portion 600-2 is improved compared to the case where a ground voltage is applied to the second surface isolation portion 620 of the second isolation portion 600-2.

[0158] It is evident from the above description that an image sensing device equipped with a protective device, based on some implementations of the disclosed technology, can effectively protect the protected transistor during plasma processing without affecting its operation.

[0159] Although several exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments may be conceived based on the description and / or illustrations in this patent document.

[0160] Cross-references to related applications

[0161] This patent document claims priority and benefit to Korean Patent Application No. 10-2020-0089719, filed on July 20, 2020, the disclosure of which is incorporated herein by reference in its entirety as part of the disclosure of this patent document.

Claims

1. An image sensing device, the image sensing device comprising: Multiple unit photosensitive pixels, the multiple unit photosensitive pixels being configured to convert light into electrical signals, each unit photosensitive pixel including a photoelectric sensor and multiple transistors configured to perform operations associated with the photoelectric sensor; Multiple protection devices, each of which is connected to any one of the multiple transistors; as well as An isolation region is provided between the area where the plurality of protective devices are provided and the area where the unit photosensitive pixels are provided. Each of the plurality of protection devices includes: A first region, wherein the first region is doped with a first type of conductive impurity; A second region, doped with a second type of conductive impurity and surrounding the first region; and A third region, which is doped with the first type of conductive impurity and surrounds the second region. The first region includes a contact portion and a first well located below the contact portion. The contact portion has a higher doping density than the first well, and the contact portion is connected to any one of the plurality of transistors. The isolation area includes: A first isolation portion doped with conductive impurities of the first type; and The second isolation portion is doped with conductive impurities of the second type. The second isolation portion is disposed between the area where the first isolation portion is disposed and the area where the plurality of protective devices are disposed, and The first isolation portion is configured to receive ground voltage, and the second isolation portion is configured to receive positive voltage.

2. The image sensing device according to claim 1, wherein, The first type of conductive impurity is a P-type impurity; and The second type of conductive impurity is an N-type impurity.

3. The image sensing device according to claim 1, wherein, The second region includes a floating portion, a second well located below the floating portion, and a first deep well located below the second well. The floating portion has a higher doping density than the second well.

4. The image sensing device according to claim 3, wherein, The second well is arranged to contact the first well; and The contact portion has a higher doping density than the second well.

5. The image sensing device according to claim 3, further comprising: A shallow trench isolation (STI) structure is disposed between the contact portion and the floating portion and is configured to isolate the contact portion and the floating portion from each other.

6. The image sensing device according to claim 3, wherein, The third region includes a ground voltage terminal portion, a third well located below the ground voltage terminal portion, and a second deep well located below the third well, wherein the ground voltage terminal portion has a higher doping density than the third well.

7. The image sensing device according to claim 6, wherein, The third well is arranged to contact the second well; and The contact portion has a higher doping density than the third well.

8. The image sensing device according to claim 6, further comprising: A shallow trench isolation (STI) structure is used to isolate the floating portion and the contact portion from each other.

9. The image sensing device according to claim 1, wherein, Each of the plurality of transistors is any one of a transfer transistor, a select transistor, and a reset transistor.

10. An image sensing device, the image sensing device comprising: Multiple photoelectric sensors, wherein the multiple photoelectric sensors are configured to convert light into electrical signals; Multiple transistors, the multiple transistors being configured to perform operations associated with the multiple photoelectric sensors; Multiple protection devices are configured to deliver charge accumulated in the transistor via a connection to the gate of the transistor; as well as An isolation zone is provided between the area where the plurality of protective devices are located and the area where the plurality of photoelectric sensors and the plurality of transistors are located. Each of the plurality of protection devices includes: The contact portion is doped with P-type impurities; A first well, which is doped with the P-type impurity, is formed below the contact portion; A second well, doped with an N-type impurity, and formed to contact the first well by surrounding it; and A first deep well, doped with the N-type impurity, is formed below the second well. in, The first deep well is formed between the semiconductor substrate and the first well; and Each of the first and second wells is doped at a lower density than the contact portion. The isolation area includes: The first isolation portion doped with the aforementioned P-type impurity; and The second isolation portion doped with the aforementioned N-type impurity, The second isolation portion is disposed between the area where the first isolation portion is disposed and the area where the plurality of protective devices are disposed, and The first isolation portion is configured to receive ground voltage, and the second isolation portion is configured to receive positive voltage.

11. The image sensing device according to claim 10, wherein, The protective device includes: A third well, doped with the P-type impurity, and formed to contact the second well by surrounding it; and A second deep well, which is doped with the P-type impurity, is formed below the third well.

12. An image sensing device, the image sensing device comprising: Multiple photoelectric sensors, wherein the multiple photoelectric sensors are configured to convert light into electrical charge; A plurality of first devices, the plurality of first devices being configured to accumulate charges generated by the plurality of photoelectric sensors; A plurality of second devices, the plurality of second devices being configured to deliver the charge accumulated in the plurality of first devices; as well as An isolation zone is provided between the area where the plurality of first devices are located and the area where the plurality of second devices are located. Each of the plurality of second devices includes: A first region, which is doped with a first type of conductive impurity; A second region, doped with a second type of conductive impurity and surrounding the first region; and A third region, which is doped with the first type of conductive impurity and surrounds the second region. The first region includes a contact portion and a first well located below the contact portion. The contact portion has a higher doping density than the first well, and the contact portion is connected to any one of the plurality of first devices. The isolation area includes: A first isolation portion doped with conductive impurities of the first type; and The second isolation portion is doped with conductive impurities of the second type. The second isolation portion is disposed between the area where the first isolation portion is disposed and the area where the plurality of second devices are disposed, and The first isolation portion is configured to receive ground voltage, and the second isolation portion is configured to receive positive voltage.

13. The image sensing device according to claim 12, wherein, The first type of conductive impurity is a P-type impurity; and The second type of conductive impurity is an N-type impurity.

14. The image sensing device according to claim 12, wherein, The second region includes a floating portion, a second well located below the floating portion, and a first deep well located below the second well. The floating portion has a higher doping density than the second well.

15. The image sensing device according to claim 14, wherein, The second well is arranged to contact the first well; and The contact portion has a higher doping density than the second well.

Images