Display substrate and display device

Abstract

A display substrate (100) and a display device (400). The display substrate (100) comprises a substrate (110), a pixel circuit layer (260) and an anode layer (170); the pixel circuit layer (260) is located on the substrate (110) and comprises a plurality of pixel driving circuits (265); the anode layer (170) is located on a side of the pixel circuit layer (260) away from the substrate (110) and comprises a plurality of anodes (175). The plurality of pixel driving circuits (265) are arranged one-to-one corresponding to the plurality of anodes (175), each pixel driving circuit (265) comprises a functional thin film transistor; the plurality of pixel driving circuits (265) comprise a first pixel driving circuit (2657) and a second pixel driving circuit (2658) arranged adjacently, and the channel region of the functional thin film transistor in the first pixel driving circuit (2657) and the channel region of the functional thin film transistor in the second pixel driving circuit (2658) are both overlapped with the normal projection of the anode (175) corresponding to the first pixel driving circuit (2657) on the substrate (110). Thus, the display substrate (100) can improve the stability and life of the functional thin film transistor, thereby improving the long-term light-emitting stability and life of the display substrate (100).

Description

Technical Field

[0001] This disclosure relates to a display substrate and a display device. Background Technology

[0002] With the continuous development of display technology, organic light-emitting diode (OLED) display technology has been increasingly used in various electronic devices due to its advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and high response speed.

[0003] On the other hand, with the continuous development of organic light-emitting diode (OLED) display technology, people have put forward higher requirements for the power consumption, color deviation, brightness, stability and other performance of OLED display products. Summary of the Invention

[0004] This disclosure provides a display substrate and a display device. The display substrate simultaneously blocks the channel regions of the compensation thin-film transistors in the first pixel driving circuit and the second pixel driving circuit through an anode, thereby improving the stability and lifespan of the compensation thin-film transistors, and consequently improving the long-term luminous stability and lifespan of the display substrate.

[0005] At least one embodiment of this disclosure provides a display substrate, comprising: a substrate; a pixel circuit layer located on the substrate and including a plurality of pixel driving circuits; and an anode layer located on the side of the pixel circuit layer away from the substrate and including a plurality of anodes, wherein the plurality of pixel driving circuits are disposed in a one-to-one correspondence with the plurality of anodes, each pixel driving circuit including a functional thin-film transistor, and the plurality of pixel driving circuits including a first pixel driving circuit and a second pixel driving circuit disposed adjacent to each other, wherein the orthographic projection of the channel region of the functional thin-film transistor in the first pixel driving circuit and the channel region of the functional thin-film transistor in the second pixel driving circuit on the substrate overlaps with the orthographic projection of the anode corresponding to the first pixel driving circuit on the substrate.

[0006] For example, in a display substrate provided in one embodiment of this disclosure, the channel region of the functional thin-film transistor includes a first channel region and a second channel region disposed at intervals, and the functional thin-film transistor further includes a common electrode located between the first channel region and the second channel region.

[0007] The orthographic projections of the common electrode of the functional thin-film transistor in the first pixel driving circuit and the common electrode of the functional thin-film transistor in the second pixel driving circuit on the substrate overlap with the orthographic projections of the anode corresponding to the first pixel driving circuit on the substrate.

[0008] For example, in a display substrate provided in an embodiment of this disclosure, the plurality of anodes includes a plurality of anode groups. The plurality of anode groups are arranged along a first direction to form a plurality of anode group columns and along a second direction to form a plurality of anode group rows. Each anode group includes a first anode, a second anode, a third anode, and a fourth anode. A first pixel driving circuit and a second pixel driving circuit are disposed along the first direction. The fourth anode in one anode group is correspondingly disposed and electrically connected to the first pixel driving circuit, and the second anode in another anode group is correspondingly disposed and electrically connected to the second pixel driving circuit.

[0009] For example, a display substrate provided in one embodiment of this disclosure further includes: a pixel defining layer located on the side of the anode layer away from the substrate, and including a plurality of openings, the plurality of openings including a plurality of opening groups, each of the opening groups including a first opening, a second opening, a third opening and a fourth opening, the first opening corresponding to and exposing the first anode, the second opening corresponding to and exposing the second anode, the third opening corresponding to and exposing the third anode, the fourth opening corresponding to and exposing the fourth anode, the first anode including a first main body portion and a first connecting portion, the orthographic projection of the first opening on the substrate falling into the orthographic projection of the first main body portion on the substrate, the first connecting portion and... The first anode is connected to the pixel driving circuit corresponding to it. The second anode includes a second main body and a second connecting part. The orthographic projection of the second opening on the substrate falls into the orthographic projection of the second main body on the substrate. The second connecting part is connected to the pixel driving circuit corresponding to the second anode. The third anode includes a third main body and a third connecting part. The orthographic projection of the third opening on the substrate falls into the orthographic projection of the third main body on the substrate. The third connecting part is connected to the pixel driving circuit corresponding to the third anode. The fourth anode includes a fourth main body and a fourth connecting part. The orthographic projection of the fourth opening on the substrate falls into the orthographic projection of the fourth main body on the substrate. The fourth connecting part is connected to the pixel driving circuit corresponding to the fourth anode.

[0010] For example, in a display substrate provided in an embodiment of this disclosure, the fourth anode further includes a first supplementary portion, and the orthographic projections of the first channel region and the second channel region of the functional thin-film transistor in the first pixel driving circuit corresponding to the fourth anode on the substrate overlap with the orthographic projections of the first supplementary portion on the substrate.

[0011] For example, in a display substrate provided in one embodiment of this disclosure, the first supplementary portion protrudes from the fourth main body portion toward the third anode portion, and the first supplementary portion is located on the side of the fourth connecting portion near the fourth main body portion.

[0012] For example, in a display substrate provided in one embodiment of this disclosure, the first supplementary portion is connected to both the fourth main body portion and the fourth connecting portion.

[0013] For example, in a display substrate provided in one embodiment of this disclosure, the fourth anode further includes a second supplementary portion, wherein the orthographic projection of the second channel region of the functional thin-film transistor in the second pixel driving circuit on the substrate overlaps with the orthographic projection of the second supplementary portion on the substrate.

[0014] For example, in a display substrate provided in one embodiment of this disclosure, the second supplementary portion protrudes from the fourth main body portion toward the first anode in the anode group adjacent in a first direction.

[0015] For example, in a display substrate provided in one embodiment of this disclosure, the common electrode of the functional thin-film transistor in the first pixel driving circuit overlaps with the orthographic projection of the first supplementary portion on the substrate, and the orthographic projection of the common electrode of the functional thin-film transistor in the second pixel driving circuit on the substrate overlaps with the orthographic projection of the fourth main body portion of the fourth anode corresponding to the first pixel driving circuit on the substrate.

[0016] For example, in a display substrate provided in one embodiment of this disclosure, the channel region of the functional thin-film transistor in the pixel driving circuit corresponding to the first anode is projected onto the substrate and falls onto the projection of the first main body portion onto the substrate.

[0017] For example, in a display substrate provided in an embodiment of this disclosure, the pixel driving circuit further includes a driving thin film transistor, the gate of the driving thin film transistor is connected to the drain of the functional thin film transistor, the first anode further includes a third supplementary portion protruding from the first main body portion toward the third anode, and the gate of the driving thin film transistor in the pixel driving circuit corresponding to the first anode and the drain of the functional thin film transistor are projected onto the substrate and fall into the projected image of the third supplementary portion on the substrate.

[0018] For example, in a display substrate provided in an embodiment of this disclosure, the first channel region of the functional thin-film transistor in the pixel driving circuit corresponding to the third anode is projected onto the substrate and falls onto the projection of the third main body portion onto the substrate.

[0019] For example, in a display substrate provided in one embodiment of this disclosure, the third anode further includes a fourth supplementary portion, and the second channel region of the functional thin-film transistor in the pixel driving circuit corresponding to the third anode is projected onto the substrate and falls into the projected image of the fourth supplementary portion onto the substrate.

[0020] For example, in a display substrate provided in an embodiment of this disclosure, two adjacent anode groups are staggered by 1 / 2 pitch, the pitch being equal to the distance between the centers of two first anodes in two adjacent anode groups in the first direction. In one anode group, the second anode and the third anode are arranged along the second direction to form an anode pair, and the first anode, the anode pair, and the fourth anode are arranged along the second direction.

[0021] For example, in a display substrate provided in one embodiment of this disclosure, the pixel circuit layer includes: a semiconductor layer located on the substrate; and a first gate layer located on the side of the semiconductor layer away from the substrate. The semiconductor layer includes a plurality of pixel driving units, which are disposed one-to-one with the plurality of anodes. Each pixel driving unit includes a first unit, a second unit, a third unit, a fourth unit, a fifth unit, a sixth unit, and a seventh unit. The first unit includes a first channel region and a first source region and a first drain region located on both sides of the first channel region. The second unit includes a second channel region and a second source region and a second drain region located on both sides of the second channel region. The third unit includes a third channel region and a third source region and a third drain region located on both sides of the third channel region. The fourth unit includes a fourth channel region and a fourth source region and a fourth drain region located on both sides of the fourth channel region. The fifth unit includes a fifth channel region and a fifth source region and a fifth drain region located on both sides of the fifth channel region. The sixth unit includes a sixth channel region and a sixth source region and a sixth drain region located on both sides of the sixth channel region. The seventh unit... The first gate layer includes a seventh channel region and a seventh source region and a seventh drain region located on both sides of the seventh channel region. The third source region, the first drain region, and the fifth source region are connected to a first node. The sixth drain region is connected to the third drain region. The first source region, the second drain region, and the fourth drain region are connected to a second node. The fifth drain region is connected to the seventh drain region. The first gate layer includes a reset signal line, a gate line, a first electrode block, and a third gate line. The reset signal line overlaps with the seventh channel region and the sixth channel region to connect with the seventh cell and... The sixth unit forms the seventh and sixth thin-film transistors. The gate line overlaps with the third channel region and the second channel region respectively to form the third and second thin-film transistors with the third and second units. The first electrode block overlaps with the first channel region to form the first thin-film transistor with the first unit. The third gate line overlaps with the fourth and fifth channel regions to form the fourth and fifth thin-film transistors with the fourth and fifth units. The third thin-film transistor is the functional thin-film transistor.

[0022] For example, in a display substrate provided in an embodiment of this disclosure, the reset signal line, the gate line, and the third gate line all extend along the first direction, and the reset signal line, the gate line, the first electrode block, and the third gate line are arranged along the second direction.

[0023] For example, in a display substrate provided in an embodiment of this disclosure, the pixel circuit layer includes: a second gate layer located on the side of the first gate layer away from the semiconductor layer; the second gate layer includes an initialization signal line and a second electrode block, the initialization signal line being connected to the seventh source region and the sixth source region, and the orthographic projection of the second electrode block on the substrate at least partially overlapping the orthographic projection of the first electrode block on the substrate to form a storage capacitor.

[0024] For example, in a display substrate provided in an embodiment of this disclosure, the pixel circuit layer further includes: a first conductive layer located on the side of the second gate layer away from the first gate layer, the first conductive layer including a data line and a power line, the second source region being connected to the data line, and the fourth source region being connected to the power line.

[0025] For example, a display substrate provided in one embodiment of this disclosure further includes: a first planarization layer located on the side of the first conductive layer away from the substrate; a second conductive layer located on the side of the first planarization layer away from the first conductive layer and including a connection electrode; and a second planarization layer located on the side of the second conductive layer away from the first planarization layer, wherein the first planarization layer includes a first via, the connection electrode is connected to a fifth drain region through the first via, the second planarization layer includes a second via, and the anode is connected to the connection electrode through the second via.

[0026] For example, a display substrate provided in one embodiment of this disclosure further includes: a light-emitting layer located on the side of the anode layer away from the substrate, and including a plurality of light-emitting portions, the plurality of light-emitting portions including a plurality of light-emitting groups, each of the light-emitting groups including a first light-emitting portion, a second light-emitting portion, a third light-emitting portion and a fourth light-emitting portion, the first light-emitting portion being at least partially located in the first opening and covering the exposed first anode, the second light-emitting portion being at least partially located in the second opening and covering the exposed second anode, the third light-emitting portion being at least partially located in the third opening and covering the exposed third anode, the fourth light-emitting portion being at least partially located in the fourth opening and covering the exposed fourth anode, the first light-emitting portion being configured to emit light of a first color, the second light-emitting portion and the third light-emitting portion being configured to emit light of a second color, and the fourth light-emitting portion being configured to emit light of a third color.

[0027] For example, in a display substrate provided in one embodiment of this disclosure, the first color is red, the second color is green, and the third color is blue.

[0028] For example, in a display substrate provided in one embodiment of this disclosure, the first direction and the second direction are substantially perpendicular.

[0029] At least one embodiment of this disclosure also provides a display device comprising the display substrate described in any of the preceding claims. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0031] Figure 1 This is a partial cross-sectional schematic diagram of a display substrate;

[0032] Figure 2 As shown Figure 1 The diagram shows a display substrate emitting light.

[0033] Figure 3 This is a plan view of a display substrate provided according to an embodiment of the present disclosure;

[0034] Figure 4A A display substrate provided in one embodiment of this disclosure is along Figure 3 A cross-sectional view along the AA direction;

[0035] Figure 4B Another display substrate provided in an embodiment of this disclosure is along Figure 3 A cross-sectional view along the AA direction;

[0036] Figure 5A A display substrate provided in one embodiment of this disclosure is along Figure 3 Cross-sectional view along the BB direction;

[0037] Figure 5B A display substrate provided in one embodiment of this disclosure is along Figure 3 A cross-sectional view along the GG direction;

[0038] Figure 6 This is a planar schematic diagram of a light-emitting element in a display substrate according to an embodiment of the present disclosure;

[0039] Figure 7 This is a schematic diagram showing the planar relationship between the second conductive layer and the anode layer in a display substrate according to an embodiment of the present disclosure;

[0040] Figure 8 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure;

[0041] Figure 9 This is a partial cross-sectional schematic diagram of another type of display substrate;

[0042] Figure 10 This is a partial cross-sectional schematic diagram of another type of display substrate;

[0043] Figure 11 A plan view of another display substrate provided in an embodiment of this disclosure;

[0044] Figure 12A A display substrate provided in one embodiment of this disclosure is along Figure 11 A cross-sectional view along the HH direction;

[0045] Figure 12B A display substrate provided in one embodiment of this disclosure is along Figure 11 A cross-sectional view along the JJ direction;

[0046] Figure 13 This is a plan view of another display substrate provided according to an embodiment of the present disclosure;

[0047] Figure 14 This is a plan view of another display substrate provided according to an embodiment of the present disclosure;

[0048] Figure 15 This is a plan view of another display substrate provided according to an embodiment of the present disclosure;

[0049] Figure 16 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure;

[0050] Figure 17 This is a schematic diagram of a vapor deposition process using a fine metal mask;

[0051] Figure 18 This is a plan view of a display substrate provided according to an embodiment of the present disclosure;

[0052] Figure 19 A display substrate provided in one embodiment of this disclosure is along Figure 18 A cross-sectional view along the CC direction;

[0053] Figure 20 This is a plan view of another display substrate provided according to an embodiment of the present disclosure;

[0054] Figure 21 A display substrate provided in one embodiment of this disclosure is along Figure 20 A cross-sectional view along the DD direction;

[0055] Figure 22 A display substrate provided in one embodiment of this disclosure is along Figure 20 A cross-sectional view along the EE direction;

[0056] Figure 23 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure;

[0057] Figure 24 This invention relates to a method for manufacturing a display substrate according to an embodiment of the present disclosure;

[0058] Figures 25-27 This is a plan view of a mask assembly provided according to an embodiment of the present disclosure;

[0059] Figure 28A This is a partial schematic diagram of another display substrate provided in an embodiment of the present disclosure;

[0060] Figure 28B This is a partial schematic diagram of another display substrate provided in an embodiment of the present disclosure;

[0061] Figure 29 A display substrate provided in one embodiment of this disclosure is along Figure 28A A cross-sectional view along the FF direction;

[0062] Figures 30A-30D This is a planar schematic diagram of a display substrate with multiple film layers according to an embodiment of the present disclosure;

[0063] Figure 31 This is an equivalent schematic diagram of a pixel driving circuit in a display substrate provided in an embodiment of the present disclosure;

[0064] Figure 32 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure;

[0065] Figure 33 This is a partial schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0066] Figure 34 A display substrate provided in one embodiment of this disclosure is along Figure 33 A cross-sectional view along the KK direction;

[0067] Figure 35A A display substrate provided in one embodiment of this disclosure is along Figure 33 Cross-sectional view along the MM direction;

[0068] Figure 35B A display substrate provided in one embodiment of this disclosure is along Figure 33 A schematic cross-sectional view along the NN direction;

[0069] Figure 35C A display substrate provided in one embodiment of this disclosure is along Figure 33 A cross-sectional view along the QQ direction;

[0070] Figure 36 A plan view of another display substrate provided in an embodiment of this disclosure;

[0071] Figure 37A This is a partial schematic diagram of another display substrate provided in an embodiment of the present disclosure;

[0072] Figure 37B A partial schematic diagram of another display substrate provided in an embodiment of this disclosure; and

[0073] Figure 38 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0075] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0076] Display devices have many performance specifications such as power consumption, brightness, and color coordinates, and color deviation is one of the important parameters. Generally, there are many factors that affect the color deviation of organic light-emitting diode (OLED) display devices. From the perspective of the design of the display substrate (the array substrate or backplane of the OLED), the flatness of the anode has a great influence on color deviation.

[0077] Figure 1 This is a partial cross-sectional schematic diagram of a display substrate; Figure 2 As shown Figure 1 The diagram shows a display substrate emitting light. Figure 1As shown, the sub-pixel of the display substrate includes a substrate 110, a semiconductor layer 120, a first gate layer 130, a second gate layer 140, a first conductive layer 150, a first planarization layer 241, a second conductive layer 160, a second planarization layer 242, an anode 175, and a pixel defining layer 190, which are sequentially disposed thereon. The semiconductor layer 120, the first gate layer 130, the second gate layer 140, and the first conductive layer 150 can form a pixel driving circuit including a thin-film transistor and a storage capacitor. The second conductive layer 160 includes a connection electrode 161, which is connected to the pixel driving circuit through a via (not shown) in the first planarization layer 241. The anode 170 is connected to the connection electrode 161 through a via 271 in the second planarization layer 242. The pixel defining layer 190 includes an opening 191 to expose a portion of the anode 170. When the subsequent organic light-emitting layer 180 is formed in the opening 191, the anode 175 can contact the organic light-emitting layer 180 and drive the organic light-emitting layer to emit light. The area defined by the opening 191 is the effective light-emitting area of ​​the sub-pixel.

[0078] The via 271 in the second planarization layer 242 affects the planarity of the anode 175. If the via 271 is close to the opening 191 (i.e., the effective light-emitting area), the anode 175 at the location of the opening 191 will be "tilted," causing a shift in the light emission direction of the sub-pixel. If the "tilt" directions of the anodes in sub-pixels of different colors are different, the intensity of light emitted by sub-pixels of different colors (e.g., red, green, blue) in different directions will be mismatched, resulting in color shift. For example, the displayed image appears reddish when viewed from one side of the display device including the display substrate, and bluish when viewed from the other side of the display device.

[0079] In this regard, embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a substrate, a first conductive layer, a first planarization layer, a second conductive layer, a second planarization layer, and a plurality of light-emitting element groups; the first conductive layer is located on the substrate; the first planarization layer is located on the side of the first conductive layer away from the substrate; the second conductive layer is located on the side of the first planarization layer away from the first conductive layer; the second planarization layer is located on the side of the second conductive layer away from the first planarization layer; and the plurality of light-emitting element groups are located on the side of the second planarization layer away from the substrate. Multiple light-emitting element groups are arranged along a first direction to form multiple light-emitting element columns and along a second direction to form multiple light-emitting element rows. Each light-emitting element group includes a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element. The second and third light-emitting elements are arranged along the second direction to form a light-emitting element pair. The first light-emitting element, the light-emitting element pair, and the third light-emitting element are arranged along the first direction. The first light-emitting element includes a first anode, the second light-emitting element includes a second anode, the third light-emitting element includes a third anode, and the fourth light-emitting element includes a fourth anode. The second conductive layer includes a first connection electrode, a second connection electrode, a third connection electrode, and a fourth connection electrode. The second planarization layer includes a first via, a second via, a third via, and a fourth via. The first anode is connected to the first connection electrode through the first via, the second anode is connected to the second connection electrode through the second via, the third anode is connected to the third connection electrode through the third via, and the fourth anode is connected to the fourth connection electrode through the fourth via. The multiple third vias corresponding to a row of light-emitting elements are generally located on a first straight line extending along the first direction. The orthographic projection of the fourth via closest to the first straight line on the substrate is located on the side of the first straight line closest to the fourth anode corresponding to the fourth via. Therefore, by moving the position of the fourth via closer to the fourth anode, the display substrate increases the distance between the fourth via and the effective light-emitting area of ​​the adjacent first light-emitting element, thereby ensuring the flatness of the first anode located in the effective light-emitting area of ​​the first light-emitting element and thus avoiding color shift; it also reduces the distance between the fourth via and the effective light-emitting area of ​​the fourth light-emitting element, thereby reducing the resistance between the fourth anode and the fourth connecting electrode located in the effective light-emitting area of ​​the fourth light-emitting element; and it also increases the distance between the first anode and the fourth anode, thereby preventing short circuits caused by residues left during the manufacturing process.

[0080] The display substrate and display device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0081] One embodiment of this disclosure provides a display substrate. Figure 3 This is a plan view of a display substrate provided according to an embodiment of the present disclosure; Figure 4A and Figure 4B A display substrate provided in one embodiment of this disclosure is along Figure 3A cross-sectional view along the AA direction; Figure 5A A display substrate provided in one embodiment of this disclosure is along Figure 3 Cross-sectional view along the BB direction; Figure 5B A display substrate provided in one embodiment of this disclosure is along Figure 3 A cross-sectional view along the GG direction; Figure 6 This is a planar schematic diagram of a light-emitting element in a display substrate according to an embodiment of the present disclosure.

[0082] like Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B and Figure 6As shown, the display substrate 100 includes a substrate 110, a first conductive layer 150, a first planarization layer 241, a second conductive layer 160, a second planarization layer 242, and a plurality of light-emitting element groups 310; the first conductive layer 150 is located on the substrate 110; the first planarization layer 241 is located on the side of the first conductive layer 150 away from the substrate 110; the second conductive layer 160 is located on the side of the first planarization layer 241 away from the first conductive layer 150; the second planarization layer 242 is located on the side of the second conductive layer 160 away from the first planarization layer 241; and the plurality of light-emitting element groups 310 are located on the side of the second planarization layer 242 away from the substrate 110. Multiple light-emitting element groups 310 are arranged along a first direction to form multiple light-emitting element columns 320 and along a second direction to form multiple light-emitting element rows 330. Each light-emitting element group 310 includes a first light-emitting element 311, a second light-emitting element 312, a third light-emitting element 313, and a fourth light-emitting element 314. The second light-emitting element 312 and the third light-emitting element 313 are arranged along the second direction to form a light-emitting element pair 315. The first light-emitting element 311, the light-emitting element pair 315, and the fourth light-emitting element 314 are arranged along the first direction. The first light-emitting element 311 includes a first anode 1751, the second light-emitting element 312 includes a second anode 1752, the third light-emitting element 313 includes a third anode 1753, and the fourth light-emitting element 314 includes a fourth anode 1754. The second conductive layer 160 includes a first connecting electrode 1611, a second connecting electrode 1612, and a third connecting electrode. The second planarization layer 242 includes a first via 2421, a second via 2422, a third via 2423, and a fourth via 2424. The first anode 1751 is connected to the first connecting electrode 1611 through the first via 2421. The second anode 1752 is connected to the second connecting electrode 1612 through the second via 2422. The third anode 1753 is connected to the third connecting electrode 1613 through the third via 2423. The fourth anode 1754 is connected to the fourth connecting electrode 1614 through the fourth via 2424. The plurality of third vias 2423 corresponding to a row of light-emitting elements 330 are generally located on a first straight line 301 extending along a first direction. The orthogonal projection of the fourth via 2424 closest to the first straight line 301 on the substrate 110 is located on the side of the first straight line 301 near the fourth anode 1754 corresponding to the fourth via 2424. It should be noted that the first conductive layer and the second conductive layer are stacked sequentially along the direction away from the substrate.

[0083] In the display substrate provided in this embodiment, the second light-emitting element and the third light-emitting element are arranged along the second direction to form a light-emitting element pair, and the first light-emitting element, the light-emitting element pair and the third light-emitting element are arranged along the first direction. That is, the second anode and the third anode are arranged along the second direction to form an anode pair, and the first anode, the anode pair and the third anode are arranged along the first direction. The orthogonal projection of the fourth via closest to the first straight line on the substrate is located on the side of the first straight line closer to the fourth anode, that is, the display substrate moves the position of the fourth via closer to the fourth anode. As a result, the display substrate has the following beneficial effects: (1) it increases the distance between the fourth via and the effective light-emitting area of ​​the adjacent first light-emitting element, thereby ensuring the flatness of the first anode located in the effective light-emitting area of ​​the first light-emitting element, and thus avoiding color shift; (2) it reduces the distance between the fourth via and the effective light-emitting area of ​​the fourth light-emitting element, thereby reducing the resistance between the fourth anode and the fourth connecting electrode located in the effective light-emitting area of ​​the fourth light-emitting element; (3) it increases the distance between the first anode and the fourth anode, thereby avoiding short circuits between the first anode and the fourth anode caused by residues left during the manufacturing process.

[0084] For example, such as Figure 5A , Figure 5B and Figure 6 As shown, the display substrate moves the position of the fourth via 2424 closer to the fourth anode 1754, thus increasing the distance between the fourth via 2424 and the effective light-emitting area (i.e., the area defined by the opening 1951) of the adjacent first light-emitting element. Furthermore, since the fourth anode has a connection portion connected to the pixel driving circuit below it, moving the position of the fourth via 2424 closer to the fourth anode 1754 does not cause it to overlap with the effective light-emitting area (i.e., the area defined by the opening 1954) of the fourth light-emitting element. At this time, the fourth via 2424 has suitable distances from both the effective light-emitting areas of the adjacent first and fourth light-emitting elements, thereby ensuring the flatness of both the first anode located in the effective light-emitting area of ​​the first light-emitting element and the fourth anode located in the effective light-emitting area of ​​the fourth light-emitting element, and thus avoiding color shift.

[0085] For example, such as Figure 5A , Figure 5B and Figure 6As shown, by moving the position of the fourth via 2424 closer to the fourth anode 1754, the display substrate also reduces the distance between the fourth via 2424 and the effective light-emitting area of ​​the fourth light-emitting element, thereby reducing the resistance between the fourth anode and the fourth connecting electrode located in the effective light-emitting area of ​​the fourth light-emitting element. On the other hand, by moving the position of the fourth via 2424 closer to the fourth anode 1754, the display substrate also increases the distance between the first anode 1751 and the fourth anode 1754, thereby preventing short circuits between the first anode 1751 and the fourth anode 1754 caused by residues left during the manufacturing process.

[0086] For example, the shortest distance between the orthographic projection of the first anode on the substrate and the orthographic projection of the adjacent fourth anode on the substrate is greater than 0.8 times the width of the effective light-emitting area of ​​the first light-emitting element in the first direction, thereby effectively avoiding short circuits between the first anode and the fourth anode caused by residues left during the manufacturing process.

[0087] For example, such as Figure 6 As shown, the fourth anode 1754 includes a main body 1754A and a connecting portion 1754B. The effective light-emitting area of ​​the fourth light-emitting element 314 falls within the orthographic projection of the main body 1754A onto the substrate 110. The connecting portion 1754B is connected to the corresponding fourth connecting electrode 1614 through a fourth via 2424. The connecting portion 1754B is located on the side of the first straight line 301 closer to the main body 1754A, thereby effectively reducing the area of ​​the connecting portion and thus reducing the resistance between the fourth anode and the fourth connecting electrode located in the effective light-emitting area of ​​the fourth light-emitting element. For example, as... Figure 6 As shown, the fourth anode 1754 also includes a first supplementary part 1754C. The first supplementary part 1754C can cover the two channel regions of the compensation thin film transistor in the corresponding pixel driving circuit, thereby improving the stability and lifespan of the compensation thin film transistor, and thus improving the long-term light emission stability and lifespan of the display substrate.

[0088] In some examples, such as Figure 6 As shown, the first supplementary part 1754C protrudes from the fourth main body part 1754A toward the third anode 1753, and the first supplementary part 1754C is located on the side of the fourth connecting part 1754B near the fourth main body part 1754A.

[0089] In some examples, such as Figure 6 As shown, the first supplementary part 1754C is connected to both the fourth main body part 1754A and the fourth connecting part 1754B. Therefore, this display substrate can fully utilize its area by closely arranging the first anode, second anode, third anode, and fourth anode, thereby ensuring the resolution of the display substrate.

[0090] For example, such as Figure 4AAs shown, the display substrate includes a substrate 110, a semiconductor layer 120, a first insulating layer 361, a first gate layer 130, a second insulating layer 362, a second gate layer 140, an interlayer insulating layer 363, a first conductive layer 150, a first planarization layer 241, a second conductive layer 160, and a second planarization layer 242, which are sequentially disposed thereon. The first gate layer 130 may include gate lines 131 and a first electrode block CE1, and the second gate layer may include a second gate block CE2. The orthographic projection of the first electrode block CE1 on the substrate 110 at least partially overlaps with the orthographic projection of the second electrode block CE2 on the substrate 110, thereby forming a storage capacitor.

[0091] For example, such as Figure 4A As shown, the first conductive layer 150 may further include power lines and data lines, and the second conductive layer 160 may include a conductive portion overlapping with the power lines, which may be electrically connected to the power lines, thereby reducing the resistance of the power lines.

[0092] For example, such as Figure 4B As shown, the display substrate may further include a passivation layer 364 located between the first conductive layer 150 and the first planarization layer 241. Of course, embodiments of this disclosure include, but are not limited to, the display substrate may also omit the passivation layer.

[0093] In some examples, such as Figure 6 As shown, the multiple second vias 2422 corresponding to the light-emitting element row 330 adjacent to the first straight line 301 are also roughly located on the first straight line 301.

[0094] In some examples, such as Figure 3 As shown, a fourth via 2424 in a light-emitting element group 310 is located on one side of the bisector of the second direction of the first anode 1751 in the light-emitting element group 310 adjacent to the first anode 1751 in the second direction. For example, the bisector of the second direction of the first anode 1751 is located near the side of the second anode 1752 in the light-emitting element group 310 containing the first anode 1751. That is, the fourth via in a light-emitting element group is located on one side of the bisector of the second direction of the first anode in the light-emitting element group adjacent to the first anode in the second direction. In some examples, such as... Figure 3 As shown, in a light-emitting element group 310, the first via 2421 is located on one side of the bisector of the second direction of the first anode 1751, for example, on the side of the bisector of the second direction of the first anode 1751 near the third anode 1753; the second via 2422 is located on the side of the bisector of the second direction of the second anode 1752 near the first anode 1751; and the third via 2423 is located on the side of the bisector of the second direction of the third anode 1753 near the first anode 1751.

[0095] In some examples, such as Figure 6 As shown, a plurality of fourth vias 2424 corresponding to a row of light-emitting elements 330 are generally located on a straight line extending along a first direction, the straight line passing through a plurality of first anodes 1751 or a plurality of first vias 2421 corresponding to the row of light-emitting elements 330.

[0096] In some examples, such as Figure 6 As shown, a plurality of fourth vias 2424 corresponding to a light-emitting element column 320 are generally located on a second straight line extending along a second direction, the second straight line passing through the effective light-emitting area of ​​a plurality of first anodes 1751 or a plurality of first light-emitting elements 311 corresponding to the light-emitting element column 320.

[0097] In some examples, such as Figure 6 As shown, the distance between the fourth anode 1754 and the nearest first anode 1751 is less than the distance between the first anode 1751 and the nearest fourth anode 1754 in the same row.

[0098] In some examples, such as Figure 6 As shown, the light-emitting element group 310 includes a first light-emitting element group and a second light-emitting element group adjacent to each other in the second direction. The first light-emitting element group and the second light-emitting element group are respectively arranged in two adjacent rows of light-emitting elements 330. The connection portion of the fourth anode 1754 in the first light-emitting element group and the connection portion of the first anode 1751 in the second light-emitting element group are both located on the same side of the bisector of the fourth anode 1754 along the second direction. That is, the main body of the fourth anode has the connection portion of the fourth anode and the connection portion of the first anode adjacent to the fourth anode in the second direction arranged on the same side of the bisector of the second direction.

[0099] In some examples, such as Figure 6 As shown, the main body of the first anode 1751 has a hexagonal shape, and the point where the first anode 1751 is closest to the fourth anode 1754 which is adjacent to the first anode 1751 in the second direction is the vertex of the hexagon.

[0100] In some examples, such as Figure 6 As shown, two adjacent rows of light-emitting elements 330 are staggered by 1 / 2 pitch. The aforementioned pitch is equal to the distance between the centers of the effective light-emitting areas of the two first light-emitting elements 311 in the two adjacent light-emitting element groups 310 in the first direction.

[0101] In some examples, such as Figure 6 As shown, the first straight line 301 is located between two adjacent rows of light-emitting elements 330.

[0102] In some examples, such as Figure 5A , Figure 5B and Figure 6As shown, the orthographic projection of the first via 2421, which is closest to the first straight line 301, on the substrate 110 is located on the side of the first straight line 301 closer to the first anode 1751 corresponding to the first via 2421. That is, the display substrate moves the position of the first via closer to the first anode. As a result, the display substrate has the following beneficial effects: (1) it increases the distance between the first via and the effective light-emitting area of ​​the fourth light-emitting element that is closest in the second direction, thereby ensuring the flatness of the fourth anode located in the effective light-emitting area of ​​the adjacent fourth light-emitting element, and thus avoiding color shift; (2) it reduces the distance between the first via and the effective light-emitting area of ​​the first light-emitting element, thereby reducing the resistance between the first anode and the first connecting electrode located in the effective light-emitting area of ​​the first light-emitting element; (3) it increases the distance between the first anode and the fourth anode, thereby avoiding short circuits caused by residues left in the manufacturing process. Of course, the embodiments disclosed herein include, but are not limited to, the orthographic projection of the first via on the substrate may also be located on the first straight line.

[0103] In some examples, such as Figure 6 As shown, the distance between the orthographic projection of the fourth via 2424 on the substrate 110 and the orthographic projection of the first straight line 301 on the substrate 110 is greater than the distance between the orthographic projection of the first via 2421 on the substrate 110 and the orthographic projection of the first straight line 301 on the substrate 110. That is, the offset of the fourth via is greater relative to the first straight line. Of course, embodiments of this disclosure include, but are not limited to, the offset of the fourth via relative to the first straight line may also be equal to the offset of the first via.

[0104] In some examples, such as Figure 6 As shown, the orthographic projection of the effective light-emitting area of ​​the second light-emitting element 312 onto the substrate 110 has a first shortest distance L1 with the orthographic projection of the second via 2422 onto the substrate 110, and the orthographic projection of the effective light-emitting area of ​​the third light-emitting element 313 onto the substrate 110 has a second shortest distance L2 with the orthographic projection of the third via 2423 onto the substrate 110. The first shortest distance L1 and the second shortest distance L2 are approximately equal. It should be noted that the above-mentioned first shortest distance and second shortest distance being approximately equal includes the case where the first shortest distance and the second shortest distance are completely equal, and also includes the case where the difference between the first shortest distance and the second shortest distance is less than 1 micrometer.

[0105] Therefore, this display substrate allows the second anode located in the effective light-emitting area of ​​the second light-emitting element and the third anode located in the effective light-emitting area of ​​the third light-emitting element to have the same tilt degree and opposite tilt direction, thereby effectively avoiding color shift. It should be noted that when the second anode located in the effective light-emitting area of ​​the second light-emitting element and the third anode located in the effective light-emitting area of ​​the third light-emitting element do not tilt, the tilt degree of the second anode located in the effective light-emitting area of ​​the second light-emitting element and the third anode located in the effective light-emitting area of ​​the third light-emitting element can be considered to be zero. Furthermore, the first shortest distance between the orthographic projection of the effective light-emitting area of ​​the second light-emitting element on the substrate and the orthographic projection of the second via on the substrate can be the shortest distance between the edge of the orthographic projection of the effective light-emitting area of ​​the second light-emitting element on the substrate and the edge of the orthographic projection of the second via on the substrate; similarly, the second shortest distance between the orthographic projection of the effective light-emitting area of ​​the third light-emitting element on the substrate and the orthographic projection of the third via on the substrate can be the shortest distance between the edge of the orthographic projection of the effective light-emitting area of ​​the third light-emitting element on the substrate and the edge of the orthographic projection of the third via on the substrate.

[0106] In some examples, such as Figure 6 As shown, the distance C between the orthographic projection of the fourth via 2424 on the substrate 110 and the orthographic projection of the effective light-emitting area of ​​the first light-emitting element 311 adjacent in the second direction on the substrate 110 is greater than 1.2 times the width A of the effective light-emitting area of ​​the first light-emitting element 311 adjacent in the second direction in the first direction. Therefore, the display substrate can ensure that the first anode located in the effective light-emitting area of ​​the first light-emitting element has good flatness.

[0107] In some examples, such as Figure 6 As shown, the shortest distance B between the fourth via 2424 in a light-emitting element group 310 and the first anode 1751 in the adjacent light-emitting element group 310 is less than the distance E between the fourth via 2424 and the effective light-emitting area of ​​the corresponding fourth light-emitting element 314 in the light-emitting element group 310.

[0108] In some examples, such as Figure 6 As shown, the shortest distance between the fourth anode 1754 in a light-emitting element group 310 and the first anode 1751 in the light-emitting element group 310 that is closest to the fourth anode 1754 in the second direction is the distance between the vertex of the first anode 1751 in the adjacent light-emitting element group 310 and the fourth anode 1754 in the light-emitting element group 310. That is, the vertex of the first anode 1751 in the adjacent light-emitting element group 310 is the point closest to the fourth anode 1754 in the light-emitting element group 310. For example, the shape of the orthographic projection of the first anode 1751 on the substrate 110 is hexagonal, and the aforementioned vertex is the vertex on the major axis of the hexagon.

[0109] In some examples, such as Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B and Figure 6 As shown, the display substrate 100 further includes a pixel defining layer 190; the pixel defining layer 190 is located on the side of the first anode 1751, the second anode 1752, the third anode 1753, and the fourth anode 1754 away from the substrate 110; the pixel defining layer 190 includes a first opening 1951, a second opening 1952, a third opening 1953, and a fourth opening 1954. The first light-emitting element 311 includes a first light-emitting portion 1851, the second light-emitting element 312 includes a second light-emitting portion 1852, the third light-emitting element 313 includes a third light-emitting portion 1853, and the fourth light-emitting element 314 includes a fourth light-emitting portion 1854. The first opening 1951 falls within the orthographic projection of the first anode 1751 onto the substrate 110. At least a portion of the first light-emitting portion 1851 is located in the first opening 1951 and covers the exposed portion of the first anode 1751. The second opening 1952 falls within the orthographic projection of the second anode 1752 onto the substrate 110. At least a portion of the second light-emitting portion 1852 is located in the second opening 1952 and covers the exposed portion of the second anode 1752. The third opening 1953 falls within the orthographic projection of the third anode 1753 onto the substrate 110. At least a portion of the third light-emitting portion 1853 is located in the third opening 1953 and covers the exposed portion of the third anode 1753. The fourth opening 1954 falls within the orthographic projection of the fourth anode 1754 onto the substrate 110. At least a portion of the fourth light-emitting portion 1854 is located in the fourth opening 1954 and covers the exposed portion of the fourth anode 1754. The area defined by the first opening 1951 is the effective light-emitting area of ​​the first light-emitting element 313, the area defined by the second opening 1952 is the effective light-emitting area of ​​the second light-emitting element 312, the area defined by the third opening 1953 is the effective light-emitting area of ​​the third light-emitting element 313, and the area defined by the fourth opening 1954 is the effective light-emitting area of ​​the fourth light-emitting element 314.

[0110] In some examples, such as Figure 6 As shown, the distance C between the orthographic projection of the fourth via 2424 on the substrate 110 and the orthographic projection of the first opening 1951 adjacent in the second direction on the substrate 110 is greater than 1.2 times the width A of the first opening 1951 in the first direction. Therefore, the display substrate can ensure that the first anode located at the first opening (i.e., the portion of the first anode exposed by the first opening) has good flatness.

[0111] In some examples, such as Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B and Figure 6 As shown, the display substrate 100 includes a first planarization layer 241 and a first conductive layer 150; the first planarization layer 241 is located on the side of the second conductive layer 160 close to the substrate 110; the first conductive layer 150 is located on the side of the first planarization layer 241 close to the substrate 110. The first conductive layer 150 includes a first drain 1511, a second drain 1512, a third drain 1513, and a fourth drain 1514; the first planarization layer 241 includes a fifth via 2415, a sixth via 2416, a seventh via 2417, and an eighth via 2418. The first connecting electrode 1611 is connected to the first drain 1511 through the fifth via 2415, the second connecting electrode 1612 is connected to the second drain 1512 through the sixth via 2416, the third connecting electrode 1613 is connected to the third drain 1513 through the seventh via 2417, and the fourth connecting electrode 1614 is connected to the fourth drain 1514 through the eighth via 2418.

[0112] In some examples, such as Figure 4A and Figure 4B As shown, the display substrate 100 further includes a first pixel driving circuit 2651, a second pixel driving circuit 2652, a third pixel driving circuit 2653, and a fourth pixel driving circuit 2654; the first drain 1511 is a part of the first pixel driving circuit 2651, the second drain 1512 is a part of the second pixel driving circuit 2652, the third drain 1513 is a part of the third pixel driving circuit 2653, and the fourth drain 1514 is a part of the fourth pixel driving circuit 2654. The first pixel driving circuit 2651 is connected to the first anode 1751 through the first connecting electrode 1611, thereby applying a driving signal to the first anode 1751; the second pixel driving circuit 2652 is connected to the second anode 1752 through the second connecting electrode 1612, thereby applying a driving signal to the second anode 1752; the third pixel driving circuit 2653 is connected to the third anode 1753 through the third connecting electrode 1613, thereby applying a driving signal to the third anode 1753; and the fourth pixel driving circuit 2654 is connected to the fourth anode 1754 through the fourth connecting electrode 1614, thereby applying a driving signal to the fourth anode 1754.

[0113] Figure 7 This is a schematic diagram showing the planar relationship between the second conductive layer and the anode layer in a display substrate according to an embodiment of this disclosure. Figure 6 and Figure 7As shown, the second anode 1752 and the third anode 1753 are arranged along a second direction to form an anode pair 1755, while the first anode 1751, the anode pair 1755, and the fourth anode 1754 are arranged along a first direction. The second conductive layer 160 also includes a first conductive portion 1621, a second conductive portion 1622, a third conductive portion 1623, and a fourth conductive portion 1624 extending along the second direction. The first conductive portion 1621 is located on the side of the first anode 1751 away from the anode pair 1755, the second conductive portion 1622 is located between the first anode 1751 and the anode pair 1755, the third conductive portion 1623 is located between the anode pair 1755 and the fourth anode 1754, and the fourth conductive portion 1624 overlaps with the fourth anode 1754. In this display substrate, the first conductive portion 1621, the second conductive portion 1622, the third conductive portion 1623, and the fourth conductive portion 1624 extending along the second direction can be connected to the power lines in the first conductive layer 150, thereby reducing the resistance of the power lines.

[0114] In some examples, such as Figure 7 As shown, the orthographic projections of the first conductive portion 1621 and the second conductive portion 1622 on the substrate 110 do not overlap with the orthographic projection of the first anode 1751 on the substrate 110, and the orthographic projections of the second conductive portion 1622 and the third conductive portion 1623 on the substrate 110 do not overlap with the orthographic projection of the anode pair 1755 on the substrate 110. Therefore, the first conductive portion 1621 and the second conductive portion 1622 have a relatively small impact on the flatness of the first anode 175; the second conductive portion 1622 and the third conductive portion 1623 have a relatively small impact on the flatness of the second anode 1752 and the third anode 1753 in the anode pair 1755. Of course, embodiments of this disclosure include, but are not limited to, the first conductive portion, the second conductive portion, and the third conductive portion may also overlap with the anode.

[0115] For example, the orthographic projections of the first conductive portion 1621 and the second conductive portion 1622 on the substrate 110 have a first overlapping portion and a second overlapping portion, respectively, with the orthographic projection of the first anode 1751 on the substrate 110. The areas of the first overlapping portion and the second overlapping portion are approximately equal, thereby improving the flatness of the first anode 1751. Similarly, the orthographic projections of the second conductive portion 1622 and the third conductive portion 1623 on the substrate 110 have a third overlapping portion and a fourth overlapping portion, respectively, with the areas of the third overlapping portion and the fourth overlapping portion being approximately equal, thereby improving the flatness of the second anode 1752 and the third anode 1753 of the anode pair 1755. It should be noted that the above-mentioned "approximately equal" includes the case of complete equality and the case where the difference between the two is less than 10% of the average value of the two.

[0116] For example, the first overlapping portion and the second overlapping portion are symmetrical about the main body of the first anode 1751, that is, the effective light-emitting area of ​​the first light-emitting element 311, along the bisector of the second direction, thereby further improving the flatness of the effective light-emitting area of ​​the first light-emitting element 311; the third overlapping portion and the fourth overlapping portion are symmetrical about the anode pair 1755 along the bisector of the second direction, thereby further improving the flatness of the second anode 1752 and the third anode 1753 of the anode pair 1755.

[0117] In some examples, such as Figure 7 As shown, the orthographic projection of the fourth conductive portion 1624 on the substrate 110 passes through the center of the orthographic projection of the fourth anode 1754 on the substrate 110, and the orthographic projection of the fourth conductive portion 1624 along the bisector of the second direction on the substrate 110 coincides with the orthographic projection of the effective light-emitting area of ​​the fourth light-emitting element 314 along the bisector of the second direction on the substrate 110. This also improves the flatness of the fourth anode 1754.

[0118] In some examples, such as Figure 7 As shown, the second conductive layer 160 further includes a fifth conductive portion 1625 and a sixth conductive portion 1626 extending along a first direction; the fifth conductive portion 1625 is connected to the second conductive portion 1622 and the third conductive portion 1623 respectively, and is located between the second anode 1752 and the third anode 1753; the sixth conductive portion 1626 is connected to the third conductive portion 1623 and the fourth conductive portion 1624 respectively, and is located between the first anode 1751 and the fourth anode 1754 adjacent in the second direction. Thus, the first conductive portion 1621, the second conductive portion 1622, the third conductive portion 1623, the fourth conductive portion 1624, the fifth conductive portion 1625, and the sixth conductive portion 1626 can form a mesh structure, thereby further reducing the resistance of the power lines in the first conductive layer, and thus improving the electrical performance of the display substrate.

[0119] In some examples, such as Figure 7 As shown, the second conductive portion 1622 includes a main body portion 1622A extending along a second direction, a pad 1622B, and a connecting block 1622C. The pad 1622B is located on the side of the main body portion 1622A near the first anode 1751 and is spaced apart from the main body portion 1622A. The pad 1622B is connected to the main body portion 1622A via the connecting block 1622C. Since the size (i.e., width) of the first anode in the first direction is usually small, the distance between the main bodies of the first conductive portion and the second conductive portion is large. By providing the aforementioned pad, the symmetry of the first conductive portion and the second conductive portion on both sides of the first anode can be improved, thereby improving the flatness of the first anode.

[0120] In some examples, the first light-emitting element is configured to emit light of a first color, the second and third light-emitting elements are configured to emit light of a second color, and the fourth light-emitting element is configured to emit light of a third color.

[0121] For example, the first color is red (R), the second color is green (G), and the third color is blue (B). That is to say, the display substrate adopts a GGRB pixel arrangement structure.

[0122] One embodiment of this disclosure also provides a display device. Figure 8 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Figure 8 As shown, the display device 400 includes a display substrate 100 as described above. Therefore, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can ensure the flatness of the first anode located in the effective light-emitting area of ​​the first light-emitting element, thereby avoiding color shift; it can reduce the resistance between the fourth anode and the fourth connecting electrode located in the effective light-emitting area of ​​the fourth light-emitting element; and it can increase the distance between the first anode and the fourth anode, thereby preventing short circuits caused by residues left during the manufacturing process.

[0123] For example, the display device can be a display panel, or it can be an electronic product with display function such as a television, computer, laptop, tablet computer, mobile phone, navigator, or electronic photo frame.

[0124] On the other hand, the inventors of this application have discovered that because the second source / drain metal layer below the anode is thick and unevenly distributed, the second source / drain metal layer can also cause the anode to become uneven.

[0125] Figure 9 This is a partial cross-sectional schematic diagram of another type of display substrate; Figure 10 This is a partial cross-sectional schematic diagram of another type of display substrate. For example... Figure 9 As shown, the second source / drain metal layer 160 includes multiple traces 168. If there are traces 168 on one side below the anode 175 but not on the other side, a height difference will occur on both sides of the anode 175, causing the anode 175 to "tilt," which in turn leads to color shift. Figure 10 As shown, if there are traces 168 on both sides of the anode 175 or no traces 168 are set below the anode 175, the anode 175 can ensure a high flatness, thereby ensuring that the luminous intensity of the anode 175 is consistent in different directions, and thus effectively improving the color deviation phenomenon.

[0126] In this regard, embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a substrate, a first conductive layer, a first planarization layer, a second conductive layer, a second planarization layer, and a plurality of light-emitting element groups; the first conductive layer is located on the substrate; the first planarization layer is located on the side of the first conductive layer away from the substrate; the second conductive layer is located on the side of the first planarization layer away from the first conductive layer; the second planarization layer is located on the side of the second conductive layer away from the first planarization layer; and the plurality of light-emitting element groups are located on the side of the second planarization layer away from the second conductive layer. Multiple light-emitting element groups are arranged along a first direction to form multiple light-emitting element columns and along a second direction to form multiple light-emitting element rows. Each light-emitting element group includes a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element. The first light-emitting element includes a first anode. The second conductive layer includes a first conductive portion and a second conductive portion extending along the second direction. The first conductive portion is located on one side of the first anode, and the second conductive portion is located on the side of the first anode away from the first conductive portion. The first conductive portion includes an extension portion and an offset portion. The orthogonal projection of the effective light-emitting area of ​​the first light-emitting element onto a straight line extending along the second direction is covered by the orthogonal projection of the offset portion onto that straight line. The orthogonal projection of the offset portion onto the substrate is spaced apart from the orthogonal projection of the first anode onto the substrate. The straight line containing the edge of the extension portion close to the second conductive portion and extending along the second direction is a first straight line. The offset portion is spaced apart from the first straight line and located on the side of the first straight line away from the second conductive portion. Therefore, since the first conductive part is located on one side of the first anode and the second conductive part is located on the side of the first anode away from the first conductive part, and the orthographic projection of the offset part on the substrate is spaced apart from the orthographic projection of the first anode on the substrate, the first conductive part and the second conductive part in the second conductive layer have a smaller impact on the flatness of the first anode, thereby ensuring that the first anode can maintain a high flatness, thus ensuring that the luminous intensity of the first anode is consistent in different directions, and thus effectively improving the color shift phenomenon.

[0127] The display substrate and display device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0128] One embodiment of this disclosure provides a display substrate. Figure 11 This is a plan view of another display substrate provided in an embodiment of the present disclosure; Figure 12A A display substrate provided in one embodiment of this disclosure is along Figure 11 A cross-sectional view along the HH direction; Figure 12B A display substrate provided in one embodiment of this disclosure is along Figure 11 A cross-sectional view along the JJ direction; Figure 13 This is a plan view of another display substrate provided according to an embodiment of the present disclosure; Figure 14This is a plan view of another display substrate provided according to an embodiment of the present disclosure. To clearly show the positional relationship between the various conductive portions and the anode in the second conductive layer, Figure 14 Only the second conductive layer and the anode layer are shown.

[0129] like Figure 11-14 As shown, the display substrate 100 includes a substrate 110, a first conductive layer 150, a first planarization layer 241, a second conductive layer 160, a second planarization layer 242, and a plurality of light-emitting element groups 310; the second conductive layer 160 is located on the substrate 110; the second planarization layer 242 is located on the side of the second conductive layer 160 away from the substrate 110; the plurality of light-emitting element groups 310 are located on the side of the second planarization layer 242 away from the substrate 110. Multiple light-emitting element groups 310 are arranged along a first direction to form multiple light-emitting element columns 320 and along a second direction to form multiple light-emitting element rows 330. Each light-emitting element group 310 includes a first light-emitting element 311, a second light-emitting element 312, a third light-emitting element 313, and a fourth light-emitting element 314. The first light-emitting element 311 includes a first anode 1751, the second light-emitting element 312 includes a second anode 1752, the third light-emitting element 313 includes a third anode 1753, and the fourth light-emitting element 314 includes a fourth anode 1754. The second anode 1752 and the third anode 1753 are arranged along the second direction to form an anode pair 1755. The first anode 1751, the anode pair 1755, and the fourth anode 1754 are arranged along the first direction. The second conductive layer 160 includes a first conductive portion 1621 and a second conductive portion 1622 extending along a second direction. The first conductive portion 1621 is located on the side of the first anode 1751 away from the anode pair 1755, and the second conductive portion 1622 is located between the first anode 1751 and the anode pair 1755, that is, on the side of the first anode 1751 away from the first conductive portion 1621. The first conductive portion 1621 includes an extension portion 1621A and an offset portion 1621B. The orthographic projection of the effective light-emitting area of ​​the first light-emitting element 311 on a straight line extending along the second direction is covered by the orthographic projection of the offset portion 1621B on the straight line. That is, the orthographic projection of the effective light-emitting area of ​​the first light-emitting element 311 on the first conductive portion 1621 is located at the position of the offset portion 1621B. In other words, the offset portion 1621B corresponds to the effective light-emitting area of ​​the first light-emitting element 311. The orthographic projection of the offset portion 1621B on the substrate 110 is spaced apart from the orthographic projection of the first anode 1751 on the substrate 110. The straight line containing the edge of the extension portion 1621A that is close to the second conductive portion 1622 and extends along the second direction is the first straight line 302. The offset portion 1621B is spaced apart from the first straight line 302 and located on the side of the first straight line 302 away from the second conductive portion 1622. It should be noted that the first conductive layer and the second conductive layer are stacked sequentially along the direction away from the substrate.

[0130] In the display substrate provided in this embodiment, since the first conductive portion is located on one side of the first anode and the second conductive portion is located on the side of the first anode away from the first conductive portion, and the orthographic projection of the offset portion on the substrate is spaced apart from the orthographic projection of the first anode on the substrate, the first and second conductive portions in the second conductive layer have a smaller impact on the flatness of the first anode. This ensures that the first anode has high flatness, thereby ensuring consistent luminous intensity in different directions and effectively improving color shift. Furthermore, since the offset portion is spaced apart from the first straight line and located on the side of the first straight line away from the second conductive portion, the offset portion is offset away from the first anode, providing space for the placement of the first anode. This allows for close arrangement of the anodes while maintaining high flatness of the first anode.

[0131] It should be noted that the arrangement of the above-mentioned multiple light-emitting elements can be found in [reference needed]. Figure 6 The arrangement shown is such that two adjacent light-emitting elements are staggered by 1 / 2 pitch. The aforementioned pitch is equal to the distance between the centers of the effective light-emitting areas of the two first light-emitting elements in two adjacent light-emitting element groups in the first direction.

[0132] In some examples, the first light-emitting element 311 is configured to emit light of a first color, the second light-emitting element 312 and the third light-emitting element 313 are configured to emit light of a second color, and the fourth light-emitting element 314 is configured to emit light of a third color.

[0133] In some examples, the first color is red, the second color is green, and the third color is blue.

[0134] In some examples, such as Figure 11-14 As shown, the orthographic projection of the first straight line 302 on the substrate 110 passes through the orthographic projection of the first anode 1751 on the substrate 110. Thus, the display substrate can achieve a close alignment of the anodes while ensuring a high degree of flatness for the first anode.

[0135] In some examples, such as Figure 11-14 As shown, the straight line containing the bisector of the extension 1621A extending along the second direction is the second straight line 303. The offset portion 1621B is spaced apart from the second straight line 303 and located on the side of the second straight line 303 away from the second conductive portion 1622. Therefore, since the offset portion is spaced apart from the second straight line and located on the side of the second straight line away from the anode pair, the offset portion is offset in a direction away from the first anode, providing space for the arrangement of the first anode. This allows for a close arrangement of the anodes while ensuring a high degree of flatness for the first anode.

[0136] In some examples, such as Figure 11-14As shown, the orthographic projection of the second straight line 303 on the substrate 110 passes through the orthographic projection of the first anode 1751 on the substrate 110. Thus, the display substrate can achieve a close alignment of the anodes while ensuring a high degree of flatness for the first anode.

[0137] In some examples, such as Figure 11-14 As shown, the first anode 1751 extends along the second direction, and the second conductive portion 1622 includes a main body portion 1622A and a pad 1622B extending along the second direction. The orthographic projection of the main body portion 1622A on the substrate 110 is spaced apart from the orthographic projection of the first anode 1751 on the substrate 110. The pad 1622B is located on the side of the main body portion 1622A close to the first anode 1751. The distance between the orthographic projection of the pad 1622B on the substrate 110 and the orthographic projection of the center of the effective light-emitting area of ​​the first light-emitting element 311 on the substrate 110 is approximately equal to the distance between the orthographic projection of the first conductive portion 1621 on the substrate 110 and the orthographic projection of the center of the effective light-emitting area of ​​the first light-emitting element 311 on the substrate 110.

[0138] In this display substrate, since the size (i.e., width) of the first anode in the first direction is usually small, the distance between the main body portions of the first conductive portion and the second conductive portion is large. Since the distance between the orthographic projection of the pad on the substrate and the orthographic projection of the center of the effective light-emitting area of ​​the first light-emitting element on the substrate is approximately equal to the distance between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the center of the effective light-emitting area of ​​the first light-emitting element on the substrate, the symmetry of the first conductive portion and the second conductive portion on both sides of the first anode can be improved by setting the aforementioned pad, thereby further improving the flatness of the first anode.

[0139] In some examples, such as Figure 11-14 As shown, the distance between the orthographic projection of the first conductive portion 1621 on the substrate 110 and the orthographic projection of the center of the effective light-emitting area of ​​the first light-emitting element 311 on the substrate 110 is less than the distance between the orthographic projection of the main body portion 1622A on the substrate 110 and the orthographic projection of the center of the effective light-emitting area of ​​the first light-emitting element 311 on the substrate 110.

[0140] For example, the ratio of the distance between the orthographic projection of the first conductive portion 1621 on the substrate 110 and the orthographic projection of the center of the effective light-emitting area of ​​the first light-emitting element 311 on the substrate 110 to the distance between the orthographic projection of the main body portion 1622A on the substrate 110 and the orthographic projection of the center of the effective light-emitting area of ​​the first light-emitting element 311 on the substrate 110 is less than or equal to 1 / 3.

[0141] In some examples, such as Figure 11-14As shown, the orthographic projection of the pad 1622B on the substrate 110 is spaced apart from the orthographic projection of the main body 1622A on the substrate 110. The second conductive portion 1622 also includes a connecting portion 1622C, and the pad 1622B is connected to the main body 1622A through the connecting portion 1622C. Therefore, since the pad 1622B is connected to the main body 1622A through the connecting portion 1622C, rather than being integrally formed with the main body 1622A, excessive overlap between the second conductive portion 1622 and the underlying film layers, such as semiconductor layers and gate layers, can be avoided, thus preventing excessive load on the film layers below the second conductive portion 1622. Thus, this display substrate can ensure the normal operation of each sub-pixel while adding pads.

[0142] For example, such as Figure 12B As shown, the first conductive layer 150 includes a power line 151 and a data line 152 extending along a second direction, a first connection block 1541, and a second connection block 1542. The first connection block 1541 is used to connect the initialization signal line to the corresponding source region in the pixel driving circuit; the second connection block 1542 is used to connect the drain region of the compensation thin-film transistor to the first electrode block CE1. The first electrode block CE1 can form a storage capacitor with the second electrode block CE2, and also serves as the gate of the driving thin-film transistor. Therefore, since the pad 1622B is connected to the main body 1622A through the connection portion 1622C, and is not formed integrally with the main body 1622A, excessive overlap between the second conductive portion 1622 and the second connection block 1542 can be avoided, thereby reducing the load on the second connection block 1542, i.e., the load on the drain of the compensation thin-film transistor and the gate of the driving thin-film transistor, and thus improving the performance of the display substrate. It should be noted that the display substrate uses a 7T1C pixel driving circuit. Of course, the embodiments disclosed herein include, but are not limited to, other suitable pixel driving circuit structures may be used for the display substrate.

[0143] For example, such as Figure 12B As shown, the orthographic projection of the offset portion 1621B on the substrate 110 is spaced apart from the orthographic projection of the first anode 1751 on the substrate; the orthographic projection of the pad 1622B on the substrate 110 is also spaced apart from the orthographic projection of the first anode 1751 on the substrate 110. For example, as... Figure 12B As shown, the display substrate may further include a passivation layer 364 located between the first conductive layer 150 and the first planarization layer 241. Of course, embodiments of this disclosure include, but are not limited to, the display substrate may also omit the passivation layer.

[0144] In some examples, such as Figure 11-14As shown, the distance between the orthographic projection of the pad 1622B on the substrate 110 and the orthographic projection of the main body 1622A on the substrate 110 is greater than the width of the orthographic projection of the pad 1622B on the substrate 110 along the first direction. Therefore, this display substrate can further avoid excessive overlap between the second conductive portion 1622 and the underlying film layers, such as semiconductor layers and gate layers, thereby avoiding increased load on the semiconductor layers, gate layers, and other film layers. Thus, this display substrate can ensure the normal operation of each sub-pixel while adding pads.

[0145] In some examples, such as Figure 11-14 As shown, the second conductive portion 1622 includes two connecting portions 1622C, which are respectively located at both ends of the pad 1622B in the second direction. The pad 1622B, the two connecting portions 1622C, and the main body portion 1622A form a rectangular opening. Therefore, this display substrate can further avoid excessive overlap between the second conductive portion 1622 and the underlying film layers, such as semiconductor layers and gate layers, thereby avoiding increased load on the semiconductor layers and gate layers. Thus, this display substrate can ensure the normal operation of each sub-pixel while adding pads.

[0146] In some examples, the ratio of the width of the pad in the first direction to the width of the main body in the first direction is less than or equal to 1 / 2, and the ratio of the width of the pad in the first direction to the distance between the main body and the pad is less than or equal to 1 / 2.

[0147] In some examples, the ratio of the length of the pad in the second direction to the length of the effective light-emitting area of ​​the first light-emitting element in the second direction is greater than or equal to 7 / 8.

[0148] In some examples, the angle between the line connecting the effective light-emitting area of ​​the first light-emitting element and the center of the pad and the first direction is less than 30 degrees. For example, the angle between the line connecting the effective light-emitting area of ​​the first light-emitting element and the center of the pad and the first direction is zero, that is, the line connecting the effective light-emitting area of ​​the first light-emitting element and the center of the pad is parallel to the first direction.

[0149] In some examples, the orthographic projection of the pad on the substrate is spaced apart from the orthographic projection of the first anode on the substrate, and the orthographic projection of the first conductive part on the substrate is spaced apart from the orthographic projection of the first anode on the substrate.

[0150] In some examples, the overlapping area of ​​the orthographic projection of the pad on the substrate and the orthographic projection of the first anode on the substrate is approximately equal to the overlapping area of ​​the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the first anode on the substrate. In some examples, such as Figure 11-14As shown, the second conductive layer 160 also includes a third conductive portion 1623 and a fourth conductive portion 1624 extending along the second direction; the third conductive portion 1623 is located between the anode pair 1755 and the fourth anode 1754, and the fourth conductive portion 1624 overlaps with the fourth anode 1754.

[0151] In some examples, such as Figure 11-14 As shown, the distance between the orthographic projection of the main body 1622A of the second conductive portion 1622 on the substrate 110 and the orthographic projection of the bisector of the effective light-emitting area of ​​the second light-emitting element 312 along the second direction on the substrate 110 is approximately equal to the distance between the orthographic projection of the third conductive portion 162 on the substrate 110 and the orthographic projection of the bisector of the effective light-emitting area of ​​the second light-emitting element 312 along the second direction on the substrate 110. Therefore, this display substrate can improve the symmetry of the anode to the second and third conductive portions on both sides, thereby further improving the flatness of the second and third anodes.

[0152] In some examples, such as Figure 11-14 As shown, the fourth anode 1754 extends along the second direction, and the orthographic projection of the fourth conductive portion 1624 on the substrate 110 passes through the center of the orthographic projection of the effective light-emitting area of ​​the fourth light-emitting element 314 on the substrate 110. Therefore, although the fourth conductive portion 1624 overlaps with the fourth anode 1754, because the orthographic projection of the fourth conductive portion 1624 on the substrate 110 passes through the center of the orthographic projection of the effective light-emitting area of ​​the fourth light-emitting element 314 on the substrate 110, the fourth conductive portion ensures that the fourth anode has high flatness, thereby ensuring consistent luminous intensity of the fourth anode in different directions and effectively improving color shift.

[0153] In some examples, such as Figure 11-14 As shown, the second conductive layer 160 further includes a fifth conductive portion 1625 and a sixth conductive portion 1626 extending along a first direction. The fifth conductive portion 1625 is connected to the main body portion 1622A and the third conductive portion 1623 respectively, and is located between the second anode 1752 and the third anode 1753 in the anode pair 1755. The sixth conductive portion 1626 is connected to the third conductive portion 1623 and the fourth conductive portion 1624 respectively, and is located between the first anode 1751 and the fourth anode 1754 adjacent in the second direction. Thus, the first conductive portion 1621, the second conductive portion 1622, the third conductive portion 1623, the fourth conductive portion 1624, the fifth conductive portion 1625, and the sixth conductive portion 1626 can form a mesh structure, thereby further reducing the resistance of the power lines in the first conductive layer and improving the electrical performance of the display substrate.

[0154] In some examples, such as Figure 11-14As shown, the second conductive layer 160 includes a first connecting electrode 1611, a second connecting electrode 1612, a third connecting electrode 1613, and a fourth connecting electrode 1614. The second planarization layer 242 includes a first via 2421, a second via 2422, a third via 2423, and a fourth via 2424. The first anode 1751 is connected to the first connecting electrode 1611 through the first via 2421. The second anode 1752 is connected to the second connecting electrode 1612 through the second via 2422. The third anode 1753 is connected to the third connecting electrode 1613 through the third via 2423. The fourth anode 1754 is connected to the fourth connecting electrode 1614 through the fourth via 2424.

[0155] In some examples, such as Figure 11-14 As shown, the first planarization layer 241 is located on the side of the second conductive layer 160 near the substrate 110; the first conductive layer 150 is located on the side of the first planarization layer 241 near the substrate 110. The first conductive layer 150 includes a first drain 1511, a second drain 1512, a third drain 1513, and a fourth drain 1514; the first planarization layer 241 includes a fifth via 2415, a sixth via 2416, a seventh via 2417, and an eighth via 2418. The first connecting electrode 1611 is connected to the first drain 1511 through the fifth via 2415, the second connecting electrode 1612 is connected to the second drain 1512 through the sixth via 2416, the third connecting electrode 1613 is connected to the third drain 1513 through the seventh via 2417, and the fourth connecting electrode 1614 is connected to the fourth drain 1514 through the eighth via 2418.

[0156] In some examples, such as Figure 11-14 As shown, the display substrate 100 further includes a first pixel driving circuit 2651, a second pixel driving circuit 2652, a third pixel driving circuit 2653, and a fourth pixel driving circuit 2654; the first drain 1511 is a part of the first pixel driving circuit 2651, the second drain 1512 is a part of the second pixel driving circuit 2652, the third drain 1513 is a part of the third pixel driving circuit 2653, and the fourth drain 1514 is a part of the fourth pixel driving circuit 2654. The first pixel driving circuit 2651 is connected to the first anode 1751 through the first connecting electrode 1611, thereby applying a driving signal to the first anode 1751; the second pixel driving circuit 2652 is connected to the second anode 1752 through the second connecting electrode 1612, thereby applying a driving signal to the second anode 1752; the third pixel driving circuit 2653 is connected to the third anode 1753 through the third connecting electrode 1613, thereby applying a driving signal to the third anode 1753; and the fourth pixel driving circuit 2654 is connected to the fourth anode 1754 through the fourth connecting electrode 1614, thereby applying a driving signal to the fourth anode 1754.

[0157] For example, the thickness of the second conductive layer can be in the range of 0.6-0.8 micrometers, such as 0.7 micrometers; the thickness of the second planarization layer can be in the range of 1.3-1.7 micrometers, such as 1.5 micrometers.

[0158] Figure 15 This is a plan view of another display substrate provided according to an embodiment of the present disclosure. To clearly show the positional relationship between the various conductive portions and the anode in the second conductive layer, Figure 15 Only the second conductive layer and the anode layer are shown. (As shown) Figure 15 As shown, the second conductive portion 1622 of the second conductive layer 160 does not have a pad. The first conductive portion 1621 of the second conductive layer 160 includes an extension portion 1621A and an offset portion 1621B. The orthographic projection of the effective light-emitting area of ​​the first light-emitting element 311 onto the first conductive portion 1621 is located at the position of the offset portion 1621B. That is, the offset portion 1621B corresponds to the effective light-emitting area of ​​the first light-emitting element 311. The orthographic projection of the offset portion 1621B onto the substrate 110 is spaced apart from the orthographic projection of the first anode 1751 onto the substrate 110. The straight line containing the edge of the extension portion 1621A that is close to the first anode 1751 and extends along the second direction is the first straight line 302. The offset portion 1621B is spaced apart from the first straight line 302 and is located on the side of the first straight line 302 away from the anode pair 1755.

[0159] In the display substrate provided in this embodiment, since the first conductive portion is located on the side of the first anode away from the anode pair, and the second conductive portion is located between the first anode and the anode pair, and the orthographic projection of the offset portion on the substrate is spaced apart from the orthographic projection of the first anode on the substrate, the first and second conductive portions in the second conductive layer have a smaller impact on the flatness of the first anode. This ensures that the first anode has high flatness, thereby ensuring consistent luminous intensity in different directions and effectively improving color shift. Furthermore, since the offset portion is spaced apart from the first straight line and located on the side of the first straight line away from the anode pair, the offset portion is offset away from the first anode, providing space for the placement of the first anode. This allows for close anode arrangement while maintaining high flatness of the first anode.

[0160] For example, such as Figure 15As shown, the first anode 1751 may include a main body portion 1751A, a connecting portion 1751B, and an augmentation portion 1751C. The effective light-emitting area of ​​the first light-emitting element falls into the main body portion 1751A. The connecting portion 1751B is used to connect the first anode 1751 to the corresponding pixel driving circuit. The augmentation portion 1751C can cover the potential on the gate G1 of the driving thin-film transistor T1 and the drain D3 of the compensation thin-film transistor T3 in the corresponding pixel driving circuit, thereby stabilizing the potential on the gate G1 of the driving thin-film transistor T1 and the drain D3 of the compensation thin-film transistor T3, thereby further improving the long-term light emission stability and lifespan of the display substrate.

[0161] For example, such as Figure 15 As shown, the distance between the first anode 1751 and the offset portion 1621B can range from 2.5 to 3.2 micrometers, for example, 2.9 micrometers; the distance between the main body portion 1751A of the first anode 1751 and the second conductive portion 1622 can range from 9 to 11 micrometers, for example, 10.5 micrometers; the distance between the connecting portion 1751B of the first anode 1751 and the second conductive portion 1622 can range from 5 to 7 micrometers; the supplementary portion 1751C of the first anode 1751 can partially overlap with the second conductive portion 1622, and the width of the overlapping portion in the first direction is less than 1 micrometer, for example, 0.79 micrometers. Since the distance between the supplementary portion near the edge of the second conductive portion and the main body portion is relatively large, the partial overlap of the supplementary portion 1751C with the second conductive portion 1622 has a relatively small impact on the flatness of the first anode.

[0162] One embodiment of this disclosure also provides a display device. Figure 16 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Figure 16 As shown, the display device 400 includes a display substrate 100 as described above. Therefore, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can ensure the flatness of the first anode located in the effective light-emitting area of ​​the first light-emitting element, thereby avoiding color shift; it can reduce the resistance between the fourth anode and the fourth connecting electrode located in the effective light-emitting area of ​​the fourth light-emitting element; and it can increase the distance between the first anode and the fourth anode, thereby preventing short circuits caused by residues left during the manufacturing process.

[0163] For example, the display device can be an electronic product with display function, such as a television, computer, laptop, tablet computer, mobile phone, navigator, or electronic photo frame.

[0164] On the other hand, in the fabrication of organic light-emitting diode (OLED) display devices, a vapor deposition process is typically used to create the light-emitting layer. Furthermore, to prevent the fine metal mask (FMM) from touching and damaging the OLED display substrate during the vapor deposition process, spacers are usually formed on the OLED display substrate, and the fine metal mask is placed on top of the spacers. In this case, the spacers act as supports for the fine metal mask, thereby protecting the OLED display substrate.

[0165] However, during the research, the inventors of this application noticed that the spacer is usually located in the middle of the straight edge of the effective light-emitting area of ​​the sub-pixel. When a fine metal mask is used for the evaporation process, the opening edge of the fine metal mask is located in the middle of the spacer. The middle position of the spacer is usually the position with the greatest thickness (i.e., the top of the spacer) due to its manufacturing process and other reasons. The opening edge of the fine metal mask just contacts the top of the spacer, which makes it easy to scratch the spacer and generate foreign objects such as particles. Figure 17 This is a schematic diagram of a vapor deposition process using a fine metal mask. Figure 17 As shown, the opening edge 252 of the fine metal mask 250 is located at the top of the spacer 220, which can easily scratch the top of the spacer 220 and generate foreign objects such as particles. After the vapor deposition process, a film layer such as an encapsulation layer will be formed on the display substrate. The foreign objects such as particles generated can easily cause defects such as cracks in the encapsulation layer, thereby reducing the stability and reliability of the product.

[0166] In this regard, the present disclosure also provides a display substrate, a method for manufacturing the same, and a display device. The display substrate includes a substrate, a light-emitting layer, and spacers. The light-emitting layer is located on the substrate and includes a plurality of light-emitting portions. The spacers are located on the side of the light-emitting layer away from the substrate. The orthographic projection of the top edge of the spacer away from the substrate onto the substrate is spaced apart from the edge of the orthographic projection of the light-emitting portion onto the substrate. Therefore, when forming the light-emitting portion using a fine metal mask through a vapor deposition process, the orthographic projection of the opening edge of the fine metal mask onto the substrate and the orthographic projection of the top edge of the spacer onto the substrate are spaced apart, thereby preventing the opening edge of the fine metal mask from contacting the top edge of the spacer and avoiding the generation of foreign matter such as particles, thus improving the yield of the display substrate.

[0167] The display substrate, its manufacturing method, and display device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0168] One embodiment of this disclosure provides a display substrate. Figure 18 This is a plan view of a display substrate provided according to an embodiment of the present disclosure; Figure 19 A display substrate provided in one embodiment of this disclosure is along Figure 18 A cross-sectional view along the CC direction.

[0169] like Figure 18 and Figure 19 As shown, the display substrate 100 includes a substrate 110, a light-emitting layer 180, and spacers 220. The light-emitting layer 180 is located on the substrate 110 and includes a plurality of light-emitting portions 185. The spacers 220 are located on the side of the substrate 110 where the light-emitting layer 180 is located. The orthographic projection of the top tip 225 of the spacers 220 away from the substrate 110 onto the substrate 110 is spaced apart from the edge of the orthographic projection of the light-emitting portion 185 onto the substrate 110. It should be noted that the top tip of the spacers refers to the portion of the spacers away from the substrate, i.e., the portion with greater thickness; in addition, the term "spaced apart" means that the orthographic projection of the top tip of the spacers away from the substrate onto the substrate and the orthographic projection of the light-emitting portion onto the substrate are spaced apart and do not overlap or contact each other.

[0170] In the fabrication process of the display substrate provided in this embodiment, when a fine metal mask 250 is used for vapor deposition to form the aforementioned light-emitting portion 185, such as Figure 19 As shown, the orthographic projection of the opening edge 252 of the fine metal mask 250 onto the substrate 110 is spaced apart from the orthographic projection of the top tip 225 of the spacer 220 onto the substrate 110; this prevents the opening edge 252 of the fine metal mask 250 from contacting the top tip 225 of the spacer 220 and avoids the generation of foreign matter such as particles. For example, as Figure 19 As shown, the opening edge 252 of the fine metal mask 250 is located at the edge of the spacer 220. Since the thickness of the edge of the spacer 220 is less than the thickness of the top 225 of the spacer 220, the opening edge 252 of the fine metal mask 250 is suspended and does not contact the spacer 220, thereby avoiding the generation of foreign objects such as particles due to scratches. As a result, this display substrate can improve the stability, reliability, and product yield of the display substrate.

[0171] In some examples, such as Figure 19 As shown, the dimension of the middle portion of the spacer 220 in the direction perpendicular to the substrate 110 is greater than the dimension of the edge portion of the spacer 220 in the direction perpendicular to the substrate 110. That is, the thickness of the middle portion of the spacer 220 is greater than the thickness of the edge portion of the spacer 220. Therefore, when the orthographic projection of the opening edge of the fine metal mask on the substrate is spaced apart from the orthographic projection of the middle portion of the spacer (i.e., the top of the spacer) on the substrate, the opening edge of the fine metal mask can be suspended and not in contact with the spacer, thereby avoiding the generation of foreign objects such as particles due to scratching.

[0172] For example, such as Figure 19 As shown, the cross-sectional shape of the spacer 220 in a plane perpendicular to the substrate 110 may include a semi-circle. Of course, embodiments of this disclosure include, but are not limited to, this. For example, when the cross-sectional shape of the spacer 220 is semi-circular, the slope angle of the semi-circle is in the range of 8-10 degrees.

[0173] In some examples, such as Figure 18 As shown, the orthographic projection of the spacer 220 onto the substrate 110 is rectangular, and the orthographic projection of the central axis of the spacer 220 along its length onto the substrate 110 is spaced apart from the edge of the orthographic projection of the light-emitting portion 185 onto the substrate 110. Therefore, this display substrate avoids the opening edge of the fine metal mask from contacting the top of the spacer, and avoids the generation of foreign matter such as particles, thereby improving the stability, reliability, and product yield of the display substrate. Of course, the shape of the orthographic projection of the spacer onto the substrate in the embodiments of this disclosure includes, but is not limited to, the rectangle described above, and may also be other shapes.

[0174] In some examples, such as Figure 18 As shown, the distance between the orthographic projection of the central axis of the spacer 220 in the longitudinal direction onto the substrate 110 and the edge of the orthographic projection of the light-emitting portion 185 onto the substrate 110 is greater than 6 micrometers. Therefore, this display substrate can effectively prevent the opening edge of the fine metal mask from contacting the top of the spacer and avoid the generation of foreign matter such as particles, thereby improving the stability, reliability, and product yield of the display substrate.

[0175] Figure 20 This is a plan view of another display substrate provided according to an embodiment of the present disclosure; Figure 21 A display substrate provided in one embodiment of this disclosure is along Figure 20 A cross-sectional view along the DD direction. This is to clearly illustrate the relationship between the spacer and the light-emitting part. Figure 20 Only the substrate, anode layer, light-emitting layer, and spacer are shown. Figure 20 As shown, the top edge 225 of the spacer 220, which is away from the substrate 110, is positioned at a distance from the edge of the top edge 225 of the light-emitting portion 185 on the substrate 110. Figure 21 As shown, when the light-emitting part is formed by evaporation using a fine metal mask, the opening edge 252 of the fine metal mask 250 is suspended and does not contact the spacer 220. Therefore, this display substrate can avoid the opening edge of the fine metal mask from contacting the top of the spacer and avoid the generation of foreign matter such as particles, thereby further improving the stability, reliability and yield of the display substrate.

[0176] In some examples, such as Figure 20As shown, the plurality of light-emitting parts 185 include a plurality of light-emitting groups 1850. The plurality of light-emitting groups 1850 are arranged along a first direction to form a plurality of light-emitting group columns 280, and arranged along a second direction to form a plurality of light-emitting group rows 290. Each light-emitting group 1850 includes a first light-emitting part 1851, a second light-emitting part 1852, a third light-emitting part 1853, and a fourth light-emitting part 1854. Adjacent light-emitting group rows 290 are staggered by 1 / 2 pitch, the aforementioned pitch being equal to the distance between the centers of the two first light-emitting parts 1851 in two adjacent light-emitting groups 1850 in the first direction. The second light-emitting part 1852 and the third light-emitting part 1853 are arranged along the second direction to form a light-emitting pair 1855, and the first light-emitting part 1851, the light-emitting pair 1855, and the fourth light-emitting part 1854 are arranged along the first direction. Figure 20 As shown, the orthographic projection of the top end 225 of the spacer 220 onto the substrate 110 is located between the orthographic projections of the first light-emitting portion 1851 and the third light-emitting portion 1853 of one light-emitting group 1850 onto the substrate 110, and between the orthographic projections of the second light-emitting portion 1852 and the fourth light-emitting portion 1854 of another light-emitting group 1850 adjacent in the second direction onto the substrate 110. Therefore, the display substrate ensures that the orthographic projection of the top end 225 of the spacer 220 onto the substrate 110 is spaced apart from the orthographic projections of the first light-emitting portion 1851, the second light-emitting portion 1852, the third light-emitting portion 1853, and the fourth light-emitting portion 1854 onto the substrate 110, thus fully utilizing the space on the display substrate.

[0177] For example, the first direction and the second direction are approximately perpendicular. It should be noted that the above-mentioned first direction and second direction being approximately perpendicular includes the case where the angle between the first direction and the second direction is 90 degrees, and also includes the case where the angle between the first direction and the second direction is in the range of 85-95 degrees.

[0178] For example, such as Figure 20As shown, in this display substrate 100, two adjacent light-emitting groups 1850 in the second direction can be a first light-emitting group 1850A and a second light-emitting group 1850B. The orthographic projection of the top end 225 of the spacer 220 on the substrate 110 is located between the orthographic projections of the first light-emitting portion 1851 of the first light-emitting group 1850A, the third light-emitting portion 1853 of the first light-emitting group 1850A, the second light-emitting portion 1852 of the second light-emitting group 1850B, and the fourth light-emitting portion 1854 of the second light-emitting group 1850B. Therefore, this display substrate ensures that the orthographic projection of the top end 225 of the spacer 220 on the substrate 110 is spaced apart from the orthographic projections of the first light-emitting portion 1851, the second light-emitting portion 1852, the third light-emitting portion 1853, and the fourth light-emitting portion 1854 on the substrate 110, and fully utilizes the space on the display substrate.

[0179] For example, the orthographic projection of the spacer 220 onto the substrate 110 can be a rectangle with a length of 20 micrometers and a width of 9.5 micrometers. In this case, the distance between the orthographic projection of the spacer 220 onto the substrate 110 and the orthographic projection of the third anode 1753 of the first light-emitting group 1850A onto the substrate 110 can be in the range of 8.5-9.5 micrometers, for example, 8.9 micrometers; the distance between the orthographic projection of the spacer 220 onto the substrate 110 and the orthographic projection of the fourth anode 1754 of the second light-emitting group 1850B onto the substrate 110 can be in the range of 6-7 micrometers, for example, 6.3 micrometers.

[0180] For example, the distance between the orthographic projection of the spacer 220 on the substrate 110 and the orthographic projection of the third light-emitting part 1853 of the first light-emitting group 1850A on the substrate 110 can be 0 micrometers, or even overlap. The distance between the orthographic projection of the spacer 220 on the substrate 110 and the orthographic projection of the second light-emitting part 1852 of the second light-emitting group 1850B on the substrate 110 can be 0 micrometers, or even overlap.

[0181] In some examples, such as Figure 20 and Figure 21As shown, the display substrate 100 further includes an anode layer 170 and a pixel defining layer 190. The anode layer 170 is located between the substrate 110 and the spacer 220, and the pixel defining layer 190 is located on the side of the anode layer 170 closer to the spacer 220. The anode layer 170 includes a plurality of anodes 175, and the pixel defining layer 190 includes a plurality of openings 195 to expose the plurality of anodes 175. The plurality of anodes 175 are correspondingly disposed with a plurality of light-emitting portions 185, and the plurality of openings 195 are correspondingly disposed with a plurality of light-emitting portions 185. The plurality of openings 195 includes a plurality of opening groups 1950, each opening group 1950 including a first opening 1951, a second opening 1952, a third opening 1953, and a fourth opening 1954. The plurality of anodes 175 are correspondingly disposed with a plurality of light-emitting portions 185, and the plurality of anodes 175 include a plurality of anode groups 1750, each anode group 1750 including a first anode 1751 and a second anode. 1752, a third anode 1753 and a fourth anode 1754; a first light-emitting part 1851 is at least partially located in the first opening 1951 and covers the exposed first anode 1751, a second light-emitting part 1852 is at least partially located in the second opening 1952 and covers the exposed second anode 1752, a third light-emitting part 1853 is at least partially located in the third opening 1953 and covers the exposed third anode 1753, and a fourth light-emitting part 1854 is at least partially located in the fourth opening 1954 and covers the exposed fourth anode 1754.

[0182] For example, such as Figure 20 and Figure 21 As shown, the orthographic projection of the spacer 220 on the substrate 110 can overlap with the orthographic projection of the first anode 1751 on the substrate 110.

[0183] For example, such as Figure 20 and Figure 21 As shown, the first virtual straight line is parallel to the length direction of the spacer 220 and passes through the center of the spacer 220; the shape of the orthographic projection of the first opening 1951 on the substrate 110 is approximately elliptical, and the ratio of the distance from the vertex of the ellipse in the major axis direction to the first virtual straight line to the shortest distance from the first opening 1951 to the first virtual straight line is in the range of 1.5-1.

[0184] For example, the distance between the first opening 1951 and the second opening 1952 is 20-25 micrometers; the distance between the first opening 1951 and the third opening 1953 is also 20-25 micrometers; the distance between the first opening 1951 and the fourth opening 1954 is also 20-25 micrometers. Of course, the embodiments of this disclosure include, but are not limited to, the distance between each opening can be determined according to the actual product size.

[0185] In some examples, such as Figure 20 and Figure 21 As shown, the orthographic projection of the spacer 220 on the substrate 110 is disposed with the first opening 1951 on the substrate 110. Therefore, in the manufacturing process of the display substrate provided in this embodiment, when the light-emitting part is formed by the evaporation process using a fine metal mask, the display substrate can avoid the opening edge of the fine metal mask from contacting the top of the spacer and avoid the generation of foreign matter such as particles.

[0186] For example, such as Figure 20 and Figure 21 As shown, the orthographic projection of the spacer 220 on the substrate 110 is spaced apart from the orthographic projection of the first opening 1951 on the substrate 110.

[0187] In some examples, such as Figure 20 and Figure 21 As shown, the orthographic projection of the first opening 1951 onto the substrate 110 is approximately elliptical, and the orthographic projection of the spacer 220 onto the substrate 110 is rectangular. The angle between the major axis of the orthographic projection of the first opening 1951 onto the substrate 110 and the extension direction of the orthographic projection of the spacer 220 onto the substrate 110 is in the range of 20-70 degrees.

[0188] In some examples, such as Figure 20 and Figure 21 As shown, the display substrate 100 also includes a pixel circuit layer 260; the pixel circuit layer 260 is located on the side of the anode layer 170 close to the substrate 110, and includes a plurality of pixel driving circuits 265; the plurality of pixel driving circuits 265 are correspondingly arranged with a plurality of anodes 175, and each anode 175 is electrically connected to the corresponding pixel driving circuit 265. The first anode 1751 includes a main body portion 1751A and a connecting portion 1751B connected to the main body portion 1751A. The orthographic projection of the first opening 1951 on the substrate 110 falls within the orthographic projection of the main body portion 1751A on the substrate 110, and the connecting portion 1751B is electrically connected to the corresponding pixel driving circuit 265.

[0189] In some examples, such as Figure 20 and Figure 21 As shown, the orthographic projection of the spacer 220 on the substrate 110 at least partially overlaps with the orthographic projection of the connector 1751B on the substrate 110. Therefore, this display substrate can fully utilize the space on the display substrate while avoiding contact between the opening edge of the fine metal mask and the top of the spacer, and avoiding the generation of foreign matter such as particles.

[0190] In some examples, such as Figure 20 and Figure 21As shown, the connecting part 1751B is located in the main body part 1751A near the third anode 1753 in the same light-emitting group 1850 and the fourth anode 1754 in the light-emitting group 1850 adjacent in the second direction.

[0191] In some examples, the area defined by the first opening 1951 is the first effective light-emitting area of ​​the first sub-pixel, the area defined by the second opening 1952 is the second effective light-emitting area of ​​the second sub-pixel, the area defined by the third opening 1953 is the third effective light-emitting area of ​​the third sub-pixel, and the area defined by the fourth opening 1954 is the fourth effective light-emitting area of ​​the fourth sub-pixel. Thus, the aforementioned multiple light-emitting groups, multiple opening groups, and multiple anode groups correspond to multiple pixel structures.

[0192] In some examples, the first light-emitting part is configured to emit light of a first color, the second and third light-emitting parts are connected and configured to emit light of a second color, and the fourth light-emitting part is configured to emit light of a third color.

[0193] For example, the first color is red (R), the second color is green (G), and the third color is blue (B). That is to say, the display substrate adopts a GGRB pixel arrangement structure.

[0194] Figure 22 A display substrate provided in one embodiment of this disclosure is along Figure 20 A cross-sectional view along the EE direction. (See diagram.) Figure 22 As shown, in the actual manufacturing process, the light-emitting portion 185 (e.g., the first light-emitting layer 1851 and the fourth light-emitting layer 1854) formed by the fine metal mask diffuses to form a thinner diffusion portion (e.g., diffusion portions 1851A and 1854A). This results in the final light-emitting layer 185 having a size larger than the opening size of the fine metal mask, causing it to overlap with the spacer 220, and even adjacent light-emitting portions may contact or overlap. In this case, the aforementioned light-emitting layer refers to the portion whose thickness is greater than or equal to the thickness of the diffusion portion, but does not include the diffusion portion itself.

[0195] One embodiment of this disclosure also provides a display device. Figure 23 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Figure 23 As shown, the display device 400 includes a display substrate 100 as described above. Therefore, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can prevent the opening edge 252 of the fine metal mask from contacting the top of the spacer during manufacturing, and avoid the generation of foreign matter such as particles, thereby improving the stability, reliability, and product yield of the display substrate.

[0196] For example, the display device can be an electronic product with display function, such as a television, computer, laptop, tablet computer, mobile phone, navigator, or electronic photo frame.

[0197] This disclosure also provides a method for manufacturing a display substrate according to one embodiment. Figure 24 This invention relates to a method for manufacturing a display substrate according to an embodiment of the present disclosure. Figure 24 As shown, the method for manufacturing the display substrate includes the following steps S101-S103.

[0198] Step S101: Form a pixel defining layer on the substrate, including multiple openings.

[0199] For example, the substrate can be a quartz substrate, a glass substrate, a plastic substrate, etc.; the pixel defining layer can be fabricated using a vapor deposition process, and multiple openings can be fabricated using an etching process. Of course, the embodiments disclosed herein include, but are not limited to, these.

[0200] Step S102: Form a spacer on the side of the pixel defining layer away from the substrate.

[0201] For example, the spacer and the pixel defining layer can be formed using the same film layer through a halftone mask or a grayscale mask, thereby saving masking processes and reducing costs. For instance, a layer structure for forming the pixel defining layer and the spacer can be formed on a substrate first; then, a first photoresist pattern is formed on the side of the layer structure away from the substrate using a halftone mask or a grayscale mask. This first photoresist pattern includes fully retained portions, partially retained portions, and fully removed portions; the layer structure is etched using the first photoresist pattern (e.g., a wet etching process) to remove the layer structure corresponding to the fully removed portions, thereby forming multiple openings in the pixel defining layer; then, the first photoresist pattern is ashed to remove the partially retained portions to form a second photoresist pattern; the layer structure is further etched using the second photoresist pattern to form the spacer at the layer structure corresponding to the fully retained portions and the pixel defining layer at the layer structure corresponding to the partially retained portions. Of course, embodiments of this disclosure include, but are not limited to, the spacer can also be formed separately.

[0202] Step S103: Place a mask on the side of the spacer away from the substrate, and use the mask as a mask to vapor-deposit luminescent material in multiple openings to form a luminescent layer including multiple luminescent parts. The mask includes multiple mask openings, and the orthographic projection of the top of the spacer away from the substrate on the substrate and the edge of the orthographic projection of the mask opening on the substrate are spaced apart.

[0203] In the fabrication process of the display substrate provided in this embodiment, a mask is placed on the side of the spacer away from the substrate, and a light-emitting material is deposited in multiple openings using the mask to form a light-emitting layer including multiple light-emitting parts. The orthogonal projection of the opening edge of the mask onto the substrate and the orthogonal projection of the top of the spacer onto the substrate are spaced apart. This avoids contact between the opening edge of the mask and the top of the spacer, and prevents the generation of foreign matter such as particles. Therefore, this method of fabricating the display substrate can improve the stability, reliability, and yield of the display substrate.

[0204] In some examples, the mask described above is a fine metal mask (FMM).

[0205] In some examples, the orthographic projection of the spacer onto the substrate is rectangular, and the orthographic projection of the central axis of the spacer along its length onto the substrate is spaced apart from the edge of the orthographic projection of the light-emitting portion onto the substrate. Therefore, this method of manufacturing the display substrate avoids the opening edge of the fine metal mask from contacting the top of the spacer and prevents the generation of foreign matter such as particles, thereby improving the stability, reliability, and yield of the display substrate.

[0206] In some examples, the orthographic projection of the spacer on the substrate is spaced apart from the edge of the orthographic projection of the light-emitting part on the substrate. This further prevents the opening edge of the fine metal mask from contacting the top of the spacer and avoids the generation of foreign matter such as particles, thereby further improving the stability, reliability, and product yield of the display substrate.

[0207] Figures 25-27 This is a plan view of a mask assembly provided according to an embodiment of the present disclosure. Figures 25-27 As shown, the mask assembly includes a first mask 510, a second mask 520, and a third mask 530. The first mask 510 includes a plurality of first mask openings 412, each of which is used to form the first light-emitting part 1851. The second mask 520 includes a plurality of second mask openings 422, each of which is used to form the second light-emitting part 1852 and the third light-emitting part 1853, meaning that the second light-emitting part 1852 and the third light-emitting part 1853 can be formed through the same mask opening. The third mask 530 includes a plurality of third mask openings 432, each of which is used to form the fourth light-emitting part 1854.

[0208] For example, such as Figures 25-27 As shown, in the method for manufacturing this display substrate, step S103 may include: as follows Figure 25As shown, a first mask 510 is placed on the side of the spacer 220 away from the substrate 110, and a light-emitting material is deposited in multiple openings 1951 using the first mask 510 as a mask to form multiple first light-emitting portions 1851; the first mask 510 is then removed; as shown Figure 26 As shown, a second mask 520 is placed on the side of the spacer 220 away from the substrate 110, and luminescent material is deposited in multiple openings 1951 and 1952 using the second mask 520 as a mask to form multiple second luminescent portions 1852 and multiple third luminescent portions 1853; the second mask 520 is then removed; as shown... Figure 27 As shown, a third mask 530 is placed on the side of the spacer 220 away from the substrate 110, and light-emitting material is vapor-deposited in a plurality of openings 1954 using the third mask 530 as a mask to form a plurality of fourth light-emitting parts 1854.

[0209] For example, such as Figures 25-27 As shown, the top of the spacer 220 away from the substrate 110 is positioned at an angle to the edge of the first light-emitting part 1851 or the fourth light-emitting part 1854 on the substrate 110.

[0210] On the other hand, with the continuous development of organic light-emitting diode (OLED) display technology, people's requirements for display effects are also increasing. In their research, the inventors of this application noted that many factors affect the display effect of OLED display devices, among which the magnitude of the gate layer loading affects the charging time of the pixel driving circuit, and the charging time of the pixel driving circuit has a significant impact on the display effect. Typically, the gate layer loading is mainly composed of the loading of the gate lines and the reset signal line. On the other hand, the magnitude of the data line (or source line) loading directly relates to the power consumption of the IC; the larger the data line loading, the higher the requirements for IC driving, thus increasing the IC's power consumption. Therefore, controlling the loading between the gate lines and the reset signal line, and the loading on the data lines, can improve the display effect of the OLED display device and reduce its power consumption.

[0211] In this regard, the present disclosure provides a display substrate and a display device. The display substrate includes a substrate, a first gate layer, a second gate layer, and a first conductive layer. The first gate layer is located on the substrate, and the second gate layer is located on the side of the first gate layer away from the substrate. The first conductive layer is located on the side of the second gate layer away from the substrate. The first gate layer includes a reset signal line extending along a first direction and a first electrode block. The second gate layer includes a second electrode block configured to form a storage capacitor with the first electrode block. The first conductive layer includes a power line extending along a second direction. The reset signal line and the power line have a first overlapping region, and the second electrode block and the power line have a second overlapping region. The width of the power line located in the first overlapping region is smaller than the width of the power line located in the second overlapping region. The first direction intersects the second direction. Therefore, by reducing the width of the power line in the first overlapping region where the reset signal line and the power line overlap, the display substrate can reduce the load on the reset signal line, thereby increasing the charging time of the pixel driving circuit and improving the display effect of the display substrate.

[0212] The display substrate and display device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0213] One embodiment of this disclosure provides a display substrate. Figure 28A This is a partial schematic diagram of another display substrate provided in an embodiment of the present disclosure; Figure 28B This is a partial schematic diagram of another display substrate provided in an embodiment of the present disclosure; Figure 29 A display substrate provided in one embodiment of this disclosure is along Figure 28A A cross-sectional view along the mid-FF direction. This is to clearly illustrate the stacked structure of each film layer in the pixel driving circuit structure of this display substrate. Figure 28B The anode layer and the second conductive layer are omitted.

[0214] like Figure 28A , Figure 28B and Figure 29As shown, the display substrate 100 includes a substrate 110, a first gate layer 130, a second gate layer 140, and a first conductive layer 150. The first gate layer 130 is located on the substrate 110, and the second gate layer 140 is located on the side of the first gate layer 130 away from the substrate 110. The first conductive layer 150 is located on the side of the second gate layer 140 away from the substrate 110. The first gate layer 130 includes a reset signal line 131 extending along a first direction and a first electrode block CE1. The second gate layer 140 includes a second electrode block CE2, which is configured to form a storage capacitor with the first electrode block CE1. The first conductive layer 150 includes a power line 151 extending along a second direction. The reset signal line 131 and the power line 151 have a first overlapping region 351, and the second electrode block CE2 and the power line 151 have a second overlapping region 352. The width of the power line 151 located in the first overlapping region 351 is smaller than the width of the power line 151 located in the second overlapping region 352. In other words, the width of the power cord 151 in the first overlapping area 351 is reduced; the first direction intersects the second direction, for example, they are perpendicular to each other. It should be noted that the width of the power cord mentioned above refers to the dimension of the power cord along the first direction, and correspondingly, the length of the power cord is the dimension of the power cord along the second direction.

[0215] In the display substrate provided in this embodiment, reducing the width of the power line in the first overlapping region where the reset signal line and the power line overlap can reduce the overlap area between the reset signal line and the power line, thereby reducing the size of the parasitic capacitance between the reset signal line and the power line. Therefore, by reducing the width of the power line in the first overlapping region where the reset signal line and the power line overlap, the display substrate can reduce the load on the reset signal line, thereby increasing the charging time of the pixel driving circuit and ultimately improving the display effect of the display substrate.

[0216] In some examples, the first conductive layer may be a first source / drain metal layer, and the display substrate may also include a second conductive layer, i.e., a second source / drain metal layer. It should be noted that, in order to clearly illustrate the film structure on the display substrate, Figure 28A The display substrate shown does not show a second conductive layer (second source / drain metal layer); of course, the embodiments disclosed herein include, but are not limited to, this, and the display substrate may also not include a second conductive layer, and may be a display substrate with a single source / drain metal layer.

[0217] In some examples, the width of the power line 151 located in the first overlapping region 351 is smaller than the average width of the power line 151.

[0218] In some examples, such as Figure 28A and Figure 28BAs shown, the width of the power line 151 in the first overlapping region 351 is less than 5 / 7 of the maximum width of the power line 151. Therefore, the display substrate can effectively reduce the load on the reset signal line.

[0219] In some examples, such as Figure 28B As shown, the power line 151 includes a main extension 151A and a narrowing portion 151B. The width of the narrowing portion 151B is smaller than the width of the main extension 151A. The orthographic projection of the narrowing portion 151B on the substrate 110 overlaps with the orthographic projection of the reset signal line 131 on the substrate 110.

[0220] In some examples, such as Figure 28A and Figure 28B As shown, the first gate layer 130 also includes a gate line 132 extending along a first direction. The gate line 132 and the power line 151 have a third overlapping region 353. The width of the power line 151 in the third overlapping region 353 is smaller than the width of the power line 151 located in the second overlapping region 352. That is, the width of the power line in the third overlapping region is also reduced. Therefore, by reducing the width of the power line in the second overlapping region where the gate line and the power line overlap, the display substrate can reduce the load on the gate line, thereby further improving the charging time of the pixel driving circuit and thus improving the display effect of the display substrate.

[0221] In some examples, the width of the power line 151 in the third overlapping region 353 is less than the average width of the power line 151.

[0222] In some examples, such as Figure 28A and Figure 28B As shown, the width of the power line 151 in the third overlapping region 353 is less than 5 / 7 of the maximum width of the power line 151. Therefore, this display substrate can effectively reduce the load on the reset signal line.

[0223] In some examples, such as Figure 28B As shown, the power line 151 includes a main extension 151A and a narrowing portion 151B. The width of the narrowing portion 151B is smaller than the width of the main extension 151A. The orthographic projection of the narrowing portion 151B on the substrate 110 overlaps with the orthographic projection of the gate line 132 on the substrate 110.

[0224] In some examples, such as Figure 28A and Figure 28BAs shown, the first conductive layer 150 also includes a data line 152 extending along the second direction. The data line 152 and the reset signal line 131 have a fourth overlapping region 354. The width of the reset signal line 131 in the fourth overlapping region 354 is smaller than the average width of the reset signal line 131. In this display substrate, reducing the width of the reset signal line in the fourth overlapping region can reduce the overlap area between the reset signal line and the data line, thereby reducing the size of the parasitic capacitance between the reset signal line and the data line. Therefore, by reducing the width of the reset signal line in the fourth overlapping region, the display substrate can reduce the load on the data line, thereby reducing the driving power consumption and further reducing the power consumption of the display substrate. It should be noted that the width of the reset signal line mentioned above refers to the dimension of the reset signal line along the second direction. Correspondingly, the length of the reset signal line is the dimension of the reset signal line along the first direction.

[0225] In some examples, such as Figure 28A and Figure 28B As shown, the width of the reset signal line 131 in the fourth overlapping region 354 is less than 3 / 4 of the maximum width of the reset signal line 131. Therefore, this display substrate can effectively reduce the load on the data lines.

[0226] In some examples, such as Figure 28A and Figure 28B As shown, the display substrate 100 further includes a semiconductor layer 120 located on the side of the first gate layer 130 near the substrate 110. The second gate layer 140 includes an initialization signal line 141 extending along the first direction. The data line 152 and the initialization signal line 141 have a fifth overlapping region 355, and the initialization signal line 141 and the semiconductor layer 120 have a sixth overlapping region 356. The width of the initialization signal line 141 located in the fifth overlapping region 355 is smaller than the width of the initialization signal line 141 located in the sixth overlapping region 356. In this display substrate, reducing the width of the initialization signal line in the fifth overlapping region can reduce the overlap area between the initialization signal line and the data line, thereby reducing the size of the parasitic capacitance between the initialization signal line and the data line. Therefore, by reducing the width of the initialization signal line in the fifth overlapping region, the display substrate can further reduce the load on the data line, thereby reducing the driving power consumption and thus reducing the power consumption of the display substrate. It should be noted that the width of the initialization signal line mentioned above refers to the dimension of the initialization signal line along the second direction, and correspondingly, the length of the initialization signal line is the dimension of the initialization signal line along the first direction.

[0227] In some examples, the width of the initialization signal line 141 located in the fourth overlapping region 354 is smaller than the average width of the initialization signal line 141.

[0228] For example, such as Figure 28BAs shown, the orthographic projection of the narrow portion 151B overlapping with the reset signal line 131 on the substrate 110 also overlaps with the orthographic projection of the initialization signal line 141 on the substrate 110.

[0229] In some examples, such as Figure 28B As shown, the power line 151 includes a main body extension 151A and a narrowing portion 151B. The width of the narrowing portion 151B is smaller than the width of the main body extension 151A. The orthographic projection of the narrowing portion 151B on the substrate 110 does not overlap with the orthographic projection of the semiconductor layer 110 on the substrate 110.

[0230] In some examples, such as Figure 28B As shown, the second gate layer 140 also includes a conductive block 143, and the main body extension 151A includes a connection portion 151C connected to the conductive block 143. The orthographic projection of the connection portion 151C on the substrate 110 overlaps with the orthographic projection of the semiconductor layer 110 on the substrate 110. The connection portion 151C and the narrowing portion 151B are adjacent in the second direction.

[0231] For example, such as Figure 28B As shown, the connecting part 151C can be located between the two narrowing parts 151B.

[0232] In some examples, such as Figure 28A and Figure 28B As shown, the width of the initialization signal line 141 in the fourth overlapping region 354 is less than 3 / 4 of the maximum width of the initialization signal line 151. Therefore, this display substrate can effectively reduce the load on the data lines.

[0233] For example, the semiconductor layer 120 may be made of a silicon-based semiconductor material, such as polycrystalline silicon. Of course, embodiments of this disclosure include, but are not limited to, the semiconductor layer may also be made of other semiconductor materials.

[0234] Figures 30A-30D This is a planar schematic diagram of a display substrate with multiple film layers according to an embodiment of the present disclosure; Figure 31 This is an equivalent schematic diagram of a pixel driving circuit in a display substrate provided in an embodiment of the present disclosure.

[0235] For example, such as Figure 30AAs shown, the semiconductor layer 120 includes a first unit 121, a second unit 122, a third unit 123, a fourth unit 124, a fifth unit 125, a sixth unit 126, and a seventh unit 127. The first unit 121 includes a first channel region C1 and a first source region S1 and a first drain region D1 located on both sides of the first channel region C1. The second unit 122 includes a second channel region C2 and a second source region S2 and a second drain region D2 located on both sides of the second channel region C2. The third unit 123 includes a third channel region C3 and a third source region located on both sides of the third channel region C3. The fourth unit 124 includes the fourth channel region C4 and the fourth source region S4 and the fourth drain region D4 located on both sides of the fourth channel region C4. The fifth unit 125 includes the fifth channel region C5 and the fifth source region S5 and the fifth drain region S5 located on both sides of the fifth channel region C5. The sixth unit 126 includes the sixth channel region C6 and the sixth source region S6 and the sixth drain region D6 located on both sides of the sixth channel region C6. The seventh unit 127 includes the seventh channel region C7 and the seventh source region S7 and the seventh drain region D7 located on both sides of the seventh channel region C7.

[0236] For example, such as Figure 30A and Figure 31 As shown, the sixth drain region D6 is connected to the third drain region D3, the third source region S3, the first drain region D1 and the fifth source region S5 are connected to the first node N1, the first source region S1, the second drain region D2 and the fourth drain region D4 are connected to the second node N2, and the fifth drain region D5 is connected to the seventh drain region D7.

[0237] For example, such as Figure 30B As shown, the first gate layer 130 includes a reset signal line 131 extending in a first direction, a gate line 132 extending in a first direction, a first electrode block CE1, and an emitter control line 133 extending in a first direction.

[0238] For example, such as Figure 30C As shown, the second gate layer 140 includes an initialization signal line 141 extending along a first direction, a second electrode block CE2, and a conductive block 143. For example, the conductive block 143 may be connected to a power supply line to reduce the resistance of the power supply line.

[0239] like Figure 31 As shown, the sixth source region S6 and the seventh source region S7 are connected to the initialization signal line 141; the first electrode block CE1 and the second electrode block CE2 can form a storage capacitor Cst.

[0240] For example, such as Figure 30DAs shown, the first conductive layer 150 includes a power line 151 and a data line 152 extending along a second direction, a first connection block 1541, a second connection block 1542, and a third connection block 1543. The first connection block 1541 is used to connect the initialization signal line 141 to the sixth source region S6 and the seventh source region S7; the second connection block 1542 is used to connect the third drain region D3 to the first electrode block CE1; the third connection block 1543 is connected to the fifth drain region D5 and can be used as a drain to connect to the corresponding anode.

[0241] For example, such as Figure 31 As shown, the second source region S2 is connected to the data line 152; the fourth source region S4 is connected to the power line 151. Thus, the first unit 121, the second unit 122, the third unit 123, the fourth unit 124, the fifth unit 125, the sixth unit 126, and the seventh unit 127 of the semiconductor layer 120 can form a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, a fourth thin-film transistor T4, a fifth thin-film transistor T5, a sixth thin-film transistor T6, and a seventh thin-film transistor T7 with the aforementioned reset signal line 131 and gate line 132.

[0242] The following will be about Figure 31 The operation of the pixel driving circuit is illustrated in one manner. First, when a reset signal is transmitted to the reset signal line 131 and the seventh thin-film transistor T7 is turned on, the residual current flowing through the anode of each sub-pixel is discharged to the sixth thin-film transistor T6 through the seventh thin-film transistor T7, thereby suppressing light emission caused by the residual current flowing through the anode of each sub-pixel. Then, when a reset signal is transmitted to the reset signal line 131 and an initialization signal is transmitted to the initialization signal line 141, the sixth thin-film transistor T6 is turned on, and an initialization voltage Vint is applied to the first gate of the first thin-film transistor T1 and the first electrode block CE1 of the storage capacitor Cst through the sixth thin-film transistor T6, thereby initializing the first gate and the storage capacitor Cst. The initialization of the first gate enables the first thin-film transistor T1 to turn on.

[0243] Subsequently, when a gate signal is transmitted to gate line 132 and a data signal is transmitted to data line 152, both the second thin-film transistor T2 and the third thin-film transistor T3 are turned on, applying a data voltage Vd to the first gate through the second thin-film transistor T2 and the third thin-film transistor T3. At this time, the voltage applied to the first gate is a compensation voltage Vd + Vth, and the compensation voltage applied to the first gate is also applied to the first electrode block CE1 of the storage capacitor Cst.

[0244] Subsequently, power line 151 applies a driving voltage Vel to the second electrode block CE2 of storage capacitor Cst and a compensation voltage Vd+Vth to the first electrode block CE1, so that the charge corresponding to the difference between the voltages applied to the two electrodes of storage capacitor Cst is stored in storage capacitor Cst, and the first thin film transistor T1 is turned on for a predetermined time.

[0245] Subsequently, when an emission control signal is applied to the emission control line 133, both the fourth thin-film transistor T4 and the fifth thin-film transistor T5 are turned on, causing the fourth thin-film transistor T4 to apply a driving voltage Vel to the fifth thin-film transistor T5. When the driving voltage Vel passes through the first thin-film transistor T1, which is turned on by the storage capacitor Cst, the driving current Id, which is the difference between the driving voltage Vel and the voltage applied to the first gate through the storage capacitor Cst, flows through the first drain region D3 of the first thin-film transistor T1. The driving current Id is applied to each sub-pixel through the fifth thin-film transistor T5, causing the light-emitting layer of each sub-pixel to emit light.

[0246] In some examples, such as Figure 29 and Figure 31 As shown, the display substrate 100 further includes a first planarization layer 241, a second conductive layer 160, a second planarization layer 242, and an anode 175; the first planarization layer 241 is located on the side of the first conductive layer 150 away from the substrate 110; the second conductive layer 160 is located on the side of the first planarization layer 241 away from the first conductive layer 150, and includes a connection electrode 161; the second planarization layer 242 is located on the side of the second conductive layer 160 away from the first planarization layer 241; the anode 175 is located on the side of the second planarization layer 242 away from the second conductive layer 160; the first planarization layer 241 includes a first via H1, and the connection electrode 161 is connected to the fifth drain region S5 through the first via H1; the second planarization layer 242 includes a second via H2, and the anode 175 is connected to the connection electrode 161 through the second via H2.

[0247] One embodiment of this disclosure also provides a display device. Figure 32 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Figure 32 As shown, the display device 400 includes a display substrate 100 as described above. Therefore, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can reduce the load on the gate layer, thereby increasing the charging time of the pixel driving circuit, and further improving the display effect of the display substrate.

[0248] For example, the display device can be an electronic product with display function, such as a television, computer, laptop, tablet computer, mobile phone, navigator, or electronic photo frame.

[0249] On the other hand, the long-term luminous stability of organic light-emitting diode (OLED) display devices is also an important specification or indicator. In their research, the inventors of this application noted that many factors affect the long-term luminous stability of OLED display devices. Besides the lifespan of the luminescent material itself, the operating state of the thin-film transistors in the pixel driving circuit also has a certain impact on both luminous brightness and long-term luminous stability.

[0250] In this regard, the present disclosure provides a display substrate and a display device. The display substrate includes a substrate, a pixel circuit layer, and an anode layer; the pixel circuit layer is located on the substrate and includes multiple pixel driving circuits; the anode layer is located on the side of the pixel circuit layer away from the substrate and includes multiple anodes. The multiple pixel driving circuits are arranged in a one-to-one correspondence with the multiple anodes, and each pixel driving circuit includes a functional thin-film transistor (TFT). The multiple pixel driving circuits include adjacent first pixel driving circuits and second pixel driving circuits. The orthographic projections of the channel regions of the TFTs in the first and second pixel driving circuits onto the substrate overlap with the orthographic projections of the anodes corresponding to the first pixel driving circuits onto the substrate. Therefore, the display substrate simultaneously shields the channel regions of the TFTs in the first and second pixel driving circuits through the anodes, thereby improving the stability and lifespan of the TFTs, and thus improving the long-term luminous stability and lifespan of the display substrate.

[0251] The display substrate and display device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0252] One embodiment of this disclosure provides a display substrate. Figure 33 This is a partial schematic diagram of a display substrate provided in an embodiment of the present disclosure; Figure 34 A display substrate provided in one embodiment of this disclosure is along Figure 33 A cross-sectional view along the KK direction; Figure 35A A display substrate provided in one embodiment of this disclosure is along Figure 33 Cross-sectional view along the MM direction; Figure 35B A display substrate provided in one embodiment of this disclosure is along Figure 33 A cross-sectional view along the NN direction; Figure 35C A display substrate provided in one embodiment of this disclosure is along Figure 33 A cross-sectional view along the QQ direction.

[0253] like Figure 33 and Figure 34As shown, the display substrate 100 includes a substrate 110, a pixel circuit layer 260, and an anode layer 170. The pixel circuit layer 260 is located on the substrate 110 and includes a plurality of pixel driving circuits 265. The anode layer 170 is located on the side of the pixel circuit layer 260 away from the substrate 110 and includes a plurality of anodes 175. The plurality of pixel driving circuits 265 are arranged in a one-to-one correspondence with the plurality of anodes 175. Each pixel driving circuit 256 includes a functional thin-film transistor, such as a compensation thin-film transistor T3. The plurality of pixel driving circuits 265 include a first pixel driving circuit 2657 and a second pixel driving circuit 2658 arranged adjacent to each other. The orthographic projections of the channel regions of the compensation thin-film transistors T3 in the first pixel driving circuit 2657 and the compensation thin-film transistors T3 in the second pixel driving circuit 2658 onto the substrate 110 overlap with the orthographic projections of the anodes 175 corresponding to the first pixel driving circuit 2657 onto the substrate 110. It should be noted that the terms "first" and "second" in the above-mentioned first pixel driving circuit and second pixel driving circuit are only used to distinguish the two pixel driving circuits in terms of text. The specific structures of the two pixel driving circuits are the same. In addition, the above-mentioned functional thin film transistor can also be other thin film transistors in the pixel driving circuit.

[0254] In the display substrate provided in this embodiment, since the orthographic projections of the channel regions of the compensation thin-film transistor T3 in the first pixel driving circuit 2657 and the compensation thin-film transistor T3 in the second pixel driving circuit 2658 onto the substrate 110 overlap with the orthographic projection of the anode 175 corresponding to the first pixel driving circuit 2657 onto the substrate 110, the anode 175 corresponding to the first pixel driving circuit 2657 can partially or completely block the channel regions of the compensation thin-film transistor T3 in the first pixel driving circuit 2657 and the compensation thin-film transistor T3 in the second pixel driving circuit 2658. Therefore, this display substrate can improve the stability and lifespan of the compensation thin-film transistor T3 in the first pixel driving circuit and the compensation thin-film transistor T3 in the second pixel driving circuit 2658, thereby improving the long-term luminous stability and lifespan of the display substrate. Figures 30A-30D This is a planar schematic diagram of a display substrate with multiple film layers according to an embodiment of the present disclosure; Figure 31This is an equivalent schematic diagram of a pixel driving circuit in a display substrate according to an embodiment of the present disclosure. The pixel driving circuit employs a 7T1C pixel driving structure. During the light-emitting phase, the voltage of node N3 controls the on / off state of the first thin-film transistor T1 (i.e., the driving thin-film transistor), and the stability of the first thin-film transistor T1 directly affects the long-term light-emitting stability of the organic light-emitting diode display device. During the charging phase, the charging voltage of node N3 is related to the states of the third thin-film transistor T3 (i.e., the compensation thin-film transistor), the first thin-film transistor T1, and the second thin-film transistor T2. Typically, thin-film transistors are particularly sensitive to light. When thin-film transistors (especially the channel region) are exposed to light, their characteristics are easily distorted, affecting the normal operation of the pixel driving circuit. In this embodiment, by shielding the channel region of the compensation thin-film transistor with the anode, the stability and lifespan of the compensation thin-film transistor can be improved, thereby improving the long-term light-emitting stability and lifespan of the display substrate.

[0255] In some examples, such as Figures 33-35C As shown, the channel regions of the compensation thin-film transistor T3 in the first pixel driving circuit 2657 and the compensation thin-film transistor T3 in the second pixel driving circuit 2658 both fall into the orthogonal projection of the anode 175 (i.e., the fourth anode 1754) corresponding to the first pixel driving circuit 2657 onto the substrate 110. The anode 175 corresponding to the first pixel driving circuit 2657 can completely block the channel regions of the compensation thin-film transistor T3 in the first pixel driving circuit 2657 and the compensation thin-film transistor T3 in the second pixel driving circuit 2658, thereby further improving the stability and lifespan of the compensation thin-film transistor, and thus improving the long-term light emission stability and lifespan of the display substrate.

[0256] In some examples, such as Figure 30A As shown, the compensation thin-film transistor T3 can be a dual-gate thin-film transistor, thereby improving its reliability. The channel region of the compensation thin-film transistor T3 includes a first channel region C1 and a second channel region C2 spaced apart, and the compensation thin-film transistor T3 also includes a common electrode SE located between the first channel region C1 and the second channel region C2. Figures 33-35BAs shown, the orthographic projections of the common electrode SE of the compensation thin-film transistor T3 in the first pixel driving circuit 2657 and the common electrode SE of the compensation thin-film transistor T3 in the second pixel driving circuit 2658 onto the substrate 110 overlap with the orthographic projection of the anode 175 corresponding to the first pixel driving circuit 2657 onto the substrate 110. Therefore, the anode 175 corresponding to the first pixel driving circuit 2657 can partially or completely block the common electrode SE of the compensation thin-film transistor T3 in the first pixel driving circuit 2657 and the common electrode SE of the compensation thin-film transistor T3 in the second pixel driving circuit 2658, thereby further improving the stability and lifespan of the compensation thin-film transistor, and consequently improving the long-term luminous stability and lifespan of the display substrate.

[0257] Figure 36 This is a plan view of another display substrate provided in an embodiment of the present disclosure. Figure 36 As shown, the plurality of anodes 175 include a plurality of anode groups 1750, each anode group 1750 including a first anode 1751, a second anode 1752, a third anode 1753, and a fourth anode 1754. It should be noted that the aforementioned first anode, second anode, third anode, and fourth anode can be anodes of different shapes and different colors of sub-pixels. Of course, embodiments of this disclosure include, but are not limited to, at least two of the aforementioned first anode, second anode, third anode, and fourth anode can be anodes of the same shape and the same color of sub-pixels.

[0258] In some examples, such as Figure 36As shown, the plurality of anodes 175 include a plurality of anode groups 1750. The plurality of anode groups 1750 are arranged along a first direction to form a plurality of anode group columns 380, and along a second direction to form a plurality of anode group rows 390. Each anode group 1750 includes a first anode 1751, a second anode 1752, a third anode 1753, and a fourth anode 1754. Adjacent anode group rows 390 are staggered by 1 / 2 pitch, the pitch being equal to the distance between the centers of the two first anodes 1751 in two adjacent anode groups 1750 in the first direction. The second anode 1752 and the third anode 1753 are arranged along the second direction to form an anode pair 1755. The first anode 1751, the anode pair 1755, and the fourth anode 1754 are arranged along the second direction. Therefore, this display substrate provides a pixel arrangement structure, thereby improving the display effect of display devices using this display substrate. It should be noted that the anode group provided in this embodiment includes, but is not limited to, the pixel arrangement structure described above; furthermore, the center of the first anode refers to the center of the main body of the first anode, that is, the effective light-emitting area of ​​the first light-emitting element corresponding to the first anode. For example, the first direction and the second direction are approximately perpendicular. It should be noted that the aforementioned approximately perpendicularity of the first direction and the second direction includes the case where the angle between the first direction and the second direction is 90 degrees, and also includes the case where the angle between the first direction and the second direction is in the range of 85-95 degrees.

[0259] In some examples, such as Figure 33 As shown, the first pixel driving circuit 2657 and the second pixel driving circuit 2658 are arranged along the first direction. The fourth anode 1754 in one anode group 1750 is correspondingly arranged and electrically connected to the first pixel driving circuit 2657, and the second anode 1752 in the other anode group 1750 is correspondingly arranged and electrically connected to the second pixel driving circuit 2658.

[0260] In some examples, such as Figure 33 , Figure 34 and Figure 36 As shown, the display substrate 100 further includes a pixel defining layer 190; the pixel defining layer 190 is located on the side of the anode layer 170 away from the substrate 110 and includes a plurality of openings 195; the plurality of openings 195 include a plurality of opening groups 1950, each opening group 1950 including a first opening 1951, a second opening 1952, a third opening 1953 and a fourth opening 1954, the first opening 1951 is corresponding to and exposes the first anode 1751, the second opening 1952 is corresponding to and exposes the second anode 1752, the third opening 1953 is corresponding to and exposes the third anode 1753, and the fourth opening 1954 is corresponding to and exposes the fourth anode 1754.

[0261] like Figure 33 and Figure 36 As shown, the first anode 1751 includes a first main body portion 1751A and a first connecting portion 1751B. The orthographic projection of the first opening 1951 on the substrate 110 falls into the orthographic projection of the first main body portion 1751A on the substrate 110. The first connecting portion 1751B is connected to the pixel driving circuit 265 corresponding to the first anode 1751. The second anode 1752 includes a second main body portion 1752A and a second connecting portion 1752B. The orthographic projection of the second opening 1952 on the substrate 110 falls into the orthographic projection of the second main body portion 1752A on the substrate 110. The second connecting portion 1752B is connected to the pixel driving circuit 265 corresponding to the second anode 1752. The third anode 1753... The third anode 1754 includes a third main body 1753A and a third connecting part 1753B. The orthographic projection of the third opening 1953 on the substrate 110 falls into the orthographic projection of the third main body 1753A on the substrate 110. The third connecting part 1753B is connected to the pixel driving circuit 265 corresponding to the third anode 1753. The fourth anode 1754 includes a fourth main body 1754A and a fourth connecting part 1754B. The orthographic projection of the fourth opening 1954 on the substrate 110 falls into the orthographic projection of the fourth main body 1754A on the substrate 110. The fourth connecting part 1754B is connected to the pixel driving circuit 265 (e.g., the first pixel driving circuit 2657 mentioned above) corresponding to the fourth anode 1754.

[0262] In some examples, such as Figure 33 and Figure 36 As shown, the shape of the first main body portion 1751A is approximately the same as the shape of the first opening 1951; the shape of the second main body portion 1752A is approximately the same as the shape of the second opening 1952; the shape of the third main body portion 1753A is approximately the same as the shape of the third opening 1953; and the shape of the fourth main body portion 1754A is approximately the same as the shape of the fourth opening 1954. For example, when the shape of the fourth opening 1954 is hexagonal, the shape of the fourth main body portion 1754A is also hexagonal. Of course, the shapes of the fourth opening and the fourth main body portion are not limited to hexagons; for example, they can also be elliptical or other shapes.

[0263] For example, such as Figures 33-36As shown, the fourth anode 1754 further includes a first supplementary portion 1754C. The orthographic projections of the first channel region C31 and the second channel region C32 of the compensation thin-film transistor T3 in the first pixel driving circuit 2657 corresponding to the fourth anode 1754 onto the substrate 110 overlap with the orthographic projections of the first supplementary portion 1754C onto the substrate 110. In this display substrate, by adding the first supplementary portion to the fourth anode, the fourth anode can cover the two channel regions of the compensation thin-film transistor in the corresponding pixel driving circuit, thereby improving the stability and lifespan of the compensation thin-film transistor, and thus improving the long-term luminous stability and lifespan of the display substrate.

[0264] In some examples, such as Figures 33-36 As shown, the first supplementary portion 1754C protrudes from the fourth main body portion 1754A toward the third anode 1753, and the first supplementary portion 1754C is located on the side of the fourth connecting portion 1754B near the fourth main body portion 1754A. In some examples, such as Figures 33-36 As shown, the first supplementary part 1754C is connected to both the fourth main body part 1754A and the fourth connecting part 1754B. Therefore, this display substrate can fully utilize its area by closely arranging the first anode, second anode, third anode, and fourth anode, thereby ensuring the resolution of the display substrate.

[0265] For example, such as Figure 35A As shown, the orthographic projection of the first supplementary part 1754C on the substrate 110 overlaps with the orthographic projection of the common electrode SE of the compensation thin film transistor T3 on the substrate 110.

[0266] For example, such as Figure 35A As shown, the orthographic projection of the first supplementary portion 1754C on the substrate 110 covers the orthographic projection of the second channel region C32 of the compensation thin film transistor T3 on the substrate 110.

[0267] For example, such as Figure 35A As shown, the orthographic projection of the fourth main body portion 1754A onto the substrate 110 covers the drain region D3 of the compensation thin-film transistor T3. For example, as... Figure 35C As shown, the first conductive layer 150 includes a second connecting block 1542. The second connecting block 1542 is used to connect the drain region of the compensation thin-film transistor to the first electrode block CE1. The first electrode block CE1 can form a storage capacitor with the second electrode block CE2, and also serves as the gate of the driving thin-film transistor. Since the connecting portion 1752B of the second anode 1752 extends away from the third anode 1753 and overlaps with or even covers the second connecting block 1542, the connecting portion 1752 can stabilize the potential on the gate of the driving thin-film transistor and the drain of the compensation thin-film transistor, thereby further improving the long-term light emission stability and lifespan of the display substrate.

[0268] Figure 37A This is a partial schematic diagram of another display substrate provided according to an embodiment of the present disclosure; Figure 37B This is a partial schematic diagram of another display substrate provided according to an embodiment of the present disclosure. To clearly show the shape of each anode, Figure 37B Only the anode layer is shown.

[0269] like Figure 37A and Figure 37B As shown, the fourth anode 1754 also includes a second supplementary portion 1754D; the orthographic projection of the second channel region C2 of the compensation thin-film transistor T3 in the second pixel driving circuit 2658 onto the substrate 110 overlaps with the orthographic projection of the second supplementary portion 1754D onto the substrate 110. By adding the second supplementary portion to the fourth anode, the fourth anode can partially or even completely cover the second channel region C2 of the compensation thin-film transistor T3 in the second pixel driving circuit 2658, thereby improving the stability and lifespan of the compensation thin-film transistor, and thus improving the long-term luminous stability and lifespan of the display substrate.

[0270] In some examples, such as Figure 37A and Figure 37B As shown, the second supplementary part 1754D protrudes from the fourth main body part 1754A toward the first anode 1751 in the anode group 1750 adjacent in the first direction.

[0271] It should be noted that, as Figure 37A and Figure 37B As shown, the orthographic projection of the first channel region C1 of the compensation thin film transistor T3 in the second pixel driving circuit 2658 onto the substrate 110 can fall into the orthographic projection of the fourth main body portion 1754A onto the substrate 110.

[0272] In some examples, such as Figure 37A and Figure 37B As shown, the common electrode SE of the compensation thin film transistor T3 in the first pixel driving circuit 2657 overlaps with the orthographic projection of the first supplementary part 1754C on the substrate 110, and the orthographic projection of the common electrode SE of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the substrate 110 overlaps with the orthographic projection of the fourth main body part 1754A of the fourth anode 1754 corresponding to the first pixel driving circuit 2657 on the substrate 110.

[0273] In some examples, such as Figure 37A and Figure 37B As shown, the channel region of the compensation thin-film transistor T3 in the pixel driving circuit 265 corresponding to the first anode 1751 is projected onto the substrate 110 and falls onto the projection of the first main body portion 1751A onto the substrate 110.

[0274] In some examples, such as Figure 31 As shown, the pixel driving circuit 265 also includes a driving thin-film transistor T1, the gate G1 of which is connected to the drain D3 of the compensation thin-film transistor T3. Figure 37A As shown, the first anode 1751 also includes a third supplementary portion 1751C, which protrudes from the first main body portion 1751A toward the third anode 1753. The gate G1 of the driving thin-film transistor T1 and the drain D3 of the compensation thin-film transistor T3 in the pixel driving circuit 265 corresponding to the first anode 1751 are projected onto the substrate 110 and fall onto the projection of the third supplementary portion 1751C onto the substrate 110. Thus, the display substrate can stabilize the potential on the gate G1 of the driving thin-film transistor T1 and the drain D3 of the compensation thin-film transistor T3 through the third supplementary portion 1751C, thereby further improving the long-term light emission stability and lifespan of the display substrate.

[0275] In some examples, such as Figure 37A and Figure 37B As shown, the first channel region C31 of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753 is projected onto the substrate 110 and falls onto the third main body 1753A on the substrate 110.

[0276] In some examples, such as Figure 37A and Figure 37B As shown, the third anode 1753 also includes a fourth supplementary portion 1753C. The orthographic projection of the second channel region C32 of the compensation thin-film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753 onto the substrate 110 falls onto the orthographic projection of the fourth supplementary portion 1753C onto the substrate 110. Therefore, the main body of the third anode and the fourth supplementary portion can partially or completely block the first channel region C31 and the second channel region C32 of the compensation thin-film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753, thereby improving the stability and lifespan of the compensation thin-film transistor, and thus improving the long-term luminous stability and lifespan of the display substrate.

[0277] In some examples, such as Figure 33 and Figure 34 As shown, the pixel circuit layer 260 further includes a semiconductor layer 120, a first gate layer 130, a second gate layer 140, and a first conductive layer 150; the first gate layer 130 is located on the side of the semiconductor layer 120 away from the substrate 110, the second gate layer 140 is located on the side of the first gate layer 130 away from the substrate 110, and the first conductive layer 150 is located on the side of the second gate layer 140 away from the substrate 110.

[0278] For example, such as Figure 30A As shown, the semiconductor layer 120 includes a plurality of pixel driving units 1200, which are correspondingly disposed with a plurality of anodes 175. Each pixel driving unit 1200 includes a first unit 121, a second unit 122, a third unit 123, a fourth unit 124, a fifth unit 125, a sixth unit 126, and a seventh unit 127. The first unit 121 includes a first channel region C1 and a first source region S1 and a first drain region D1 located on both sides of the first channel region C1. The second unit 122 includes a second channel region C2 and a second source region S2 and a second drain region D2 located on both sides of the second channel region C2. The third unit 123 includes a third channel region S2 and a second drain region D2 located on both sides of the second channel region C2. C3 and the third source region S3 and the third drain region D3 located on both sides of the third channel region C3; the fourth unit 124 includes the fourth channel region C4 and the fourth source region S4 and the fourth drain region D4 located on both sides of the fourth channel region C4; the fifth unit 125 includes the fifth channel region C5 and the fifth source region S5 and the fifth drain region S5 located on both sides of the fifth channel region C5; the sixth unit 126 includes the sixth channel region C6 and the sixth source region S6 and the sixth drain region D6 located on both sides of the sixth channel region C6; the seventh unit 127 includes the seventh channel region C7 and the seventh source region S7 and the seventh drain region D7 located on both sides of the seventh channel region C7.

[0279] For example, such as Figure 30A and Figure 31 As shown, the sixth drain region D6 is connected to the third drain region D3, the third source region S3, the first drain region D1 and the fifth source region S5 are connected to the first node N1, the first source region S1, the second drain region D2 and the fourth drain region D4 are connected to the second node N2, and the fifth drain region D5 is connected to the seventh drain region D7.

[0280] For example, such as Figure 30B As shown, the first gate layer 130 includes a reset signal line 131 extending in a first direction, a gate line 132 extending in the first direction, a first electrode block CE1, and an emitter control line 133 extending in the first direction. The reset signal line 131 overlaps with the seventh channel region C7 and the sixth channel region C6 to form a seventh thin-film transistor T7 and a sixth thin-film transistor T6 with the seventh unit 127 and the sixth unit 126, respectively. The gate line 132 overlaps with the third channel region C3 and the second channel region C2 to form a third thin-film transistor T3 and a second thin-film transistor T2 with the third unit 123 and the second unit 122, respectively. The first electrode block CE1 overlaps with the first channel region C1 to form a first thin-film transistor T1 with the first unit 121. The emitter control line 133 overlaps with the fourth channel region C4 and the fifth channel region C5 to form a fourth thin-film transistor T4 and a fifth thin-film transistor T5 with the fourth unit 124 and the fifth unit 125. It can be seen that the aforementioned third thin-film transistor T3 is a compensation thin-film transistor.

[0281] For example, such as Figure 30B As shown, the reset signal line 131, the gate line 132, and the transmit control line 133 all extend along the first direction, while the reset signal line 131, the gate line 132, the first electrode block CE1, and the transmit control line 133 are arranged along the second direction.

[0282] For example, such as Figure 30C As shown, the second gate layer 140 includes an initialization signal line 141 extending along a first direction, a second electrode block CE2, and a conductive block 143. For example, the conductive block 143 can be connected to a power supply line, thereby reducing the resistance of the power supply line. Additionally, the initialization signal line 141 is connected to the seventh source region S7 and the first source region S1, and the orthographic projection of the second electrode block CE2 on the substrate 110 at least partially overlaps with the orthographic projection of the first electrode block CE1 on the substrate 110 to form a storage capacitor Cst. It should be noted that the conductive block can also provide some light-shielding; furthermore, Figure 33 Only a portion of the leftmost conductive block is shown. Figure 33 The shape of the leftmost conductive block is the same as the other conductive blocks.

[0283] For example, such as Figure 30D As shown, the first conductive layer 150 includes a power line 151 and a data line 152 extending along a second direction, a first connection block 1541, a second connection block 1542, and a third connection block 1543. The data line 152 can be connected to the second source region S2, and the fourth source region S4 is connected to the power line 151; the first connection block 1541 is used to connect the initialization signal line 141 to the sixth source region S6 and the seventh source region S7; the second connection block 1542 is used to connect the third drain region D3 to the first electrode block CE1; the third connection block 1543 is connected to the fifth drain region D5 and can be used as a drain connected to the corresponding anode.

[0284] The following will be about Figure 31 The operation of the pixel driving circuit is illustrated in one manner. First, when a reset signal is transmitted to the reset signal line 131 and the seventh thin-film transistor T7 is turned on, the residual current flowing through the anode of each sub-pixel is discharged to the sixth thin-film transistor T6 through the seventh thin-film transistor T7, thereby suppressing light emission caused by the residual current flowing through the anode of each sub-pixel. Then, when a reset signal is transmitted to the reset signal line 131 and an initialization signal is transmitted to the initialization signal line 141, the sixth thin-film transistor T6 is turned on, and an initialization voltage Vint is applied to the first gate of the first thin-film transistor T1 and the first electrode block CE1 of the storage capacitor Cst through the sixth thin-film transistor T6, thereby initializing the first gate and the storage capacitor Cst. The initialization of the first gate enables the first thin-film transistor T1 to turn on.

[0285] Subsequently, when a gate signal is transmitted to gate line 132 and a data signal is transmitted to data line 152, both the second thin-film transistor T2 and the third thin-film transistor T3 are turned on, applying a data voltage Vd to the first gate through the second thin-film transistor T2 and the third thin-film transistor T3. At this time, the voltage applied to the first gate is a compensation voltage Vd + Vth, and the compensation voltage applied to the first gate is also applied to the first electrode block CE1 of the storage capacitor Cst.

[0286] Subsequently, power line 151 applies a driving voltage Vel to the second electrode block CE2 of storage capacitor Cst and a compensation voltage Vd+Vth to the first electrode block CE1, so that the charge corresponding to the difference between the voltages applied to the two electrodes of storage capacitor Cst is stored in storage capacitor Cst, and the first thin film transistor T1 is turned on for a predetermined time.

[0287] Subsequently, when an emission control signal is applied to the emission control line 133, both the fourth thin-film transistor T4 and the fifth thin-film transistor T5 are turned on, causing the fourth thin-film transistor T4 to apply a driving voltage Vel to the fifth thin-film transistor T5. When the driving voltage Vel passes through the first thin-film transistor T1, which is turned on by the storage capacitor Cst, the driving current Id, which is the difference between the driving voltage Vel and the voltage applied to the first gate through the storage capacitor Cst, flows through the first drain region D3 of the first thin-film transistor T1. The driving current Id is applied to each sub-pixel through the fifth thin-film transistor T5, causing the light-emitting layer of each sub-pixel to emit light.

[0288] In some examples, such as Figure 33 and Figure 34 As shown, the display substrate 100 further includes a first planarization layer 241, a second conductive layer 160, a second planarization layer 242, and an anode 175; the first planarization layer 241 is located on the side of the first conductive layer 150 away from the substrate 110; the second conductive layer 160 is located on the side of the first planarization layer 241 away from the first conductive layer 150, and includes a connection electrode 161; the second planarization layer 242 is located on the side of the second conductive layer 160 away from the first planarization layer 241; the anode 175 is located on the side of the second planarization layer 242 away from the second conductive layer 160; the first planarization layer 241 includes a first via H1, and the connection electrode 161 is connected to the sixth drain region S6 through the first via H1; the second planarization layer 242 includes a second via H2, and the anode 175 is connected to the connection electrode 161 through the second via H2.

[0289] In some examples, such as Figure 33 , Figure 34 and Figure 36As shown, the display substrate 100 further includes a light-emitting layer 180 located on the side of the anode layer 170 away from the substrate 110, and includes a plurality of light-emitting portions 185. The plurality of light-emitting portions 185 include a plurality of light-emitting groups 1850. Each light-emitting group 1850 includes a first light-emitting portion 1851, a second light-emitting portion 1852, a third light-emitting portion 1853, and a fourth light-emitting portion 1854. The first light-emitting portion 1851 is at least partially located in the first opening 1951 and covers the exposed first anode 1751. The second light-emitting portion 1852 is at least... The first light-emitting part 1851 is partially located in the second opening 1952 and covers the exposed second anode 1752; the third light-emitting part 1753 is at least partially located in the third opening 1953 and covers the exposed third anode 1753; the fourth light-emitting part 1854 is at least partially located in the fourth opening 1954 and covers the exposed fourth anode 1754; the first light-emitting part 1851 is configured to emit light of a first color; the second light-emitting part 1852 and the third light-emitting part 1853 are configured to emit light of a second color; and the fourth light-emitting part 1854 is configured to emit light of a third color.

[0290] For example, the first color is red (R), the second color is green (G), and the third color is blue (B). That is to say, the display substrate adopts a GGRB pixel arrangement structure.

[0291] For example, such as Figure 34 As shown, the overlapping area of ​​the first conductive portion 1621 located on the side of the first anode 1751 away from the second anode 1752 and the power line 151 located in the first conductive layer 150 is smaller than the overlapping area of ​​the second conductive portion 1622 located on the side of the first anode 1751 close to the second anode 1752 and the power line 151 in the first conductive layer 150.

[0292] One embodiment of this disclosure also provides a display device. Figure 38 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Figure 38 As shown, the display device 400 includes a display substrate 100 as described above. Therefore, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can improve the stability and lifespan of the compensation thin-film transistor, thereby improving the long-term luminous stability and lifespan of the display substrate.

[0293] For example, the display device can be an electronic product with display function, such as a television, computer, laptop, tablet computer, mobile phone, navigator, or electronic photo frame.

[0294] The following points need to be explained:

[0295] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0296] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0297] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display substrate, comprising: Substrate; A pixel circuit layer is located on the substrate and includes multiple pixel driving circuits; as well as An anode layer, located on the side of the pixel circuit layer away from the substrate, includes multiple anodes. The plurality of pixel driving circuits are configured one-to-one with the plurality of anodes. Each pixel driving circuit includes a functional thin-film transistor and a driving thin-film transistor. The source of the functional thin-film transistor is connected to the drain of the driving thin-film transistor, and the drain of the functional thin-film transistor is connected to the gate of the driving thin-film transistor. The plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit arranged adjacent to each other. The orthographic projections of the channel regions of the functional thin-film transistors in the first pixel driving circuit and the functional thin-film transistors in the second pixel driving circuit on the substrate overlap with the orthographic projections of the anodes corresponding to the first pixel driving circuit on the substrate. The orthographic projections of the gates of the functional thin-film transistors in the first pixel driving circuit and the functional thin-film transistors in the second pixel driving circuit onto the substrate overlap with the orthographic projections of the corresponding anodes of the first pixel driving circuit onto the substrate. The plurality of anodes includes a plurality of anode groups, which are arranged along a first direction to form a plurality of anode group columns and along a second direction to form a plurality of anode group rows. Each anode group includes a first anode, a second anode, a third anode, and a fourth anode, with the anode corresponding to the first pixel driving circuit being the fourth anode. The pixel circuit layer includes a first conductive layer and a second conductive layer. The second conductive layer is located on the side of the first conductive layer near the anode layer. The second conductive layer includes a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion extending along the second direction. The orthographic projection of the fourth conductive portion onto the substrate passes through the center of the orthographic projection of the effective light-emitting area of ​​the fourth light-emitting element corresponding to the fourth anode onto the substrate. The second conductive layer further includes a fifth conductive portion and a sixth conductive portion. The fifth conductive portion is connected to the second conductive portion and the third conductive portion respectively, and is located between the second anode and the third anode. The sixth conductive portion is connected to the third conductive portion and the fourth conductive portion respectively, and is located between the first anode and the fourth anode adjacent to each other in the second direction. The display substrate includes: A first planarization layer is located between the first conductive layer and the second conductive layer; The second planarization layer is located on the side of the second conductive layer away from the first planarization layer. The second conductive layer further includes a first connecting electrode, a second connecting electrode, a third connecting electrode, and a fourth connecting electrode. The second planarization layer includes a first via, a second via, a third via, and a fourth via. The first anode is connected to the first connecting electrode through the first via, the second anode is connected to the second connecting electrode through the second via, the third anode is connected to the third connecting electrode through the third via, and the fourth anode is connected to the fourth connecting electrode through the fourth via. The orthographic projections of the plurality of third vias corresponding to the plurality of anode groups on the substrate are approximately located on a first straight line extending along the first direction, and the orthographic projection of the fourth via closest to the first straight line on the substrate is located on the side of the first straight line close to the orthographic projection of the fourth anode corresponding to the fourth via on the substrate.

2. The display substrate according to claim 1, wherein, The channel region of the functional thin-film transistor includes a first channel region and a second channel region spaced apart, and the functional thin-film transistor also includes a common electrode located between the first channel region and the second channel region. The orthographic projections of the common electrode of the functional thin-film transistor in the first pixel driving circuit and the common electrode of the functional thin-film transistor in the second pixel driving circuit on the substrate overlap with the orthographic projections of the anode corresponding to the first pixel driving circuit on the substrate.

3. The display substrate according to claim 2, wherein, The first pixel driving circuit and the second pixel driving circuit are arranged along the first direction. The fourth anode in one of the anode groups is correspondingly arranged and electrically connected to the first pixel driving circuit. The second anode in the other anode group is correspondingly arranged and electrically connected to the second pixel driving circuit.

4. The display substrate according to claim 3, further comprising: A pixel defining layer, located on the side of the anode layer away from the substrate, includes multiple openings, comprising multiple opening groups. Each opening group includes a first opening, a second opening, a third opening, and a fourth opening. The first opening corresponds to and exposes the first anode, the second opening corresponds to and exposes the second anode, the third opening corresponds to and exposes the third anode, and the fourth opening corresponds to and exposes the fourth anode. The first anode includes a first main body and a first connecting portion. The orthographic projection of the first opening on the substrate falls into the orthographic projection of the first main body on the substrate. The first connecting portion is connected to the pixel driving circuit corresponding to the first anode. The second anode includes a second main body and a second connecting portion. The orthographic projection of the second opening on the substrate falls on the orthographic projection of the second main body on the substrate. The second connecting portion is connected to the pixel driving circuit corresponding to the second anode. The third anode includes a third main body and a third connecting part. The orthographic projection of the third opening on the substrate falls into the orthographic projection of the third main body on the substrate. The third connecting part is connected to the pixel driving circuit corresponding to the third anode. The fourth anode includes a fourth main body and a fourth connecting part. The orthographic projection of the fourth opening on the substrate falls into the orthographic projection of the fourth main body on the substrate. The fourth connecting part is connected to the pixel driving circuit corresponding to the fourth anode.

5. The display substrate according to claim 4, wherein the fourth anode further includes a first supplementary portion. in, The first channel region and the second channel region of the functional thin-film transistor in the first pixel driving circuit corresponding to the fourth anode have their orthographic projections on the substrate overlapping with the orthographic projections of the first supplementary portion on the substrate, respectively.

6. The display substrate according to claim 5, wherein, The first supplementary portion protrudes from the fourth main body portion toward the third anode portion, and the first supplementary portion is located on the side of the fourth connecting portion near the fourth main body portion.

7. The display substrate according to claim 5, wherein, The first supplementary part is connected to both the fourth main body part and the fourth connecting part.

8. The display substrate according to claim 5, wherein, The fourth anode also includes a second supplementary part. In this case, the orthographic projection of the second channel region of the functional thin-film transistor in the second pixel driving circuit onto the substrate overlaps with the orthographic projection of the second supplementary portion onto the substrate.

9. The display substrate according to claim 8, wherein, The second supplementary portion protrudes from the fourth main body portion toward the first anode in the adjacent anode group in the first direction.

10. The display substrate according to any one of claims 5-9, wherein, The common electrode of the functional thin-film transistor in the first pixel driving circuit overlaps with the orthographic projection of the first supplementary portion on the substrate, and the orthographic projection of the common electrode of the functional thin-film transistor in the second pixel driving circuit on the substrate overlaps with the orthographic projection of the fourth main body portion of the fourth anode corresponding to the first pixel driving circuit on the substrate.

11. The display substrate according to any one of claims 4-8, wherein, The orthographic projection of the channel region of the functional thin-film transistor in the pixel driving circuit corresponding to the first anode onto the substrate falls onto the orthographic projection of the first main body onto the substrate.

12. The display substrate according to any one of claims 4-8, wherein, The pixel driving circuit further includes a driving thin-film transistor, the gate of which is connected to the drain of the functional thin-film transistor. The first anode further includes a third supplementary portion that protrudes from the first main body portion toward the third anode. The gate of the driving thin-film transistor in the pixel driving circuit corresponding to the first anode and the drain of the functional thin-film transistor are projected onto the substrate and fall into the projection of the third supplementary portion onto the substrate.

13. The display substrate according to any one of claims 4-8, wherein, The first channel region of the functional thin-film transistor in the pixel driving circuit corresponding to the third anode is projected onto the substrate and falls onto the third main body portion.

14. The display substrate according to any one of claims 3-8, wherein, The third anode further includes a fourth supplementary portion, wherein the second channel region of the functional thin-film transistor in the pixel driving circuit corresponding to the third anode is projected onto the substrate and falls onto the fourth supplementary portion on the substrate.

15. The display substrate according to any one of claims 3-8, wherein, The adjacent anode groups are staggered by 1 / 2 pitch, where the pitch is equal to the distance between the centers of the two first anodes in the two adjacent anode groups in the first direction. In one of the anode groups, the second anode and the third anode are arranged along the second direction to form an anode pair, and the first anode, the anode pair, and the fourth anode are arranged along the second direction.

16. The display substrate according to any one of claims 3-8, wherein, The pixel circuit layer further includes: A semiconductor layer is located on the substrate; and The first gate layer is located on the side of the semiconductor layer away from the substrate. The semiconductor layer includes multiple pixel driving units, each corresponding to one of the multiple anodes. Each pixel driving unit includes a first unit, a second unit, a third unit, a fourth unit, a fifth unit, a sixth unit, and a seventh unit. The first unit includes a first channel region and a first source region and a first drain region located on both sides of the first channel region. The second unit includes a second channel region and a second source region and a second drain region located on both sides of the second channel region. The third unit includes a third channel region and a third source region and a third drain region located on both sides of the third channel region. The fourth unit includes a fourth channel region and a fourth source region and a fourth drain region located on both sides of the fourth channel region. The fifth unit includes a fifth channel region and a fifth source region and a fifth drain region located on both sides of the fifth channel region. The sixth unit includes a sixth channel region and a sixth source region and a sixth drain region located on both sides of the sixth channel region. The seventh unit includes a seventh channel region and a seventh source region and a seventh drain region located on both sides of the seventh channel region. The third source region, the first drain region, and the fifth source region are connected to the first node; the sixth drain region is connected to the third drain region; the first source region, the second drain region, and the fourth drain region are connected to the second node; and the fifth drain region is connected to the seventh drain region. The first gate layer includes a reset signal line, a gate line, a first electrode block, and a third gate line. The reset signal line overlaps with the seventh channel region and the sixth channel region to form a seventh thin-film transistor and a sixth thin-film transistor with the seventh unit and the sixth unit, respectively. The gate line overlaps with the third channel region and the second channel region to form a third thin-film transistor and a second thin-film transistor with the third unit and the second unit, respectively. The first electrode block overlaps with the first channel region to form a first thin-film transistor with the first unit. The third gate line overlaps with the fourth channel region and the fifth channel region to form a fourth thin-film transistor and a fifth thin-film transistor with the fourth unit and the fifth unit, respectively. The third thin-film transistor is the functional thin-film transistor.

17. The display substrate according to claim 16, wherein, The reset signal line, the gate line, and the third gate line all extend along the first direction, and the reset signal line, the gate line, the first electrode block, and the third gate line are arranged along the second direction.

18. The display substrate according to claim 16, wherein, The pixel circuit layer further includes: The second gate layer is located on the side of the first gate layer away from the semiconductor layer; The second gate layer includes an initialization signal line and a second electrode block. The initialization signal line is connected to the seventh source region and the sixth source region. The orthographic projection of the second electrode block on the substrate at least partially overlaps with the orthographic projection of the first electrode block on the substrate to form a storage capacitor.

19. The display substrate according to claim 18, wherein, The first conductive layer is located on the side of the second gate layer away from the first gate layer. The first conductive layer includes a data line and a power line, the second source region is connected to the data line, and the fourth source region is connected to the power line.

20. The display substrate according to any one of claims 4-8, further comprising: A light-emitting layer is located on the side of the anode layer away from the substrate and includes multiple light-emitting portions. These multiple light-emitting portions include multiple light-emitting groups, and each light-emitting group includes a first light-emitting portion, a second light-emitting portion, a third light-emitting portion, and a fourth light-emitting portion. The first light-emitting part is at least partially located in the first opening and covers the exposed first anode; the second light-emitting part is at least partially located in the second opening and covers the exposed second anode; the third light-emitting part is at least partially located in the third opening and covers the exposed third anode; and the fourth light-emitting part is at least partially located in the fourth opening and covers the exposed fourth anode. The first light-emitting part is configured to emit light of a first color, the second and third light-emitting parts are configured to emit light of a second color, and the fourth light-emitting part is configured to emit light of a third color.

21. The display substrate according to claim 20, wherein, The first color is red, the second color is green, and the third color is blue.

22. The display substrate according to any one of claims 3-8, wherein, The first direction and the second direction are approximately perpendicular.

23. A display device comprising a display substrate according to any one of claims 1-22.

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