Digital signal processing circuit and corresponding operation method

Abstract

Embodiments of the present disclosure relate to digital signal processing circuits and corresponding operation methods. An embodiment circuit includes: a plurality of processing units; a plurality of data memory banks configured to store data; and a plurality of coefficient memory banks configured to store rotation factors for fast Fourier transform processing. The processing unit is configured to extract input data from the data memory bank using a burst read memory transaction at each FFT calculation stage in the FFT calculation stage; extract different rotation factors from the corresponding sets of rotation factors from different coefficient memory banks in the coefficient memory bank at each FFT calculation cycle in the FFT calculation cycle; process the input data and the set of rotation factors to generate output data; and store the output data in the data memory bank using a burst write memory transaction at each FFT calculation stage in the FFT calculation stage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Italian Application No. 102020000016393, filed on July 7, 2020, which is incorporated herein by reference. Technical Field

[0003] The description relates to digital signal processing circuits, such as Fast Fourier Transform (FFT) processors, and associated methods. Background Art

[0004] Modern broadband communication systems based on Orthogonal Frequency Division Multiplexing (OFDM), such as Digital Video Broadcasting (DVB) and Digital Audio Broadcasting (DAB), or modern radar systems, as increasingly used in the automotive industry, for example, are exemplary processing systems involving the calculation of Fast Fourier Transforms (FFTs), the length (or size) of which can reach 8192 points, or even more.

[0005] The calculation of the fast Fourier transform can be performed by a hardware-implemented FFT processor. The FFT processor may include one or more processing elements (PEs) (e.g., a radix-2 butterfly processing element) and one or more read-only memories (ROMs). The read-only memory in the FFT processor may be configured to store rotation factors for the fast Fourier transform calculation.

[0006] In case of long FFT algorithms involving a large number of different twiddle factors, the ROM memory may represent a significant portion (eg in terms of occupied silicon area) of the entire FFT processor.

[0007] ROM memories may represent a significant part of an FFT processor, especially if the FFT processor relies on the use of parallel computing, ie if the FFT processor comprises a plurality of processing elements and a corresponding plurality of ROM memories coupled thereto.

[0008] The twiddle factors are typically stored (eg, hardwired) in ROM memory and retrieved by a ROM address generator (RAG) implemented inside the processing element to perform the butterfly multiplication. The ROM address generator can provide the memory address where the required twiddle factors are stored.

[0009] If multiple processing elements are used in the FFT processor for parallel computation, multiple ROM lookup tables may be provided in the FFT processor (e.g., one dedicated ROM memory for each processing element) in order to avoid memory access conflicts when the processing elements access the ROM memory to extract the twiddle factors.

[0010] Alternatively, a complex conflict-free access scheme can be implemented, for example, as disclosed by P. Jui, C. Wey, and M. Shiue, “Low-cost parallel FFT processors with conflict-free ROM-based twiddle factor generator for DVB-T2 applications,” 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, Ohio, 2013, pp. 1003-1006, doi:10.1109 / MWSCAS.2013.6674821. Summary of the invention

[0011] One or more embodiments are directed to providing an FFT processor having an efficient architecture for twiddle factor index generation (eg, twiddle factor storage and extraction), for example in terms of tradeoff between silicon area usage and performance. One or more embodiments may be directed to a corresponding method of operating a circuit.

[0012] One or more embodiments may rely on an advantageous scheme for storing twiddle factors in ROM memory that may avoid memory access conflicts while facilitating reducing the dimensions of the ROM memory.

[0013] One or more embodiments may provide a corresponding ROM address generator that cooperates with the ROM controller circuitry for extracting the twiddle factors from the ROM memory.

[0014] According to one or more embodiments, a circuit is provided, which may include multiple processing units, the multiple processing units including: P processing units; multiple data memory banks configured to store data; and multiple coefficient memory banks configured to store rotation factors for fast Fourier transform (FFT) processing. The multiple coefficient memory banks may include P coefficient memory banks equal to the P processing units.

[0015] The circuit may be configured to process a fast Fourier transform having size N with N=2 n The form of is applied to the data stored in the data memory bank, where n is an integer. Applying the fast Fourier transform processing with size N may include processing the data in a plurality of FFT calculation stages including n FFT calculation stages. Each FFT calculation stage may include a plurality of FFT calculation cycles.

[0016] The processing unit may be configured to extract input data from a data memory repository using a burst read memory transaction (e.g., at each FFT calculation stage in an FFT calculation stage); extract a corresponding set of rotation factors from a coefficient memory repository (e.g., at each FFT calculation cycle in an FFT calculation cycle); process the input data and the set of rotation factors to generate output data; and store the output data in the data memory repository using a burst write memory transaction (e.g., at each FFT calculation stage in an FFT calculation stage).

[0017] The processing unit may be configured to extract different twiddle factors of the respective set of twiddle factors from different coefficient memory banks at each of the FFT calculation cycles.

[0018] One or more embodiments may therefore provide efficient twiddle factor index generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are now described, by way of example only, with reference to the accompanying drawings, in which:

[0020] Figure 1 is an exemplary circuit block diagram of a fast Fourier transform processor circuit according to one or more embodiments of the present specification;

[0021] Figure 2 is an exemplary circuit block diagram of a ROM controller circuit according to one or more embodiments of the present specification;

[0022] Figure 3 is an exemplary flow chart of a process for calculating twiddle factor indices for FFT processing; and

[0023] Figure 4 is an exemplary circuit block diagram of a ROM address generator circuit according to one or more embodiments of the present description. DETAILED DESCRIPTION

[0024] In the following description, one or more specific details are illustrated to provide a deeper understanding of the examples of embodiments of the present specification. The embodiments can be obtained without one or more of the specific details or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that some aspects of the embodiments are not obscured.

[0025] References to "an embodiment" or "an embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in an embodiment" that may be present in one or more points of this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or features may be combined in any suitable manner.

[0026] The headings / references used herein are provided for convenience only and therefore do not limit the scope of protection or the embodiments.

[0027] Figure 1 is an exemplary circuit block diagram of the architecture of a parallel memory based fast Fourier transform (PMBFFT) processor 10 .

[0028] like Figure 1 The parallel memory-based FFT processor 10 illustrated in the figure is suitable for being integrated in an electronic system (such as a system on a chip (SoC)) for use in a vehicle (such as an automobile), for example, to process digital signals collected by one or more sensors (such as a radar sensor) provided in the vehicle.

[0029] like Figure 1 As shown in FIG. 1 , the parallel memory-based FFT processor 10 includes a plurality of (eg, P) processing elements 1000, 1001, . . . , 100 P-1 (e.g., radix-2 butterfly processing element), a plurality of (e.g., Q=2*P) local data memory banks M0, ..., M Q-1 and a plurality of (eg, P) local read-only memory libraries 1050, 1051, ..., 105 P-1 .

[0030] For simplicity, throughout this specification:

[0031] Reference numeral 100 may be used to collectively refer to processing elements 1000, 1001, ..., 100 P-1 ,

[0032] Reference numeral 105 may be used to collectively refer to local read-only memory libraries 1050, 1051, ..., 105 P-1 ,

[0033] Reference numeral M may be used to collectively refer to local data storage libraries M0, . . . , M Q-1 ,as well as

[0034] Terms such as "FFT length," "transform length," "FFT size" are used to specify the size of the FFT transform (eg, 4096 points, 8192 points, or even more).

[0035] Additionally:

[0036] Throughout all the drawings attached herein, similar parts or elements are indicated by similar symbols / numerals, and the corresponding descriptions will not be repeated for the sake of brevity.

[0037] To avoid cluttering the description, the various tables numbered I to VIII referenced in the description are grouped at the end of the description.

[0038] like Figure 1 As shown in FIG. 1 , the parallel memory-based FFT processor 10 may include a local control unit 101 , a local data memory controller 103 coupled to a local data memory bank M, and a local ROM controller 104 coupled to a local read-only memory bank 105 .

[0039] A local interconnect network 102 may be provided to couple the local control unit 101 , the processing element 100 , and the local data memory controller 103 .

[0040] The local interconnect network 102 may also provide a connection to a system control unit (e.g., a microprocessor unit or a microcontroller unit), not visible in the figures attached herein. The system control unit may be used to configure the FFT processor 10 and may trigger the start of the FFT algorithm calculation. Additionally, the connection to the system control unit may be used to upload data to a local data memory bank M.

[0041] Different embodiments may include a different P number of processing elements 100 and local read-only memory banks 105 , and / or a different Q number of local data memory banks M. By way of non-limiting example only, P may be equal to eight, and Q may be equal to sixteen.

[0042] In one or more embodiments, processing element 100 includes corresponding internal direct memory access (DMA) controllers 1080, 1081, ..., 108 P-1 These internal direct memory access controllers (collectively designated by reference numeral 108 ) are configured to interface processing element 100 to local data memory bank M via local data memory controller 103 .

[0043] In one or more embodiments, local data memory controller 103 may be configured to arbitrate (eg, by processing element 100 ) access to local data memory bank M. As shown in FIG.

[0044] The processing element 100 as illustrated herein is configured to retrieve input data from the local data memory bank M via the corresponding DMA controller 108, as directed by the local control unit 101. The processing element may thus elaborate the retrieved input data to generate processed output data, wherein such elaboration involves the use of twiddle factors extracted from the ROM memory bank 105. The processing element is configured to write the processed output data into the local data memory bank M via the corresponding DMA controller 108.

[0045] In one or more embodiments, the local data memory controller 103 may convert incoming read / write transaction bursts (eg, AXI bursts) generated by the read / write DMA controller 108 into read / write memory access sequences according to a specified burst type, burst length, and memory access scheme.

[0046] In one or more embodiments, providing a set of local data memory banks M may facilitate parallel processing of data and reduce memory access conflicts.

[0047] Optionally, the local data memory bank M may be provided with buffering (e.g. double buffering), which may facilitate recovery of memory upload times (write operations) and / or download times (read operations). In particular, each local data memory bank may be replicated so that data may be read from one of the two memory banks (e.g. for processing), and (new) data may be stored in the other memory bank at the same time (e.g. for processing later). Thus, moving data may not negatively impact computing performance, as it may be shielded.

[0048] In one or more embodiments, the double buffering scheme of the local data memory bank M can be advantageously combined with data processing in a streaming mode or back-to-back (e.g., as applicable to a FFTN point processor configured to elaborate a continuous sequence of N data inputs).

[0049] In one or more embodiments, the local data memory bank M may include a memory bank with limited storage capacity (and therefore, limited silicon footprint). For example, each of the local data memory banks may have a storage capacity of at least (maxN) / Q, where maxN is the longest FFT that the hardware processor can handle. A typical value in an application involving a memory-based FFT processor may be N=4096 points, where, for example, each point is a floating point single precision complex number (real, imaginary) with a size of 64 bits (or 8 bytes), and P=8, thereby making Q=16, so that the storage capacity of each local data memory bank may be equal to (4096*8 bytes) / 16=2KB (KB=kilobytes).

[0050] In one or more embodiments, local read-only memory bank 105 accessible by processing element 100 via local ROM controller 104 is configured to store twiddle factors for FFT calculations.

[0051] In one or more embodiments, processing element 100 includes corresponding internal ROM address generator (RAG) circuits 1100, 1101, ..., 110 P-1 (collectively designated by reference numeral 110), these internal ROM address generator circuits are configured to interface processing element 100 to local ROM memory bank 105 via local ROM controller 104. Processing element 100 may be configured to retrieve input data (e.g., twiddle factors) from local ROM memory bank 105 to perform FFT processing.

[0052] In one or more embodiments, the local read-only memory is advantageously divided into P ROM memory banks 105 equal to the P number of processing elements 100 included in FFT processor 10. This may facilitate avoiding conflicts during parallel computations.

[0053] As expected, storage and / or retrieval of twiddle factors (TF) is a relevant aspect in parallel memory based FFT processor design, particularly where computations involving FFTs with large transform lengths (e.g., 4096 points, 8192 points, or more) are involved.

[0054] Therefore, one or more embodiments are directed to providing a hardware-implemented high-performance solution for a ROM-based twiddle factor generator circuit.

[0055] In one or more embodiments, radix-2 butterfly processing elements 100 may share local ROM controller 104 and the same ROM lookup tables divided into different banks (eg, where the number of ROM banks 105 is equal to the number of processing elements 100 ).

[0056] The burst-based FFT processing implemented by the internal DMA controller 108 of the processing element 100 and the ROM access scheme implemented by the local ROM controller 104 facilitate avoiding contention during FFT calculations and also reduce costs in terms of hardware resources.

[0057] Figure 1 The circuit architecture illustrated in (having only one ROM lookup table comprising N / 2 words equally divided into P different memory banks 105 (where each ROM memory bank stores a number of words equal to N / (2*P))) can improve processing throughput.

[0058] Table I attached to this specification is an exemplary possible value of the architecture parameters.

[0059] In one or more embodiments, data bursts may be received by internal read / write DMA controller 108 of processing element 100 according to a selected length N of the fast Fourier transform (e.g., length N may be software configurable, where the only constraint is that it is a power of 2, i.e., N=2). n According to the P processing elements in the parallel FFT processor 10 and the selected length N, the burst length LENGTH and the stride STRIDE at each FFT calculation stage can be defined, as illustrated in Table II attached to this specification.

[0060] For example, as illustrated in Table II, for all stages of the FFT calculation, the value LENGTH of the burst length can be equal to N / (2*P). Also as illustrated in Table II, the value STRIDE of the burst stride can be equal to P in the first calculation stage (e.g., stage 0) and can be right shifted in each subsequent calculation stage. For example, in the second calculation stage (e.g., stage 1), the value STRIDE can be equal to P>>1 (i.e., the value P is shifted right by one position), and in the last calculation stage (e.g., stage n-1), the value STRIDE can be equal to P>>n-1 (i.e., the value P is shifted right by n-1 positions, which returns the value 2*P because the value STRIDE is stored in an n-bit circular right shift register).

[0061] The control and programming of the DMA controller 108 can be handled by the local control unit 101, for example using a simple circular right shift register (for example, to control the burst stride, a circular right shift register on n bits can be used) (which simple circular right shift register can be initialized (only) at the beginning of the FFT calculation) according to the selected length N and then updated at the beginning of each calculation phase.

[0062] Table II attached to this specification is also an example of how the read / write bursts may be programmed at each FFT stage for each instantiated processing element 100 (PE#i) when a Fast Fourier Transform of length N is calculated.

[0063] In one or more embodiments, employing a burst-based data processing scheme for FFT computation facilitates implementing a simple ROM-based twiddle factor generator (eg, managing ROM bank address generation and ROM handling), which facilitates when P=2 p The radix-2 butterfly units or processing elements are used in parallel for computing length N=2 n Avoid memory access conflicts when performing FFT.

[0064] One or more embodiments may thus provide significant hardware simplifications relative to known solutions (e.g., in terms of ROM address generation and access schemes). Additionally, one or more embodiments may rely on a simple ROM lookup table using only N / 2 words, which are equally divided into P sub-tables.

[0065] Italian patent application 102020000009364 filed by the same applicant (and not yet available to the public at the time of filing the present application) discloses an efficient way to extend a standard bus to support vector access with programmable stride and a memory access scheme to a local memory bank M, and how this solution can be used to implement a high-performance parallel memory-based FFT processor.

[0066] It should be noted that organizing data memory accesses in a single burst for each radix-2 processing element input / output during each FFT stage in the manner illustrated in Table II facilitates defining a simple and efficient architectural scheme for the twiddle factor generator.

[0067] For example, Tables III, IV, and V attached to this specification are exemplary rotation factors Wi that each processing element 100 retrieves from the ROM memory bank 105 at various stages and cycles of FFT calculations when a burst-based scheme as illustrated in Table II is used by the DMA controller 108 to access data stored in the memory bank M, wherein:

[0068]

[0069] Equation (1) above allows calculation of the values ​​of the rotation factors Wi to be stored in the ROM memory bank 105 (where the index i is in the range of 0 to N / 2-1, e.g., in the exemplary case of N=64 in the range of 0 to 31). Equation (2) above is an exemplary general discrete Fourier transform (DFT) equation.

[0070] By way of non-limiting example only:

[0071] Table III indicates the twiddle factors Wi that each processing element (PE) retrieves from the ROM memory bank 105 at various stages and cycles of the FFT calculation, in the case of N=64 and P=8,

[0072] Table IV indicates the twiddle factors Wi that each processing element (PE) retrieves from the ROM memory bank 105 at various stages and cycles of the FFT calculation in the case of N=32 and P=8, and

[0073] Table V indicates the twiddle factors Wi that each processing element (PE) fetches from the ROM memory bank 105 at various stages and cycles of the FFT calculation in the case of N=32 and P=4.

[0074] It should be noted that the twiddle factors listed in the same row of any of Tables III, IV and V are retrieved by the processing element in the same clock cycle. Therefore, if the indices i of these twiddle factors are different, they can be advantageously stored in different ROM memory banks.

[0075] In one or more embodiments, using a burst-based data processing solution may facilitate managing ROM memory conflicts.

[0076] One or more embodiments may rely on the recognition that storing the N / 2 rotation factors in the ROM memory bank 105 in a manner that avoids conflicts in the first FFT calculation phase (e.g., phase 0) may result in conflicts being avoided in all subsequent FFT calculation phases. In fact, the rotation factors involved during the cycles of the calculation phases after the first calculation phase (i.e., the calculation phases with indices greater than 0, e.g., phase 1 to phase n-1) may be selected as a subset of the rotation factors that are read from the ROM memory bank 105 during the cycles of the first calculation phase (e.g., phase 0), as illustrated in Tables III, IV, and V.

[0077] In one or more embodiments, storing the N / 2 rotation factors in the ROM memory bank 105 in a manner that avoids conflicts in the first FFT calculation stage can rely on a low-order or standard interleaving scheme, such as disclosed by GS Sohi in "High-bandwidth interleaved memories for vector processors-A simulation study", IEEE Transactions on Computers, Vol. 42, No. 1, pp. 34-44, January 1993, doi:10.1109 / 12.192212.

[0078] For example, Table VI attached to this specification is an example possible scheme for storing the rotation factors Wi in P different ROM memory banks 105 in a way that avoids conflicts in the first FFT calculation stage. It should be noted that each ROM memory bank 105 i(where index i ranges from 0 to P-1) may include a number of rows equal to N / (2*P). The row numbered j of the ROM memory bank numbered i (where index j ranges from 0 to N / (2*P)-1) may be configured to store a rotation factor with index i+jP. Thus, in the universal ROM memory bank numbered i, the first row with index j=0 may store the rotation factor Wi, the middle row with universal index j may store the rotation factor Wi+jP, and the last row with index j=N / (2*P)-1 may store the rotation factor Wi+(N / 2)-P.

[0079] Therefore, the N / 2 rotation factors (labeled from W0 to W(N / 2-1)) can be stored in the ROM memory bank 105 without duplication, while allowing access conflicts to be avoided. According to the storage scheme described above, even in the case of parallel FFT calculations, a single instance of each rotation factor Wi can be stored in the ROM memory bank 105 without jeopardizing the possibility of accessing the rotation factor without conflict, within the range that a conflict may (only) occur when two different processing elements 100 request access to two rotation factors with different indices stored in the same ROM memory bank 105 in the same clock cycle.

[0080] Two (or more) different processing elements attempting to access the same twiddle factor in the same clock cycle do not generate a conflict as long as the ROM controller 104 can be configured to merge two (or more) incoming requests for access to the same twiddle factor by two (or more) different processing elements into a single ROM access and deliver the read value back to the requesting processing element within range.

[0081] Figure 2 is an example circuit block diagram of the internal architecture of the ROM controller 104 according to one or more embodiments.

[0082] like Figure 2 As illustrated in FIG. 1 , the ROM controller 104 may include P ports 2000, 2001, . . . , 200 P-2 , 200 P-1 (collectively designated by reference numeral 200), these ports are configured to be coupled to corresponding P RAG circuits 110 provided in the processing element 100. The ports 200 may be coupled to corresponding dispatcher circuits 2020, 2021, ..., 202 P-2 , 202 P-1 (collectively designated by reference numeral 202). ROM controller 104 may additionally include P merging stages 2040, 2041, ..., 204 P-2 , 204 P-1(collectively designated by reference numeral 204). The dispatcher circuits 202 and the merging stages 204 may be fully connected, i.e., each dispatcher circuit 202 may be connected to all merging stages 204, such as Figure 2 exemplified in .

[0083] In one or more embodiments, dispatcher circuit 202 may be configured to implement a low-order interleaving scheme.

[0084] In one or more embodiments, merge stage 204 may be configured to merge two (or more) incoming requests for access to the same twiddle factor by two (or more) different processing elements into a single ROM memory access.

[0085] In one or more embodiments, where a burst-based scheme as illustrated in Table II is employed, the indices of the rotation factors retrieved by each processing element 100 during FFT computation may be based on Figure 3 Such a process may be run, for example, by the local control unit 101 in coordination with the RAG circuit 110 .

[0086] At step 300, calculation of twiddle factor indices may begin.

[0087] The following step 302 may include checking whether the current value of the variable stage (which is initialized to zero and counts to n-1, where n=log2N and N is the length of the calculated FFT algorithm) is lower than or equal to a value p, where p=log2P and P is the number of processing elements 100 in the FFT processor (e.g., where the constraint is a power of 2).

[0088] As a result of a positive outcome (Y) of step 302, the next step 304 may include dividing the number i (which identifies the processing element 100 currently under consideration, where i ranges from 0 to P-1) by the number 2 stage And check if the remainder of the division is equal to zero.

[0089] As a result of a positive result (Y) of step 304, the next step 306 may include indexing the i =i+period*P calculates the index of the rotation factor currently required by processing element i (i.e., at a certain cycle of a certain stage of FFT calculation), where period is a variable initialized to zero at the beginning of each FFT stage and counts to N / (2P)-1.

[0090] As a result of a negative result (N) of step 304, the next step 308 may include indexing i =Index i-1The index of the rotation factor currently required by processing element i (ie, in a certain cycle of a certain stage of FFT calculation) is calculated, that is, the processing element numbered i may need the rotation factor required by the processing element numbered i-1.

[0091] As a result of a negative result (N) of step 302, the next step 310 may include dividing the digital period by the number 2. stage-p And check if the remainder of the division is equal to zero.

[0092] As a result of a positive result (Y) of step 310, the next step 312 may include indexing the i = cycle * P calculates the index of the twiddle factor currently required by processing element i. In other words, all processing elements 100 can access the same twiddle factor simultaneously, where the index of the twiddle factor depends (only) on the current cycle and the number P of processing elements.

[0093] As a result of a negative outcome (N) of step 310, the following step 314 may include calculating the indices of the twiddle factors currently required by all processing elements by retaining the same indices calculated in the previous calculation cycle.

[0094] At step 316, the calculation of the twiddle factor indices may end.

[0095] Figure 3 The process illustrated in (blocks 300 to 316) may be repeated at each cycle of each stage of the FFT calculation.

[0096] In one or more embodiments, Figure 3 The process illustrated in FIG. 1 may be implemented in hardware by the RAG circuit 110 of the processing element 100 , driven by control signals provided by the local control unit 101 .

[0097] Figure 4 1 is an example circuit block diagram of a possible implementation of the RAG circuit 110 according to one or more embodiments. The RAG circuit 110 may be ideally configured from a first RAG circuit having an index i=0 included in the first processing element 1000 to a RAG circuit having an index i=0 included in the last processing element 1000. P-1 The last RAG circuit with index i=P-1 included in is sorted.

[0098] Each RAG circuit 110 may include a respective multiplexer circuit 40 and a respective configurable power-of-two counter circuit 42 coupled at an output of the multiplexer circuit. Each counter circuit 42 may be configured to output a twiddle factor index required by a respective processing element at a particular stage and cycle of FFT processing, wherein such twiddle factor index is passed to a respective port 200 of the ROM controller circuit 104.

[0099] Each multiplexer circuit 40 includes a first input configured to receive (e.g., when the corresponding select signal is equal to 1) a value provided at the output of a previous multiplexer circuit in the ordered sequence of multiplexer circuits (e.g., to implement a daisy-chain connection); and a second input configured to receive (e.g., when the corresponding select signal is equal to 0) a binary value corresponding to the position of the multiplexer circuit in the ordered sequence (i.e., from 0 for the first multiplexer circuit 400 to 1 for the last multiplexer circuit 400). P-1 Starting from P-1).

[0100] Each multiplexer circuit 40 is controlled by bits S0, . . . , S0 of the selection signal S provided by the local control unit 101. p-1 control (e.g., where S0 is the least significant bit and S p-1 is the most significant bit). The selection signal S may therefore be a signal comprising a number p=log2P of bits.

[0101] In particular, a multiplexer circuit 40 with an index i (where i ranges from 0 to P-1) may be configured to receive the jth bit S of the select signal j , the condition is the division i / 2 j The remainder is zero, and j is the largest integer that satisfies the condition. Table VII and Table VIII attached to this specification are respectively the bits of the selection signal S and the corresponding sequential multiplexer circuits 400, 401, ..., 40 P-2 , 40 P-1 The examples may be relevant.

[0102] In one or more embodiments, the first multiplexer circuit 400 may be configured to receive a fixed selection signal (e.g., 0) such that the input of the first multiplexer circuit 400 is fixed at a value of zero. Alternatively, the first RAG circuit 1100 may not be provided with a corresponding multiplexer circuit, and a zero value may be provided directly at the input of the corresponding counter circuit 420. It should be noted that providing the first multiplexer circuit 400 with a fixed selection signal may be advantageous, as the multiplexer circuit 40 may be present by default in the instantiated RAG circuit 110 and thus also in the first processing element 1000.

[0103] Each configurable power-of-two counter 42 can receive an enable signal EN from the local control unit 101 and a counter according to, for example, Formula 2 xP determines the configuration signal x of the offset of the power-of-2 counter. In one or more embodiments, when the counter enable signal EN is asserted (e.g., equal to 1), the new increment value is output by the counter circuit 42 and stored in the status register on the next clock cycle. At the active edge of the clock signal, the count register value is updated according to the previous value and the programmed offset.

[0104] Therefore, the RAG circuit 110 implemented in the processing element 100 may be configured to connect ports 2000 to 2000 of the ROM controller 104 according to the logic illustrated in Table III, IV, or V. P-1 A rotation factor request is generated at .

[0105] In addition to driving the configuration signal of the internal DMA controller 108, the internal control unit 101 of the FFT processor 10 is configured to drive the selection bits S0, . . . , S1, . . . for the RAG multiplexer circuit 40. p-1 and an enable signal EN and a configuration signal x for the counter circuit 42. The values ​​of such signals vary from one phase to another and / or from one cycle to another in order to implement Figure 3 The process illustrated in .

[0106] The following rules may be applied by the control unit 101 for generating the selection signal S:

[0107] The bits S0, ..., S of the selection signal S p-1 may be initially (eg, during a first FFT calculation phase) set to zero so that none of the multiplexer circuits in multiplexer circuit 40 are daisy-chained to one another,

[0108] Since the variable stage is lower than or equal to p (see e.g. Figure 3 304, 306 and 308 in step 306), so bits S0, ..., S0 of signal S are selected. p-1 can be updated at each stage of the FFT calculation by bitwise ORing the previous value of the selection signal S with the signal STAGE carrying a 1 at the bit whose index is equal to the previous stage value, and

[0109] Since the variable stage is higher than p, bits S0, ..., S of the selection signal S are p-1 can be set to 1 so that all multiplexer circuits 40 are daisy-chained.

[0110] Merely by way of example, considering a three-bit select signal S and a three-bit signal STAGE, since the variable stage is lower than or equal to p, the select signal S can be generated as follows:

[0111] If stage=0→then S=000;

[0112] If stage=1→then STAGE=001, S=000OR 001=001;

[0113] If stage=2→then STAGE=010, S=001OR 010=011;

[0114] If stage=3→then STAGE=100, S=011OR 100=111.

[0115] The following rules may be applied by the control unit 101 for generating the counter enable signal EN and the counter configuration signal x:

[0116] Since the variable stage is lower than or equal to p (see e.g. Figure 3 ), so the enable signal EN may be asserted (eg, EN=1) and the configuration signal x may be equal to zero,

[0117] Since the variable stage is higher than p and the division period is / 2 stage-p The remainder is equal to zero (see e.g. Figure 3 ), so the enable signal EN can be asserted (eg, EN=1) and the configuration signal x can be equal to stage-p, and

[0118] Since the variable stage is higher than p and the division period is / 2 stage-p The remainder is not equal to zero (see for example Figure 3 ), so the enable signal EN may be de-asserted (eg, EN=0) and the configuration signal x may be equal to stage-p.

[0119] Thus, one or more embodiments may improve the storage and retrieval of twiddle factors in the ROM memory 105 of the FFT hardware processor. In one or more embodiments, the ROM memory may have a depth of only N / 2 words, which are equally divided into P banks for use with a parallel memory based FFT processor and may facilitate avoiding data collisions during FFT calculations.

[0120] One or more embodiments may support a variable FFT length N. For example, the hardware FFT processor 10 may be designed to support a certain maximum FFT length (eg, N=8192 points), where a shorter length may be selected by software.

[0121] As illustrated herein, a circuit (eg, 10) (eg, a digital signal processor) may include: a plurality of processing units (eg, 1000, . . . , 100 P-1), including P processing units (e.g., radix-2 butterfly processing units); multiple data memory banks (e.g., M0, ..., M Q-1 ), configured to store data; and a plurality of coefficient memory banks (e.g., 1050, ..., 105 P-1 ), configured to store rotation factors for Fast Fourier Transform (FFT) processing (e.g., a read-only memory bank). The plurality of coefficient memory banks may include P coefficient memory banks equal to the P processing units.

[0122] As illustrated herein, the circuit may be configured to process a Fast Fourier Transform of size N with N=2 n The form of is applied to data stored in a data memory library, where n is an integer, and applying a fast Fourier transform processing having a size N may include processing the data in a plurality of FFT calculation stages including n FFT calculation stages, wherein each FFT calculation stage includes a plurality of FFT calculation cycles.

[0123] As exemplified herein, a processing unit may be configured to:

[0124] At each of the FFT calculation stages, input data is fetched (e.g., 108, 103) from a data memory bank using a burst read memory transaction,

[0125] At each of the FFT calculation cycles, a corresponding set of twiddle factors is extracted (e.g., 110, 104) from a coefficient memory bank,

[0126] Processing the set of input data and twiddle factors to generate output data, and

[0127] At each of the FFT calculation stages, the output data is stored (eg, 108, 103) into a data memory bank using a burst write memory transaction.

[0128] As illustrated herein, the processing unit may be configured to extract different twiddle factors of the corresponding set of twiddle factors from different coefficient memory banks at each of the FFT computation cycles.

[0129] As illustrated herein, each of the processing units may include a corresponding coefficient index generation circuit (eg, 1100, ..., 110 P-1 ), the coefficient index generation circuit is configured to generate a corresponding index of the rotation factor used by the corresponding processing unit according to the current FFT calculation stage and the current FFT calculation cycle.

[0130] As illustrated herein, the circuitry may include a coefficient memory controller (eg, 104) configured to interface the coefficient index generation circuitry to a coefficient memory bank.

[0131] As exemplified herein, a coefficient memory controller may include:

[0132] Multiple communication ports (e.g. 2000, ..., 200 P-1 ), comprising P communication ports, each of which is coupled to a coefficient index generation circuit of a processing unit,

[0133] Multiple dispatcher circuits (e.g., 2020, ..., 202 P-1 ), comprising P dispatcher circuits equal to the P processing units, the dispatcher circuits being coupled to the communication ports, respectively, and

[0134] Multiple combiner circuits (e.g., 2040, ..., 204 P-1 ), comprising P combiner circuits equal to P processing units, the combiner circuits being respectively coupled to coefficient memory banks.

[0135] As illustrated herein, each of the dispatcher circuits may be coupled to all of the combiner circuits in the fully connected network.

[0136] As illustrated herein, the processing units may be from a first processing unit (eg, 1000) to a last processing unit (eg, 100 P-1 ) are arranged in an ordered sequence; each coefficient index generation circuit in the ordered sequence of processing units may include a corresponding multiplexer circuit (e.g., 400, ..., 40 P-1 ) and corresponding power-of-two counter circuits (e.g., 420, ..., 42 P-1 ), the power-of-2 counter circuit is configured to generate a corresponding index of a rotation factor used by a corresponding processing unit; and each of the multiplexer circuits may be configured to transmit, to the corresponding power-of-2 counter circuit, a signal selected from a signal output from a previous multiplexer circuit in the ordered sequence of multiplexer circuits or a signal indicating a position of a multiplexer circuit in the ordered sequence of multiplexer circuits (e.g., S0, ..., S1, ..., S2, ..., S3, ..., S4, ..., S5, ..., S6, ..., S7, ..., S8, ..., S9, ..., S10, ..., S11, ..., S12, ..., S13, ..., S14, ..., S15, ..., S16, ..., S17, ..., S18, ..., S19, ..., S21, ..., S22, ..., S23, ..., S24, ... p-1 ).

[0137] As illustrated herein, multiplexer circuits arranged in an ordered sequence may be selectively coupled in groups of daisy-chained multiplexer circuits, and the groups may have a cardinality according to the current FFT calculation stage.

[0138] As illustrated herein, the cardinality of the daisy-chain multiplexer circuit group may be equal to 2 stage, where stage is a progressive number indicating the current FFT calculation stage, wherein the first FFT calculation stage is identified by the number zero. As illustrated herein, the cardinality of the daisy-chain multiplexer circuit group may be limited to P processing units.

[0139] As illustrated herein, the corresponding power-of-two counter circuits may be configured to update the corresponding count register values ​​at each FFT calculation cycle. Updating the corresponding count register values ​​may include adding an offset value calculated as a function of the current FFT calculation cycle to the previously stored count register value.

[0140] As illustrated herein, the burst length of the burst read memory transaction and the burst write memory transaction may be equal to N / 2P, and the burst stride of the burst read memory transaction and the burst write memory transaction may be calculated as a function of P processing units at each FFT calculation stage.

[0141] As illustrated herein, each of the coefficient memory banks may include N / 2P rows, and the N / 2 rotation factors may be stored in the plurality of coefficient memory banks without duplication according to a low-order interleaving scheme or a standard interleaving scheme.

[0142] As illustrated herein, a row with index j of a coefficient memory bank with index i may have stored therein a rotation factor with index i+jP.

[0143] As illustrated herein, the plurality of data memory banks may include a plurality of data memory banks equal to twice the number of P processing units.

[0144] As illustrated herein, a method of operating a circuit according to one or more embodiments may include:

[0145] storing the rotation factors for Fast Fourier Transform (FFT) processing in a plurality of coefficient memory banks,

[0146] The Fast Fourier Transform with size N is processed with N=2 n , wherein n is an integer, wherein applying the fast Fourier transform process having a size N may include processing the data in a plurality of FFT calculation stages including n FFT calculation stages, wherein each FFT calculation stage may include a plurality of FFT calculation cycles,

[0147] At each of the FFT calculation stages, input data is extracted from the data memory bank using a burst read memory transaction,

[0148] At each of the FFT computation cycles, extracting a corresponding set of twiddle factors from the coefficient memory bank,

[0149] processing the set of input data and twiddle factors in a plurality of processing units to generate output data, and

[0150] At each of the FFT calculation stages, the output data is stored in the data memory bank using a burst write memory transaction.

[0151] As illustrated herein, extracting the twiddle factors may include extracting different twiddle factors of the corresponding set of twiddle factors from different coefficient memory banks at each of the FFT computation cycles.

[0152] Without affecting the underlying principle, the details and embodiments may vary, even significantly, with respect to those which have been described purely by way of example, without departing from the scope of protection.

[0153] The scope of protection is determined by the appended claims.

[0154] Table I

[0155]

[0156]

[0157] Table III N=64 (n=6), P=8 (p=3)

[0158]

[0159]

[0160] Table II

[0161]

[0162]

[0163] Table IV N=32 (n=5), P=8 (p=3)

[0164]

[0165] Table VN=32 (n=5), P=4 (p=2)

[0166]

[0167]

[0168] Table VI

[0169]

[0170] Table VII P = 8 (p = 3)

[0171]

[0172] Table VIII P=16 (p=4)

[0173]

Claims

1. A circuit comprising: a plurality of processing units, including P processing units, the processing units being arranged in an ordered sequence from a first processing unit to a last processing unit; a plurality of data storage libraries configured to store data; as well as A plurality of coefficient memory banks configured to store rotation factors for Fast Fourier Transform (FFT) processing, the plurality of coefficient memory banks comprising P coefficient memory banks equal to the P processing units; wherein the circuit is configured to process the FFT with size N to N=2 n , wherein n is an integer, and wherein applying the FFT processing having the size N comprises processing the data in a plurality of FFT calculation stages comprising n FFT calculation stages, wherein each FFT calculation stage comprises a plurality of FFT calculation cycles; The processing unit is configured as follows: At each of the FFT calculation stages, extracting input data from the data memory bank using a burst read memory transaction; At each of the FFT computation cycles, extracting different twiddle factors in the corresponding set of twiddle factors from different ones of the coefficient memory banks; Processing the input data and the set of twiddle factors to generate output data; as well as At each of the FFT calculation stages, storing the output data in the data memory repository using a burst write memory transaction; Each of the processing units comprises a respective coefficient index generation circuit configured to generate a respective index for a rotation factor used by the respective processing unit according to a current FFT calculation stage and a current FFT calculation cycle; The circuit includes a coefficient memory controller configured to interface the coefficient index generation circuit to the coefficient memory bank; each of said coefficient index generation circuits in said ordered sequence of processing units comprising a respective multiplexer circuit and a respective power-of-two counter circuit configured to generate a respective said index for said twiddle factor used by the respective said processing unit; Each of the multiplexer circuits is configured to pass a signal to the corresponding power-of-2 counter circuit based on the current FFT calculation stage and the current FFT calculation cycle, and the signal is selected from the following items: a first signal output from a previous multiplexer circuit in the ordered sequence of multiplexer circuits or a second signal indicating the position of the multiplexer circuit in the ordered sequence of multiplexer circuits.

2. The circuit of claim 1 , wherein the coefficient memory controller comprises: a plurality of communication ports, including P communication ports, the P communication ports being respectively coupled to the coefficient index generation circuit of the processing unit; a plurality of dispatcher circuits, including P dispatcher circuits equal to the P processing units, the dispatcher circuits being coupled to the communication ports, respectively; as well as a plurality of combiner circuits, including P combiner circuits equal to the P processing units, the combiner circuits being respectively coupled to the coefficient memory banks; Wherein each of the dispatcher circuits is coupled to all of the combiner circuits in the combiner circuits in a fully connected network.

3. The circuit of claim 1, wherein the multiplexer circuits arranged in the ordered sequence are selectively coupleable in a daisy-chained group of multiplexer circuits having a radix according to the current FFT calculation stage.

4. The circuit of claim 3, wherein the cardinality of the daisy-chain multiplexer circuit group is equal to 2. stage , wherein stage is a progressive number indicating the current FFT calculation stage, the first FFT calculation stage is identified by the number zero, and the cardinality of the daisy-chain multiplexer circuit group is limited to the P processing units.

5. The circuit of claim 1 , wherein the corresponding power-of-two counter circuit is configured to update the corresponding count register value at each FFT calculation cycle, wherein updating the corresponding count register value comprises adding an offset value to a previously stored count register value, the offset value being calculated based on the current FFT calculation cycle.

6. The circuit of claim 1 , wherein a burst length of the burst read memory transaction and the burst write memory transaction is equal to N / 2P, and a burst stride of the burst read memory transaction and the burst write memory transaction is calculated according to the P processing units at each FFT calculation stage.

7. The circuit of claim 1 , wherein each of the coefficient memory banks comprises N / 2P rows, and wherein N / 2 of the rotation factors are stored in the plurality of coefficient memory banks without duplication according to a low-order interleaving scheme or a standard interleaving scheme.

8. The circuit of claim 7, wherein the row with index j of the corresponding coefficient memory bank with index i has a twiddle factor with index i+jP stored therein.

9. The circuit of claim 1, wherein the plurality of data memory banks comprises a number of data memory banks equal to twice the number of the P processing units.

10. A method of operating a circuit, the method comprising: storing rotation factors for fast Fourier transform (FFT) processing in a plurality of coefficient memory banks; The FFT processing with size N is divided into N=2 n , wherein n is an integer, and wherein applying the FFT processing having the size N comprises processing the data in a plurality of FFT calculation stages comprising n FFT calculation stages, wherein each FFT calculation stage comprises a plurality of FFT calculation cycles; At each of the FFT calculation stages, extracting input data from the data memory bank using a burst read memory transaction; At each of the FFT computation cycles, extracting different twiddle factors in the corresponding set of twiddle factors from different ones of the coefficient memory banks; processing the input data and the set of twiddle factors in a plurality of processing units to generate output data; At each of the FFT calculation stages, storing the output data in the data memory repository using a burst write memory transaction; generating, by a corresponding coefficient index generation circuit, corresponding indices for rotation factors used by corresponding processing units according to a current FFT calculation stage and a current FFT calculation cycle; connecting the coefficient index generation circuit interface to the coefficient memory bank via a coefficient memory controller; wherein the processing units are arranged in an ordered sequence from a first processing unit to a last processing unit, and each of the processing units comprises a corresponding coefficient index generation circuit; Each of the coefficient index generation circuits in the ordered sequence of processing units comprises a respective multiplexer circuit and a respective power-of-two counter circuit, and the method further comprises: generating, by respective said power-of-two counter circuits, respective said indices for said twiddle factors for use by respective said processing units; as well as According to the current FFT calculation stage and the current FFT calculation cycle, a signal is transmitted to the corresponding power-of-2 counter circuit through each corresponding multiplexer circuit, and the signal is selected from the following items: a first signal output from a previous multiplexer circuit in the ordered sequence of multiplexer circuits or a second signal indicating the position of the multiplexer circuit in the ordered sequence of multiplexer circuits.

11. The method according to claim 10, further comprising: The multiplexer circuits arranged in the ordered sequence are selectively coupled in a daisy-chained group of multiplexer circuits having a radix according to the current FFT calculation stage.

12. The method of claim 11, wherein the cardinality of the daisy-chain multiplexer circuit group is equal to 2. stage , wherein stage is a progressive number indicating the current FFT calculation stage, the first FFT calculation stage is identified by the number zero, and the cardinality of the daisy-chain multiplexer circuit group is limited to P processing units.

13. The method according to claim 10, further comprising: The corresponding count register value is updated at each FFT calculation cycle by the corresponding power-of-2 counter circuit, and the updating of the corresponding count register value includes adding an offset value to a previously stored count register value, the offset value being calculated according to the current FFT calculation cycle.

14. The method of claim 10, wherein the burst lengths of the burst read memory transaction and the burst write memory transaction are equal to N / 2P, and the method further comprises: The burst strides of the burst read memory transaction and the burst write memory transaction are calculated at each FFT calculation stage according to the P processing units.

15. The method of claim 10, wherein each of the coefficient memory banks comprises N / 2P rows, and the method further comprises: The N / 2 rotation factors are stored in the plurality of coefficient memory banks without duplication according to a low-order interleaving scheme or a standard interleaving scheme.

16. The method of claim 15, wherein the row with index j of the corresponding coefficient memory bank with index i has a twiddle factor with index i+jP stored therein.

17. The method of claim 10, the plurality of data storage vaults comprising a number of data storage vaults equal to twice the number of P processing units.

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