Optimization method, device and thermal resistance network model of chip thermal resistance network model

Abstract

The present application relates to the technical field of thermal reliability of chip packaging, and discloses an optimization method, device and thermal resistance network model of a chip thermal resistance network model. The embodiment of the present application constructs a chip thermal resistance network model according to different surface node selection schemes, and compares the constructed chip thermal resistance network model with the chip three-dimensional simulation model for thermal simulation to obtain the chip junction temperature difference between the two, and selects the chip thermal resistance network model with the smallest chip junction temperature difference with the chip three-dimensional simulation model as the final optimized chip thermal resistance network model. The present application realizes the optimization modeling of the chip thermal resistance network model, and the constructed chip thermal resistance network model can be well equivalent to the chip three-dimensional simulation model, laying a good foundation for the subsequent accurate calculation of the chip junction temperature.

Description

Technical Field

[0001] The present application relates to the technical field of thermal reliability of chip packaging, and in particular to an optimization method and device for a chip thermal resistance network model and a thermal resistance network model. Background Art

[0002] The increase in chip power consumption causes the chip junction temperature to continue to rise, and the chip will fail due to overheating. Therefore, the prediction of chip junction temperature becomes increasingly important. In order to facilitate technicians to calculate the chip junction temperature under actual working environment, the relevant technology realizes the prediction of chip junction temperature by establishing a thermal resistance network model.

[0003] When establishing a thermal resistance network model, it is usually necessary to divide the surface of the chip three-dimensional simulation model into multiple areas, select a surface node that can represent the average temperature of the area at the surface position of each area, and connect each surface node to the chip node with a thermal resistor to form a corresponding network topology.

[0004] A variety of surface node selection schemes can be formed according to different surface area divisions. Currently, a surface node selection scheme is usually determined directly based on the chip manual, and the corresponding thermal resistance network model may not be able to better equate the detailed model of the chip.

[0005] Application Contents

[0006] To this end, the purpose of the embodiments of the present application is to provide an optimization method, device and thermal resistance network model of a chip thermal resistance network model, thereby realizing the optimized modeling of the chip thermal resistance network model. The constructed chip thermal resistance network model can be well equivalent to the chip three-dimensional simulation model, laying a good foundation for the subsequent accurate calculation of the chip junction temperature.

[0007] In order to achieve the above objectives, this application adopts the following technical solutions:

[0008] In a first aspect, the present application provides a method for optimizing a chip thermal resistance network model, the method comprising:

[0009] S1: Obtain all surface node selection schemes applicable to the chip three-dimensional simulation model;

[0010] S2: constructing a corresponding chip thermal resistance network model according to each of the surface node selection schemes, wherein the network topology of the chip thermal resistance network model is composed of chip nodes and surface nodes selected by the surface node selection scheme, and each surface node is connected to the chip node by a thermal resistor;

[0011] S3: performing thermal simulation comparison on each of the constructed chip thermal resistance network models and the chip three-dimensional simulation model to obtain a chip junction temperature difference between each of the chip thermal resistance network models and the chip three-dimensional simulation model;

[0012] S4: Outputting the chip thermal resistance network model corresponding to the minimum value of the chip junction temperature difference as the optimized chip thermal resistance network model.

[0013] According to an achievable manner of the first aspect of the present application, the obtaining of the chip junction temperature difference between each chip thermal resistance network model and the chip three-dimensional simulation model includes:

[0014] Setting multiple sets of boundary conditions corresponding to the working environment of the chip;

[0015] Calculate the difference between the chip junction temperature simulation values ​​of the chip thermal resistance network model and the chip three-dimensional simulation model under each set of boundary conditions;

[0016] The maximum value is selected from all calculated differences as the chip junction temperature difference between the chip thermal resistance network model and the chip three-dimensional simulation model.

[0017] According to an implementation method of the first aspect of the present application, the method further includes:

[0018] Establish a corresponding chip physical simulation model according to chip parameters;

[0019] Performing thermal simulation on the chip physical simulation model to obtain a junction-to-ring thermal resistance simulation value of the chip;

[0020] The junction-ring thermal resistance simulation value is compared with the junction-ring thermal resistance reference value. If the error between the two is less than a preset error threshold, the chip physical simulation model is used as the chip three-dimensional simulation model.

[0021] According to an achievable manner of the first aspect of the present application, the chip thermal resistance network model is a star thermal resistance model or a Delphi thermal resistance network model.

[0022] A second aspect of the present application provides a device for optimizing a chip thermal resistance network model, the device comprising:

[0023] An acquisition module is used to acquire all surface node selection schemes applicable to a chip three-dimensional simulation model;

[0024] A model building module, used for building a corresponding chip thermal resistance network model according to each of the surface node selection schemes, wherein the network topology of the chip thermal resistance network model is composed of chip nodes and surface nodes selected by the surface node selection scheme, and each surface node is connected to the chip node by a thermal resistor;

[0025] A simulation comparison module, used for performing thermal simulation comparison between each of the chip thermal resistance network models constructed and the chip three-dimensional simulation model, and obtaining a chip junction temperature difference between each of the chip thermal resistance network models and the chip three-dimensional simulation model;

[0026] The output module is used to output the chip thermal resistance network model corresponding to the minimum value of the chip junction temperature difference as the optimized chip thermal resistance network model.

[0027] According to an achievable manner of the second aspect of the present application, the simulation comparison module includes:

[0028] A setting unit, used to set multiple groups of boundary conditions corresponding to the working environment of the chip;

[0029] A calculation unit, used for calculating the difference between the chip junction temperature simulation values ​​of the chip thermal resistance network model and the chip three-dimensional simulation model under each set of boundary conditions;

[0030] The chip junction temperature difference determination unit is used to select a maximum value from all calculated differences as the chip junction temperature difference between the chip thermal resistance network model and the chip three-dimensional simulation model.

[0031] According to an implementation method of the second aspect of the present application, the device further includes:

[0032] A chip physical simulation model building module is used to build a corresponding chip physical simulation model according to chip parameters;

[0033] A thermal simulation module, used for performing thermal simulation on the chip physical simulation model to obtain a junction-to-ring thermal resistance simulation value of the chip;

[0034] The comparison and verification module is used to compare the junction-ring thermal resistance simulation value with the junction-ring thermal resistance reference value. If the error between the two is less than a preset error threshold, the chip physical simulation model is used as the chip three-dimensional simulation model.

[0035] According to an achievable manner of the second aspect of the present application, the chip thermal resistance network model is a star thermal resistance model or a Delphi thermal resistance network model.

[0036] A third aspect of the present application provides an optimization device for a chip thermal resistance network model, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, it implements the optimization method for the chip thermal resistance network model as described in any one of the above embodiments.

[0037] A fourth aspect of the present application provides a computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, and when the computer program is executed, the optimization method of the chip thermal resistance network model as described in any one of the above embodiments is implemented.

[0038] A fifth aspect of the present application provides a chip thermal resistance network model, which is obtained according to the chip thermal resistance network model optimization method described in any one of the above embodiments.

[0039] Compared with the prior art, this application has at least the following beneficial technical effects:

[0040] The embodiment of the present application constructs a chip thermal resistance network model according to different surface node selection schemes, and performs thermal simulation comparison on the constructed chip thermal resistance network model and the chip three-dimensional simulation model to obtain the chip junction temperature difference between the two, and selects the chip thermal resistance network model with the smallest chip junction temperature difference with the chip three-dimensional simulation model as the final optimized chip thermal resistance network model, thereby realizing the optimized modeling of the chip thermal resistance network model. The constructed chip thermal resistance network model can be well equivalent to the chip three-dimensional simulation model, laying a good foundation for the subsequent accurate calculation of the chip junction temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a flow chart of a preferred embodiment of a chip thermal resistance network model optimization method provided by the present application;

[0042] Figure 2 It is a structural schematic diagram of a preferred embodiment of the chip thermal resistance network model optimization device provided in the present application.

[0043] Reference numerals:

[0044] Acquisition module 1, model building module 2, simulation comparison module 3, output module 4. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] Figure 1 Shown is a flow chart of a preferred embodiment of a chip thermal resistance network model optimization method provided by the present application.

[0047] like Figure 1 As shown, the method includes:

[0048] S1: Obtain all surface node selection schemes applicable to the chip 3D simulation model;

[0049] S2: constructing a corresponding chip thermal resistance network model according to each of the surface node selection schemes, wherein the network topology of the chip thermal resistance network model is composed of chip nodes and surface nodes selected by the surface node selection scheme, and each surface node is connected to the chip node by a thermal resistor;

[0050] S3: performing thermal simulation comparison on each of the constructed chip thermal resistance network models and the chip three-dimensional simulation model to obtain a chip junction temperature difference between each of the chip thermal resistance network models and the chip three-dimensional simulation model;

[0051] S4: Outputting the chip thermal resistance network model corresponding to the minimum value of the chip junction temperature difference as the optimized chip thermal resistance network model.

[0052] Among them, all surface node selection schemes applicable to the chip three-dimensional simulation model refer to all surface node selection schemes that can be used to construct the chip thermal resistance network model corresponding to the chip three-dimensional simulation model. The surface nodes and chip nodes selected by the surface node selection scheme constitute the network topology structure of the corresponding chip thermal resistance network model. When the method is specifically implemented, in order to reduce the number of simulation tests, several surface node selection schemes can be determined according to the chip packaging structure in the applicable surface node selection schemes, and then the method is used to determine the optimal scheme from the determined several surface node selection schemes to complete the optimization modeling of the chip thermal resistance network model.

[0053] The embodiment of the present application constructs a chip thermal resistance network model according to different surface node selection schemes, and performs thermal simulation comparison on the constructed chip thermal resistance network model and the chip three-dimensional simulation model to obtain the chip junction temperature difference between the two, and selects the chip thermal resistance network model with the smallest chip junction temperature difference with the chip three-dimensional simulation model as the final optimized chip thermal resistance network model, thereby realizing the optimized modeling of the chip thermal resistance network model. The constructed chip thermal resistance network model can be well equivalent to the chip three-dimensional simulation model, laying a good foundation for the subsequent accurate calculation of the chip junction temperature.

[0054] Wherein, the chip thermal resistance network model is a thermal simulation model of multiple thermal resistances of chip packaging.

[0055] In some embodiments, the chip thermal resistance network model is a star thermal resistance model, and the surface nodes that need to be selected include four nodes representing the top surface, side surface, bottom surface and pins of the chip package. The network topology structure of the star thermal resistance model is a star structure. The four nodes are connected to the chip nodes, and each node is connected to the chip node through a thermal resistance.

[0056] In other embodiments, the chip thermal resistance network model is a Delphi thermal resistance network model, and the selected surface nodes include five nodes representing the inner side of the top surface, the outer side of the top surface, the inner side of the bottom surface, the outer side of the bottom surface and the pins of the chip package. The network topology structure of the Delphi thermal resistance network model is: the five nodes are connected to the chip nodes, and each node is connected to the chip node through a thermal resistance.

[0057] When constructing a chip thermal resistance network model according to the surface node selection scheme, the chip three-dimensional simulation model can be used to calculate the chip junction temperature and the heat flow through each surface node, and then the specific values ​​of each thermal resistance in the chip thermal resistance network model can be calculated based on the chip junction temperature and heat flow.

[0058] In some embodiments, the step of obtaining the chip junction temperature difference between each of the chip thermal resistance network models and the chip three-dimensional simulation model includes:

[0059] Setting multiple sets of boundary conditions corresponding to the working environment of the chip;

[0060] Calculate the difference between the chip junction temperature simulation values ​​of the chip thermal resistance network model and the chip three-dimensional simulation model under each set of boundary conditions;

[0061] The maximum value is selected from all calculated differences as the chip junction temperature difference between the chip thermal resistance network model and the chip three-dimensional simulation model.

[0062] Among them, when setting multiple groups of boundary conditions according to the working environment of the chip, the boundary conditions corresponding to the working environment that the chip may encounter can be selected from the 38 boundary conditions proposed in the JEDEC (Solid State Technology Association) standard, where the 38 boundary conditions include natural convection, forced convection, cold plate, liquid immersion and other environments, and each group of boundary conditions is a combination of heat transfer coefficients on the top surface, bottom surface, side surface and pins of the chip package.

[0063] In some embodiments, the method further comprises:

[0064] Establish a corresponding chip physical simulation model according to chip parameters;

[0065] Performing thermal simulation on the chip physical simulation model to obtain a junction-to-ring thermal resistance simulation value of the chip;

[0066] The junction-ring thermal resistance simulation value is compared with the junction-ring thermal resistance reference value. If the error between the two is less than a preset error threshold, the chip physical simulation model is used as the chip three-dimensional simulation model.

[0067] The chip parameters include the chip's structural parameters and material parameters. The structural parameters mainly include the chip's size and shape parameters, and the material parameters mainly include the material's thermal conductivity. The chip physical simulation model established based on the chip parameters needs to reflect all characteristics of the chip's internal structure and materials in detail.

[0068] The embodiment of the present application verifies the chip three-dimensional simulation model through the junction-ring thermal resistance, further improving the accuracy of the chip thermal resistance network model. Since the environmental error of the junction-ring thermal resistance test by different manufacturers is small, it is easy to implement to verify the chip three-dimensional simulation model through the junction-ring thermal resistance.

[0069] It should be noted that when modeling the above-mentioned various models, professional modeling software can be used for modeling, and thermal simulation software can also be used for direct modeling. The modeling software can be any of the following: SolidWorks, comsol, ANSYS, Icepak, MENTOR, FloTHERM, FloEFD and STAR.

[0070] A second aspect of the present application provides an optimization device for a chip thermal resistance network model.

[0071] Figure 2 The figure shows a schematic diagram of the structure of a preferred embodiment of the chip thermal resistance network model optimization device provided in the present application, and the device can implement the entire process of the chip thermal resistance network model optimization method described in any of the above embodiments.

[0072] like Figure 2 As shown, the device comprises:

[0073] An acquisition module 1 is used to acquire all surface node selection schemes applicable to a chip three-dimensional simulation model;

[0074] Model building module 2, used for building a corresponding chip thermal resistance network model according to each of the surface node selection schemes, wherein the network topology of the chip thermal resistance network model is composed of chip nodes and surface nodes selected by the surface node selection scheme, and each surface node is connected to the chip node by a thermal resistor;

[0075] A simulation comparison module 3 is used to perform thermal simulation comparison between each of the constructed chip thermal resistance network models and the chip three-dimensional simulation model to obtain a chip junction temperature difference between each of the chip thermal resistance network models and the chip three-dimensional simulation model;

[0076] The output module 4 is used to output the chip thermal resistance network model corresponding to the minimum value of the chip junction temperature difference as the optimized chip thermal resistance network model.

[0077] In some embodiments, the simulation comparison module includes:

[0078] A setting unit, used to set multiple groups of boundary conditions corresponding to the working environment of the chip;

[0079] A calculation unit, used for calculating the difference between the chip junction temperature simulation values ​​of the chip thermal resistance network model and the chip three-dimensional simulation model under each set of boundary conditions;

[0080] The chip junction temperature difference determination unit is used to select a maximum value from all calculated differences as the chip junction temperature difference between the chip thermal resistance network model and the chip three-dimensional simulation model.

[0081] In some embodiments, the apparatus further comprises:

[0082] A chip physical simulation model building module is used to build a corresponding chip physical simulation model according to chip parameters;

[0083] A thermal simulation module, used for performing thermal simulation on the chip physical simulation model to obtain a junction-to-ring thermal resistance simulation value of the chip;

[0084] The comparison and verification module is used to compare the junction-ring thermal resistance simulation value with the junction-ring thermal resistance reference value. If the error between the two is less than a preset error threshold, the chip physical simulation model is used as the chip three-dimensional simulation model.

[0085] In some embodiments, the chip thermal resistance network model is a star thermal resistance model or a Delphi thermal resistance network model.

[0086] The functions and implementation methods of each module of the above-mentioned embodiment of the device of the present application are the same as those of the embodiment of the above-mentioned method for optimizing the thermal resistance network model of a chip. For specific analysis, reference can be made to the embodiment of the above-mentioned method for optimizing the thermal resistance network model of a chip. In order to avoid repetition, they will not be described here.

[0087] A third aspect of the present application provides an optimization device for a chip thermal resistance network model, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor implements the chip thermal resistance network model optimization method as described in any one of the above embodiments when executing the computer program.

[0088] A fourth aspect of the present application provides a computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, and when the computer program is executed, the method for optimizing the chip thermal resistance network model as described in any one of the above embodiments is implemented.

[0089] A fifth aspect of the present application provides a chip thermal resistance network model, and the chip thermal resistance network model is obtained according to the chip thermal resistance network model optimization method described in any one of the above embodiments.

[0090] It should be noted that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the optimization device of the chip thermal resistance network model, and uses various interfaces and lines to connect various parts of the optimization device of the entire chip thermal resistance network model.

[0091] The memory can be used to store the computer program and / or module, and the processor realizes various functions of the optimization device of the chip thermal resistance network model by running or executing the computer program and / or module stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating device, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0092] Wherein, if the module / unit integrated in the optimization device of the chip thermal resistance network model is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal and software distribution medium, etc.

[0093] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications are also considered to be within the scope of protection of the present application.

Claims

1. A method for optimizing a chip thermal resistance network model, characterized in that: The method comprises: S1: Obtain all surface node selection schemes applicable to the chip 3D simulation model; S2: constructing a corresponding chip thermal resistance network model according to each of the surface node selection schemes, wherein the network topology of the chip thermal resistance network model is composed of chip nodes and surface nodes selected by the surface node selection scheme, and each surface node is connected to the chip node by a thermal resistor; S3: performing thermal simulation comparison on each of the constructed chip thermal resistance network models and the chip three-dimensional simulation model to obtain a chip junction temperature difference between each of the chip thermal resistance network models and the chip three-dimensional simulation model; S4: Outputting the chip thermal resistance network model corresponding to the minimum value of the chip junction temperature difference as the optimized chip thermal resistance network model; Wherein, obtaining the chip junction temperature difference between each chip thermal resistance network model and the chip three-dimensional simulation model includes: Setting multiple sets of boundary conditions corresponding to the working environment of the chip; Calculate the difference between the chip junction temperature simulation values ​​of the chip thermal resistance network model and the chip three-dimensional simulation model under each set of boundary conditions; The maximum value is selected from all calculated differences as the chip junction temperature difference between the chip thermal resistance network model and the chip three-dimensional simulation model.

2. The chip thermal resistance network model optimization method according to claim 1, characterized in that: The method further comprises: Establish a corresponding chip physical simulation model according to chip parameters; Performing thermal simulation on the chip physical simulation model to obtain a junction-to-ring thermal resistance simulation value of the chip; The junction-ring thermal resistance simulation value is compared with the junction-ring thermal resistance reference value. If the error between the two is less than a preset error threshold, the chip physical simulation model is used as the chip three-dimensional simulation model.

3. The chip thermal resistance network model optimization method according to claim 1, characterized in that: The chip thermal resistance network model is a star thermal resistance model or a Delphi thermal resistance network model.

4. An optimization device for a chip thermal resistance network model, characterized in that: The device comprises: An acquisition module is used to acquire all surface node selection schemes applicable to the chip three-dimensional simulation model; A model building module, used for building a corresponding chip thermal resistance network model according to each of the surface node selection schemes, wherein the network topology of the chip thermal resistance network model is composed of chip nodes and surface nodes selected by the surface node selection scheme, and each surface node is connected to the chip node by a thermal resistor; A simulation comparison module, used for performing thermal simulation comparison between each of the chip thermal resistance network models constructed and the chip three-dimensional simulation model, and obtaining a chip junction temperature difference between each of the chip thermal resistance network models and the chip three-dimensional simulation model; An output module, used for outputting the chip thermal resistance network model corresponding to the minimum value of the chip junction temperature difference as an optimized chip thermal resistance network model; Wherein, the simulation comparison module includes: A setting unit, used to set multiple groups of boundary conditions corresponding to the working environment of the chip; A calculation unit, used for calculating the difference between the chip junction temperature simulation values ​​of the chip thermal resistance network model and the chip three-dimensional simulation model under each set of boundary conditions; The chip junction temperature difference determination unit is used to select a maximum value from all calculated differences as the chip junction temperature difference between the chip thermal resistance network model and the chip three-dimensional simulation model.

5. The chip thermal resistance network model optimization device according to claim 4, characterized in that: The device also includes: A chip physical simulation model building module is used to build a corresponding chip physical simulation model according to chip parameters; A thermal simulation module, used for performing thermal simulation on the chip physical simulation model to obtain a junction-to-ring thermal resistance simulation value of the chip; The comparison and verification module is used to compare the junction-ring thermal resistance simulation value with the junction-ring thermal resistance reference value. If the error between the two is less than a preset error threshold, the chip physical simulation model is used as the chip three-dimensional simulation model.

6. The chip thermal resistance network model optimization device according to claim 4, characterized in that: The chip thermal resistance network model is a star thermal resistance model or a Delphi thermal resistance network model.

7. An optimization device for a chip thermal resistance network model, characterized in that: The method comprises a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, the method for optimizing the chip thermal resistance network model according to any one of claims 1 to 3 is implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the method for optimizing the chip thermal resistance network model according to any one of claims 1 to 3 is implemented.

9. A chip thermal resistance network model, characterized in that: The chip thermal resistance network model is obtained according to the chip thermal resistance network model optimization method according to any one of claims 1 to 3.

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