Display substrate and display device

Abstract

This invention provides a display substrate and a display device. The display substrate includes a plurality of sub-pixels, each sub-pixel including a plurality of transistors; the display substrate further includes a substrate and N array layers sequentially disposed on the substrate; N is an integer greater than 1; the transistors included in the sub-pixels are divided into N groups, and the nth group of transistors is formed by the nth array layer; n is a positive integer less than or equal to N. The display substrate of this invention occupies less layout space, which is beneficial for improving display resolution and display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] OLED (Organic Light Emitting Diode) displays are widely used in the display field due to their thinness, self-illumination, and fast response time. Currently, OLED displays generally have low resolution. If these low-resolution displays are used in near-eye displays such as VR (Virtual Reality), the unique optical path structure of near-eye displays can easily cause a screen-door effect, affecting the user experience. To improve the screen-door effect, an effective method is to increase the display resolution. Generally speaking, to eliminate the screen-door effect in near-eye displays, the resolution of the display product should be increased.

[0003] Because OLED pixel circuitry is complex, it requires a significant amount of layout space. Existing glass-based OLED displays struggle to achieve high PPI (pixels per inch). Therefore, a suitable technological solution is needed to address this issue. Summary of the Invention

[0004] The main objective of this invention is to provide a display substrate and a display device that solve the problem that existing display substrates occupy a large layout space, which is not conducive to achieving high PPI (pixels per inch) display and improving display resolution.

[0005] To achieve the above objectives, embodiments of the present invention provide a display substrate comprising a plurality of sub-pixels, wherein each sub-pixel comprises a plurality of transistors; the display substrate further comprises a substrate, and N array layers sequentially disposed on the substrate; N is an integer greater than 1;

[0006] The sub-pixel includes transistors divided into N groups, with the nth group of transistors formed by the nth array layer; n is a positive integer less than or equal to N.

[0007] Optionally, the nth array layer includes an nth semiconductor layer, an nth gate metal layer, and a gate insulating layer disposed between the nth semiconductor layer and the nth gate metal layer, which are sequentially disposed on the substrate.

[0008] The gate of the nth group of transistors is formed by the nth gate metal layer, and the active layer pattern of the nth group of transistors is formed by the nth semiconductor layer.

[0009] Optionally, the nth array layer further includes an nth source / drain metal layer and an nth interlayer dielectric layer disposed between the nth gate metal layer and the nth source / drain metal layer.

[0010] Optionally, the display substrate described in at least one embodiment of the present invention further includes an isolation layer disposed between two adjacent array layers;

[0011] The isolation layer includes an insulating layer.

[0012] Optionally, the isolation layer further includes an electric field shielding layer;

[0013] The electric field shielding layer is connected to a constant potential to avoid signal interference between adjacent array layers.

[0014] Optionally, the sub-pixel further includes a light-emitting element, and the display substrate further includes an anode layer; the N array layers are disposed between the substrate and the anode layer;

[0015] The anode of the light-emitting element is formed by the anode layer.

[0016] Optionally, the display substrate described in at least one embodiment of the present invention further includes a transition conductive pattern; the connecting film layers in different array layers are coupled to each other through vias and the transition conductive pattern; the connecting film layers in the array layers include at least one of a metal layer and a semiconductor layer in the array layers;

[0017] The display substrate further includes an anode layer, which is coupled to a semiconductor layer in at least one of the array layers via vias and the transition conductive pattern.

[0018] Optionally, the conductive transition pattern is formed by at least one metal layer in the array layer; or,

[0019] The display substrate further includes a transition conductive layer, and the transition conductive pattern is formed by the transition conductive layer.

[0020] Optionally, the semiconductor layers in a portion of the N array layers are made of polysilicon, and the semiconductor layers in another portion of the N array layers are made of oxide; or, all the semiconductor layers in the N array layers are made of polysilicon.

[0021] Optionally, the sub-pixel includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a reset control line, an initial voltage line, a data line, a gate line, and a light emission control line;

[0022] The gate of the first transistor is coupled to the reset control line, the first electrode of the first transistor is coupled to the initial voltage line, and the second electrode of the first transistor is coupled to the first node;

[0023] The gate of the second transistor is coupled to the gate line, the first electrode of the second transistor is coupled to the first node, and the second electrode of the second transistor is coupled to the second electrode of the third transistor.

[0024] The gate of the third transistor is coupled to the first node, and the first electrode of the third transistor is coupled to the second electrode of the fourth transistor.

[0025] The gate of the fourth transistor is coupled to the gate line, and the first electrode of the fourth transistor is coupled to the data line;

[0026] The gate of the fifth transistor is coupled to the light-emitting control line, the first electrode of the fifth transistor is coupled to the power supply voltage line, and the second electrode of the fifth transistor is coupled to the second electrode of the fourth transistor.

[0027] The gate of the sixth transistor is coupled to the light-emitting control line, the first electrode of the sixth transistor is coupled to the second electrode of the second transistor, and the second electrode of the sixth transistor is coupled to the anode of the light-emitting element.

[0028] The display substrate includes a first array layer, a second array layer and a third array layer sequentially disposed on the substrate;

[0029] The third transistor, the fifth transistor, and the sixth transistor are formed by the first array layer;

[0030] The fourth transistor is formed by the second array layer;

[0031] The first transistor and the second transistor are formed by the third array layer.

[0032] Optionally, the sub-pixel further includes a storage capacitor; the gate of the third transistor is coupled to the first plate of the storage capacitor, and the power supply voltage line is coupled to the second plate of the storage capacitor.

[0033] Optionally, the first transistor, the second transistor, and the fourth transistor are all dual-gate transistors;

[0034] The first transistor includes a first gate and a second gate that are coupled together; the second transistor includes a first gate and a second gate that are coupled together; and the fourth transistor includes a first gate and a second gate that are coupled together.

[0035] The first gate is a top gate, and the second gate is a bottom gate.

[0036] Optionally, the semiconductor layer included in the first array layer is made of polycrystalline silicon, and the semiconductor layers included in the second array layer and the third array layer are both made of oxide; or,

[0037] The semiconductor layers included in the first array layer, the second array layer, and the third array layer are all made of polycrystalline silicon.

[0038] Optionally, the first array layer includes a first semiconductor layer, a first first gate insulating layer, a first first gate metal layer, a second first gate insulating layer, and a second second gate metal layer sequentially disposed on the substrate;

[0039] The display substrate further includes a first isolation layer disposed between the first array layer and the second array layer;

[0040] The second array layer includes a second semiconductor layer, a second gate insulating layer, a second gate metal layer, a second interlayer dielectric layer, and a second source / drain metal layer, which are sequentially disposed on the side of the first isolation layer away from the substrate.

[0041] The display substrate further includes a second isolation layer disposed between the second array layer and the third array layer;

[0042] The third array layer includes a third semiconductor layer, a third gate insulating layer, a third gate metal layer, a third interlayer dielectric layer, and a third source / drain metal layer, which are sequentially disposed on the side of the second isolation layer away from the second array layer.

[0043] The display substrate further includes an anode layer disposed on the side of the third array layer away from the substrate, and a first planarization layer disposed between the anode layer and the third array layer; the anode of the light-emitting element included in the sub-pixel is formed in the anode layer.

[0044] Optionally, the active layer patterns of the third transistor, the fifth transistor, and the sixth transistor are formed by the first semiconductor layer, the gates of the third transistor, the fifth transistor, and the sixth transistor are formed by the first gate metal layer, and the power supply voltage line is formed by the second gate metal layer.

[0045] The active layer pattern of the fourth transistor is formed by the second semiconductor layer, the gate of the fourth transistor is formed by the second gate metal layer, and the data line is formed on the second source-drain metal layer.

[0046] The gates of the first transistor and the second transistor are formed by the third gate metal layer;

[0047] The active layer patterns of the first transistor and the second transistor are formed by the third semiconductor layer; the active layer pattern of the first transistor includes a first first conductive portion, a first channel portion and a second first conductive portion, and the active layer pattern of the second transistor includes a first second conductive portion, a second channel portion and a second second conductive portion;

[0048] The display substrate further includes a conductive connection portion formed on a third source / drain metal layer; the conductive connection portion is coupled to a second first conductive portion through a via, and the conductive connection portion is coupled to a first second conductive portion through a via.

[0049] Optionally, the active layer pattern of the third transistor includes a third channel portion, a first third conductive portion, and a second third conductive portion, wherein the first third conductive portion is multiplexed as the first electrode of the third transistor, and the second third conductive portion is multiplexed as the second electrode of the third transistor.

[0050] The active layer pattern of the fifth transistor includes a fifth channel portion, a first fifth conductive portion and a second fifth conductive portion, wherein the first fifth conductive portion is multiplexed as the first electrode of the fifth transistor and the second fifth conductive portion is multiplexed as the second electrode of the fifth transistor;

[0051] The active layer pattern of the sixth transistor includes a sixth channel portion, a first sixth conductive portion and a second sixth conductive portion, wherein the first sixth conductive portion is multiplexed as the first electrode of the sixth transistor and the second sixth conductive portion is multiplexed as the second electrode of the sixth transistor.

[0052] The active layer pattern of the fourth transistor includes a fourth channel portion, a first fourth conductive portion, and a second fourth conductive portion; the first fourth conductive portion is multiplexed as the first electrode of the fourth transistor, and the second fourth conductive portion is multiplexed as the second electrode of the fourth transistor.

[0053] The gate of the third transistor is coupled to the second electrode of the first transistor through a via, and the first electrode of the third transistor is coupled to the second electrode of the fourth transistor through a via. The first electrode of the third transistor is multiplexed as the second electrode of the fifth transistor.

[0054] The second electrode of the third transistor is coupled to the second electrode of the second transistor through a via, and the second electrode of the third transistor is multiplexed as the first electrode of the sixth transistor;

[0055] The second electrode of the sixth transistor is coupled to the anode of the light-emitting element through a via;

[0056] One of the plates of the parasitic capacitance of the first node is composed of the gate of the third transistor, the second first conductive portion, the conductive connection portion, and the first second conductive portion coupled together.

[0057] Optionally, the display substrate further includes a first insulating layer and a first metal layer disposed between the third gate metal layer and the third interlayer dielectric layer; the first metal layer is disposed between the first insulating layer and the third interlayer dielectric layer;

[0058] The initial voltage line is formed by the first metal layer and is coupled to the first electrode of the first transistor through a via.

[0059] Optionally, the second gate metal layer includes a first transition conductive pattern, a second transition conductive pattern, and a third transition conductive pattern; the second first gate metal layer includes a fourth transition conductive pattern.

[0060] The second electrode of the second transistor is coupled to the first transition conductive pattern through a via, and the first transition conductive pattern is coupled to the second electrode of the third transistor through a via, so that the second electrode of the second transistor is coupled to the second electrode of the third transistor.

[0061] The second electrode of the fourth transistor is coupled to the second transition conductive pattern through a via, and the second transition conductive pattern is coupled to the first electrode of the third transistor through a via, so that the second electrode of the fourth transistor is coupled to the first electrode of the third transistor.

[0062] The anode of the light-emitting element is coupled to the third conductive pattern through a via, and the third conductive pattern is coupled to the second electrode of the sixth transistor through a via, so that the anode of the light-emitting element is coupled to the second electrode of the sixth transistor.

[0063] The second electrode of the fourth transistor is coupled to the fourth transition conductive pattern through a via, and the fourth transition conductive pattern is coupled to the second electrode of the fifth transistor through a via, so that the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor.

[0064] This invention also provides a display device, including the display substrate described above.

[0065] The display substrate and display device described in this embodiment of the invention form the transistors included in the sub-pixels through at least two array layers. The at least two array layers are stacked and coupled to each other through conductive connections to form the driving portion of the sub-pixel with a specific function. The display substrate described in this embodiment of the invention occupies less layout space, which is beneficial for achieving high PPI (pixels per inch) displays, improving display resolution, enhancing display effect, and eliminating the screen-door effect. Attached Figure Description

[0066] Figure 1 This is a layered schematic diagram of the display substrate according to at least one embodiment of the present invention;

[0067] Figure 2 This is a cross-sectional view of the display substrate according to at least one embodiment of the present invention;

[0068] Figure 3 This is a cross-sectional view of the display substrate according to at least one embodiment of the present invention;

[0069] Figure 4 This is a cross-sectional view of the display substrate according to at least one embodiment of the present invention;

[0070] Figure 5A This is a schematic diagram showing the positional relationship between the test transistor, the electric field shielding layer, and the predetermined metal layer;

[0071] Figure 5B yes Figure 5A Simulation diagrams showing the performance of transistors under different electric field shielding conditions;

[0072] Figure 6A This is a circuit diagram of at least one embodiment of a sub-pixel;

[0073] Figure 6B This is a circuit diagram of a dual-gate transistor.

[0074] Figure 7 yes Figure 6A The timing diagram of at least one embodiment of the sub-pixel is shown.

[0075] Figure 8 This is a circuit diagram of at least one embodiment of a sub-pixel;

[0076] Figure 9 This invention is as follows Figure 6A A schematic diagram of a layout of at least one embodiment of the sub-pixels shown;

[0077] Figure 10 yes Figure 9 A schematic diagram of the layout of the first semiconductor layer in the process;

[0078] Figure 11 yes Figure 9 A schematic diagram of the layout of the first gate metal layer in the image;

[0079] Figure 12 yes Figure 9 A schematic diagram of the layout of the second first gate metal layer;

[0080] Figure 13 yes Figure 9 A schematic diagram of the layout of the second semiconductor layer;

[0081] Figure 14 yes Figure 9 A schematic diagram of the layout of the second gate metal layer;

[0082] Figure 15 yes Figure 9 A schematic diagram of the layout of the second source / drain metal layer in the image;

[0083] Figure 16 yes Figure 9 A schematic diagram of the layout of the third semiconductor layer;

[0084] Figure 17 yes Figure 9 A schematic diagram of the layout of the third gate metal layer;

[0085] Figure 18 yes Figure 9 A schematic diagram of the layout of the first metal layer in the middle;

[0086] Figure 19 yes Figure 9 A schematic diagram of the third source / drain metal layer in the diagram;

[0087] Figure 20 yes Figure 10 and Figure 11 An overlay diagram;

[0088] Figure 21 yes Figure 20 and Figure 12 An overlay diagram;

[0089] Figure 22 yes Figure 21 and Figure 13 An overlay diagram;

[0090] Figure 23 yes Figure 22 and Figure 14 An overlay diagram;

[0091] Figure 24 yes Figure 23 and Figure 15 An overlay diagram;

[0092] Figure 25 yes Figure 24 and Figure 16 An overlay diagram;

[0093] Figure 26 yes Figure 25 and Figure 17 An overlay diagram;

[0094] Figure 27 yes Figure 26 and Figure 18 An overlay diagram;

[0095] Figure 28 yes Figure 27 and Figure 19 An overlay diagram;

[0096] Figure 29 Is Figure 28 A schematic diagram of adding the ninth via H9 based on the existing diagram;

[0097] Figure 30 This is a schematic diagram of the parasitic capacitance of the first node using a sandwich structure;

[0098] Figure 31 This is a cross-sectional view of the display substrate according to at least one embodiment of the present invention. Detailed Implementation

[0099] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0100] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode, and the other as the second electrode.

[0101] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0102] The display substrate described in this embodiment of the invention includes a plurality of sub-pixels, each sub-pixel including a plurality of transistors; the display substrate further includes a substrate, and N array layers sequentially disposed on the substrate; N is an integer greater than 1;

[0103] The sub-pixel includes transistors divided into N groups, with the nth group of transistors formed by the nth array layer; n is a positive integer less than or equal to N.

[0104] The display substrate described in this embodiment of the invention forms the transistors included in the sub-pixels using at least two array layers. These at least two array layers are stacked and coupled to each other via conductive connections to form the driving portion of the sub-pixel with a specific function. The display substrate described in this embodiment of the invention occupies less layout space, which is beneficial for achieving high PPI (pixels per inch) displays, improving display resolution, enhancing display quality, and eliminating the screen-door effect.

[0105] In at least one embodiment of the present invention, the substrate may be a glass substrate, or the substrate may include a glass substrate and a PI (polyimide) film stacked together, but is not limited thereto.

[0106] like Figure 1 As shown, when N equals 3, the display substrate of at least one embodiment of the present invention includes a first array layer 11, a second array layer 12, a third array layer 13 and a light-emitting functional layer 10;

[0107] The light-emitting functional layer 10 may include, but is not limited to, a stacked anode layer, a light-emitting material layer, and a cathode layer.

[0108] In a specific implementation, the sub-pixel may further include a light-emitting element, and the display substrate may further include an anode layer; the N array layers are disposed between the substrate and the anode layer;

[0109] The anode of the light-emitting element is formed by the anode layer.

[0110] In at least one embodiment of the present invention, the semiconductor layer in a portion of the N array layers is made of polysilicon, and the semiconductor layer in another portion of the N array layers is made of oxide; or, all the semiconductor layers in the N array layers are made of polysilicon.

[0111] Optionally, the nth array layer may include an nth semiconductor layer, an nth gate metal layer, and a gate insulating layer disposed between the nth semiconductor layer and the nth gate metal layer, which are sequentially disposed on the substrate.

[0112] The gate of the nth group of transistors is formed by the nth gate metal layer, and the active layer pattern of the nth group of transistors is formed by the nth semiconductor layer.

[0113] Optionally, the nth array layer further includes an nth source / drain metal layer and an nth interlayer dielectric layer disposed between the nth gate metal layer and the nth source / drain metal layer.

[0114] In at least one embodiment of the present invention, the nth array layer may include an nth source-drain metal layer, and the nth source-drain metal layer is patterned to form signal lines or conductive connections.

[0115] In a specific implementation, the active layer pattern of the nth group of transistors may include a first conductive portion, a channel portion, and a second conductive portion. The channel portion is disposed between the first conductive portion and the second conductive portion. The first conductive portion in the nth group of transistors is multiplexed as the first electrode of the nth group of transistors, and the second conductive portion in the nth group of transistors is multiplexed as the second electrode of the nth group of transistors.

[0116] The display substrate described in this embodiment of the invention may further include an isolation layer disposed between two adjacent array layers;

[0117] The isolation layer includes an insulating layer.

[0118] In a preferred embodiment, the isolation layer may further include an electric field shielding layer;

[0119] The electric field shielding layer is connected to a constant potential to avoid signal interference between adjacent array layers.

[0120] In at least one embodiment of the present invention, the isolation layer may further include an electric field shielding layer to shield signal interference between adjacent array layers, thereby achieving a smaller layout space and improving product resolution.

[0121] Optionally, the electric field shielding layer may be made of metal, but is not limited thereto.

[0122] like Figure 2 As shown, the display substrate of at least one embodiment of the present invention includes a substrate 20, a first array layer, a second array layer, a third array layer, a first isolation layer 61, a second isolation layer 62, a first planarization layer 71, an anode layer 80, and a pixel defining layer 81; a buffer layer 201 is disposed between the substrate 20 and the first array layer;

[0123] The first array layer includes a first semiconductor layer 31, a first first gate insulating layer 32, a first first gate metal layer 33, a second first gate insulating layer 34, and a second first gate metal layer 35, which are sequentially disposed on the side of the buffer layer 201 away from the substrate 20.

[0124] The first isolation layer 61 is disposed between the first array layer and the second array layer;

[0125] The second array layer includes a second semiconductor layer 41, a second gate insulating layer 42, a second gate metal layer 43, a second interlayer dielectric layer 44, and a second source / drain metal layer 45, which are sequentially disposed on the side of the first isolation layer 61 away from the substrate 20.

[0126] The second isolation layer 62 is disposed between the second array layer and the third array layer;

[0127] The third array layer includes a third semiconductor layer 51, a third gate insulating layer 52, a third gate metal layer 53, a third interlayer dielectric layer 54, and a third source / drain metal layer 55, which are sequentially disposed on the side of the second isolation layer 62 away from the substrate 20.

[0128] The first planarization layer 71, the anode layer 80, and the pixel defining layer 81 are disposed on the side of the third source / drain metal layer 55 away from the substrate 20. The first planarization layer 71 is disposed between the third source / drain metal layer 55 and the anode layer 80, and the anode layer 80 is disposed between the first planarization layer 71 and the pixel defining layer 81.

[0129] exist Figure 2 In at least one embodiment shown, the first isolation layer 61 and the second isolation layer 62 may be insulating layers, the first isolation layer 61 and the second isolation layer 62 may be made of resin, or the first isolation layer 61 and the second isolation layer 62 may be inorganic layers, but are not limited thereto;

[0130] The first planarization layer 71 can be an organic layer or an inorganic layer; for example, the first planarization layer 71 can be a PI (polyimide) layer, or the first planarization layer 71 can be one or more layers of silicon nitride, silicon oxide, and silicon oxynitride.

[0131] The first gate insulating layer 32, the second gate insulating layer 42 and the third gate insulating layer 42 can be inorganic layers;

[0132] The second interlayer dielectric layer 44 and the third interlayer dielectric layer 54 can be inorganic layers;

[0133] The inorganic layer may be one or more layers of silicon nitride, silicon oxide, or silicon oxynitride, but is not limited thereto.

[0134] exist Figure 2 In at least one of the embodiments shown, the first semiconductor layer 31 may be made of polycrystalline silicon, and the second semiconductor layer 41 and the third semiconductor layer 51 may be made of oxide, for example, the oxide may be IGZO (indium gallium zinc oxide), but is not limited thereto.

[0135] In specific implementations, the first semiconductor layer 31, the second semiconductor layer 41, and the third semiconductor layer 51 may all be made of polycrystalline silicon.

[0136] exist Figure 2 In at least one embodiment shown, the substrate 20 may include a glass substrate and a PI film stacked together, wherein the PI film may be disposed between the glass substrate and the first semiconductor layer.

[0137] In making the present invention as follows Figure 2 In at least one embodiment of the display substrate shown, a first semiconductor layer may be deposited on the substrate first, and a patterning process may be performed on the first semiconductor layer to form an active layer pattern of a first group of transistors. Then, a first first gate insulating layer and a first first gate metal layer may be deposited sequentially, and a patterning process may be performed on the first first gate metal layer to form the gate of the first group of transistors. Next, a second first gate insulating layer and a second first gate metal layer may be deposited sequentially, and a patterning process may be performed on the second first gate metal layer to form a power supply voltage line. Then, a first isolation layer may be formed, and a second semiconductor layer may be deposited on the side of the first isolation layer away from the substrate, and a patterning process may be performed on the second semiconductor layer to form an active layer pattern of a second group of transistors. Finally, a second gate insulating layer and a second gate metal layer may be deposited sequentially, and a patterning process may be performed on the second gate metal layer to form a... The gate of the second group of transistors is then deposited, followed by the sequential deposition of a second interlayer dielectric layer and a second source / drain metal layer. The pattern of the second source / drain metal layer is patterned to form a data line. A second isolation layer is then deposited, and a third semiconductor layer is deposited on the side of the second isolation layer away from the substrate. The third semiconductor layer is patterned to form the active layer pattern of the third group of transistors. A third gate insulating layer and a third gate metal layer are then deposited sequentially, and the third gate metal layer is patterned to form the gate of the third group of transistors. A third interlayer dielectric layer and a third source / drain metal layer are then deposited sequentially, and the third source / drain metal layer is patterned to form a conductive connection. A first planarization layer is then deposited, and an anode layer is deposited on the side of the first planarization layer away from the substrate. The anode layer is patterned to form the anode of the light-emitting element.

[0138] Furthermore, after forming the anode of the light-emitting element, a light-emitting material layer, a cathode layer, and an encapsulation film layer can be sequentially fabricated on the side of the anode layer away from the substrate.

[0139] Optionally, the display substrate described in at least one embodiment of the present invention may further include a transition conductive pattern; the connecting film layers in different array layers are coupled to each other through vias and the transition conductive pattern; the connecting film layers in the array layers include at least one of a metal layer and a semiconductor layer in the array layers;

[0140] The display substrate may further include an anode layer, which is coupled to a semiconductor layer in at least one of the array layers via a via and the transition conductive pattern.

[0141] In at least one embodiment of the present invention, there may be a problem of high overlap resistance between the connecting film layers between different array layers. In addition, there is a problem of excessively deep vias between the anode layer and the semiconductor layer in at least one array layer. Therefore, at least one embodiment of the present invention uses a transition conductive pattern to connect the semiconductor layers in different array layers to reduce resistance, and uses a transition conductive pattern to connect the anode layer and the semiconductor layer in at least one array layer to reduce the depth of the vias.

[0142] Optionally, when the array layer includes a source / drain metal layer, the connection film layer may include at least one of a gate metal layer, a source / drain metal layer, and a semiconductor layer;

[0143] When the array layer does not include source / drain metal layers, the connection film layer may include at least one of a gate metal layer and a semiconductor layer;

[0144] However, this is not the limit.

[0145] In specific implementation, the transition conductive pattern can be formed by at least one metal layer in the array layer; or,

[0146] The display substrate may further include a transition conductive layer, and the transition conductive pattern may be formed by the transition conductive layer.

[0147] In practice, to save on film layers, the transition conductive pattern can be formed by at least one metal layer in the array layer, or a separate transition conductive layer can be provided to facilitate the transition between semiconductor layers in different array layers.

[0148] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the display substrate shown, the second gate metal layer 43 includes a first transition conductive pattern Z1, a second transition conductive pattern Z2 and a third transition conductive pattern Z3, and the second first gate metal layer 35 includes a fourth transition conductive pattern Z4.

[0149] The third source / drain metal layer 55 includes a conductive pattern that is coupled to the first transition conductive pattern Z1 through a via, and the first transition conductive pattern Z1 is coupled to a conductive pattern included in the first gate metal layer 33 through a via.

[0150] The second semiconductor layer 41 includes an active layer pattern that is coupled to the second transition conductive pattern Z2 through a via, and the second transition conductive pattern Z2 is coupled to the first semiconductor layer 31 through a via.

[0151] The anode of the light-emitting element included in the anode layer 80 is coupled to the third transition conductive pattern Z3 through a via, and the third transition conductive pattern Z3 is coupled to the first semiconductor layer 31 through a via.

[0152] The second semiconductor layer 41 includes an active layer pattern that is coupled to the fourth transition conductive pattern Z4 through a via, and the fourth transition conductive pattern Z4 is coupled to the first semiconductor layer 31 through a via.

[0153] This invention Figure 4 The at least one embodiment of the display substrate shown is similar to the present invention. Figure 2 The differences between at least one embodiment of the display substrate shown are as follows:

[0154] The first isolation layer includes a first insulating layer 611, a first electric field shielding layer 612, and a second planarization layer 613, which are sequentially disposed on the side of the second first gate metal layer 35 away from the substrate 20.

[0155] The second isolation layer includes a second insulating layer 621, a second electric field shielding layer 622, and a third planarization layer 623, which are sequentially disposed on the side of the second source / drain metal layer 45 away from the substrate 20.

[0156] exist Figure 4 In at least one embodiment of the display substrate shown, the first electric field shielding layer 612 is used to avoid signal crosstalk between the first array layer and the second array layer, and the second electric field shielding layer 622 is used to avoid signal crosstalk between the second array layer and the third array layer.

[0157] exist Figure 4 In at least one embodiment of the display substrate shown, the first electric field shielding layer 612 and the second electric field shielding layer 622 may be made of metal.

[0158] The first insulating layer 611, the second insulating layer 621, the second planarization layer 613 and the third planarization layer 623 may be made of resin, or the first insulating layer 611, the second insulating layer 621, the second planarization layer 613 and the third planarization layer 623 may be inorganic layers, but are not limited thereto;

[0159] The inorganic layer may be one or more layers of silicon nitride, silicon oxide, or silicon oxynitride, but is not limited thereto.

[0160] The present invention is as follows Figure 4In at least one embodiment of the display substrate shown, the first electric field shielding layer 612 and the second electric field shielding layer 622 can be connected to a fixed potential during operation, for example, a 0V voltage can be connected, but not limited thereto.

[0161] To address the issue of multi-layer discontinuities, planarization layers or CMP (Chemical Mechanical Polishing) processes can be used to eliminate them. Currently, the IC (integrated circuit) manufacturing field has relatively complete discontinuity planarization solutions.

[0162] like Figure 5A As shown, the gate lead of the test transistor is labeled Gt, the source lead of the test transistor is labeled St, and the drain lead of the test transistor is labeled Dt.

[0163] The gate lead Gt is coupled to the gate of the test transistor, the source lead St is coupled to the source of the test transistor, and the drain lead Dt is coupled to the drain of the test transistor.

[0164] exist Figure 5A In the diagram, the layer marked 60 is the electric field shielding layer, and the layer marked P0 is the predetermined metal layer;

[0165] During testing, the electric field shielding layer 60 is coupled to the voltage supply terminal F0, and the predetermined metal layer P0 can be connected to a -10V potential through the pad F1;

[0166] like Figure 5B As shown, tests have shown that when the electric field shielding layer 60 is not working (that is, when the electric field shielding layer 60 is in a floating state), the test transistor is negatively biased, the conduction current Ion of the test transistor decreases, and the larger the width-to-length ratio W / L of the test transistor, the more obvious the effect.

[0167] When the electric field shielding layer 60 is connected to a 0V potential, the characteristics of the test transistor are stable and unaffected by the predetermined metal layer P0.

[0168] In at least one embodiment of the present invention, the sub-pixel may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a reset control line, an initial voltage line, a data line, a gate line, and a light emission control line;

[0169] The gate of the first transistor is coupled to the reset control line, the first electrode of the first transistor is coupled to the initial voltage line, and the second electrode of the first transistor is coupled to the first node;

[0170] The gate of the second transistor is coupled to the gate line, the first electrode of the second transistor is coupled to the first node, and the second electrode of the second transistor is coupled to the second electrode of the third transistor.

[0171] The gate of the third transistor is coupled to the first node, and the first electrode of the third transistor is coupled to the second electrode of the fourth transistor.

[0172] The gate of the fourth transistor is coupled to the gate line, and the first electrode of the fourth transistor is coupled to the data line;

[0173] The gate of the fifth transistor is coupled to the light-emitting control line, the first electrode of the fifth transistor is coupled to the power supply voltage line, and the second electrode of the fifth transistor is coupled to the second electrode of the fourth transistor.

[0174] The gate of the sixth transistor is coupled to the light-emitting control line, the first electrode of the sixth transistor is coupled to the second electrode of the second transistor, and the second electrode of the sixth transistor is coupled to the anode of the light-emitting element.

[0175] The display substrate includes a first array layer, a second array layer and a third array layer sequentially disposed on the substrate;

[0176] The third transistor, the fifth transistor, and the sixth transistor are formed by the first array layer;

[0177] The fourth transistor is formed by the second array layer;

[0178] The first transistor and the second transistor are formed by the third array layer.

[0179] In a specific implementation, at least one embodiment of the sub-pixel may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The display substrate may include a first array layer, a second array layer, and a third array layer sequentially disposed on the substrate. The third transistor, the fifth transistor, and the sixth transistor are formed by the first array layer. The fourth transistor is formed by the second array layer. The first transistor and the second transistor are formed by the third array layer, so as to reduce the layout space of the sub-pixel.

[0180] In a specific implementation, the sub-pixel also includes a storage capacitor; the gate of the third transistor is coupled to the first plate of the storage capacitor, and the power supply voltage line is coupled to the second plate of the storage capacitor.

[0181] In at least one embodiment of the present invention, the light-emitting element may be an organic light-emitting diode or a light-emitting diode, but is not limited thereto.

[0182] like Figure 6A As shown, at least one embodiment of the sub-pixel includes an organic light-emitting diode O1, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a storage capacitor C1, a reset control line RST, an initial voltage line Vint, a data line Data, a gate line Gate, and a light-emitting control line EM.

[0183] The gate G1 of the first transistor T1 is coupled to the reset control line RST, the first electrode S1 of the first transistor T1 is coupled to the initial voltage line Vint, and the second electrode D1 of the first transistor T1 is coupled to the first node N1; the initial voltage line Vint is used to provide an initial voltage signal.

[0184] The gate G2 of the second transistor T2 is coupled to the gate line Gate, the first electrode S2 of the second transistor T2 is coupled to the first node N1, and the second electrode D2 of the second transistor T2 is coupled to the second electrode D3 of the third transistor T3.

[0185] The gate G3 of the third transistor T3 is coupled to the first node N1, and the first electrode S3 of the third transistor T3 is coupled to the second electrode D4 of the fourth transistor T4.

[0186] The gate G4 of the fourth transistor T4 is coupled to the gate line Gate, and the first electrode S4 of the fourth transistor T4 is coupled to the data line Data.

[0187] The gate G5 of the fifth transistor T5 is coupled to the light-emitting control line EM, the first electrode S5 of the fifth transistor T5 is coupled to the power supply voltage line VDD, and the second electrode D5 of the fifth transistor T5 is coupled to the second electrode D4 of the fourth transistor T4.

[0188] The gate G6 of the sixth transistor T6 is coupled to the light-emitting control line EM, the first electrode S6 of the sixth transistor T6 is coupled to the second electrode D2 of the second transistor T2, and the second electrode D6 of the sixth transistor T6 is coupled to the anode of the organic light-emitting diode O1.

[0189] The gate G3 of the third transistor T3 is coupled to the first plate C1a of the storage capacitor C1, and the power supply voltage line VDD is coupled to the second plate C1b of the storage capacitor C1.

[0190] The cathode of the organic light-emitting diode O1 is coupled to the low-voltage line VSS.

[0191] exist Figure 6AIn at least one embodiment of the sub-pixels shown, T1, T2 and T4 can be oxide thin-film transistors, and T3, T5 and T6 can be low-temperature polycrystalline silicon thin-film transistors, but are not limited thereto.

[0192] like Figure 7 As shown, Figure 6A When at least one embodiment of the sub-pixel shown is in operation, the display cycle may include a first stage t1, a second stage t2, and a third stage t3 set sequentially.

[0193] In the first phase t1, RST provides a high voltage signal, Gate provides a low voltage signal, EM provides a high voltage signal, T1 is turned on, and T2, T4, T5 and T6 are all turned off. The initial voltage signal provided by Vint is written to the first node N1 so that T3 can be turned on at the beginning of the second phase t2.

[0194] In the second stage t2, RST provides a low voltage signal, Gate provides a high voltage signal, EM provides a high voltage signal, and the data line Data provides the data voltage Vdata. T1 is turned off, T2 is turned on, and T4 is turned on to write the data voltage Vdata to the first electrode S3 of T3 and control the connection between the first node N1 and the second electrode D3 of T3.

[0195] At the start of the second stage t2, T3 is turned on, charging C1 through the data voltage Vdata to increase the potential of the first node N1 until the potential of the first node N1 becomes Vdata+Vth, at which point T3 is turned off, and Vth is the threshold voltage of T3.

[0196] In the third stage t3, RST provides a low voltage signal, Gate provides a low voltage signal, EM provides a low voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0197] like Figure 8 As shown, the third transistor T3, the fifth transistor T5, and the third transistor T6 can be formed from the same array layer, the fourth transistor T4 can be formed from the same array layer, and the first transistor T1 and the second transistor T2 can be formed from the same array layer.

[0198] In related technologies, placing all transistors in a sub-pixel within the same array layer requires a large layout space. Therefore, at least one embodiment of the present invention uses at least two stacked array layers to form the sub-pixel, reducing the layout space occupied by a single sub-pixel and thus achieving better resolution.

[0199] For example, when the structure of the sub-pixel is as follows Figure 6AAs shown, in at least one embodiment of the present invention, three stacked array layers are used to form the sub-pixel. T3, T5 and T6 are prepared using the first array layer, T4 is prepared using the second array layer, and T1 and T2 are prepared using the third array layer. The different array layers are coupled to each other through vias.

[0200] In this embodiment of the invention, the structure of the sub-pixel is not limited to... Figure 6A The structure shown can be such that the sub-pixel includes multiple transistors and at least one capacitor. For example, the sub-pixel can be a 4T1C pixel circuit, a 5T1C pixel circuit, a 6T1C pixel circuit, a 7T1C pixel circuit, a 4T2C pixel circuit, a 5T2C pixel circuit, a 6T2C pixel circuit, or a 7T2C pixel circuit, but is not limited thereto. Furthermore, when the number of transistors and capacitors included in the sub-pixel is fixed, the structure of the sub-pixel can be modified in this embodiment of the invention to enable the sub-pixel to drive light emission normally.

[0201] In practical applications, regardless of how the structure of the sub-pixel changes, when the transistors included in the sub-pixel are disposed in at least two stacked array layers, it is within the protection scope of this invention.

[0202] Figures 9-29 The structure of sub-pixels is as follows Figure 6A The diagram shown illustrates one possible layout of the transistors and capacitors. In a specific implementation, when the structure of the sub-pixel is as follows... Figure 6A As shown, the arrangement of the transistors and capacitors is not limited to the following. Figures 9-29 As shown.

[0203] Optionally, the first transistor, the second transistor, and the fourth transistor are all dual-gate transistors;

[0204] The first transistor includes a first gate and a second gate that are coupled together; the second transistor includes a first gate and a second gate that are coupled together; and the fourth transistor includes a first gate and a second gate that are coupled together.

[0205] The first gate can be a top gate, and the second gate can be a bottom gate.

[0206] In at least one embodiment of the present invention, the first transistor, the second transistor, and the fourth transistor are all dual-gate transistors (the circuit diagram of the dual-gate transistor can be shown in the figure below). Figure 6BAs shown in the diagram, the top and bottom gates are coupled together, which can improve the driving current and shield the interference of signals from other layers to the second and third semiconductor layers. The top and bottom gates can be coupled together around the periphery of the AA area (effective display area) to avoid resolution reduction caused by internal vias in the AA area.

[0207] In at least one embodiment of the present invention, the semiconductor layer included in the first array layer is made of polycrystalline silicon, and the semiconductor layers included in the second array layer and the third array layer are both made of oxide; or,

[0208] The semiconductor layers included in the first array layer, the second array layer, and the third array layer are all made of polycrystalline silicon.

[0209] In a specific implementation, the first array layer may include a first semiconductor layer, a first first gate insulating layer, a first first gate metal layer, a second first gate insulating layer, and a second second gate metal layer sequentially disposed on the substrate.

[0210] The display substrate further includes a first isolation layer disposed between the first array layer and the second array layer;

[0211] The second array layer includes a second semiconductor layer, a second gate insulating layer, a second gate metal layer, a second interlayer dielectric layer, and a second source / drain metal layer, which are sequentially disposed on the side of the first isolation layer away from the substrate.

[0212] The display substrate further includes a second isolation layer disposed between the second array layer and the third array layer;

[0213] The third array layer includes a third semiconductor layer, a third gate insulating layer, a third gate metal layer, a third interlayer dielectric layer, and a third source / drain metal layer, which are sequentially disposed on the side of the second isolation layer away from the second array layer.

[0214] The display substrate further includes an anode layer disposed on the side of the third array layer away from the substrate, and a first planarization layer disposed between the anode layer and the third array layer; the anode of the light-emitting element included in the sub-pixel is formed in the anode layer.

[0215] Optionally, the display substrate further includes a first insulating layer and a first metal layer disposed between the third gate metal layer and the third interlayer dielectric layer; the first metal layer is disposed between the first insulating layer and the third interlayer dielectric layer;

[0216] The initial voltage line is formed by the first metal layer and is coupled to the first electrode of the first transistor through a via.

[0217] In a specific implementation, a first insulating layer and a first metal layer can be deposited sequentially between the third gate metal layer and the third interlayer dielectric layer, and the first metal layer can be patterned to form the initial voltage line, so as to facilitate the coupling of the initial voltage line with the first electrode of the first transistor.

[0218] Figure 9 This invention is as follows Figure 6A The diagram shows a layout schematic of at least one embodiment of the sub-pixels. Figure 10 yes Figure 9 A schematic diagram of the layout of the first semiconductor layer in the middle. Figure 11 yes Figure 9 A schematic diagram of the layout of the first gate metal layer in the diagram. Figure 12 yes Figure 9 A schematic diagram of the layout of the second first gate metal layer in the diagram. Figure 13 yes Figure 9 A schematic diagram of the layout of the second semiconductor layer in the diagram. Figure 14 yes Figure 9 A schematic diagram of the layout of the second gate metal layer. Figure 15 yes Figure 9 A schematic diagram of the layout of the second source / drain metal layer in the diagram. Figure 16 yes Figure 9 A schematic diagram of the layout of the third semiconductor layer in the diagram. Figure 17 yes Figure 9 A schematic diagram of the layout of the third gate metal layer. Figure 18 yes Figure 9 A schematic diagram of the layout of the first metal layer in the middle. Figure 19 yes Figure 9 A schematic diagram of the third source / drain metal layer.

[0219] exist Figure 9 In the schematic diagram shown, a first semiconductor layer, a first first gate metal layer, a second first gate metal layer, a second semiconductor layer, a second gate metal layer, a second source / drain metal layer, a third semiconductor layer, a third gate metal layer, a first metal layer, and a third source / drain metal layer are sequentially disposed on the substrate.

[0220] In a specific implementation, a first first gate insulating layer is disposed between the first semiconductor layer and the first first gate metal layer; a second first gate insulating layer is disposed between the first first gate metal layer and the second first gate metal layer; a first isolation layer is disposed between the second first gate metal layer and the second semiconductor layer; a second gate insulating layer is disposed between the second semiconductor layer and the second gate metal layer; a second interlayer dielectric layer is disposed between the second gate metal layer and the second source / drain metal layer; a second isolation layer is disposed between the second source / drain metal layer and the third semiconductor layer; a third insulating layer is disposed between the third semiconductor layer and the third gate metal layer; a first insulating layer is disposed between the third gate metal layer and the first metal layer; a third interlayer dielectric layer is disposed between the first metal layer and the third source / drain metal layer; and a third source / drain metal layer and an anode layer are disposed in a manner that integrates the first semiconductor layer and the second gate metal layer. Figure 9 A first flat layer is provided between the anode layers (shown in the middle).

[0221] Figure 20 yes Figure 10 and Figure 11 The superimposed diagram, and in Figure 20 The first via H1 is shown in the figure; Figure 21 yes Figure 20 and Figure 12 The superimposed diagram, and in Figure 21 The second via H2 is shown in the figure; Figure 22 yes Figure 21 and Figure 13 An overlay diagram; Figure 23 yes Figure 22 and Figure 14 The superimposed schematic diagram, in Figure 23 The third via H3 is shown in the image; Figure 24 yes Figure 23 and Figure 15 The superimposed diagram, and in Figure 24 The fourth via H4 and the fifth via H5 are shown in the diagram; Figure 25 yes Figure 24 and Figure 16 An overlay diagram; Figure 26 yes Figure 25 and Figure 17 The superimposed diagram, and in Figure 26 The sixth via H6 is shown in the image; Figure 27 yes Figure 26 and Figure 18 The superimposed diagram, and in Figure 27 The seventh via H7 and the eighth via H8 are shown in the figure; Figure 28 yes Figure 27 and Figure 19 An overlay diagram; Figure 29 Is Figure 28The diagram shows the addition of the ninth via H9.

[0222] In at least one embodiment of the present invention, the active layer pattern of the third transistor, the active layer pattern of the fifth transistor, and the active layer pattern of the sixth transistor are formed by the first semiconductor layer, the gate of the third transistor, the gate of the fifth transistor, and the gate of the sixth transistor are formed by the first first gate metal layer, and the power supply voltage line is formed by the second first gate metal layer.

[0223] The active layer pattern of the fourth transistor is formed by the second semiconductor layer, the gate of the fourth transistor is formed by the second gate metal layer, and the data line is formed on the second source-drain metal layer.

[0224] The gates of the first transistor and the second transistor are formed by the third gate metal layer;

[0225] The active layer patterns of the first transistor and the second transistor are formed by the third semiconductor layer; the active layer pattern of the first transistor includes a first first conductive portion, a first channel portion and a second first conductive portion, and the active layer pattern of the second transistor includes a first second conductive portion, a second channel portion and a second second conductive portion;

[0226] The display substrate further includes a conductive connection portion formed on a third source / drain metal layer; the conductive connection portion is coupled to a second first conductive portion through a via, and the conductive connection portion is coupled to a first second conductive portion through a via, so that the second first conductive portion is coupled to the first second conductive portion.

[0227] Optionally, the light emission control line may include a first light emission control line and a second light emission control line, and the gate line may include a first gate line and a second gate line;

[0228] The first light-emitting control line and the second light-emitting control line can be formed on the first gate metal layer, the gate of the fifth transistor can be formed as an integral structure with the first light-emitting control line, and the gate of the sixth transistor can be formed as an integral structure with the second light-emitting control line.

[0229] The first gate line can be formed on the second gate metal layer, and the gate of the fourth transistor can be formed as an integral structure with the first gate line;

[0230] The reset control line and the second gate line can be formed on the third gate metal layer. The gate of the second transistor can be formed integrally with the second gate line, and the gate of the first transistor can be formed integrally with the reset control line. In a specific implementation, the active layer pattern of the third transistor includes a third channel portion, a first third conductive portion, and a second third conductive portion. The first third conductive portion is multiplexed as the first electrode of the third transistor, and the second third conductive portion is multiplexed as the second electrode of the third transistor.

[0231] The active layer pattern of the fifth transistor includes a fifth channel portion, a first fifth conductive portion and a second fifth conductive portion, wherein the first fifth conductive portion is multiplexed as the first electrode of the fifth transistor and the second fifth conductive portion is multiplexed as the second electrode of the fifth transistor;

[0232] The active layer pattern of the sixth transistor includes a sixth channel portion, a first sixth conductive portion and a second sixth conductive portion, wherein the first sixth conductive portion is multiplexed as the first electrode of the sixth transistor and the second sixth conductive portion is multiplexed as the second electrode of the sixth transistor.

[0233] The active layer pattern of the fourth transistor includes a fourth channel portion, a first fourth conductive portion, and a second fourth conductive portion; the first fourth conductive portion is multiplexed as the first electrode of the fourth transistor, and the second fourth conductive portion is multiplexed as the second electrode of the fourth transistor.

[0234] The gate of the third transistor is coupled to the second electrode of the first transistor through a via, and the first electrode of the third transistor is coupled to the second electrode of the fourth transistor through a via. The first electrode of the third transistor is multiplexed as the second electrode of the fifth transistor.

[0235] The second electrode of the third transistor is coupled to the second electrode of the second transistor through a via, and the second electrode of the third transistor is multiplexed as the first electrode of the sixth transistor;

[0236] The second electrode of the sixth transistor is coupled to the anode of the light-emitting element through a via;

[0237] One of the plates of the parasitic capacitance of the first node is composed of the gate of the third transistor, the second first conductive portion, the conductive connection portion, and the first second conductive portion coupled together.

[0238] In at least one embodiment of the present invention, one plate of the parasitic capacitance of the first node can be composed of a gate of a third transistor, a second first conductive portion, a conductive connection portion, and a first second conductive portion coupled together. The gate of the third transistor is disposed on a first first gate metal layer, the second first conductive portion and the first second conductive portion are disposed on a third semiconductor layer, and the conductive connection portion is disposed on the third source / drain metal layer. Since the capacitance value of the storage capacitor in the sub-pixels of a high PPI display panel is relatively small, embodiments of the present invention use the coupling between patterns included in multiple film layers to form one plate of the parasitic capacitance of the first node, thereby increasing the capacitance value of the parasitic capacitance of the first node.

[0239] like Figure 10 As shown, the active layer pattern of T5 includes a first fifth conductive portion 511, a fifth channel portion 500, and a second fifth conductive portion 512 arranged sequentially from top to bottom;

[0240] The active layer pattern of T3 includes a first third conductive portion 311, a third channel portion 300, and a second third conductive portion 312 arranged sequentially from top to bottom; the second fifth conductive portion 512 and the first third conductive portion 311 are coupled together.

[0241] The active layer pattern of T6 includes a first sixth conductive portion 611, a sixth channel portion 600, and a second sixth conductive portion 612 arranged sequentially from top to bottom; the second sixth conductive portion 312 is coupled to the first sixth conductive portion 611.

[0242] The first fifth conductive portion 511 is reused as the first electrode of T5, and the second fifth conductive portion 512 is reused as the second electrode of T5; the first third conductive portion 311 is reused as the first electrode of T3, and the second third conductive portion 312 is reused as the second electrode of T3; the first sixth conductive portion 611 is reused as the first electrode of T6, and the second third conductive portion 312 is reused as the second electrode of T3.

[0243] like Figure 11 As shown, G5 is the gate of T5, G3 is the gate of T3, G6 is the gate of T6, and the gate of T3 G3 is reused as the first plate of storage capacitor C1.

[0244] exist Figure 11 In the diagram, EM1 is the first light-emitting control line, EM2 is the second light-emitting control line, the gate G5 of T5 is integrated with the first light-emitting control line EM1, and the gate of T6 is integrated with the second light-emitting control line EM2.

[0245] exist Figure 12 In the diagram, the line labeled VDD is the power supply voltage line, such as... Figure 21 As shown, the power supply voltage line VDD is coupled to the first fifth conductive part 511 through the first via H1, that is, the power supply voltage line VDD is coupled to the first electrode of T5.

[0246] The second plate of the storage capacitor C1 is labeled C1b, and the second plate C1b of the storage capacitor C1 is coupled to the power supply voltage line VDD.

[0247] like Figure 13 As shown, the active layer pattern of T4 includes a fourth channel portion 400, a first fourth conductive portion 411, and a second fourth conductive portion 412; the first fourth conductive portion 411 is multiplexed as the first electrode of T4, and the second fourth conductive portion 412 is multiplexed as the second electrode of T4.

[0248] like Figure 22 As shown, the second fourth conductive part 412 is coupled to the first third conductive part 311 through the second via H2, that is, the second electrode of T4 is coupled to the first electrode of T3 through the second via H2.

[0249] like Figure 14 As shown, G4 is the gate of T4, and Gate1 is the first gate line. The first gate line Gate1 and the gate G4 of T4 are formed as a single structure.

[0250] like Figure 15 As shown, the line labeled "Data" is the data line. Figure 24 As shown, the data line Data is coupled to the first fourth conductive part 411 through the third via H3, that is, the data line Data is coupled to the first electrode of T4 through the third via H3.

[0251] like Figure 16 As shown, the active layer pattern of T1 includes a first first conductive portion 111, a first channel portion 100, and a second first conductive portion 112 arranged sequentially from top to bottom; the first first conductive portion 111 is multiplexed as the first electrode of T1, and the second first conductive portion 112 is multiplexed as the second electrode of T1.

[0252] The active layer pattern of T2 includes a second second conductive portion 212, a second channel portion 200, and a first second conductive portion 211 arranged sequentially from top to bottom; the second second conductive portion 212 is multiplexed as the second electrode of T2, and the first second conductive portion 211 is multiplexed as the first electrode of T2.

[0253] like Figure 25As shown, the second first conductive portion 112 is coupled to the gate G3 of T3 through the fourth via H4;

[0254] The second conductive portion 212 is coupled to the second conductive portion 312 through the fifth via H5.

[0255] like Figure 17 As shown, G1 is the gate of T1, and G2 is the gate of T2; RST is the reset control line, and Gate2 is the second gate line; the gate G1 of T1 and the reset control line RST are integrated into a single structure, and the gate G2 of the second transistor T2 and the second gate line Gate2 are integrated into a single structure.

[0256] like Figure 18 As shown, the line labeled Vint is the initial voltage line, such as... Figure 27 As shown, the initial voltage line Vint is coupled to the first conductive portion 111 through the sixth via H6, that is, the initial voltage line Vint is coupled to the first electrode of T1 through the sixth via H6.

[0257] like Figure 19 As shown, the part labeled L1 is the conductive connection part;

[0258] like Figure 28 As shown, the conductive connection part L1 is coupled to the second first conductive part 112 through the seventh through hole H7, and the conductive connection part L1 is coupled to the first second conductive part 211 through the eighth through hole H8, so that the second electrode of T1 is coupled to the first electrode of T2.

[0259] exist Figure 29 In the diagram, H9 is the ninth via. The second sixth conductive part 612 can be coupled to the anode of the light-emitting element through the ninth via H9. That is, the second electrode of the sixth transistor can be coupled to the anode of the light-emitting element through the ninth via H9.

[0260] exist Figures 9-29In at least one embodiment of the display substrate, one electrode of the parasitic capacitance of the first node N1 can be formed by coupling the gate G3 of the third transistor T3, the second first conductive portion 112, the conductive connection portion L1, and the first second conductive portion 211. G3 is disposed on the first first gate metal layer, the second first conductive portion 112 (i.e., the second electrode of T1) is disposed on the third semiconductor layer, the first second conductive portion 211 (i.e., the first electrode of T2) is disposed on the third semiconductor layer, and the conductive connection portion is disposed on the third source / drain metal layer. Since the capacitance value of the storage capacitor in the sub-pixels of a high PPI display panel is relatively small, this embodiment of the invention uses the coupling between patterns included in multiple film layers to form one electrode of the parasitic capacitance of the first node, thereby increasing the capacitance value of the parasitic capacitance of the first node.

[0261] In at least one embodiment of the present invention, such as Figure 30 As shown, the parasitic capacitance of the first node can also use a sandwich structure to increase the capacitance value of the parasitic capacitance of the first node.

[0262] In at least one embodiment of the present invention, the second gate metal layer may include a first transition conductive pattern, a second transition conductive pattern, and a third transition conductive pattern; the second first gate metal layer may include a fourth transition conductive pattern;

[0263] The second electrode of the second transistor is coupled to the first transition conductive pattern through a via, and the first transition conductive pattern is coupled to the second electrode of the third transistor through a via, so that the second electrode of the second transistor is coupled to the second electrode of the third transistor.

[0264] The second electrode of the fourth transistor is coupled to the second transition conductive pattern through a via, and the second transition conductive pattern is coupled to the first electrode of the third transistor through a via, so that the second electrode of the fourth transistor is coupled to the first electrode of the third transistor.

[0265] The anode of the light-emitting element is coupled to the third conductive pattern through a via, and the third conductive pattern is coupled to the second electrode of the sixth transistor through a via, so that the anode of the light-emitting element is coupled to the second electrode of the sixth transistor.

[0266] The second electrode of the fourth transistor is coupled to the fourth transition conductive pattern through a via, and the fourth transition conductive pattern is coupled to the second electrode of the fifth transistor through a via, so that the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor.

[0267] like Figure 31 As shown, in Figure 3Based on at least one embodiment of the display substrate shown, 212 is the second second conductive portion, 312 is the second third conductive portion, 412 is the second fourth conductive portion, 311 is the first third conductive portion, A0 is the anode of the light-emitting element, 612 is the second sixth conductive portion, and 512 is the second fifth conductive portion.

[0268] like Figure 31 As shown, the second conductive portion 212 is coupled to the first conductive pattern Z1 through a via, and the first conductive pattern Z1 is coupled to the second conductive portion 312 through a via, so that the second electrode of the second transistor is coupled to the second electrode of the third transistor.

[0269] The second fourth conductive portion 412 is coupled to the second transition conductive pattern Z2 through a via, and the second transition conductive pattern Z2 is coupled to the first third conductive portion 311 through a via, so that the second electrode of the fourth transistor is coupled to the first electrode of the third transistor.

[0270] The anode A0 of the light-emitting element is coupled to the third transition conductive pattern Z3 through a via, and the third transition conductive pattern Z3 is coupled to the second sixth conductive portion 612 through a via, so that the anode of the light-emitting element is coupled to the second electrode of the sixth transistor.

[0271] The second fourth conductive portion 412 is coupled to the fourth transition conductive pattern Z4 through a via, and the fourth transition conductive pattern Z4 is coupled to the second fifth conductive portion 512 through a via, so that the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor.

[0272] In at least one embodiment of the present invention, there may be a problem of high overlap resistance between the connecting film layers between different array layers. In addition, there is a problem of excessively deep vias between the anode layer and the semiconductor layer in at least one array layer. Therefore, at least one embodiment of the present invention uses a transition conductive pattern to connect the semiconductor layers in different array layers to reduce resistance, and uses a transition conductive pattern to connect the anode layer and the semiconductor layer in at least one array layer to reduce the depth of the vias.

[0273] The display device described in this embodiment of the invention includes the display substrate described above.

[0274] In at least one embodiment of the present invention, the display device may be an OLED (organic light-emitting diode) display device or an LED (light-emitting diode) display device, but is not limited thereto.

[0275] The display device provided in this embodiment of the invention can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0276] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A display substrate, comprising a plurality of sub-pixels, the sub-pixel comprising a plurality of transistors; characterized in that, The display substrate further comprises a substrate, and N array layers arranged on the substrate in sequence; N is an integer greater than 1; the N array layers are arranged in a stack; The transistors included in the sub-pixel are divided into N groups, and the nth group of transistors is formed by the nth array layer; n is a positive integer less than or equal to N; The display substrate further comprises an isolation layer arranged between two adjacent array layers; The isolation layer comprises an insulating layer The isolation layer further comprises an electric field shielding layer; the electric field shielding layer is connected to a constant potential, and is used for avoiding signal interference between adjacent array layers; The display substrate further comprises a switching conductive pattern; The semiconductor layers in different array layers are coupled through a via and the switching conductive pattern; The sub-pixel comprises a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor is coupled with a reset control line, the first electrode of the first transistor is coupled with an initial voltage line, and the second electrode of the first transistor is coupled with a first node; The gate of the second transistor is coupled with a gate line, the first electrode of the second transistor is coupled with the first node, and the second electrode of the second transistor is coupled with the second electrode of the third transistor; The gate of the third transistor is coupled with the first node, and the first electrode of the third transistor is coupled with the second electrode of the fourth transistor; The gate of the fourth transistor is coupled with a gate line, and the first electrode of the fourth transistor is coupled with a data line; The active layer pattern of the first transistor and the active layer pattern of the second transistor are formed by a third semiconductor layer; the active layer pattern of the first transistor comprises a first first conductive part, a first channel part and a second first conductive part, and the active layer pattern of the second transistor comprises a first second conductive part, a second channel part and a second second conductive part; The display substrate further comprises a conductive connection part, the conductive connection part is formed in a third source-drain metal layer; the conductive connection part is coupled with the second first conductive part through a via, and the conductive connection part is coupled with the first second conductive part through a via; The display substrate comprises a first array layer, a second array layer and a third array layer arranged on the substrate in sequence; The third transistor is formed by the first array layer; the fourth transistor is formed by the second array layer; the first transistor and the second transistor are formed by the third array layer; The first array layer comprises a first first gate metal layer; the third array layer comprises a third semiconductor layer and a third source-drain metal layer; The gate of the third transistor is arranged in the first first gate metal layer. 2.The display substrate of claim 1, wherein, The nth array layer comprises an nth semiconductor layer, an nth gate metal layer arranged on the substrate in sequence, and a gate insulating layer arranged between the nth semiconductor layer and the nth gate metal layer; The gate of the nth group of transistors is formed by the nth gate metal layer, and the active layer pattern of the nth group of transistors is formed by the nth semiconductor layer. 3.The display substrate of claim 1, wherein, The nth array layer further comprises an nth source-drain metal layer, and an nth interlayer dielectric layer arranged between the nth gate metal layer and the nth source-drain metal layer.

4. The display substrate of claim 1, wherein, The sub-pixel further comprises a light emitting element, and the display substrate further comprises an anode layer; the N array layers are arranged between the substrate and the anode layer; The anode of the light emitting element is formed by the anode layer.

5. The display substrate according to any one of claims 1 to 4, wherein, The display substrate further comprises an anode layer, and a semiconductor layer in at least one of the array layers is coupled to the anode layer through a via and the transfer conductive pattern. 6.The display substrate of claim 5, wherein, The transfer conductive pattern is formed by at least one metal layer in the array layers; or, The display substrate further comprises a transfer conductive layer, and the transfer conductive pattern is formed by the transfer conductive layer. 7.The display substrate of any one of claims 1 to 4, wherein, The semiconductor layer in a part of the N array layers is made of polysilicon, and the semiconductor layer in another part of the N array layers is made of oxide; or, the semiconductor layer in the N array layers is made of polysilicon. 8.The display substrate of any one of claims 1 to 4, wherein, The sub-pixel further comprises a fifth transistor, a sixth transistor, a reset control line, an initial voltage line, a data line, a gate line and a light emitting control line; The gate of the fifth transistor is coupled to the light emitting control line, the first electrode of the fifth transistor is coupled to a power voltage line, and the second electrode of the fifth transistor is coupled to the second electrode of the fourth transistor; The gate of the sixth transistor is coupled to the light emitting control line, the first electrode of the sixth transistor is coupled to the second electrode of the second transistor, and the second electrode of the sixth transistor is coupled to the anode of the light emitting element; The fifth transistor and the sixth transistor are formed by the first array layer. 9.The display substrate of claim 8, wherein, The sub-pixel further comprises a storage capacitor, the gate of the third transistor is coupled to a first plate of the storage capacitor, and the power voltage line is coupled to a second plate of the storage capacitor. 10.The display substrate of claim 8, wherein, The first transistor, the second transistor and the fourth transistor are all double-gate transistors; The first gate of the first transistor is coupled to the second gate of the first transistor, the first gate of the second transistor is coupled to the second gate of the second transistor, and the first gate of the fourth transistor is coupled to the second gate of the fourth transistor; The first gate is a top gate, and the second gate is a bottom gate. 11.The display substrate of claim 8, wherein, The semiconductor layer of the first array layer is made of polysilicon, and the semiconductor layers of the second array layer and the third array layer are both made of oxide; or, The semiconductor layers of the first array layer, the second array layer and the third array layer are all made of polysilicon. 12.The display substrate of claim 8, wherein, The first array layer comprises a first semiconductor layer, a first first gate insulating layer, a first first gate metal layer, a second first gate insulating layer and a second second gate metal layer arranged in sequence on the substrate; The display substrate further comprises a first isolation layer arranged between the first array layer and the second array layer; The second array layer comprises a second semiconductor layer, a second gate insulating layer, a second gate metal layer, a second interlayer dielectric layer and a second source-drain metal layer arranged in sequence on a side of the first isolation layer away from the substrate; The display substrate further comprises a second isolation layer arranged between the second array layer and the third array layer; The third array layer comprises a third semiconductor layer, a third gate insulating layer, a third gate metal layer, a third interlayer dielectric layer and a third source-drain metal layer arranged in sequence on a side of the second isolation layer away from the second array layer; The display substrate further comprises an anode layer arranged on a side of the third array layer away from the substrate, and a first planar layer arranged between the anode layer and the third array layer; the anode of the light-emitting element included in the sub-pixel is formed on the anode layer. 13.The display substrate of claim 12, wherein, The active layer pattern of the third transistor, the active layer pattern of the fifth transistor and the active layer pattern of the sixth transistor are formed by the first semiconductor layer, the gate of the third transistor, the gate of the fifth transistor and the gate of the sixth transistor are formed by the first gate metal layer, and the power voltage line is formed by the second first gate metal layer; The active layer pattern of the fourth transistor is formed by the second semiconductor layer, the gate of the fourth transistor is formed by the second gate metal layer, and the data line is formed on the second source-drain metal layer; The gate of the first transistor and the gate of the second transistor are formed by the third gate metal layer. 14.The display substrate of claim 13, wherein, The active layer pattern of the third transistor comprises a third channel portion, a first third conductive portion and a second third conductive portion, the first third conductive portion is multiplexed as a first electrode of the third transistor, and the second third conductive portion is multiplexed as a second electrode of the third transistor; The active layer pattern of the fifth transistor comprises a fifth channel portion, a first fifth conductive portion and a second fifth conductive portion, the first fifth conductive portion is multiplexed as a first electrode of the fifth transistor, and the second fifth conductive portion is multiplexed as a second electrode of the fifth transistor; The active layer pattern of the sixth transistor comprises a sixth channel portion, a first sixth conductive portion and a second sixth conductive portion, the first sixth conductive portion is multiplexed as a first electrode of the sixth transistor, and the second sixth conductive portion is multiplexed as a second electrode of the sixth transistor; The active layer pattern of the fourth transistor comprises a fourth channel portion, a first fourth conductive portion and a second fourth conductive portion; the first fourth conductive portion is multiplexed as a first electrode of the fourth transistor, and the second fourth conductive portion is multiplexed as a second electrode of the fourth transistor; The gate of the third transistor is coupled with the second electrode of the first transistor through a via, the first electrode of the third transistor is coupled with the second electrode of the fourth transistor through a via, and the first electrode of the third transistor is multiplexed as the second electrode of the fifth transistor; The second electrode of the third transistor is coupled with the second electrode of the second transistor through a via, and the second electrode of the third transistor is reused as the first electrode of the sixth transistor; The second electrode of the sixth transistor is coupled with the anode of the light emitting element through a via; One plate of the parasitic capacitance of the first node is composed of the gate of the third transistor, the second first conductive part, the conductive connection part and the first second conductive part. 15.The display substrate of claim 13, wherein, The display substrate further comprises a first insulating layer and a first metal layer arranged between the third gate metal layer and the third interlayer dielectric layer; the first metal layer is arranged between the first insulating layer and the third interlayer dielectric layer; The initial voltage line is formed by the first metal layer, and the initial voltage line is coupled with the first electrode of the first transistor through a via. 16.The display substrate of claim 14, wherein, The second gate metal layer comprises a first transfer conductive pattern, a second transfer conductive pattern and a third transfer conductive pattern; the second first gate metal layer comprises a fourth transfer conductive pattern; The second electrode of the second transistor is coupled with the first transfer conductive pattern through a via, and the first transfer conductive pattern is coupled with the second electrode of the third transistor through a via, so that the second electrode of the second transistor is coupled with the second electrode of the third transistor; The second electrode of the fourth transistor is coupled with the second transfer conductive pattern through a via, and the second transfer conductive pattern is coupled with the first electrode of the third transistor through a via, so that the second electrode of the fourth transistor is coupled with the first electrode of the third transistor; The anode of the light emitting element is coupled with the third transfer conductive pattern through a via, and the third transfer conductive pattern is coupled with the second electrode of the sixth transistor through a via, so that the anode of the light emitting element is coupled with the second electrode of the sixth transistor; The second electrode of the fourth transistor is coupled with the fourth transfer conductive pattern through a via, and the fourth transfer conductive pattern is coupled with the second electrode of the fifth transistor through a via, so that the second electrode of the fourth transistor is coupled with the second electrode of the fifth transistor.

17. A display device comprising: The display substrate comprises the display substrate as claimed in any one of claims 1 to 16. The display substrate comprises the display substrate as claimed in any one of claims 1 to 16.

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