Semiconductor element and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The semiconductor device primarily includes a magnetoresistive random access memory (MRAM) region and a logic region defined on a substrate. A first metal interconnect is disposed in the MRAM region, and a second metal interconnect is disposed in the logic region. A stop layer extends from the first metal interconnect to the second metal interconnect, and the stop layer on the first metal interconnect and the stop layer on the second metal interconnect have different thicknesses. A magnetic tunneling junction (MTJ) is disposed on the first metal interconnect.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor element, and in particular to a method for manufacturing a magnetoresistive random access memory (MRAM) element. Background Art

[0002] The magnetoresistance (MR) effect is known to occur when a material's electrical resistance changes with an applied magnetic field. Its physical quantity is defined as the difference in resistance in the presence and absence of a magnetic field divided by the original resistance, representing the rate of change of resistance. Currently, the magnetoresistance effect has been successfully applied to hard drive production and holds significant commercial value. Furthermore, by exploiting the characteristic of giant magnetoresistance materials exhibiting varying resistance values under different magnetization states, magnetic random access memory (MRAM) can be fabricated, which has the advantage of retaining stored data even when power is off.

[0003] The magnetoresistance effect is also used in the field of magnetic field sensing. For example, the electronic compass components of mobile phones equipped with the global positioning system (GPS) are used to provide information such as the user's movement direction. Currently, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned existing technologies generally include: occupying more chip area, more expensive manufacturing process, higher power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and further improvement is necessary. Summary of the Invention

[0004] One embodiment of the present invention discloses a semiconductor device comprising a magnetoresistive random access memory (MRAM) region and a logic region defined on a substrate. A first metal interconnect is disposed in the MRAM region, a second metal interconnect is disposed in the logic region, a stop layer extends from the first metal interconnect to the second metal interconnect, and the stop layer on the first metal interconnect and the stop layer on the second metal interconnect have different thicknesses. A magnetic tunneling junction (MTJ) is disposed on the first metal interconnect. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1 to 4 FIG. 1 is a schematic diagram of a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0006] Description of main component symbols

[0007] 12: Base

[0008] 14: MRAM area

[0009] 16:Logical Area

[0010] 18: Interlayer dielectric layer

[0011] 20: Metal interconnect structure

[0012] 22: Metal interconnect structure

[0013] 24: Intermetallic dielectric layer

[0014] 26: Metal interconnects

[0015] 28: Stop layer

[0016] 30: Intermetallic dielectric layer

[0017] 32: Metal interconnects

[0018] 34: Barrier layer

[0019] 36:Metal layer

[0020] 38:MTJ stacking structure

[0021] 42: Lower electrode

[0022] 44: Fixed layer

[0023] 46: Barrier layer

[0024] 48: Free layer

[0025] 50: Upper electrode

[0026] 52:MTJ

[0027] 54: Covering layer

[0028] 56: gap wall

[0029] 58: Intermetallic dielectric layer

[0030] 60: Barrier layer

[0031] 62:Metal layer

[0032] 64:Metal interconnect

[0033] 66: Stop layer DETAILED DESCRIPTION

[0034] Please refer to Figures 1 to 4 , Figures 1 to 4 FIG. 1 is a schematic diagram of a method for manufacturing an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.

[0035] The substrate 12 may include active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and dielectric layers such as an interlayer dielectric (ILD) 16 covering the substrate 12. More specifically, the substrate 12 may include planar or non-planar MOS transistors (e.g., fin-structured transistors), wherein the MOS transistors may include a gate structure (e.g., a metal gate) and transistor components such as source / drain regions, spacers, epitaxial layers, and contact etch stop layers. An interlayer dielectric 18 may be disposed on the substrate 12 and cover the MOS transistors. The interlayer dielectric 18 may have a plurality of contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistors. Since the manufacturing processes for planar or non-planar transistors and interlayer dielectrics are well known in the art, they are not further described here.

[0036] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plugs, wherein the metal interconnect structure 20 includes an intermetallic dielectric layer 24 and a metal interconnect 26 embedded in the intermetallic dielectric layer 24, and the metal interconnect structure 22 includes a stop layer 28, an intermetallic dielectric layer 30, and a metal interconnect 32 embedded in the stop layer 28 and the intermetallic dielectric layer 30.

[0037] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably comprises a trench conductor, while the metal interconnect 32 in the metal interconnect structure 22 disposed in the MRAM region 14 comprises a via conductor. Furthermore, each metal interconnect 26, 32 in each metal interconnect structure 20, 22 may be inlaid in the intermetal dielectric layer 24, 30 and / or the stop layer 28 using a single damascene process or a dual damascene process and electrically connected to each other. For example, each metal interconnect 26, 32 may further comprise a barrier layer 34 and a metal layer 36. The barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single damascene or dual damascene fabrication processes are well known in the art, they will not be further described here. Furthermore, in this embodiment, metal layer 36 in metal interconnect 26 preferably comprises copper, metal layer 36 in metal interconnect 32 preferably comprises tungsten, intermetallic dielectric layers 24 and 30 preferably comprise silicon oxide such as tetraethylorthosilicate (TEOS), and stop layer 28 comprises, but is not limited to, nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN).

[0038] Next, a lower electrode 42, an MTJ stack structure 38, a top electrode 50, and a patterned mask (not shown) are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 38 can be formed by first sequentially forming a pinned layer 44, a barrier layer 46, and a free layer 48 on the lower electrode 42. In this embodiment, the lower electrode 42 and the top electrode 50 preferably comprise a conductive material, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 44 can comprise a ferromagnetic material, such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), cobalt (Co), etc. In addition, the pinned layer 44 may also be made of an antiferromagnetic (AFM) material, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., to fix or limit the magnetic moment direction of the adjacent layer. The barrier layer 46 may be made of an insulating material including an oxide, such as aluminum oxide (AlO x ) or magnesium oxide (MgO), but are not limited thereto. The free layer 48 can be made of a ferromagnetic material, such as, but not limited to, iron, cobalt, nickel, or alloys thereof, such as cobalt-iron-boron (CoFeB). The magnetization direction of the free layer 48 is "free" to change in response to an external magnetic field.

[0039] Then as Figure 2As shown, one or more etching processes are performed using a patterned mask as a mask to remove a portion of the top electrode 50, a portion of the MTJ stack structure 38, a portion of the bottom electrode 42, and a portion of the intermetallic dielectric layer 30 to form the MTJ 52 in the MRAM region 14. It is noteworthy that the etching process performed in patterning the top electrode 50, the MTJ stack structure 38, the bottom electrode 42, and the intermetallic dielectric layer 30 in this embodiment may include a reactive ion etching process (RIE) and / or an ion beam etching process (IBE). Due to the characteristics of the ion beam etching process, the top surface of the remaining intermetallic dielectric layer 30 is preferably slightly lower than the top surface of the metal interconnect 32, and the top surface of the intermetallic dielectric layer 30 preferably has an arc or curved surface. It is also noteworthy that when the ion beam etching process is used in this embodiment to remove a portion of the intermetallic dielectric layer 30, a portion of the metal interconnect 32 is preferably removed at the same time, so that the metal interconnect 32 forms a sloped sidewall near the junction of the MTJ 62. A capping layer 54 is then formed on the MTJ 52 and covers the surface of the IMD layer 30. In this embodiment, the capping layer 54 preferably comprises silicon nitride, but other dielectric materials such as but not limited to silicon oxide, silicon oxynitride, or silicon carbide nitride may be selected based on manufacturing process requirements.

[0040] like Figure 3 As shown, an etching process is then performed to remove a portion of the capping layer 54 to form a spacer 56 that surrounds the MTJ 52 and simultaneously covers and contacts the sloped sidewalls of the metal interconnect 32. It is noteworthy that, in this stage, the etching process to remove the capping layer 54 to form the spacer 56 not only removes a portion of the capping layer 54 in the MRAM region 14 but also preferably simultaneously removes all of the capping layer 54, a portion of the inter-metal dielectric layer 30, and a portion of the stop layer 28 in the logic region 16, so that the overall thickness of the remaining stop layer 28 in the logic region 16 is slightly lower than the thickness of the stop layer 28 in the MRAM region 14. In this embodiment, the thickness of all or part of the remaining stop layer 28 in the logic region 16 is preferably approximately 0.45 to 0.8 times, or more preferably approximately 0.75 times, the thickness of the stop layer 28 in the MRAM region 14. The thickness of the stop layer 28 in the MRAM region 14 is preferably approximately 19-21 nanometers, while the thickness of the stop layer 28 in the logic region 16 is approximately 14-16 nanometers. The thickness of the stop layer 28 in the MRAM region 14 or the logic region 16 is preferably approximately one-eighth to one-tenth of the thickness of the subsequent intermetallic dielectric layer 58. The stop layers 28 in the MRAM region 14 and the logic region 16 preferably have uniform thickness and a flat surface.

[0041] Afterwards Figure 4As shown, another intermetallic dielectric layer 58 is first formed in the MRAM region 14 and the logic region 16. A planarization process, such as CMP, is used to align the top surface of the intermetallic dielectric layer 58 with the top surface of the top electrode 50. A pattern transfer process is then performed, for example, using a patterned mask to remove a portion of the intermetallic dielectric layer 58 in the logic region 16 to form a contact hole (not shown) and expose the underlying metal interconnect 26. The contact hole is then filled with a desired conductive material, such as a barrier layer 60 comprising titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and a low-resistance metal layer 62 selected from a low-resistance material such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof. A planarization process is then performed, such as chemical mechanical polishing (CMP), to remove a portion of the metal material to form a metal interconnect 64 within the contact hole, electrically connecting to the metal interconnect 26. Then, a stop layer 66 is formed on the IMD layer 58 and the metal interconnect 64. The stop layer 66 may include silicon dioxide, silicon nitride, or silicon carbon nitride (SiCN), and preferably includes silicon carbon nitride, but is not limited thereto.

[0042] In summary, the present invention primarily removes the capping layer, a portion of the intermetallic dielectric layer, and a portion of the stop layer from the logic region during the formation of the MTJ sidewall spacer. This allows the remaining stop layer thickness in the logic region to be slightly lower than the stop layer thickness in the MRAM region, or more specifically, to be controlled to be 0.75 times the stop layer thickness in the MRAM region. According to a preferred embodiment of the present invention, controlling the overall stop layer thickness in the logic region to be slightly lower than that in the MRAM region results in better breakdown voltage performance, thereby improving the reliability of the entire device.

[0043] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: Include: A substrate including a magnetoresistive random access memory (MRAM) area and a logic area; A first metal interconnect is provided in the magnetoresistive random access memory region; A second metal interconnect is provided in the logic area; a stop layer extending from the first metal interconnect to the second metal interconnect, wherein a thickness of the stop layer on the first metal interconnect is greater than a thickness of the stop layer on the second metal interconnect, and a top surface of the stop layer on the first metal interconnect is a flat surface; as well as A magnetic tunneling junction (MTJ) is provided on the first metal interconnect. 2 . The semiconductor device as claimed in claim 1 , further comprising a third metal interconnect disposed between the first metal interconnect and the magnetic tunnel junction. The semiconductor device as claimed in claim 2 , wherein the stop layer surrounds the third metal interconnect. 4 . The semiconductor device as claimed in claim 2 , wherein the first metal interconnect and the third metal interconnect comprise different materials.

5. The semiconductor device according to claim 2, further comprising: a first intermetallic dielectric layer surrounding the first metal interconnect and the second metal interconnect; a second intermetal dielectric layer surrounding the third metal interconnect; and A third intermetallic dielectric layer surrounds the magnetic tunnel junction. The semiconductor device as claimed in claim 1 , wherein a top surface of the first metal interconnect is flush with a top surface of the second metal interconnect.

Images