Preparation method for semiconductor device, semiconductor device and electronic apparatus

Abstract

Provided in the present disclosure are a preparation method for a semiconductor device, the semiconductor device and an electronic apparatus. The preparation method for a semiconductor device comprises: forming an active structure on a substrate; forming a first semiconductor structure; bonding the first semiconductor structure and a first carrier wafer and flipping same over; removing the substrate to expose a second active structure; forming a second semiconductor structure; bonding the second semiconductor structure and a second carrier wafer and flipping same over; removing the first carrier wafer to expose the first semiconductor structure; forming a first gate structure in the first semiconductor structure; forming first source-drain metal on a first source-drain structure; forming a first metal interconnect structure on a first transistor; bonding the first metal interconnect structure and a third carrier wafer and flipping same over; removing the second carrier wafer to expose the second semiconductor structure; and forming a second metal interconnect structure.

Description

[Amended according to Rule 26, July 22, 2024] Semiconductor device fabrication methods, semiconductor devices and electronic devices

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202410434413.4, filed on April 11, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor device, a semiconductor device, and an electronic device. Background Technology

[0004] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacking transistors, by integrating two or more layers of transistors in a vertical space, further increases transistor integration density and has become one of the important technologies for continuing the miniaturization of integrated circuits.

[0005] In the fabrication of transistors, the source and drain epitaxial structures are prepared at relatively high temperatures, while metal gates and metal interconnects can withstand lower processing temperatures. For stacked transistors, two layers of transistors and their interconnects need to be fabricated, and the thermal processes during the fabrication of the upper layer may affect the lower layer devices and interconnects.

[0006] Summary of the Invention

[0007] This disclosure provides a method for fabricating a semiconductor device, a semiconductor device, and an electronic device.

[0008] This disclosure provides a method for fabricating a semiconductor device, comprising: forming an active structure on a substrate; wherein the active structure includes a first active structure and a second active structure stacked in a first direction perpendicular to the substrate; forming a first semiconductor structure based on the first active structure, the first semiconductor structure including a first dummy gate structure and a first source / drain structure; bonding and flipping the first semiconductor structure with a first wafer carrier; removing the substrate and exposing a second active structure; forming a second semiconductor structure based on the second active structure, the second semiconductor structure including a second gate structure and a second source / drain structure; bonding and flipping the second semiconductor structure with a second wafer carrier; removing the first wafer carrier to expose the first semiconductor structure; removing the fill metal of the first dummy gate structure in the first semiconductor structure to form a first gate structure; forming a first source / drain metal on the first source / drain structure to form a first transistor; forming a first metal interconnect structure on the first transistor through a back-end process; bonding and flipping the first metal interconnect structure with a third wafer carrier; removing the second wafer carrier to expose the second semiconductor structure; and forming a second metal interconnect structure based on the second semiconductor structure.

[0009] The second aspect of this disclosure provides a semiconductor device, which is prepared by a method as described in the first aspect or any possible implementation thereof; the semiconductor device includes: a first transistor; a second transistor, the second transistor being disposed opposite to the first transistor; wherein a first active structure of the first transistor and a second active structure of the second transistor are formed in the same process, and the first transistor and the second transistor are self-aligned in the vertical direction.

[0010] A third aspect of this disclosure provides an electronic device. The electronic device includes: a circuit board and a semiconductor device as described in the second aspect, the semiconductor device being disposed on the circuit board.

[0011] Compared with the prior art, this disclosure has the following advantages:

[0012] This application provides a method for fabricating a semiconductor device. This method involves multiple wafer bonding and flipping processes, which forms the first gate structure and the first metal interconnect structure of the first transistor after the second source-drain structure of the second transistor. This avoids the high process temperature of the second transistor during the formation of the second source-drain structure from affecting the first gate structure and the first metal interconnect structure of the first transistor, thereby improving the thermal budget of the semiconductor device.

[0013] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of embodiments of this disclosure.

[0015] Figure 1 is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 2 is a top view of a semiconductor device provided according to an embodiment of the present disclosure.

[0017] Figures 3 to 17 are schematic diagrams illustrating the fabrication process of a semiconductor device according to embodiments of the present disclosure.

[0018] Figures 18 to 24 are schematic diagrams illustrating the fabrication process of a semiconductor device according to embodiments of the present disclosure.

[0019] Explanation of reference numerals in the attached figures

[0020] Semiconductor device 10; first transistor 11; second transistor 12; first dummy gate sidewall 111; first source / drain structure 112; first interlayer dielectric structure 113; first gate structure 114; first source / drain metal 115; first metal interconnect structure 116; second dummy gate sidewall 121; second source / drain structure 122; second interlayer dielectric structure 123; second gate structure 124; second source / drain metal 125; second metal interconnect structure 126; substrate 20; first active structure 21; second active structure 22; stacked structure 23; first dummy gate structure 24; shallow trench isolation structure 25; first insulating layer 26; first carrier wafer 27; second insulating layer 28; second carrier wafer 29; third insulating layer 30; third carrier wafer 31; first metal contact hole 32; second metal contact hole 33; first metal interconnect layer 34; second metal interconnect layer 35; first contact metal layer 36; second contact metal layer 37. Detailed Implementation

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure.

[0022] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments disclosed herein. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0023] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional stacking, can integrate two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. This technology is considered one of the key technologies for continuing the miniaturization of integrated circuits. There are at least two manufacturing processes for stacked transistors: monolithic and sequential.

[0024] The characteristics of the monolithic solution include: (1) It does not use wafer bonding technology, but instead fabricates N-type metal-oxide-semiconductor (NMOS) transistors and P-type metal-oxide-semiconductor (PMOS) transistors on the same substrate and stacks the two types of transistors vertically. This determines that the transistors in the same layer must be of the same type, i.e., NMOS or PMOS; (2) The transistors in the same layer must be strictly in the same plane space, and there is no alignment deviation. The advantage of the monolithic solution is that it has better integration density, while the disadvantages of the monolithic solution include the following: (1) The process is complex, requiring a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied upon to form a basic complementary metal-oxide-semiconductor circuit, resulting in poor design flexibility.

[0025] The sequential approach is characterized by wafer bonding and layer-by-layer processing to achieve vertical stacking of upper and lower transistors. Thanks to wafer bonding, the device structure, channel orientation, and even channel materials used in the upper and lower transistors can be optimized to obtain better and more matched device performance. However, the thermal process during the processing of the upper transistors may affect the lower transistors and interconnects, and the thermal budget must be strictly controlled throughout the processing. At the same time, the temperature that the subsequent interconnects can withstand is also limited, which will also limit the thermal budget. Therefore, the sequential approach currently faces the following technical challenges: (1) the fabrication of high-quality upper transistor active layers; (2) the thinning and defect control of the upper transistor bonding wafers; and (3) the alignment errors between the upper and lower transistors, which require extremely high photolithography precision.

[0026] The common technical challenges faced by the two schemes mentioned above include: (1) the thermal stability of the lower device when fabricating the upper device; (2) the performance of the upper device under low thermal budget; and (3) the metal interconnection of transistors between the upper and lower layers.

[0027] In the fabrication of transistors, the source and drain epitaxial structures are prepared at relatively high temperatures, while metal gates and metal interconnects can withstand lower processing temperatures. For stacked transistors, two layers of transistors and their interconnects need to be fabricated, and the thermal processes during the fabrication of the upper layer may affect the lower layer devices and interconnects.

[0028] To address the aforementioned technical problems, this disclosure provides a method for fabricating a semiconductor device to achieve self-alignment of the gate structure between upper and lower transistor layers.

[0029] In some embodiments, this disclosure provides a method for fabricating a semiconductor device. The method for fabricating a semiconductor device can be used to fabricate stacked transistors. FIG1 is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this disclosure. Referring to FIG1, the method for fabricating a semiconductor device may include steps S101 to S113.

[0030] Step S101: Form an active structure on a substrate; wherein the active structure includes a first active structure and a second active structure stacked in a first direction, the first direction being perpendicular to the substrate;

[0031] Step S102: Based on the first active structure, a first semiconductor structure is formed, the first semiconductor structure including a first dummy gate structure and a first source / drain structure;

[0032] Step S103: Bond the first semiconductor structure to the first carrier wafer and flip it over;

[0033] Step S104: Remove the substrate and expose the second active structure;

[0034] Step S105: Based on the second active structure, a second semiconductor structure is formed, the second semiconductor structure including a second gate structure and a second source / drain structure;

[0035] Step S106: Bond the second semiconductor structure to the second carrier wafer and flip it over;

[0036] Step S107: Remove the first carrier wafer to expose the first semiconductor structure;

[0037] Step S108: In the first semiconductor structure, remove the fill metal of the first dummy gate structure to form the first gate structure;

[0038] Step S109: Form a first source / drain metal on the first source / drain structure to form a first transistor;

[0039] Step S110: Form a first metal interconnect structure on the first transistor using a back-end process;

[0040] Step S111: Combine and flip the first metal interconnect structure with the third wafer carrier;

[0041] Step S112: Remove the second carrier wafer to expose the second semiconductor structure;

[0042] Step S113: Based on the second semiconductor structure, form a second metal interconnect structure.

[0043] It should be noted that the steps shown in Figure 1 are not exclusive, and other steps can be performed before, after, or between any of the steps shown in the operation; the order of the steps shown in Figure 1 can be adjusted according to actual needs.

[0044] Figure 2 is a top view of a semiconductor device according to an embodiment of the present disclosure, and Figure 2 has cross-sections AA', BB', and CC'. The AA' cross-section is a section cut along the gate structure of the semiconductor device; the BB' cross-section is a section cut along the source / drain structure of the semiconductor device; and the CC' cross-section is a section cut along the gate structure of the semiconductor device. Figures 3 to 17 are schematic diagrams of the fabrication process of a semiconductor device according to an embodiment of the present disclosure, wherein (a) in Figures 3 to 17 is a cross-sectional view along the dashed line AA' in Figure 2; (b) in Figures 3 to 17 is a cross-sectional view along the dashed line BB' in Figure 2; and (c) in Figures 3 to 17 is a cross-sectional view along the dashed line CC' in Figure 2.

[0045] The following description, in conjunction with Figures 1 to 17, will provide an exemplary account of the method for fabricating the semiconductor device 10 provided in the embodiments of this disclosure and the semiconductor device 10 obtained therefrom.

[0046] In step S101, an active structure is formed on the substrate 20.

[0047] In one embodiment, the active structure includes a first active structure 21 and a second active structure 22 stacked in a first direction. Here, the first direction is perpendicular to the substrate 20.

[0048] In some embodiments, the first active structure 21 and the second active structure 22 are two parts of an active structure, wherein the second active structure 22 is closer to the substrate 20 than the first active structure 21. Since the first active structure 21 and the second active structure 22 are formed by etching the substrate 20 in one step, the transistor formed according to the first active structure 21 and the second active structure 22 can achieve self-alignment of the active structure in a first direction, thereby achieving self-alignment of the first transistor 11 and the second transistor 12.

[0049] In some embodiments, in step S101, a semiconductor material layer may be grown on the substrate 20. By etching the semiconductor material layer, one or more active structures are formed on the substrate 20. The active structure may be divided into upper and lower parts, with the upper part (i.e., the first active structure 21) serving as the active structure of the first transistor 11 and the lower part (i.e., the second active structure 22) serving as the active structure of the second transistor 12.

[0050] In some embodiments, in step S101, a sacrificial layer and a silicon layer may be sequentially grown on the substrate 20. An active structure is formed on the substrate 20 by etching the sacrificial layer and the silicon layer. Exemplarily, a sacrificial layer (such as a silicon-germanium (SiGe) layer) is epitaxially grown on the bottom silicon layer (i.e., the substrate 20), and a top silicon layer is epitaxially grown above the sacrificial layer. The sacrificial layer protects the main structure of the top silicon layer, reduces external shocks and vibrations, improves the durability and reliability of the top silicon layer, and extends its service life.

[0051] In one embodiment, the thickness of the sacrificial layer is approximately 10nm-20nm, and the thickness of the top silicon layer is greater than 100nm. It should be noted that the thicknesses of the sacrificial layer and the top silicon layer can be selected according to actual application requirements. For example, in a fin field-effect transistor, the top silicon layer has a larger thickness to facilitate etching the fin structure; while in a gate-all-around transistor, the sacrificial layer and the silicon layer are stacked, with the sacrificial layer being a semiconductor material layer spaced apart in the stack. In this case, the thicknesses of both the sacrificial layer and the silicon layer are selected according to actual application requirements; this disclosure does not limit this aspect.

[0052] In one embodiment, anisotropic etching can be used to form an active structure extending in the same direction in the active region (see the finned structure in Figure 4). Of course, in other types of transistors, the finned structure can also be replaced by parallel nanosheets, bulk planar structures, etc. When the active structure is a finned structure, the first transistor 11 and the second transistor 12 can be fin field-effect transistors (FinFETs); when the active structure is multiple parallel nanosheets, the first transistor 11 and the second transistor 12 can be gate-all-around field-effect transistors (GAAFETs); when the active structure is a bulk planar structure, the first transistor 11 and the second transistor 12 are planar transistors.

[0053] In some embodiments, the first transistor 11 and the second transistor 12 can be transistors of different types. For example, one transistor is a fin field-effect transistor and the other is a gate-all-around transistor; or, one transistor is a fin field-effect transistor and the other is a planar transistor; or, one transistor is a gate-all-around transistor and the other is a planar transistor.

[0054] In one embodiment, firstly, a stacked structure 23 is epitaxially formed on a substrate 20, as shown in FIG3; then, the stacked structure 23 is etched to form an active structure, as shown in FIG4. The active structure includes a first active structure 21 and a second active structure 22.

[0055] In one embodiment, the substrate 20 can be a silicon (Si) substrate or a silicon-on-insulator (SOI) substrate. Of course, the substrate 20 can also be other semiconductor materials, and this disclosure does not limit this. It should be noted that the etching process mentioned in this disclosure can include any of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal processes, and this disclosure does not limit this.

[0056] In some embodiments, after the active structure is formed by S101, ion implantation can be performed at the junction of the first active structure 21 and the second active structure 22 of the active structure to form an electrical isolation layer, which is used to electrically isolate the first active structure 21 and the second active structure 22.

[0057] For example, the ions implanted can include P-type ions, N-type ions, oxygen ions, etc. Specifically, P-type ions can be one of the following: boron (B), gallium (Ga), or aluminum (Al). N-type ions can be one of the following: phosphorus (P), arsenic (As), or antimony (Sb).

[0058] In step S102, a first semiconductor structure is formed based on the first active structure 21.

[0059] In one embodiment, the first semiconductor structure may include a first dummy gate structure 24 and a first source / drain structure 112.

[0060] In some embodiments, in step S102, a pseudo-gate material can be deposited on the first active structure 21 to form a first pseudo-gate structure 24, as shown in FIG7; then, a sidewall is deposited around the first pseudo-gate structure 24, and a first source / drain structure 112 is epitaxially grown on the first active structure 21 and filled with interlayer dielectric material to form a first interlayer dielectric structure 113, as shown in FIG8.

[0061] It should be noted that the dummy gate material can define the shape, structure, and size of the subsequent gate structure. Furthermore, compared to metal gates, the dummy gate structure formed by the dummy gate material has higher temperature resistance, which is beneficial for the formation of the source / drain structure.

[0062] It should be noted that the pseudo-gate structure needs to be replaced with a metal gate in subsequent processes to meet the electrical performance requirements of the device (i.e., metal gate replacement process).

[0063] In one example, the dummy gate material can be polycrystalline silicon or amorphous silicon.

[0064] In one example, the interlayer dielectric material can be silicon oxide, silicon nitride, etc.

[0065] In some embodiments, after forming the active structures, trenches are formed in the regions between adjacent active structures. Oxide is filled in the trenches to form a shallow trench isolation (STI) structure 25, as shown in FIG5. Next, after forming the shallow trench isolation structure 25, it is etched until the first active structure 21 is exposed and flush with the connection between the first active structure 21 and the second active structure 22, i.e., the upper half of the shallow trench isolation structure 25 is removed, as shown in FIG6. Then, a semiconductor material (such as polysilicon) is deposited in the gate region above the etched shallow trench isolation structure 25, thus forming the first dummy gate structure 24, as shown in FIG7. In one example, the first dummy gate structure 24 covers the first active structure 21.

[0066] In some embodiments, after the first pseudo-gate structure 24 is formed, first pseudo-gate sidewalls 111 can be formed on both sides of the first pseudo-gate structure 24, and the first pseudo-gate sidewalls 111 can be used as masks to form source structure and drain structure (i.e., first source-drain structure 112).

[0067] In some embodiments, the oxide forming the shallow trench isolation structure 25 can be silicon dioxide (SiO2), silicon oxycarbide (SiCO), etc. In some embodiments, the solvent used to etch the shallow trench isolation structure 25 can be a DHF solution (including hydrofluoric acid (HF), hydrogen peroxide (H2O2), and water (H2O)) or a buffered oxide etch (BOE) solution. The solvent used in the etching process in this embodiment can be selected according to actual conditions and is not limited to the aforementioned DHF solution or BOE solution.

[0068] In some embodiments, to facilitate subsequent processing, after forming the first pseudo-gate structure 24, the shallow trench isolation structure 25 can also be polished or chemical-mechanical planarization (CMP) treated so that when the shallow trench isolation structure 25 is etched in a subsequent manner, the etching depth of the shallow trench isolation structure 25 in different regions is the same, thereby making the top height of the exposed active structure the same.

[0069] In some embodiments, after the first dummy gate structure 24 is fabricated, a first source / drain structure 112 is formed on both sides of the first dummy gate structure 24 based on the first active structure 21. Here, the first source / drain structure 112 can be understood as the source structure and / or drain structure of the first transistor 11. Next, an interlayer dielectric material (such as silicon dioxide) is deposited on the first source / drain structure 112 to form a first interlayer dielectric structure 113, as shown in FIG8. Thus, the fabrication of the first semiconductor structure is completed.

[0070] In this embodiment of the disclosure, since only the first pseudo-gate structure 24 and the first source-drain structure 112 are prepared when the first semiconductor structure is prepared in step S102 above, and the gate dielectric, metal gate, metal interconnect structure, etc. are not prepared, the preparation of the second source-drain structure 122 of the second transistor 12 will not affect the gate dielectric, metal gate, and metal interconnect structure in the first transistor 11, thereby effectively improving the thermal budget of the semiconductor device.

[0071] In step S103, the first semiconductor structure is bonded to and flipped with the first carrier wafer 27.

[0072] In some embodiments, in step S103, after forming the first semiconductor structure, an insulating material (such as silicon oxide) is deposited on top of the first semiconductor structure to form a first insulating layer 26; the formed first insulating layer 26 may be planarized using a CMP process; subsequently, the planarized first insulating layer 26 may be bonded to the first carrier wafer 27. Then, the substrate 20 may be flipped so that the first semiconductor structure is placed downwards and the substrate 20 is placed upwards.

[0073] In step S104, the substrate 20 is removed, and the second active structure 22 is exposed.

[0074] In some embodiments, after flipping the substrate 20, wafer thinning, such as a CMP process, can be performed to remove the substrate 20 and expose the surface of the second active structure 22, as shown in FIG9. Next, the lower half of the shallow trench isolation structure 25 is removed by etching to expose the second active structure 22 covered by the shallow trench isolation structure 25, as shown in FIG10.

[0075] In some embodiments, when removing the lower half of the shallow trench isolation structure 25, a portion of the shallow trench isolation structure 25 may be retained as an isolation layer to isolate the first transistor 11 and the second transistor 12.

[0076] In step S105, a second semiconductor structure is formed based on the second active structure 22.

[0077] In one embodiment, the second semiconductor structure includes a second gate structure 124 and a second source / drain structure 122.

[0078] In some embodiments, after exposing the second active structure 22, front-end processes can be performed first. First, a semiconductor material (such as polysilicon) is deposited in the gate region above the etched shallow trench isolation structure 25, thus forming the second dummy gate structure. Here, the second dummy gate structure covers the second active structure 22. Next, a source structure and a drain structure (i.e., the second source-drain structure 122) are formed on both sides of the second dummy gate structure based on the second active structure 22. Here, the second source-drain structure 122 can be understood as the source structure and / or drain structure of the second transistor 12. Next, an interlayer dielectric material (such as silicon dioxide) is deposited on the second source-drain structure 122 and the retained shallow trench isolation structure 25 to form the second interlayer dielectric structure 123. This completes the fabrication of the second semiconductor structure.

[0079] In one embodiment, after the second semiconductor structure is formed, the second dummy gate structure can be removed by an etching process to deposit metal material at the etched second dummy gate structure to form the second gate structure 124, that is, the gate structure of the second transistor 12, as shown in FIG11.

[0080] It should be noted that when the gate structure of the second transistor 12 is being fabricated, the gate dielectric, metal gate, and metal interconnect structure of the first transistor 11 have not yet been formed, so the thermal budget is basically unrestricted.

[0081] In some embodiments, the second gate structure 124 can be formed using a metal substitution gate process, in which case the second gate structure 124 can be a high-k metal gate (HKMG), where k refers to the dielectric constant. After fabricating and removing the second dummy gate structure, a gate dielectric layer can be deposited on the surface of the second active structure 22 to isolate the second active structure 22 from the second gate structure 124. In one example, the gate dielectric layer is formed of a high-k material.

[0082] In step S106, the second semiconductor structure is bonded to and flipped with the second carrier wafer 29.

[0083] In some embodiments, in step S106, after forming the second semiconductor structure, an insulating material (such as silicon oxide) is deposited on top of the second semiconductor structure to form a second insulating layer 28, and the second insulating layer 28 is bonded to the second carrier wafer 29. Then, the second carrier wafer 29 can be flipped so that the second semiconductor structure is placed downwards and the first carrier wafer 27 is placed upwards, as shown in FIG12.

[0084] It is understood that when the second semiconductor structure includes the second gate structure 124 and the second source / drain structure 122, depositing insulating material on top of the second semiconductor structure may include depositing insulating material on the second gate structure 124 and the second interlayer dielectric structure 123 to form the second insulating layer 28.

[0085] In step S107, the first carrier wafer 27 is removed to expose the first semiconductor structure.

[0086] In some embodiments, after flipping the first carrier wafer 27, a CMP process can be used to thin the wafer until the first dummy gate structure 24 is exposed, i.e., the first insulating layer 26 and the first carrier wafer 27 are removed, as shown in FIG13.

[0087] In step S108, the fill metal of the first dummy gate structure 24 is removed from the first semiconductor structure to form the first gate structure 114.

[0088] In some embodiments, in step S108, the first dummy gate structure 24 may be removed using a countable process. Then, metal material is filled at the removed first dummy gate structure 24 to form a first gate structure 114, as shown in FIG14.

[0089] In some embodiments, the first gate structure 114 can be formed using a metal substitution gate process, in which case the first gate structure 114 can be an HKMG. Then, after removing the first dummy gate structure 24, a gate dielectric layer can be deposited on the surface of the first active structure 21 to isolate the first active structure 21 from the first gate structure 114. In one example, the gate dielectric layer is formed of a high-K material.

[0090] In some embodiments, the shallow trench isolation structure 25 may not be provided between the first gate structure 114 and the second gate structure 124, depending on the actual situation. In one example, before forming the first gate structure 114, the shallow trench isolation structure 25 is etched until the second gate structure 124 is exposed, forming a gate direct connection trench. Metal is deposited on the second gate structure to form the first gate structure 114. In this way, the first transistor 11 and the second transistor 12 can be interconnected through the contact of their gate structures without the need for interconnect wires.

[0091] In the embodiments of this disclosure, the metal materials used to prepare the first gate structure 114 and the metal materials used to prepare the second gate structure 124 may be the same or different metal materials depending on the actual situation, and this disclosure does not limit this.

[0092] In the embodiments disclosed herein, the metal material may be one of the following: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), or titanium aluminum nitride (TiAlN). The selection may be made according to the actual situation and is not limited to the metal materials listed above.

[0093] In step S109, a first source-drain metal 115 is formed on the first source-drain structure 112 to form a first transistor 11.

[0094] In some embodiments, the first interlayer dielectric structure 113 located above the first source / drain structure 112 is etched until the first source / drain structure 112 is exposed. Then, metal material is deposited at the etched area to form the first source / drain metal 115. This completes the front-end process of the first transistor 11, resulting in the first transistor 11, as shown in FIG14.

[0095] In step S110, a first metal interconnect structure 116 is formed on the first transistor 11.

[0096] In some embodiments, still referring to FIG14, a mid-process is used to deposit an interlayer dielectric material (such as silicon dioxide) on the first source / drain metal 115 to form an interlayer dielectric, and a first metal contact hole 32 of the first source / drain structure 112 is formed on the interlayer dielectric layer. Then, a back-process is used to form a first metal interconnect layer 34 on the interlayer dielectric layer. At this point, the first metal interconnect structure 116 is formed.

[0097] In one embodiment, the interlayer dielectric layer having the first metal contact hole 32 forms the first contact metal layer 36.

[0098] In step S111, the first metal interconnect structure 116 and the third carrier wafer 31 are bonded together and flipped.

[0099] In some embodiments, in step S111, after forming the first metal interconnect structure 116, an insulating material (such as silicon oxide) is deposited on top of the first metal interconnect structure 116 to form a third insulating layer 30; the formed third insulating layer 30 may be planarized using a CMP process; subsequently, the planarized third insulating layer 30 may be bonded to the third carrier wafer 31. Then, the third carrier wafer 31 may be flipped so that the first transistor 11 is placed downwards again and the second carrier wafer 29 is placed upwards, as shown in FIG15.

[0100] In step S112, the second carrier wafer 29 is removed to expose the second semiconductor structure.

[0101] In some embodiments, after flipping the second carrier wafer 29, a CMP process can be used to thin the wafer until the second gate structure 124 is exposed, i.e., the second insulating layer 28 and the second carrier wafer 29 are removed, as shown in FIG16.

[0102] It is understandable that when the second semiconductor structure includes the second gate structure 124 and the second source / drain structure 122, the second gate structure 124 and the second interlayer dielectric structure 123 can be exposed after the second carrier wafer 29 is removed.

[0103] In step S113, a second metal interconnect structure 126 is formed based on the second semiconductor structure.

[0104] In some embodiments, referring to FIG17, the second interlayer dielectric structure 123 located above the second source / drain structure 122 is etched until the second source / drain structure 122 is exposed. Then, a metal material is deposited at the etched area to form the second source / drain metal 125. This completes the front-end process of the second transistor 12. Then, using a mid-end process, an interlayer dielectric material (such as silicon dioxide) is deposited on the second source / drain metal 125 to form the interlayer dielectric, and a second metal contact hole 33 of the second source / drain structure 122 is fabricated on the interlayer dielectric layer. Then, using a back-end process, a second metal interconnect layer 35 is formed on the interlayer dielectric layer. This completes the second metal interconnect structure 126.

[0105] It should be noted that the interlayer dielectric layer with the second metal contact hole 33 forms the second contact metal layer 37, which is formed on the second gate structure 124 and the second source / drain metal 125. A second metal interconnect layer 35 can be formed on the second contact metal layer 37 to obtain the second metal interconnect structure 126.

[0106] It is understandable that the metal material forming the second metal contact hole 33 can be a high-temperature resistant material. In one example, the metal material forming the second metal contact hole 33 can be tungsten (W), cobalt (Co), etc.

[0107] This completes the fabrication of the semiconductor device in the embodiments of this disclosure.

[0108] In this embodiment of the disclosure, by multiple wafer bonding and flipping, the first gate structure and the first metal interconnect structure of the first transistor are formed after the second source-drain structure of the second transistor. This avoids the high process temperature of the second transistor during the formation of the second source-drain structure from affecting the first gate structure and the first metal interconnect structure of the first transistor, thereby improving the thermal budget of the semiconductor device.

[0109] Figures 18 to 24 are schematic diagrams of the fabrication process of a semiconductor device according to an embodiment of the present disclosure, wherein (a) in Figures 18 to 24 is a cross-sectional view along the direction of the dashed line AA' in Figure 2; (b) in Figures 18 to 24 is a cross-sectional view along the direction of the dashed line BB' in Figure 2; and (c) in Figures 18 to 24 is a cross-sectional view along the direction of the dashed line CC' in Figure 2.

[0110] The following description, in conjunction with Figures 1 to 2 and Figures 18 to 24, will provide an exemplary account of the method for fabricating the semiconductor device 10 provided in the embodiments of this disclosure and the semiconductor device 10 obtained therefrom.

[0111] In some embodiments, during the above-described fabrication process, to simplify the process flow while increasing the thermal budget of the stacked transistor fabrication process, step S201 can also be performed during the fabrication of the second semiconductor structure via step S105. In this case, the second semiconductor structure further includes a second source / drain metal 125 and a second contact metal layer 37. The second source / drain metal 125 is formed by depositing metal on the second source / drain structure 122, and the second contact metal layer 37 is formed on the second gate structure 124 and the second source / drain metal 125.

[0112] In step S201, a second source / drain metal 125 and a second contact metal layer 37 are formed based on the second active structure 22.

[0113] In some embodiments, referring to FIG10, after steps S101 to S104, the exposed second active structure 22 can be obtained. Subsequently, referring to FIG11, the second source / drain structure 122, the second interlayer dielectric structure 123, and the second gate structure 124 can be formed through step S105. Subsequently, the second source / drain metal 125 and the second contact metal layer 37 can also be formed through step S201.

[0114] In one embodiment, a second interlayer dielectric structure 123 located above the second source / drain structure 122 may be etched until the second source / drain structure 122 is exposed. Then, a metal material is deposited at the etched area to form a second source / drain metal 125. An interlayer dielectric layer is formed on the second interlayer dielectric structure 123 and the second source / drain metal 125, and a second metal contact hole 33 for the second source / drain structure 122 is fabricated on the interlayer dielectric layer, as shown in FIG18.

[0115] It should be noted that the interlayer dielectric layer with the second metal contact hole 33 forms the second contact metal layer 37, which is formed on the second gate structure 124 and the second source / drain metal 125. Here, the metal material forming the second metal contact hole 33 can be a high-temperature resistant tungsten, cobalt, or other metal material.

[0116] It should be noted that the process temperature during steps S108 and S109 is higher than the process temperature for forming the second contact metal layer 37. Therefore, the second contact metal layer 37 is made of a high-temperature resistant metal material, which can avoid the impact on the second contact metal layer 37 during steps S108 and S109.

[0117] It should be noted that the fabrication of the second contact metal layer 37 facilitates the photolithographic alignment of the front and back transistors.

[0118] In some embodiments, after performing step S201, the front-end and middle-end processes of the second transistor 12 can be completed. Next, step S106 can be performed, as shown in FIG19, to bond the second semiconductor structure to the second carrier wafer 29, including: bonding the second contact metal layer 37 to the second carrier wafer 29.

[0119] It is understood that after the second contact metal layer 37 is formed, an insulating material (such as silicon oxide) can be deposited on top of the second contact metal layer 37 to form a second insulating layer 28, and the second insulating layer 28 can be bonded to the second carrier wafer 29 to obtain the structure shown in FIG19.

[0120] In some embodiments, after performing step S106, steps S107 to S111 may be performed.

[0121] Referring to Figures 20 to 22, after forming the second semiconductor structure (including the second source / drain metal 125 and the second contact metal layer 37), the steps in one or more of the above embodiments can be used to complete the second wafer flipping and then re-fabricate the first transistor 11.

[0122] In one embodiment, the second carrier wafer 29 is first flipped so that the second semiconductor structure faces downwards and the first semiconductor structure and the first carrier wafer 27 face upwards. Then, a CMP process is used to thin the wafer until the first dummy gate structure 24 is exposed, as shown in FIG20. Subsequently, a replacement metal gate (RMG) process is used to form the first gate structure 114, a first source / drain metal 115 is formed on the first source / drain structure 112 using the process of the first interlayer dielectric structure 113, and a first metal interconnect structure 116 is formed using a mid-to-back-end process, as shown in FIG21. Then, the first metal interconnect structure 116 is bonded to and flipped with the third carrier wafer 31 so that the third carrier wafer 31 faces downwards and the second carrier wafer 29 faces upwards, as shown in FIG22.

[0123] In some embodiments, after performing step S111, step S112 can be performed to remove the second carrier wafer 29 to expose the second semiconductor structure (including the second source / drain metal 125 and the second contact metal layer 37). In one example, the second contact metal layer 37 can be exposed after wafer thinning using a CMP process, as shown in FIG23. Subsequently, step S113 is performed to form a second metal interconnect layer 35 on the second contact metal layer 37 through a back-end process to form a second metal interconnect structure 126, as shown in FIG24.

[0124] This completes the fabrication of the semiconductor device 10 in this embodiment of the present disclosure.

[0125] In this embodiment of the disclosure, by multiple wafer bonding and flipping, the first gate structure and the first metal interconnect structure of the first transistor are formed after the second source-drain structure of the second transistor. This avoids the high process temperature of the second transistor during the formation of the second source-drain structure from affecting the first gate structure and the first metal interconnect structure of the first transistor, thereby improving the thermal budget of the semiconductor device.

[0126] In some embodiments, this disclosure provides a semiconductor device. As shown in Figures 18 and 24, the semiconductor device 10 is fabricated using the methods described in one or more of the above embodiments. The semiconductor device 10 includes a first transistor 11 and a second transistor 12. The second transistor 12 is disposed opposite to the first transistor 11. The first active structure 21 of the first transistor 11 and the second active structure 22 of the second transistor 12 are formed in the same process, and the first transistor 11 and the second transistor 12 are self-aligned in the vertical direction.

[0127] In one embodiment, the vertical direction refers to the direction perpendicular to the substrate forming the semiconductor device 10. Self-alignment of the first transistor 11 and the second transistor 12 means that the gate region of the first transistor 11 is aligned with the gate region of the second transistor 12, and the source / drain regions of the first transistor 11 are aligned with the source / drain regions of the second transistor 12.

[0128] In one example, the gate region refers to the region that forms the gate structure; the source / drain region refers to the region that forms the source / drain structure.

[0129] It is understood that, in the fabrication process of the semiconductor device in this embodiment, a deep STI and a relatively high active region are first formed by etching. Then, the source-drain structure of a first transistor is fabricated above this active region. Following this, a wafer flipping process is performed, exposing the lower part of the active region through self-aligned etching, while simultaneously forming a partial structure of a second transistor. After the partial structure of the second transistor is fabricated, another wafer flipping is performed to complete the subsequent fabrication of the first transistor. A third wafer flipping is then performed to complete the subsequent fabrication of the second transistor.

[0130] In one embodiment, the dummy gate and source / drain fabrication in the upper and lower transistor layers are performed using multiple flip-flops, replacing the metal gate process. The sequence of processes such as the mid-stage (MOL) and back-end (BEOL) processes is optimized to prioritize the fabrication of the high-temperature resistant source / drain structures. This effectively improves the thermal budget in subsequent fabrication processes, solving the technical problem that the source / drain fabrication process temperature of transistors is high, while the process temperature that metal gates and metal interconnects can withstand is low, resulting in a limited thermal budget for stacked transistors.

[0131] It should be noted that the first and second fabrication processes of the semiconductor device described above are merely two exemplary embodiments embodying the technical concept of this disclosure. It should be understood that any technical solution that forms the first gate structure and the first metal interconnect structure of the first transistor after the second source-drain structure of the second transistor, thereby avoiding the influence of the process temperature during the formation of the second source-drain structure on the first gate structure and the first metal interconnect structure of the first transistor, is within the protection scope of this disclosure.

[0132] In one example, a two-stage wafer flipping scheme exists. This scheme uses a standard process flow to etch a deep STI (Silicon Tilt) and a high active region onto the original silicon substrate, and deposit a dummy gate to form the source / drain structure of the first transistor. Subsequently, the first transistor is bonded to a first carrier wafer, undergoing a first wafer flipping to place the substrate on the front side. Then, a standard STI etching and active region exposure process is used to expose the active region of the second transistor in a self-aligned manner. After completing the front-end, middle-end, and back-end processes of the second transistor (i.e., fabricating the metal interconnect layer to the second transistor, with each interconnect using a high-temperature resistant material to improve the thermal budget of subsequent processes), the second transistor is bonded to a second carrier wafer, undergoing a second wafer flipping. After the second wafer flipping, the first carrier wafer is removed, exposing the first transistor, where the gate forming process, as well as the middle-end and back-end processes, are completed.

[0133] This disclosure optimizes the process flow of stacked transistors and also addresses issues such as the consistency of active regions and gates of upper and lower transistors, defect density, alignment, and thermal budget. This disclosure employs a multi-flipping scheme, considering the fabrication sequence of the stacked transistor device structure and its subsequent interconnects, thereby improving the overall thermal budget of the device fabrication process. This disclosure solves the long-standing problems of complex processes and fixed polarity inherent in existing monolithic stacked transistor solutions. This disclosure also solves the long-standing problems of alignment difficulties and high defect density in upper semiconductor materials inherent in existing sequential stacked transistor solutions. This disclosure promotes the industrialization of transistor stacking technology.

[0134] The solution presented in this disclosure is an organic integration of current sequential and monolithic stacked transistor solutions. It boasts high reusability of mature technologies, avoiding extensive and costly process development to save costs, thus demonstrating high feasibility. Furthermore, in this disclosure, the flip-chip transistor employs a self-aligned "back-to-back" active region and metal gate design. The front and back transistors have independent signal and power supply networks, interconnected through local interconnects. Without altering the ultra-miniaturized 4T track cell design, it significantly frees up metal wiring resources (improving by over 60% compared to current solutions), offering enormous potential for collaborative optimization in process design. Finally, the flip-chip transistor solution is compatible with existing mainstream device architectures, enabling front and back stacking of planar transistors, fin transistors, all-around gate transistors, and even vertical transistors without requiring special process development for specific device architectures. This high flexibility and strong scalability from the perspective of semiconductor process node iteration make it highly advanced conceptually, possessing significant industrial value, strong practicality, and broad expansion prospects.

[0135] In some embodiments, this disclosure provides an electronic device. The electronic device includes a circuit board and a semiconductor device as described in one or more of the above embodiments, the semiconductor device being disposed on the circuit board.

[0136] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0137] The above description is merely an exemplary embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating semiconductor devices, wherein, include: An active structure is formed on a substrate; wherein the active structure includes a first active structure and a second active structure stacked in a first direction perpendicular to the substrate; Based on the first active structure, a first semiconductor structure is formed, the first semiconductor structure including a first pseudo-gate structure and a first source-drain structure; The first semiconductor structure is bonded to the first carrier wafer and flipped; Remove the substrate and expose the second active structure; Based on the second active structure, a second semiconductor structure is formed, the second semiconductor structure including a second gate structure and a second source / drain structure; The second semiconductor structure is bonded to the second carrier wafer and flipped; Remove the first carrier wafer to expose the first semiconductor structure; In the first semiconductor structure, the fill metal of the first dummy gate structure is removed to form a first gate structure; A first source / drain metal is formed on the first source / drain structure to form a first transistor; A first metal interconnect structure is formed on the first transistor using a subsequent process; The first metal interconnect structure is combined and flipped with the third wafer carrier bond; Remove the second carrier wafer to expose the second semiconductor structure; A second metal interconnect structure is formed based on the second semiconductor structure.

2. The method according to claim 1, wherein, The formation of a second metal interconnect structure based on the second semiconductor structure includes: A second source / drain metal is formed on the second source / drain structure to form a second transistor; The second metal interconnect structure is formed on the second transistor.

3. The method according to claim 1, wherein, The second semiconductor structure further includes: a second source / drain metal and a second contact metal layer, wherein the second source / drain metal is formed by depositing metal on the second source / drain structure, and the second contact metal layer is formed on the second gate structure and the second source / drain metal; The formation of a second metal interconnect structure based on the second semiconductor structure includes: A second metal interconnect layer is formed on the second contact metal layer through a subsequent process to form a second metal interconnect structure.

4. The method according to claim 3, wherein, The second contact metal layer is formed using a high-temperature resistant metal material.

5. The method according to claim 1, wherein, After forming the active structure on the substrate and before forming the first semiconductor structure based on the first active structure, the method further includes: Semiconductor material is deposited on the substrate to form a shallow trench isolation layer, the shallow trench isolation layer encapsulating the second active structure, and the first active structure being exposed outside the shallow trench isolation layer.

6. The method according to claim 5, wherein, The removal of the substrate and exposure of the second active structure includes: The substrate and a portion of the shallow trench isolation layer are removed by a chemical mechanical polishing process to expose the second active structure.

7. The method according to claim 1, wherein, An electrical isolation layer is formed at the junction of the first active structure and the second active structure by ion implantation, and the electrical isolation layer is used to electrically isolate the first active structure and the second active structure.

8. The method according to claim 1, wherein, The first transistor is one of a fin field-effect transistor, a gate-all-around transistor, and a planar transistor.

9. A semiconductor device, said semiconductor device being prepared by the method according to any one of claims 1 to 8; wherein, The semiconductor device includes: First transistor; The second transistor is positioned opposite to the first transistor; The first active structure of the first transistor and the second active structure of the second transistor are formed through the same process, and the first transistor and the second transistor are self-aligned in the vertical direction.

10. An electronic device, wherein, include: The circuit board and the semiconductor device as described in claim 9, wherein the semiconductor device is disposed on the circuit board.

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