Integrated circuit device

Abstract

The present disclosure provides an integrated circuit device in which a capacitor is connected between two vias through a passivation stack to couple a power supply contact to a metal interconnect structure. By providing enough high capacitance and enough low equivalent series resistance for the capacitor, the noise in the power supply can be effectively filtered. The capacitor may have a trench capacitance structure as part of a solution for providing sufficiently high capacitance. Placing all or part of the capacitor within the passivation stack allows the capacitor to be implemented without moving the wiring or device in the metal interconnect structure.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit device. Background Technology

[0002] The integrated circuit (IC) manufacturing industry has experienced exponential growth over the past few decades. As ICs have evolved, functional density (the number of interconnects per unit chip area) has increased while feature size has decreased. Today's ICs may contain millions or billions of transistors and other devices with complex relationships. Utility Model Content

[0003] According to some embodiments of this disclosure, an integrated circuit (IC) device includes a substrate, a metal interconnect structure above the substrate, and a passivation stack above the metal interconnect structure. The metal interconnect structure includes a first conductive line and a second conductive line. A first contact and a second contact are disposed above the passivation stack. A first via extending through the passivation stack connects the first contact to the first conductive line. A second via extending through the passivation stack connects the second contact to the second conductive line. A metal-insulator-metal (MIM) capacitor having a trench capacitor structure is connected between the first via and the second via.

[0004] According to some embodiments of this disclosure, an integrated circuit (IC) device includes a semiconductor substrate, a metal interconnect structure on the semiconductor substrate, a dielectric structure on the metal interconnect structure, first and second contacts on the dielectric structure, and a capacitor. The capacitor includes a first plate and a second plate separated from each other by a capacitor dielectric layer. A first via passes through the dielectric structure and couples the first contact to the metal interconnect structure. A second via passes through the dielectric structure and couples the second contact to the metal interconnect structure. The first via passes through and contacts the first plate. The second via passes through and contacts the second plate. The first plate includes a first vertical portion disposed between first two sidewalls of the dielectric structure. The second plate includes a second vertical portion disposed between the first two sidewalls of the dielectric structure.

[0005] According to some embodiments of this disclosure, a method for forming an IC device includes: providing a semiconductor substrate having a first contact region and a second contact region; forming a metal interconnect structure including a plurality of metallization layers on the semiconductor substrate; forming a first dielectric layer over the metal interconnect structure; forming a trench extending to the first dielectric layer; forming a first electrode metal layer over the first dielectric layer and within the trench; forming a first mask and etching to selectively remove the first electrode metal layer from the first contact region; forming a capacitor dielectric layer and a second electrode metal layer over the first electrode metal layer; and forming a first mask and etching to selectively remove the first electrode metal layer from the first contact region. A second dielectric layer is formed above the second electrode metal layer, and holes are etched out, wherein the holes include a first hole in the first contact region and a second hole in the second contact region, wherein the first hole extends through the second dielectric layer, the second electrode metal layer and the first dielectric layer, and the second hole extends through the second dielectric layer, the first electrode metal layer and the first dielectric layer, and the holes are filled with conductive material to form a plurality of through holes, wherein the plurality of through holes includes a first through hole in the first hole and a second through hole in the second hole, wherein the first through hole contacts the second electrode metal layer, and the second through hole contacts the first electrode metal layer.

[0006] To make the above-described features and advantages of this disclosure more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figures 1 to 4 Cross-sectional views of IC devices according to various embodiments of the present disclosure are shown.

[0009] Figures 5 to 7 A plan view of an IC device and a capacitor according to various embodiments is shown.

[0010] Figures 8 to 9 A cross-sectional view of an IC device according to some additional embodiments is shown.

[0011] Figure 10A and 10B These are a pair of plan views showing the layout of the first and second capacitor plates according to an embodiment.

[0012] Figure 11A and 11BThese are a pair of plan views showing the layout of the first and second capacitor plates according to different embodiments.

[0013] Figures 12 to 22 A series of cross-sectional views are shown of an IC device undergoing the process disclosed herein.

[0014] Figures 23 to 25 It shows Figures 12 to 22 A series of cross-sectional views of variations of the process shown.

[0015] Figure 26 This is a flowchart of a method for manufacturing an IC device according to some embodiments.

[0016] Explanation of reference numerals in the attached figures

[0017] 100, 200, 300, 400, 800, 900, 1110: IC devices

[0018] 101: First contact pad

[0019] 103: Horizontal plate

[0020] 105, 305, 405, 805, 905, 1105: Capacitors

[0021] 107: Third Plate

[0022] 109: Capacitor dielectric layer

[0023] 111: Second plate

[0024] 115: First plate

[0025] 117: Second contact pad

[0026] 121, 221, 1201: Passivation stack

[0027] 125, 125A, 125B, 125C: Second through hole

[0028] 129: Oxide layer

[0029] 131: Barrier Layer

[0030] 135: Second conductor

[0031] 139, 201, 205: Etching stop layer

[0032] 141, 203: low-k dielectric layer

[0033] 143: Metal interconnect structure

[0034] 147: Semiconductor substrate

[0035] 149: Second contact area

[0036] 151: Transistor

[0037] 153: First contact area

[0038] 157, 403: Metallization layer

[0039] 161: First conductor

[0040] 165, 165A, 165B, 165C: First through hole

[0041] 171, 801, 1101: Sidewalls

[0042] 181: Vertical plate

[0043] 401: Through-hole layer

[0044] 500, 600, 700, 1000A, 1000B, 1100A, 1100B: Floor Plan

[0045] 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500: Cross-sectional views

[0046] 901: Third contact pad

[0047] 903: Third through hole

[0048] 1301, 1501, 1701, 1901, 2101, 2203: Masks

[0049] 1303: Trench

[0050] 2001: Upper

[0051] 2103: Kong

[0052] 2201: Metal

[0053] 2600: Method

[0054] 2601, 2603, 2605, 2607, 2609, 2611, 2613, 2615, 2617, 2619, 2621, 2623, 2625, 2627, 2629, 2631: Actions Detailed Implementation

[0055] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these elements and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may further include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0056] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. The terms “first,” “second,” “third,” “fourth,” etc., are merely general designations and are therefore interchangeable in various embodiments. For example, while an element (e.g., an opening) may be referred to as a “first” element in some embodiments, it may be referred to as a “second” element in other embodiments.

[0057] Shrinking transistors offers advantages such as higher circuit density and faster switching speeds, but it also makes them more sensitive to voltage fluctuations in the power supply. Even small fluctuations can compromise signal integrity, cause jitter, and otherwise affect circuit functionality.

[0058] This disclosure relates to a structure for mitigating the effects of voltage fluctuations (noise) in a power supply for an integrated circuit. The integrated circuit may be of the type comprising multiple metallization layers on a semiconductor substrate and a passivation stack above the top of the metallization layers. Power supply contacts or power rails may be disposed above the passivation stack. Capacitors are connected between two vias passing through the passivation stack to couple with the power supply contacts or power rails. Vias (V DD One of the through holes can carry the power supply voltage (V). DD Another through hole (V) SS The via can be maintained at the reference voltage (V). SS(Or grounded). In some embodiments, the capacitor is a metal-insulator-metal (MIM) type. In some embodiments, the capacitor comprises three or more plates. If the capacitor has sufficiently high capacitance and sufficiently low equivalent series resistance, it can effectively filter out noise.

[0059] In some embodiments, the capacitor has a 3D structure. The 3D structure provides the capacitor with an effective area much larger than its footprint. Increasing the effective area significantly improves the capacitor's noise reduction performance. The 3D structure may include trench capacitor structures. In some embodiments, the 3D structure includes multiple trench capacitor structures. In some embodiments, the multiple trench capacitor structures are disposed between two vias. In some embodiments, one or more of the trench capacitor structures are located outside the region between the two vias. Utilizing the additional region outside the region between the two vias can increase capacitance.

[0060] In some embodiments, at least a portion of the capacitor is within the passivation stack. In some embodiments, the capacitor is entirely within the passivation stack. Placing all or part of the capacitor within the passivation stack allows the capacitor to be implemented without moving wiring or other structures. DD The through-hole passes through and connects to the first set of capacitor plates. V SS A through-hole passes through and connects to a second set of capacitor plates. In some embodiments, there are multiple V... DD Through-holes pass through and connect to the first group of capacitor plate assemblies. In some embodiments, there are multiple V... SS Through-holes pass through and connect to a second set of capacitor plate assemblies. In some embodiments, the through-holes are enlonged in the horizontal direction, in the form of vertical slabs. Multiple through-holes and / or elongated through-holes reduce the equivalent series resistance of the capacitor.

[0061] Some aspects of this disclosure relate to a method of manufacturing an integrated circuit device having a capacitor that mitigates power supply noise. This method begins with a partially manufactured integrated circuit (IC) device having a metal interconnect structure above a semiconductor substrate. A lower portion of a passivation stack is formed over a top metallization layer of the metal interconnect structure. One or more trenches are etched in the lower portion. A lower substrate layer is deposited to line the trenches and is located on the lower portion of the passivation stack outside the trenches. The lower substrate layer is etched from a first via region, and then a capacitor dielectric layer and an upper substrate layer are deposited. The upper substrate layer is etched from a second via region. Additional capacitor dielectric layers and substrate layers may be deposited and similarly etched to complete the capacitor formation. The upper portion of the passivation stack is formed over the capacitor. Holes (which may also be trenches) are etched through the passivation layer and through the capacitor substrate. Holes include a first hole in a first region and a second hole in a second region. The holes are filled with a conductive material to form a first through-hole in the first hole and a second through-hole in the second hole. The first through-hole contacts a first conductor in the upper board layer and the top metallization layer. The second through-hole contacts a second conductor in the lower board layer and the top metallization layer. Contact pads or power rails may be formed above the passivation layer to form connections to the first and second through-holes.

[0062] Figure 1 An IC device 100 according to some aspects of this disclosure is shown. The IC device 100 includes a metal interconnect structure 143 above a semiconductor substrate 147. The metal interconnect structure 143 includes a plurality of metallization layers, including a top metallization layer 157 located at the topmost point of the metal interconnect structure 143. A passivation stack 121 is disposed above the top metallization layer 157. A first contact pad 101 and a second contact pad 117 are located on top of the passivation stack 121. A first via 165 passes through the passivation stack 121 to couple the first contact pad 101 to a first conductor 161 in the top metallization layer 157. A second via 125 passes through the passivation stack 121 to couple the second contact pad 117 to a second conductor 135 in the top metallization layer 157.

[0063] A capacitor 105 is disposed in a passivation stack 121 and coupled between a first via 165 and a second via 125. The capacitor 105 may include a first plate 115, a second plate 111, and a third plate 107 in order from lowest to highest. A capacitor dielectric layer 109 separates the first plate 115 from the second plate 111 and the second plate 111 from the third plate 107. The first via 165 passes through the second plate 111, is surrounded by the second plate 111, and is connected to the second plate 111 to form a first contact region 153. The first contact region 153 does not contain the first plate 115 or the third plate 107. The second via 125 passes through the first plate 115 and the third plate 107, is surrounded by the first plate 115 and the third plate 107, and is connected to form a second contact region 149. The second contact region 149 does not contain the second plate 111.

[0064] The first contact pad 101 can be V DD Contact pads and the second contact pad 117 can be V SS Contact pads. When a supply voltage is coupled to the first contact pad 101 and a reference voltage is coupled to the second contact pad 117, the IC device 100 is powered and becomes operable. A capacitor 105 buffers fluctuations in the supply voltage, making the voltage on the first conductor 161 more stable than the voltage on the first contact pad 101. In some embodiments, the capacitor 105 reduces peak-to-peak voltage variations by 50% or more. In some embodiments, the capacitor 105 reduces peak-to-peak voltage variations by 75% or more.

[0065] Capacitor 105 is a 3D MIM capacitor including a trench capacitor structure. The trench capacitor structure means that the first plate 115, the second plate 111, and the third plate 107 include a vertical plate 181 within a trench defined by the sidewalls 171 of the passivation stack 121. The first plate 115, the second plate 111, and the third plate 107 further include a horizontal plate 103. The vertical plate 181 allows capacitor 105 to have an effective area larger than its footprint. In some embodiments, the effective area is about 3 to about 10 times larger than the footprint. In some embodiments, the effective area is about 10 to about 50 times larger than the footprint. In some embodiments, capacitor 105 has vertical plates 181 within three or more different trenches.

[0066] The passivation stack 121 is a dielectric structure that may include an etch stop layer 139, a barrier layer 131, and an oxide layer 129. The etch stop layer 139 may be a material such as silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbide (SIOC), silicon carbonitride (SiOCN), or combinations thereof. The barrier layer 131 may be a material such as silicon nitride (SiN), which provides excellent moisture resistance and has greater mechanical strength than silicon dioxide (SiO2). In some embodiments, the material of the barrier layer 131 is different from the material of the etch stop layer 139. In some embodiments, the first plate 115 abuts the etch stop layer 139.

[0067] The oxide layer 129 may be silicon dioxide (SiO2) or the like, providing good insulation and process compatibility. In some embodiments, the passivation stack 121 has a thickness ranging from about 0.5 μm to about 3 μm. In some embodiments, the passivation stack 121 has a thickness ranging from about 1.9 μm to about 2.2 μm. In some embodiments, the etch stop layer 139 has a thickness ranging from about 5 nm to about 50 nm. In some embodiments, the barrier layer 131 has a thickness of at least about 0.2 μm. In some embodiments, the oxide layer 129 has a thickness of at least about 0.3 μm. The material of the barrier layer 131 may be the same as that of the etch stop layer 139 or another etch stop layer (e.g., the material in the metal interconnect structure 143), but the barrier layer 131 is much thicker than any etch stop layer in the IC device 100.

[0068] The dielectric layer in the passivation stack 121 is typically different from the dielectric layer in the metal interconnect structure 143. The metal interconnect structure 143 includes a low-k dielectric layer 141. The low-k dielectric layer 141 can be, for example, an organosilicon glass (OSG) (such as carbon-doped silicon dioxide), a fluorinated silicate glass (FSG), a porous silicate glass, etc.

[0069] Figure 2 Similar Figure 1The IC device 200 differs from the IC device 100 in that it has a passivation stack 221 with a different structure than the passivation stack 121 of the IC device 100. The passivation stack 221 may have a dielectric structure similar to the metal interconnect structure 143. The passivation stack 221 includes a low-k dielectric layer 203, a first etch stop layer 205, and a second etch stop layer 201. The low-k dielectric layer 203 may have the same composition as the low-k dielectric layer 141. The first etch stop layer 205 or the second etch stop layer 201 may have the same composition and thickness as the etch stop layer 139. Although the passivation stack 221 may not have the same protective quality as the passivation stack 121, its advantage is that it can be formed through the continuation of the process loop used to form the metal interconnect structure 143.

[0070] Figure 3 Similar Figure 1 The IC device 300 differs from the IC device 100 in that it has a capacitor 305. Aside from some structural differences in the capacitor dielectric layer 109, the capacitor 305 is similar to the capacitor 105 in the IC device 100. In the capacitor 305, the capacitor dielectric layer 109 extends over the second plate 111 in the first contact region 153 and has a greater thickness between the first plate 115 and the third plate 107 in the second contact region 149. These differences are due to variations in the manufacturing process. Specifically, the IC device 300 is manufactured using an etching process that stops at the capacitor dielectric layer 109, as will be described in more detail below. Figure 1 Compared to capacitor 105, capacitor 305 has a slightly lower capacitance, but may have advantages in terms of reliability or ease of manufacture.

[0071] Figure 4 Similar Figure 1 The IC device 400 differs from the IC device 100 in that it has a capacitor 405. The capacitor 405 extends below the passivation stack 121 and into the top metallization layer 157. Alternatively, the capacitor 405 may extend deeper into the metal interconnect structure 143. In some embodiments, the capacitor 405 extends into a via layer 401 located between the top metallization layer 157 and a second metallization layer 403 from the top. In some embodiments, the capacitor 405 extends into the via layer 401. In some embodiments, the capacitor 405 extends into the second metallization layer 403 from the top. Extending the capacitor 405 deeper into the metal interconnect structure 143 results in the capacitor 405 occupying more space, but it can increase capacitance without increasing the capacitor's footprint.

[0072] Figure 5Plan view 500 is shown, which corresponds to some embodiments. Figure 1 A plan view of the IC device 100 is shown. Three first through-holes 165A and three second through-holes 125A are present in plan view 500. The first through-holes 165 and the second through-holes 125 are elongated to form a vertical plate. In some embodiments, the length of the first through-holes 165 and the second through-holes 125 is two or more times their width. In some embodiments, the length of the first through-holes 165 and the second through-holes 125 is four or more times their width. Having multiple through-holes and through-holes extending to the plate reduces the equivalent series resistance of the capacitor 105.

[0073] Figure 6 Plan view 600 is shown, which in some embodiments may correspond to Figure 1 Another plan view of the IC device 100. Plan view 600 shows three first through-holes 165B and three second through-holes 125B. The first through-holes 165B and second through-holes 125B are similar to the first through-holes 165A and second through-holes 125A in plan view 500, except that the first through-holes 165A and second through-holes 125A extend in the same direction as the trench defined by the sidewall 171, while the first through-holes 165B and second through-holes 125B extend in a direction perpendicular to the trench, defined by the sidewall 171.

[0074] Figure 7 Plan view 700 is shown, which in some embodiments may correspond to Figure 1 Another plan view of the IC device 100. In plan view 700, there are nine first through-holes 165C and nine second through-holes 125C. The first through-holes 165C and the second through-holes 125C are circular or elliptical and arranged in an array. These can be 2x2 arrays, 3x3 arrays as shown, or arrays with other numbers of rows and columns. Having a large number of through-holes provides a similar effect to having elongated through-holes.

[0075] Figure 8 A cross-sectional view of an IC device 800 according to another embodiment is shown. The IC device 800 and... Figure 1 Similar to IC device 100, the difference lies in that IC device 800's capacitor 805 has an expanded area, including additional trench structures. The capacitor 805 has trench structures between the sidewalls 171 of the passivation stack 121 in the region between the first via 165 and the second via 125, and additional trench structures between the sidewalls 801 of the passivation stack 121, located on the opposite side of the first via 165 relative to the second via 125. This embodiment illustrates the concept of increasing capacitance using an additional area beyond the space between the first contact pad 101 and the second contact pad 117.

[0076] Figure 9 A cross-sectional view of an IC device 900 according to another embodiment is shown. The IC device 900 is similar to... Figure 8 The IC device 800 differs from the IC device 900 in that it has a capacitor 905 that extends further to connect to one or more third vias 903 coupled to a third contact pad 901. The third contact pad 901 may be connected to the same power supply pole as the second contact pad 117. The third via 903 is connected in parallel with the second via 125 to the capacitor 905. This embodiment demonstrates a further increase in area and connectivity that can be used to improve noise filtering.

[0077] Figure 10A and 10B It shows the corresponding Figure 8 Plan views 1000A and 1000B of the IC device 800 are provided. Plan view 1000A shows the layout of the second board 111. As shown in plan view 1000A, the second board 111 may stop before the second contact region 149. Plan view 1000B shows the layout of the first board 115. As shown in plan view 1000B, the first board 115 may extend around the first contact region 153 to provide continuity between portions of the first board 115 on one side of the first contact region 153 and portions of the first board 115 on the opposite side of the first contact region 153. In some embodiments, the first board 115 surrounds the first contact region 153.

[0078] Figure 11A and 11B Plan views 1100A and 1100B are shown corresponding to an IC device 1110 according to another embodiment. The IC device 1110 is similar to... Figure 8 The IC device 800 differs in that the IC device 1110 has a capacitor 1105, which includes an additional trench structure located between a sidewall 1101 and a passivation stack 121. The sidewall 1101 is located on the opposite side of the first contact region 153 in the second contact region 149. The capacitor 1105 has a first plate 115 extending through the second contact region 149 and a second plate 111 extending around the second contact region 149. This embodiment illustrates another possible extension of the capacitor region. The capacitor region can be further extended by extending to the contact region associated with and around adjacent contact pads (not shown).

[0079] Figure 12-22 A series of cross-sectional views 600-4400 are provided, illustrating integrated circuit devices disclosed herein at various manufacturing stages according to the process of this disclosure. Although Figure 12-22 It describes a series of actions, but it should be understood that in some cases the order of the actions can be changed, and this series of actions can be applied to structures other than those shown. In some embodiments, some of these actions may be omitted, either wholly or partially. Furthermore, although... Figure 12-22 It is described as a series of actions, but it should be understood that... Figure 12-22 The structure shown is not limited to the manufacturing method, but can exist independently as a structure separate from the method.

[0080] like Figure 12 As shown in cross-sectional view 1200, the process can begin by forming a lower portion of a passivation stack 1201 on an integrated circuit device comprising a semiconductor substrate 147 and a metal interconnect structure 143. The metal interconnect structure 143 includes multiple conductive lines (e.g., first conductive line 161 and second conductive line 135) and multiple vias, which respectively form alternating stacked metallization layers and via layers. The top metallization layer 157 is the uppermost metallization layer. The lower portion of the passivation stack 1201 includes a portion of an etch stop layer 139, a barrier layer 131, and an oxide layer 129. The lower portion of the passivation stack 1201 may have additional or different layers, such as a low-k dielectric layer 203, an etch stop layer 205, and an etch stop layer 201, as... Figure 2 As shown.

[0081] Semiconductor substrate 147 can be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor can be silicon (Si), a III-V group semiconductor (e.g., GaAs), or some other binary semiconductor, ternary semiconductor (e.g., AlGaAs), higher-order semiconductor, or any other suitable semiconductor. Various semiconductor devices, such as transistor 151, can be formed on semiconductor substrate 147. Transistor 151 may be in a circuit that operates when connected to a power supply. The wires and vias can be, for example, copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zi), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, alloys of these metals, etc.

[0082] like Figure 13As shown in cross-sectional view 1300, a mask 1301 can be formed and used to etch trenches 1303 in a passivation stack 1201. The mask 1301 and other masks used in this process can be or include photoresist, hard masks, etc. The mask 1301 and other masks used in this process can be patterned by photolithography, ion beam lithography, or some other suitable process. The trenches 1303 have sidewalls 171 provided by the passivation stack 1201. The etching process can be dry etching, such as plasma etching. In some embodiments, etching stops at an etch stop layer 139 or some other etch stop layer to provide the bottom of the trenches 1303. Providing the etch stop layer 139 with a different composition than the barrier layer 131 enables the etch stop layer 139 to stop etching. After etching, the mask 1301 can be stripped.

[0083] like Figure 14 As shown in the cross-sectional view 1400, an electrode metal layer is deposited in order to... Figure 13 A first plate 115 is formed above the structure shown in cross-sectional view 1300. An electrode metal layer deposited in trench 1303 paves the sidewalls 171, thereby forming a vertical plate 181. An electrode metal layer is deposited below the passivation stack 1201 to form a horizontal plate 103.

[0084] The electrode metal layer can be, for example, titanium nitride (TiN), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TaN), copper (Cu), silver (Ag), aluminum (Al), nickel (Ni), and their conductive alloys. In some embodiments, the electrode metal layer is titanium nitride (TiN), etc. Using titanium nitride (TiN) as the electrode metal layer helps to achieve extremely low equivalent series resistance. In some embodiments, the electrode metal layer is deposited to a thickness ranging from about 1 nm to about 20 nm. In some embodiments, the electrode metal layer is deposited to a thickness ranging from about 20 nm to about 50 nm. Thinner electrode metal layer deposition allows for the deposition of more plate material in trench 1303 and provides higher capacitance. Thicker electrode metal layer deposition can reduce equivalent series resistance. The electrode metal layer can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, electroless plating, etc., or any other suitable process.

[0085] like Figure 15 As shown in cross-sectional view 1500, a mask 1501 is formed and used to etch the first plate 115 from the first contact area 153. The etching process can be dry etching, such as plasma etching, or some other suitable etching process. After etching, the mask 1501 is stripped off.

[0086] like Figure 16 As shown in cross-sectional view 1600, the capacitor dielectric layer 109 and the second electrode metal layer are deposited on... Figure 15The structure shown in cross-sectional view 1500 is above the first plate 115. A second electrode metal layer provides the second plate 111 and may have the same (or different) composition as the first plate 115. The second electrode metal layer may be deposited using the same (or different) process as the first electrode metal layer and may be deposited to the same (or different) thickness. The capacitor dielectric layer 109 may be any suitable dielectric. In some embodiments, the capacitor dielectric layer 109 is a high-k dielectric. Examples of high-k dielectrics include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), europium tantalum oxide (HfTaO), europium titanium oxide (HfTiO), europium tantalum oxide (HfZrO), hafnium aluminum oxide (HfO2-Al2O3), zirconium oxide (ZrO2), tantalum aluminum oxide (HfO2-Al2O3), zirconium oxide (ZrO2), tantalum aluminum oxide (HfO2-Al2O3), zirconium oxide (ZrO2), tantalum aluminum oxide (HfO2-Al2O3), zirconium oxide (ZrO2), bismuth oxide (Ta2O5), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), titanium oxide (SrTiO3), and the like.

[0087] The capacitor dielectric layer 109 can be deposited to any suitable thickness. In some embodiments, the capacitor dielectric layer 109 is deposited to have a thickness ranging from about 5 nm to about 20 nm within the trench 1303. In some embodiments, the capacitor dielectric layer 109 has the same thickness outside the trench 1303. In some embodiments, the capacitor dielectric layer 109 is deposited to have a greater thickness outside the trench 1303 (i.e., on top of the lower portion of the passivation stack 1201). In some embodiments, the thickness is 50% or more greater. In some embodiments, the thickness is greater than twice or more. Providing a capacitor dielectric layer 109 with a greater thickness on top of the lower portion of the passivation stack 1201 can reduce leakage current. The capacitor dielectric layer 109 can be deposited using ALD, CVD, PVD, or any suitable process. ALD, CVD, or PVD can be used to provide a capacitor dielectric layer 109 with a uniform thickness, with ALD being the most effective for this purpose. CVD or PVD can be used to provide a capacitor dielectric layer 109 with a greater thickness outside the trench 1303.

[0088] like Figure 17 As shown in cross-sectional view 1700, a mask 1701 can be formed and used to etch the second plate 111 from the second contact region 149. The etching process can be dry etching, such as plasma etching, or some other suitable etching process. Etching may stop at the first plate 115. After etching, the mask 1701 can be stripped.

[0089] like Figure 18 As shown in the cross-sectional view 1800, another capacitor dielectric layer 109 can be deposited, followed by the deposition of a third electrode metal layer providing the third plate 107. As... Figure 19 As shown in the cross-sectional view 1900, a mask 1901 can be formed and used to etch the third plate 107 from the first contact area 153. Figure 18 and Figure 19 The process is optional, as capacitor 105 may have only two plates. Alternatively, additional capacitor dielectric layers and electrode metal layers can be deposited and etched to provide more plates until trench 1303 is filled. In some embodiments, the final electrode metal layer deposition fills trench 1303.

[0090] like Figure 20 As shown in cross-sectional view 2000, the upper portion 2001 of the passivation stack 121 can be deposited to complete the formation of the passivation stack 121. The upper portion 2001 may be more oxide layers 129 or may be some other dielectric. In some embodiments, the upper portion 2001 includes silicon nitride (SiN) or the like, which provides a capping layer.

[0091] The upper portion 2001 may be a fraction of the total thickness of the passivation stack 121, such that the trench defined by the sidewall 171 extends through a large portion of the passivation stack 121. In some embodiments, the upper portion 2001 is about 20% or less of the thickness of the passivation stack 121. In some embodiments, the upper portion 2001 is about 10% or less of the thickness of the passivation stack 121. In some embodiments, the upper portion 2001 is about 5% or less of the thickness of the passivation stack 121.

[0092] like Figure 21 As shown in cross-sectional view 2100, a mask 2101 can be formed and used to etch holes 2103 through the passivation stack 121. The etching process can be one or more stages of dry etching, such as plasma etching, or any other suitable etching process. In some embodiments, the holes 2103 are elongated, such that they are trenches. In the first contact region 153, the holes 2103 pass through the second plate 111 and expose the first conductor 161. In the second contact region 149, the holes 2103 pass through the first plate 115 and the third plate 107 and expose the second conductor 135.

[0093] like Figure 22As shown in cross-sectional view 2200, deposited metal 2201 or other conductive material fills via 2103 and provides first via 165 and second via 125. Metal 2201 may be the same metal as the first conductor 161 and second conductor 135. In some embodiments, metal 2201 is a different metal from the metals of the first conductor 161 and second conductor 135. Metal 2201 may be deposited by PVD, CVD, electroplating, electroless plating, or any other suitable process. After deposition, metal 2201 may be planarized. In some embodiments, the planarization process leaves a layer of metal 2201 over the passivation stack 121. A mask 2203 may be formed and used to pattern this metal 2201 to form first contact pad 101 and second contact pad 117, as shown. Figure 1 As shown. The metal 2201 above the passivation stack 121 can alternatively be patterned to form power rails.

[0094] Figure 23-25 A variation of the aforementioned process is shown. For example... Figure 23 As shown in cross-sectional view 2300, the etching of the second plate 111 from the second contact region 149 can stop at the capacitor dielectric layer 109. Figure 24 The cross-sectional view 2400 is shown below, and then it can be seen that... Figure 23 The structure shown in cross-sectional view 2300 forms a capacitor dielectric layer 109 and a second layer of the third plate 107 on top of it. For example... Figure 25 As shown in cross-sectional view 2500, the etching of the third plate 107 from the first contact region 153 can also stop at the capacitor dielectric layer 109. The process can be as follows: Figure 20-22 The cross-sectional views 2000-2200 are shown to continue providing Figure 3 The IC device 300 shown. Using an etching process that stops at the capacitor dielectric layer 109 can have advantages, such as maintaining the integrity of the underlying capacitor board.

[0095] Figure 26 A flowchart of a method 2600 for forming an IC device according to some embodiments is provided. While method 2600 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all actions shown are required to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0096] Method 2600 begins with action 2601, the front-end-of-line (FEOL) process of the semiconductor substrate. The FEOL process forms semiconductor devices in or on the semiconductor substrate. These can include, for example, transistors, diodes, capacitors, memory cells, thyristors, resistors, and combinations thereof. Action 2603 is the back-end-of-line (BEOL) process that provides a metal interconnect structure. The metal interconnect structure has wires connecting various semiconductor devices to functional circuitry. Action 2605 forms the lower portion of a passivation stack on the metal interconnect structure. Figure 12 The cross-sectional view 1200 provides an example.

[0097] Action 2607 involves etching trenches in the lower part of the passivation stack. Figure 13 The cross-sectional view 1300 provides an example. When multiple layers of capacitor stacks are deposited on and inside these trenches, they form a trench capacitor structure.

[0098] Action 2609 is to deposit the first capacitor plate. Figure 14 Cross-sectional view 1400 provides an example. Action 2611 is to etch the first capacitor plate from the first contact area. Figure 15 The cross-sectional view 1500 provides an example.

[0099] Action 2613 is depositing a capacitor dielectric layer. In some embodiments, the capacitor dielectric layer has a uniform thickness. In some embodiments, the capacitor dielectric layer is made thicker where it extends horizontally above the passivation stack than it is within the trench. Action 2615 is depositing a second capacitor plate. Figure 16 The cross-sectional view 1600 provides an example.

[0100] Action 2617 is to etch the second capacitor plate from the second contact area. Figure 17 The cross-sectional view 1700 provides an example of the etching process stopping on the first capacitor plate. Figure 23 The cross-sectional view 2300 provides an example of an etching process stopping on the capacitor dielectric layer.

[0101] Actions 2619 to 2623 are optional. Action 2619 is the deposition of an additional capacitor dielectric layer. Action 2621 is the deposition of an additional capacitor plate. Figure 18 and 24 The cross-sectional views 1800 and 2400 provide examples.

[0102] Action 2623 involves etching the additional capacitor plate from the first contact area. Figure 19 The cross-sectional view 1900 provides an example of the etching process stopping on the first capacitor plate. Figure 25Cross-sectional view 2500 provides an example of an etching process stopping on the capacitor dielectric layer. Operations 2619 to 2623 can be repeated, in which a continuous board is etched from alternating contact areas.

[0103] Action 2625 is the upper part of forming the passivation stack. Figure 20 The cross-sectional view 2000 provides an example. Action 2627 is to etch holes or trenches through the passivation stack in the contact area. Figure 21 Cross-sectional view 2100 provides an example. Action 2629 is filling the hole to form a through hole that connects to the contact capacitor plate and to the wires in the underlying metal interconnect structure. Figure 22 The cross-sectional view 2200 provides an example.

[0104] Action 2631 is to form contacts. The contacts are coupled to vias and may be located above a passivation stack. In some embodiments, the contacts are contact pads located directly above the conductors. In some embodiments, the contact pads are etched from the deposited metal to form the via. Figure 22 The cross-sectional view 2200 provides an example of how this etching can be accomplished. Alternatively, vias can be connected to contact pads through power rails on the passivated stack. The contacts are coupled to an external power supply to power the integrated circuit device.

[0105] Some aspects of this disclosure relate to an integrated circuit (IC) device, including a substrate, a metal interconnect structure above the substrate, and a passivation stack above the metal interconnect structure. The metal interconnect structure includes a first conductor and a second conductor. A first contact and a second contact are disposed above the passivation stack. A first via extending through the passivation stack connects the first contact to the first conductor. A second via extending through the passivation stack connects the second contact to the second conductor. A metal-insulator-metal (MIM) capacitor having a trench capacitor structure is connected between the first and second vias.

[0106] In some embodiments, a first through-hole passes through and is surrounded by a first plate of the metal-insulator-metal capacitor, and a second through-hole passes through and is surrounded by a second plate of the metal-insulator-metal capacitor. In some embodiments, the trench capacitor structure extends below the first line.

[0107] In some embodiments, the first and second contacts connect the IC device to a power supply. In some embodiments, the IC device has a third contact located above a passivation stack and a third via disposed in the passivation stack and connected to the third contact, wherein the third via is connected in parallel with the first via to a metal-insulator-metal capacitor. In some embodiments, the first and second vias are elongated to form vertical plates. In some embodiments, the first via is one of a plurality of first vias connecting the first contact to the metal-insulator-metal capacitor. In some embodiments, the metal-insulator-metal capacitor is entirely within the passivation stack. In some embodiments, the passivation stack includes a barrier layer, and the metal-insulator-metal capacitor extends into the barrier layer.

[0108] Some aspects of this disclosure relate to integrated circuit (IC) devices, including a semiconductor substrate, a metal interconnect structure on the semiconductor substrate, a dielectric structure on the metal interconnect structure, first and second contacts on the dielectric structure, and a capacitor. The capacitor includes a first plate and a second plate separated from each other by a capacitor dielectric layer. A first via passes through the dielectric structure and couples the first contact to the metal interconnect structure. A second via passes through the dielectric structure and couples the second contact to the metal interconnect structure. The first via passes through and contacts the first plate. The second via passes through and contacts the second plate. The first plate includes a first vertical portion disposed between first two sidewalls of the dielectric structure. The second plate includes a second vertical portion disposed between the first two sidewalls of the dielectric structure.

[0109] In some embodiments, a first plate is adjacent to and above an etch stop layer. In some embodiments, the capacitor includes a third plate, a second plate extends between the first and third plates, and a first via passes through and contacts the third plate. In some embodiments, the first plate descends into one of a plurality of metallization layers. In some embodiments, the first plate includes a third vertical portion disposed between second sidewalls of a dielectric structure, wherein the second sidewalls are laterally offset from the first sidewalls, and the second plate includes a fourth vertical portion disposed between the second sidewalls of the dielectric structure. In some embodiments, the second sidewalls are located on opposite sides of the first via relative to the first sidewalls. In some embodiments, the first plate includes a horizontal portion. A capacitor dielectric layer is disposed above the horizontal portion and between the first sidewalls, and the capacitor dielectric layer is thicker above the horizontal portion than it is between the first sidewalls.

[0110] This disclosure relates to methods for forming IC devices, the methods comprising: providing a semiconductor substrate having a first contact region and a second contact region; forming a metal interconnect structure including a plurality of metallization layers on the semiconductor substrate; forming a first dielectric layer over the metal interconnect structure; forming a trench extending to the first dielectric layer; forming a first electrode metal layer over the first dielectric layer and within the trench; forming a first mask and etching to selectively remove the first electrode metal layer from the first contact region; forming a capacitor dielectric layer and a second electrode metal layer over the first electrode metal layer; and forming a first mask and etching to selectively remove the first electrode metal layer from the first contact region. A second dielectric layer is formed above the second electrode metal layer, and holes are etched out, wherein the holes include a first hole in the first contact region and a second hole in the second contact region, wherein the first hole extends through the second dielectric layer, the second electrode metal layer and the first dielectric layer, and the second hole extends through the second dielectric layer, the first electrode metal layer and the first dielectric layer, and the holes are filled with conductive material to form a plurality of through holes, wherein the plurality of through holes includes a first through hole in the first hole and a second through hole in the second hole, wherein the first through hole contacts the second electrode metal layer, and the second through hole contacts the first electrode metal layer.

[0111] In some embodiments, etching to selectively remove the first electrode metal layer from the first contact region leaves the first electrode metal layer surrounding the first contact region. In some embodiments, etching to selectively remove the second electrode metal layer from the second contact region is an etching process that stops at the capacitor dielectric layer. In some embodiments, forming the capacitor dielectric layer includes a deposition process that results in the capacitor dielectric layer being thinner inside the trench than outside the trench.

[0112] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various alterations, substitutions, and changes can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, characterized in that, include: Substrate; A metal interconnect structure is disposed above the substrate, wherein the metal interconnect structure includes a first wire and a second wire; A passivation stack is disposed above the metal interconnect structure; The first contact and the second contact are disposed above the passivation stack; A first through-hole is disposed in the passivation stack and connects the first contact to the first wire; A second through-hole is disposed in the passivation stack and connects the second contact to the second wire; as well as A metal-insulator-metal capacitor is connected between the first through hole and the second through hole, wherein the metal-insulator-metal capacitor has a trench capacitor structure.

2. The integrated circuit device according to claim 1, characterized in that, The first through hole passes through and is surrounded by the first plate of the metal-insulator-metal capacitor, and the second through hole passes through and is surrounded by the second plate of the metal-insulator-metal capacitor.

3. The integrated circuit device according to claim 1, characterized in that, It further includes a third contact disposed above the passivation stack and a third through hole disposed in the passivation stack and connected to the third contact, wherein the third through hole is connected in parallel with the first through hole to the metal-insulator-metal capacitor.

4. The integrated circuit device according to claim 1, characterized in that, The first through hole is one of a plurality of first through holes connecting the first contact to the metal-insulator-metal capacitor.

5. The integrated circuit device according to claim 1, characterized in that, The metal-insulator-metal capacitor is entirely within the passivation stack.

6. An integrated circuit device, characterized in that, include: Semiconductor substrate; A metal interconnect structure is disposed above the semiconductor substrate, wherein the metal interconnect structure includes a plurality of wires grouped into a plurality of metallization layers and a plurality of vias grouped into a plurality of via layers, wherein the via layers and the metallization layers are interleaved with each other; A dielectric structure is disposed above the metal interconnect structure; The first contact is disposed above the dielectric structure; A first through-hole passes through the dielectric structure and couples the first contact to the metal interconnect structure; The second contact is disposed above the dielectric structure; A second through-hole passes through the dielectric structure and couples the second contact to the metal interconnect structure; as well as A capacitor, comprising a first plate and a second plate separated by a capacitor dielectric layer; The first through hole passes through and contacts the first plate; The second through hole passes through and contacts the second plate; The first plate includes a first vertical portion disposed between the first two side walls of the dielectric structure; and The second plate includes a second vertical portion disposed between the first two side walls of the dielectric structure.

7. The integrated circuit device according to claim 6, characterized in that, The first plate is adjacent to and above the etch stop layer.

8. The integrated circuit device according to claim 6, characterized in that, The capacitor includes a third plate, the second plate extends between the first plate and the third plate, and the first through hole passes through and contacts the third plate.

9. The integrated circuit device according to claim 6, characterized in that: The first plate includes a third vertical portion disposed between the second two side walls of the dielectric structure, wherein the second two side walls are laterally offset from the first two side walls; and The second plate includes a fourth vertical portion disposed between the second two side walls of the dielectric structure, the second two side walls being located on the opposite side of the first through hole to the first two side walls.

10. The integrated circuit device according to claim 6, characterized in that, The first plate includes a horizontal portion; The capacitor dielectric layer is disposed above the horizontal portion and between the first two side walls; and The capacitor dielectric layer is thicker above the horizontal portion than between the first two side walls.

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