A fast address reading circuit and reading method

Abstract

The invention relates to a fast address readout circuit and a readout method, comprising a plurality of groups of channels, each group of channels having the same circuit connection structure; each group of channels is integrated with a control latch and a pull-up and pull-down unit, wherein the pull-up and pull-down units are configured in different ways, and a channel hit signal of each group of channels is transmitted to a lower-level encoding circuit as a chip select signal of the group after operation, and the lower-level encoding circuit transmits the chip select signal step by step in the same way; each group of channels is provided with a three-state buffer as a control switch, and by integrating a control latch and a pull-up and pull-down unit in the channel to directly read the value, the address transmission delay is significantly reduced, the address readout speed is accelerated, and the readout circuit is integrated inside the channel and processed as a standard module or IP, which is conducive to module circuit multiplexing and easy to expand a chip array; the pull-up and pull-down units are provided in the channel to quickly read out the low-order address, and the high-order address is obtained by combining a hierarchical address encoding scheme, thereby ensuring the power consumption requirement.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a fast address readout circuit and a readout method. Background Art

[0002] The address readout circuit is a commonly used circuit for information detection, which is used to obtain the position information of arrays such as images and particle trajectories. After the sensor array is hit, the hit information is transmitted to the digital circuit after amplification and shaping by the analog circuit. The hit position information is encoded by the digital circuit through multiple levels to obtain the corresponding address, and is read out under the control of the peripheral circuit. As the requirements for the accuracy of position information in medical imaging, particle detection and other fields become higher and higher, and the array scale becomes larger and larger, the readout time and area size of the traditional address readout circuit structure are difficult to meet the requirements, resulting in the loss of address information. The readout speed must be accelerated through circuit design. Reference 1, "C. Young Lee, C. Won Kim, H. Im, S. Youn Kim and M. Song, "A Low Power Priority Encoding Technique with Address-Encoder and Reset-Decoder for an Improved Hierarchical Asynchronous Detector," 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2018, pp. 289-292." contains a hierarchical address coding readout circuit. For the encoding process, please refer to Figure 1 When resetting, the reset signal is transmitted step by step according to the circuit level. SYNC is used for synchronous operation. When a pixel is hit, the VALID signal is quickly obtained through OR operation and is transmitted to the next level circuit as the readout start mark, and the encoding is performed step by step. Please refer to the 16-bit pixel encoding process Figure 2 , 4-2 encoding is performed for every four pixels as a group, and the low-order encoding address is obtained and then passed to the next level, and the high-order address is encoded again. During the reading period, the address reading is controlled by the SELECT signal, and the hit flag is reset immediately after the reading is completed for the next reading operation.

[0003] The main disadvantage of the existing address readout method is that when the array reaches a certain scale, the number of levels of the encoding circuit increases. For example, if an array has 1024 channels that need to read address information, the existing method requires five levels of circuits for address readout, the propagation path is complex, and it takes a long time to propagate the address, which affects the circuit operating frequency. In addition, under deep submicron technology, complex circuits will further increase the difficulty of layout and wiring. Summary of the invention

[0004] In order to overcome the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide a fast address readout circuit that can solve the above-mentioned technical problems.

[0005] To achieve the above object, the present invention adopts the following technical solution: a fast address readout circuit, comprising a plurality of groups of channels, each group of channels having the same circuit connection structure;

[0006] Each group of channels has an integrated address control register and a pull-up and pull-down unit. The pull-up and pull-down units in each group of channels are configured differently. The channel hit signals in each group of channels are transmitted to the lower-level encoding circuit as the chip select signal of the group after calculation. The lower-level encoding circuit transmits the chip select signal step by step in the same way.

[0007] Each group of the channels is provided with a tri-state buffer as a control switch, and the tri-state buffer controls the output state of the address data, controls the latch to latch the hit signal, and controls the opening and closing state of the tri-state buffer.

[0008] Furthermore, the pull-up and pull-down units are configured with address data when being reset, and after being reset, the corresponding values ​​of the addresses remain unchanged.

[0009] Furthermore, when the channel is outputting, it indicates that the pixel point corresponding to the channel is hit, and a plurality of the pixel points form an array. According to the array size and the total number of channels, the number of configuration bits of the pull-up and pull-down units in the channel is set to x bits, representing the lower x bits of the data address.

[0010] Furthermore, the channels are grouped according to the address, and each group has a fixed channels.

[0011] Furthermore, the total number of stages of the overall circuit is calculated as:

[0012]

[0013] Where N is the total number of circuit stages and K is the total number of channels.

[0014] Furthermore, if the value obtained by dividing the number of pixels of the array is not a multiple of 4, the total number of levels is obtained by rounding down, and the upper two bits of the address are not encoded.

[0015] Furthermore, each level of circuits in each group of the channels is composed of a different number of 4-2 encoders and obtains two-bit addresses.

[0016] In order to achieve the above object and other related objects, the present invention provides a method for reading an address fast reading circuit, comprising the following steps:

[0017] During reset, the address is configured by the pull-up and pull-down units in the channel, and the address registers in each channel of each group are coded in binary mode;

[0018] The hit signals of each channel in each group are transmitted to the lower circuit as chip selection signals for further encoding through OR operation. The lower circuit uses the chip selection signal as the hit signal of this level and transmits it downward through the OR gate again step by step until the last level circuit, which outputs the hit flag.

[0019] The low-order address readout and high-order address encoding are operated in parallel, and each stage of each channel group outputs a partial address to form the hit address;

[0020] The control latch latches the hit information and controls the read switch of the tri-state buffer, that is, when there is no hit, the output is in high impedance state, and when there is a hit, the corresponding value of the output pull-up and pull-down units is output as the low-order address to the peripheral circuit, ensuring that when a hit is effective, only one channel outputs data to the bus;

[0021] A current mirror driving circuit is used to output the integrated low and high address to the address bus, and the state of the current mirror driving circuit is controlled by the address signal.

[0022] Compared with the prior art, the present invention can:

[0023] 1) Integrate the address register and the pull-up and pull-down units in the channel, so that the address readout circuit is basically independent of the number of channels, the circuit in the channel is simple and easy to implement, and the circuits of each group of channels are fixed and the same, which is easy to expand the array;

[0024] 2) The number of circuit levels is small, the signal propagation speed is fast, the readout circuit can reach a higher operating frequency, and the area of ​​the readout circuit is effectively improved in the case of multi-channel and large array applications;

[0025] 3) Each address read channel shares a current mirror drive circuit to reduce power consumption.

[0026] 4) For small-scale circuits or circuits with a certain scale but low requirements on the area within the channel, only one first-level low-order address readout circuit can be used for address reading, which can achieve the fastest readout speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Attached Figure 1 It is the internal connection mode of the coding reset module of the hierarchical address coding circuit in the background technology;

[0028] Attached Figure 2 It is the inter-level connection mode of the 16-bit hierarchical address coding circuit in the background technology;

[0029] Attached Figure 3 It is a fast readout method of the fixed 6-bit address register address in the present invention;

[0030] Attached Figure 4 This is the internal connection mode of the low-order address readout circuit in the present invention;

[0031] Attached Figure 5 It is a specific implementation method of the address bit in the channel of the present invention;

[0032] Attached Figure 6 It is the specific implementation of the 4-2 encoder;

[0033] Attached Figure 7 It is a current mirror drive control circuit. DETAILED DESCRIPTION

[0034] The present invention will be further described below in conjunction with the accompanying drawings and implementation modes. Example 1

[0035] This embodiment provides a fast address readout circuit, including multiple groups of channels, each group of channels has the same circuit connection structure;

[0036] Each channel group has an integrated address control register and a pull-up and pull-down unit. The pull-up and pull-down units in each channel group are configured differently. The channel hit signal in each channel group is transmitted to the lower-level encoding circuit as the chip select signal of the group after calculation. The lower-level encoding circuit transmits the chip select signal step by step in the same way.

[0037] Each group of channels is provided with a three-state buffer as a control switch. The three-state buffer controls the output state of the address data, controls the latch to latch the hit signal, and controls the opening and closing state of the three-state buffer.

[0038] In this embodiment, the pull-up and pull-down units are configured with address data when they are reset, and after reset, the corresponding values ​​of the addresses remain unchanged.

[0039] Furthermore, when the channel is outputting, it means that the pixel point corresponding to the channel is hit, and multiple pixels form an array. According to the array size and the total number of channels, the number of configuration bits of the pull-up and pull-down units in the channel is set to x bits, representing the lower x bits of the data address.

[0040] Specifically, in this embodiment, the channels are grouped according to the addresses, and each group has a fixed channels.

[0041] Furthermore, the total number of stages of the overall circuit is calculated as:

[0042]

[0043] Where N is the total number of circuit stages and K is the total number of channels.

[0044] Furthermore, if the value obtained by dividing the number of pixels in the array is not a multiple of 4, the total number of levels is obtained by rounding down, and the upper two bits of the address are not encoded.

[0045] Furthermore, each level of circuits in each group of channels is composed of a different number of 4-2 encoders and obtains two-bit addresses.

[0046] In order to achieve the above object and other related objects, the present invention provides a method for reading an address fast reading circuit, comprising the following steps:

[0047] Step 1: During reset, the pull-up and pull-down units in the channel configure the address, and the address registers in each channel of each group are coded in binary mode;

[0048] Step 2, the hit signal of each channel in each group is transmitted to the lower circuit as a chip selection signal through an OR operation for further encoding, and the lower circuit uses the chip selection signal as the hit signal of this level and transmits it downward again through the OR gate step by step until the last level circuit, and the last level outputs a hit flag;

[0049] Step 3: The low-order address is read out and the high-order address is encoded in parallel, and each level of each channel group outputs a partial address to form a hit address;

[0050] Step 4, the control latch latches the hit information and controls the read switch of the tri-state buffer, that is, when there is no hit, the output is in high impedance state, and when there is a hit, the corresponding value of the output pull-up and pull-down units is output as the low address to the peripheral circuit, ensuring that when a hit is effective, only one channel outputs data to the bus;

[0051] Step 5: Use the current mirror drive circuit to output the integrated low and high address to the address bus, and use the address signal to control the state of the current mirror drive circuit. Example 2

[0052] In this embodiment, please refer to the attached Figure 3 , Figure 3 The figure shows the overall block diagram of the first-level circuit with a fixed 6-bit address. The low-order address readout circuit is divided into K / 64 groups. The overall circuit level is suitable for circuits with 256 channels or above.

[0053] Taking a circuit containing 1024 channels as an example, there are 16 first-level low-order address readout circuits, 4 second-level encoding circuits, and a total of three levels of the overall circuit.

[0054] The reset signal is valid at low level. During reset, the pull-up and pull-down units are used to configure the address bits of the module. In the figure, ADDR_1ST[5:0] is the address bit of each channel. This value remains unchanged after reset, that is, each first-level low-order address readout circuit module contains 64 channels and 384 address bits. The figure is simplified, and the hit signal is the same.

[0055] When a hit occurs, the output corresponding channel address bit value is transmitted to the peripheral circuit as the lower 6-bit address. The module that is hit generates a first-level chip select signal CS_1ST and transmits it to the second-level encoding circuit. The second-level encoding circuit is fixed to a 4-2 encoding circuit. After encoding, it is transmitted to the drive circuit for output. The chip select hit module generates a second-level chip select signal CS_2ND and transmits it to the third-level encoding circuit. Similarly, the higher two bits of address are generated. After the integration of each address bit, it is transmitted to the current mirror drive circuit for reading. Finally, the circuit generates a HIT signal to indicate that a channel has been hit and this reading is valid. Example 3

[0056] In this embodiment, please refer to the attached Figure 4 , the internal circuit of the channel was expanded.

[0057] Taking the fixed 6-bit address register size as an example, each first-level low-order address readout circuit module contains 64 channels. When reset, the channel corresponds to the address, for example, CH0 corresponds to 000000, and CH63 corresponds to 111111. The address bit content remains unchanged during the entire transmission process.

[0058] When a hit occurs, the switch is turned on and the output is in high impedance state to prevent bus contention. When a hit occurs, the switch is turned off and the output address data is output to the peripheral circuit as the low-order address ADDR_1ST.

[0059] At the same time, each hit signal is OR-operated to generate a chip select signal CS_1ST which is transmitted to the secondary encoding circuit. If only the first-level low-order address readout structure is used as the overall readout structure, this signal does not need to be generated. Example 4

[0060] Please refer to the attached Figure 5 In this embodiment, the address bits in the channel are configured using pull-up and pull-down units.

[0061] Set the pull-up and pull-down units according to the channel number. Take channel CH7 as an example. Its address bit corresponds to the binary code 000111. Set the pull-down unit PULL0 to connect to the high 3-bit address, and the pull-up unit PULL1 to connect to the low 3-bit address. Both the pull-up unit and the pull-down unit can be implemented using a digital standard cell library.

[0062] Set up a three-state buffer T_BUF, and the hit signal controls T_BUF through the control latch. When a hit occurs, T_BUF outputs the six-bit address value set by the pull-up and pull-down units. When a hit does not occur, T_BUF outputs a high-impedance state and prohibits data output, thereby preventing bus contention. Example 5

[0063] Please refer to the attached Figure 6 In this embodiment, a 4-2 encoder is used to encode the high-order address. The encoding circuits of all levels except the first level are the same, which are all 4-2 encoders. Taking a certain encoder of the second level as an example, the enco_1 signal is directly transmitted to the next level circuit as the hit signal CS_2ND after the OR operation, and the signal is encoded at the same time. The encoding result is output as a part of the high-order address ADDR_2ND. The encoding method is: 4'b0001 -> 2'b00, 4'b0010 -> 2'b01, 4'b0100 -> 2'b10, 4'b1000 -> 2'b11. Example 6

[0064] Please refer to the attached Figure 7 The present invention uses a current mirror driving circuit to avoid the bus competition problem when reading the address. The current mirror driving circuit enhances the driving ability of the circuit when the address is output, and uses an NMOS tube as a switch to control the output channel by the address signal, which can prevent invalid data from being read out.

[0065] Since each channel has the possibility of hitting, the current generating circuit should be connected to each channel and share a current mirror driving circuit.

[0066] When not hit, all NMOS switches are in the off state, and no data is allowed to be output to the address bus. When hit, the corresponding address signal is transmitted to the NMOS switch to open the corresponding address line of the channel and output to the address bus.

[0067] This embodiment is applicable to the situation where only one channel is hit at the same time. If simultaneous hits occur due to delay or other reasons, a certain address is obtained randomly and other addresses are discarded.

[0068] If you want to read out the addresses of multiple channels hitting the circuit at the same time, you can add priority logic to the hitting signal so that it can be read out according to priority.

[0069] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0070] The above embodiments are merely examples of the present invention and do not limit the protection scope of the present invention. All designs that are the same or similar to the present invention fall within the protection scope of the present invention.

Claims

1. A fast address readout circuit, characterized in that: It includes multiple groups of channels, and each group of channels has the same circuit connection structure; Each group of channels integrates an address control register and a pull-up and pull-down unit. The channels are grouped according to the address bits. Each group has multiple fixed channels. The pull-up and pull-down units are used to configure the address bits in the channels. The channel hit signals in each group of channels are calculated and transmitted to the lower-level encoding circuit as the chip select signal of the group. The lower-level encoding circuit transmits the chip select signal step by step in the same way. Each group of the channels is provided with a tri-state buffer as a control switch, and the tri-state buffer controls the output state of the address data, controls the latch to latch the hit signal, and controls the opening and closing state of the tri-state buffer.

2. The fast address readout circuit according to claim 1, characterized in that: The pull-up and pull-down units are configured with address data when being reset, and after being reset, the corresponding values ​​of each address remain unchanged.

3. The fast address readout circuit according to claim 1, characterized in that: When the channel is outputting, it means that the pixel point corresponding to the channel is hit. Multiple pixel points form an array. According to the array size and the total number of channels, the number of pull-up and pull-down unit configuration bits in the channel is set to x bits, representing the lower x bits of the data address.

4. The fast address readout circuit according to claim 3, characterized in that: Channels are grouped according to address bits, and each group is fixed channels, and x represents the number of bits configured for the pull-up and pull-down units in each channel.

5. The fast address readout circuit according to claim 4, characterized in that: The calculation formula for the total number of stages of the overall circuit is: ； Where N is the total number of circuit stages and K is the total number of channels.

6. The fast address readout circuit according to claim 5, characterized in that: The number of pixels in the array divided by If the obtained value is not a multiple of 4, the total number of levels is obtained by rounding down, and the upper two addresses are not encoded.

7. The fast address readout circuit according to claim 1, characterized in that: Except for the first stage, the other stages of the circuit are composed of different numbers of 4-2 encoders to obtain two-bit addresses.

8. A method for reading an address fast reading circuit according to any one of claims 1 to 7, characterized in that: The following steps are involved: During reset, the address is configured by the pull-up and pull-down units in the channel, and the address registers in each channel of each group of channels are coded in binary format; The hit signals of each channel in each group of channels are transmitted to the lower circuit as chip selection signals for further encoding through OR operation. The lower circuit uses the chip selection signal as the hit signal of this level and transmits it downward through the OR gate again step by step until the last level circuit, which outputs the hit flag. The low-order address readout and high-order address encoding are operated in parallel, and each level of circuit outputs a partial address to form the hit address; The control latch latches the hit information and controls the read switch of the tri-state buffer, that is, when there is no hit, the output is in high impedance state, and when there is a hit, the corresponding value of the pull-up and pull-down units is output as the low-order address to the peripheral circuit, ensuring that when a hit is effective, only one channel outputs data to the bus; A current mirror driving circuit is used to output the integrated low and high address to the address bus, and the state of the current mirror driving circuit is controlled by the address signal.

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