A novel electrostatic protection method

Abstract

This application discloses a novel electrostatic discharge (ESD) protection method, comprising: placing an integrated circuit on a first chip; and placing an ESD protection circuit on a second chip. The ESD protection circuit includes: a first input output port, a second input contact port, a first diode, a first resistor, a first N-type field-effect transistor (FET), and a ground output port, and further includes a second diode, a capacitor, and a second N-type FET. The first input output port is connected to the input port of the integrated circuit, enabling the ESD protection method to achieve dual protection for the integrated circuit and effectively ensuring the reliability of the integrated circuit. Furthermore, by placing the integrated circuit and the ESD protection circuit on different chips, the ESD protection design is avoided on the chip containing the integrated circuit, thus avoiding the problem of being unable to perform ESD protection design due to limitations in the substrate material of the chip containing the integrated circuit. This facilitates the realization of ESD protection for ESD-sensitive novel material integrated circuits.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a novel electrostatic discharge protection method. Background Technology

[0002] With the development of integrated circuit technology, its applications are becoming increasingly widespread, making electrostatic discharge (ESD) protection for integrated circuits increasingly important. However, in reality, the impact of ESD on integrated circuits in their environment is uncontrollable and unpredictable. Therefore, providing a robust ESD protection method to effectively suppress ESD damage to integrated circuits is crucial for their development.

[0003] Furthermore, with the development of integrated circuit technology, an increasing number of new material integrated circuits have emerged or are about to be released. These new material integrated circuits use substrate materials different from those of traditional silicon-based integrated circuits, exhibiting superior performance and becoming a rising star in improving computer speed and reducing power consumption in electronic devices. However, these new material integrated circuits are typically very sensitive to static electricity and prone to electrostatic damage. Moreover, due to limitations in the characteristics of their substrate materials, existing integrated circuit electrostatic protection designs are often ineffective, making it impossible to provide effective electrostatic protection for these circuits. This results in the easy failure of these integrated circuits due to electrostatic damage in practical applications. Therefore, providing a novel electrostatic protection method for these new material integrated circuits has become a key research focus for those skilled in the art. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a novel electrostatic discharge (ESD) protection method. This method has strong ESD protection capabilities and can also provide ESD protection for ESD-sensitive novel material integrated circuits, thereby helping to ensure the reliability of the integrated circuits.

[0005] To address the above problems, the embodiments of this application provide the following technical solutions:

[0006] A novel electrostatic discharge (ESD) protection method utilizes an ESD protection circuit to protect integrated circuits from ESD. The method includes:

[0007] A first chip is provided, and the integrated circuit is disposed on the first chip, the integrated circuit including an input port;

[0008] A second chip is provided, on which the electrostatic discharge (ESD) protection circuit is disposed. The ESD protection circuit includes: an input / output port, a first diode, a first resistor, a first N-type field-effect transistor (FET), and a ground terminal. The input / output port includes a first input / output port and a second input / output port. The second input / output port is connected to the first input / output port through the first resistor. A first end of the first resistor is connected to the first input / output port, and a second end is connected to the second input / output port. The drain of the first N-type FET is connected to the first end of the first resistor, and the source is connected to the gate of the first N-type FET and the ground terminal. The ground terminal is grounded. The cathode of the first diode is connected to the second end of the first resistor, and the anode is connected to the ground terminal.

[0009] The electrostatic discharge protection circuit further includes: a second diode, a capacitor, and a second N-type field-effect transistor; wherein, the positive terminal of the second diode is connected to the negative terminal of the first diode, the negative terminal is connected to the drain of the second N-type field-effect transistor through the first terminal of the capacitor, the gate of the second N-type field-effect transistor is connected to the second terminal of the capacitor, and the source is connected to the ground terminal.

[0010] The first input output port is connected to the input port of the integrated circuit so that the electrostatic discharge protection circuit provides electrostatic protection for the integrated circuit.

[0011] Optionally, the first chip is a carbon-based chip, and the second chip is a silicon-based chip.

[0012] Optionally, the integrated circuit further includes an output port, and the electrostatic discharge protection circuit further includes: an output terminal, a third diode, and a fourth diode, wherein the output terminal includes a first output terminal and a second output terminal, the second output terminal is connected to the first output terminal through the anode of the three diodes, the cathode of the third diode is connected to the drain of the second N-type field-effect transistor, the cathode of the fourth diode is connected to the anode of the third diode, and the anode of the fourth diode is connected to the ground terminal; the method further includes:

[0013] Connect the first output port to the output port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

[0014] Optionally, the integrated circuit further includes a power supply port, and the electrostatic discharge protection circuit further includes: a power output port and a fifth diode, wherein the power output port includes a first power output port and a second power output port, the first power output port is connected to the drain of the second N-type field-effect transistor, the second power output port is connected to the cathode of the second diode, the cathode of the fifth diode is connected to the first power output port, and the anode is connected to the ground output port; the method further includes:

[0015] The first power output port is connected to the power port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

[0016] Optionally, the first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode.

[0017] Optionally, the electrostatic discharge protection circuit further includes a second resistor; the method further includes:

[0018] The first end of the second resistor is connected to the gate of the second N-type field-effect transistor, and the second end is connected to the ground terminal.

[0019] Optionally, the integrated circuit further includes a ground port, the ground output port including a first ground output port and a second ground output port; the method further includes:

[0020] Connect the first ground output port to the ground port of the integrated circuit, connect the second ground output port to the first ground output port, and ground the second ground output port.

[0021] Compared with existing technologies, the above technical solution has the following advantages:

[0022] The technical solution provided in this application includes: providing a first chip, on which an integrated circuit is disposed, the integrated circuit including an input port; providing a second chip, on which an electrostatic discharge (ESD) protection circuit is disposed, the ESD protection circuit including: an input output port, a first diode, a first resistor, a first N-type field-effect transistor (FET), and a ground output port, and further including a second diode, a capacitor, and a second N-type FET, wherein the input output port includes a first input output port and a second input output port; connecting the first input output port to the input port of the integrated circuit, so that the ESD protection circuit provides ESD protection for the integrated circuit and suppresses ESD damage to the integrated circuit. Furthermore, the ESD protection circuit in the ESD protection method provided in this application includes an input output port, a first diode, a first resistor, a first N-type FET, and a ground output port, and further includes a second diode, a capacitor, and a second N-type FET, enabling the ESD protection circuit to achieve dual protection for the integrated circuit, possessing strong ESD protection capability, and more effectively suppressing ESD damage to the integrated circuit. Furthermore, the method places the electrostatic discharge (ESD) protection circuit on the second chip and the integrated circuit on the first chip, so that the integrated circuit and the ESD protection circuit are placed on different chips. This eliminates the need for ESD protection design on the first chip, i.e., it eliminates the need for ESD protection design on the chip where the integrated circuit is located. This avoids the problem of being unable to perform ESD protection design due to the limitations of the substrate material of the chip where the integrated circuit is located. It enables ESD protection for ESD-sensitive novel material integrated circuits and contributes to the development of novel material integrated circuits. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A flowchart illustrating a novel electrostatic discharge protection method provided in this application embodiment;

[0025] Figure 2 This is a schematic diagram of the circuit structure in a novel electrostatic discharge protection method provided in an embodiment of this application;

[0026] Figure 3 A schematic diagram of the positive electrostatic pulse IV curve at the input output port and the leakage current curve between the second input output port and the ground port of an electrostatic protection circuit provided in this application embodiment;

[0027] Figure 4 A schematic diagram of the negative electrostatic pulse IV curve of the input / output / power output port of an electrostatic protection circuit provided in this application embodiment, and the leakage current curve between the input / output / power output port and the ground output port.

[0028] Figure 5 A schematic diagram of the positive electrostatic pulse IV curve at the output port and the leakage current curve between the second output port and the ground port of an electrostatic protection circuit provided in this application embodiment.

[0029] Figure 6 This is a schematic diagram of the positive electrostatic pulse (IV) curve at the power supply output port and the leakage current curve between the second power supply output port and the ground output port, provided in an embodiment of this application for an electrostatic protection circuit. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0032] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0033] As described in the background section, in order to effectively suppress damage to integrated circuits caused by electrostatic discharge, it is crucial to provide a protection method with strong electrostatic protection capabilities for the development of integrated circuits.

[0034] Furthermore, to overcome the physical limitations of traditional silicon-based integrated circuits, researchers have focused on fabricating integrated circuits on novel material chips to create novel material integrated circuits. These novel material integrated circuits use different substrate materials than traditional silicon-based integrated circuits. Carbon-based integrated circuits, formed by fabricating integrated circuits on carbon-based chips, exhibit superior performance, making them one of the most widely studied novel material integrated circuits. The core component of carbon-based integrated circuits is the carbon-based transistor, which operates five times faster than a silicon-based transistor of the same size while consuming less than one-fifth the energy. This combination of higher processing speed and lower energy consumption makes carbon-based integrated circuits a promising candidate for widespread research.

[0035] According to the inventors' research, most of these novel material integrated circuits are typically highly sensitive to electrostatic pulses and are referred to as electrostatic-sensitive novel material integrated circuits. They are prone to electrostatic damage. Furthermore, due to limitations in the properties of their substrate materials, these electrostatic-sensitive novel material integrated circuits cannot be directly designed for electrostatic protection on the chip where the integrated circuit is located. In other words, on-chip electrostatic protection design for integrated circuits is not possible. This makes it impossible for existing integrated circuit electrostatic protection designs to protect against electrostatic damage, thus failing to suppress electrostatic damage. As a result, in practical applications, these integrated circuits are prone to functional failure due to electrostatic damage, affecting the application and development of novel material integrated circuits.

[0036] For example, carbon-based integrated circuits suffer from problems such as thin carbon film, low conductivity, and poor heat dissipation. As a result, it is impossible to directly complete the electrostatic discharge (ESD) protection design for the carbon-based integrated circuit on the chip itself. In other words, it is impossible to achieve on-chip ESD protection for the integrated circuit, and thus it is impossible to effectively suppress ESD damage to the carbon-based integrated circuit, affecting its application.

[0037] Therefore, in order to support the development of integrated circuits and achieve electrostatic protection for electrostatic-sensitive novel material integrated circuits, providing an electrostatic protection method that can achieve electrostatic protection for the aforementioned electrostatic-sensitive novel material integrated circuits has become a research focus for those skilled in the art.

[0038] Based on this, embodiments of this application provide a novel electrostatic discharge (ESD) protection method. This method uses an ESD protection circuit to protect integrated circuits from ESD, such as... Figure 1 As shown, the method includes:

[0039] S1: As Figure 2 As shown, a first chip 100 is provided, and the integrated circuit is disposed on the first chip 100 to complete the fabrication of an integrated circuit chip with a specific function. The integrated circuit includes an input port 01. The integrated circuit is a novel material integrated circuit, but this application does not limit it and it depends on the specific circumstances.

[0040] S2: Continue as follows Figure 2 As shown, a second chip 200 is provided, and an electrostatic discharge (ESD) protection circuit is laid on the second chip 200 to complete the fabrication of an ESD protection circuit with protective capabilities. The ESD protection circuit includes: an input / output port, a first diode 11, a first resistor 12, a first N-type field-effect transistor 13, and a ground output port 20.

[0041] The input / output ports include a first input / output port 111 and a second input / output port 112. The second input / output port 112 is connected to the first input / output port 111 through the first resistor 12. The first end of the first resistor 12 is connected to the first input / output port 111, and the second end is connected to the second input / output port 112. The drain of the first N-type field-effect transistor 13 is connected to the first end of the first resistor 12, and the source is connected to the gate of the first N-type field-effect transistor 13 and the ground terminal output port 20, respectively. The ground terminal output port 20 is grounded. Since the drain of the first N-type field-effect transistor is connected to the first end of the first resistor, and the first end of the first resistor is connected to the first input / output port, the drain of the first N-type field-effect transistor is also connected to the first input / output port. Since the second end of the first resistor is connected to the second input / output port, the drain of the first N-type field-effect transistor is connected to the second input / output port through the first resistor. The cathode of the first diode 11 is connected to the second end of the first resistor 12, and the anode is connected to the ground terminal output port 20. Since the second input output port 112 is connected to the second end of the first resistor 12, and the cathode of the first diode 11 is connected to the second end of the first resistor 12, the cathode of the first diode 11 is also connected to the second input output port 112.

[0042] The electrostatic discharge protection circuit further includes: a second diode 14, a capacitor 15, and a second N-type field-effect transistor 16; wherein, the anode of the second diode 14 is connected to the cathode of the first diode 11, and as previously known, the cathode of the first diode 11 is connected to the second input output port 112, thus the anode of the second diode 14 is also connected to the second input output port 112; the cathode of the second diode 14 is connected to the drain of the second N-type field-effect transistor 16 through the first terminal of the capacitor 15; the gate of the second N-type field-effect transistor 16 is connected to the second terminal of the capacitor 15, and the source is connected to the ground output port 20;

[0043] S3: Connect the first input output port to the input port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

[0044] It should be noted that the first input output port is connected to the integrated circuit input port by a wire bonding method, and the first input output port is connected to the first end of the first resistor by a metal wire. Therefore, even if the first input output port is connected to the integrated circuit input port and is also connected to the first end of the first resistor, the integrated circuit input port will not be directly connected to the first end of the first resistor.

[0045] It should also be noted that, in the embodiments of this application, the input output port includes two input output ports: a first input output port and a second input output port. The integrated circuit includes one input port, but this application does not limit this. In other embodiments of this application, the electrostatic discharge protection circuit may also include one input output port or at least three input output ports, and the integrated circuit may include at least two input ports, depending on the specific circumstances.

[0046] Specifically, in this embodiment, the integrated circuit is disposed on the first chip, and the electrostatic discharge (ESD) protection circuit is disposed on the second chip. The input port of the integrated circuit is connected to the first input / output port of the ESD protection circuit, enabling the ESD protection circuit to be connected to the integrated circuit. This allows the ESD protection method to provide ESD protection for the integrated circuit, thereby helping to suppress ESD damage and ensuring the reliability of the integrated circuit. Furthermore, the ESD protection circuit in the ESD protection method provided in this embodiment includes an input / output port, a first diode, a first resistor, a first N-type field-effect transistor, and a ground port. It also includes a second diode, a capacitor, and a second N-type field-effect transistor, enabling the ESD protection method to achieve dual protection for the integrated circuit, providing strong ESD protection capabilities and more effectively suppressing ESD damage to the integrated circuit.

[0047] Furthermore, due to limitations in the substrate material of the aforementioned known electrostatic-sensitive novel material integrated circuits, on-chip electrostatic protection designs cannot be implemented. This prevents existing electrostatic protection designs from effectively suppressing electrostatic damage to these circuits, thus hindering their practical application. However, the electrostatic protection method provided in this application places the electrostatic protection circuit on a second chip and the integrated circuit on a first chip. This allows the integrated circuit and the electrostatic protection circuit to be located on different chips, eliminating the need for electrostatic protection design on the first chip. This avoids the problem of electrostatic protection design limitations due to the substrate material of the integrated circuit chip, enabling electrostatic protection for electrostatic-sensitive novel integrated circuits. This, in turn, improves the reliability of novel material integrated circuits and promotes their development. Meanwhile, the electrostatic discharge (ESD) protection method provided in this application places the integrated circuit and the ESD protection circuit on different chips, enabling the ESD protection circuit to provide off-chip ESD protection for the integrated circuit. This allows the ESD protection method to also be applied to integrated circuits with high on-chip ESD protection design costs, which helps save ESD protection costs for integrated circuits and promotes the development of integrated circuits.

[0048] Based on the above embodiments, in this embodiment, when a positive electrostatic pulse flows in from the second input output port, due to the forward conduction characteristic of the diode, the positive electrostatic pulse will not flow through the first diode, but will flow through the first resistor. The drain of the first N-type field-effect transistor is connected to the first end of the first resistor, so the positive electrostatic pulse flows through the first resistor and then through the drain of the first N-type field-effect transistor. It is known that the gate and source of the first N-type field-effect transistor are connected, and the gate is connected to the ground output port, that is, the gate and source of the first N-type field-effect transistor are short-circuited and both are grounded (called Gate Ground NMOS, abbreviated as GGNMOS), so that the source of the first N-type field-effect transistor is at a low potential, and the gate of the first N-type field-effect transistor is also at a low potential. So when the positive electrostatic pulse flows through the drain of the first N-type field-effect transistor and the intensity is low, the first N-type field-effect transistor is in the off state. When the intensity of the positive electrostatic pulse is large, the first N-type field-effect transistor will be turned on, and the positive electrostatic pulse will flow through the first N-type field-effect transistor and flow out from the ground output port. The integrated circuit input port is connected to the first input output port, and the first input output port is connected to the second input output port through the first resistor. Thus, after the positive electrostatic pulse flows through the first resistor, it will also flow through the first input output port and into the integrated circuit through the integrated circuit input port.

[0049] It should be noted that integrated circuits typically include multiple electronic devices such as resistors, capacitors, and field-effect transistors. In this embodiment, the resistance of the integrated circuit is made relatively large, greater than the resistance of the first N-type field-effect transistor. Since the current intensity flowing into each parallel branch is related to the resistance of each branch, the current intensity flowing into a branch with a large resistance is low, and the current intensity flowing into a branch with a small resistance is high. Therefore, after the positive electrostatic pulse flows through the first resistor, the electrostatic pulse intensity flowing through the first N-type field-effect transistor is greater than the electrostatic pulse intensity flowing into the integrated circuit through the first input / output port and the integrated circuit input port. This causes most of the positive electrostatic pulse intensity to flow out through the first N-type field-effect transistor, effectively reducing the intensity of the electrostatic pulse flowing into the integrated circuit. Consequently, the electrostatic protection circuit can, to a certain extent, suppress electrostatic damage to the integrated circuit, helping to ensure the reliability of the integrated circuit. It should also be noted that although integrated circuits are sensitive to electrostatic pulses, the intensity of the electrostatic pulse flowing into the integrated circuit must reach a certain value before electrostatic damage occurs. The first N-type field-effect transistor in the electrostatic protection circuit provided in this application will conduct when the positive electrostatic pulse intensity is high, preventing high-intensity electrostatic pulses from flowing into the integrated circuit. This allows the electrostatic protection method to suppress electrostatic damage to the integrated circuit, thereby enabling the method to provide electrostatic protection. Furthermore, GGNMOS is a commonly used MOS device in electrostatic protection circuits, and its working principle is well known to those skilled in the art; therefore, a detailed description of the specific working principle of GGNMOS will not be provided here.

[0050] It should also be noted that, in order to ensure the protection of the integrated circuit by the electrostatic discharge (ESD) protection circuit, the conduction voltage of the first N-type field-effect transistor in the ESD protection circuit of the ESD protection method provided in this application embodiment is lower than the ESD damage voltage of the integrated circuit. This means that the ESD pulse intensity that the first N-type field-effect transistor can conduct is less than the ESD pulse intensity that causes ESD damage to the integrated circuit, thereby ensuring the protection of the integrated circuit by the ESD protection circuit.

[0051] It should also be noted that the electrostatic discharge (ESD) protection circuit further includes a second diode, a capacitor, and a second N-type field-effect transistor (FET). This ensures that when a positive ESD pulse flows in from the second input port, the pulse also flows through the path formed by the second diode and the second N-type FET, exiting from the ground port. The principle behind the positive ESD pulse flowing through the path is as follows: after flowing through the second diode, the pulse couples with the capacitor, releasing charge to the gate of the second N-type FET, raising its gate potential, and turning it on. This allows the positive ESD pulse to flow through the second N-type FET and exit from the ground port.

[0052] It is known that the resistance of the integrated circuit is greater than that of the second N-type field-effect transistor (FET). Since the diode's resistance is smaller, the resistance of the path formed by the second diode and the second N-type FET is still smaller than the integrated circuit's resistance. Simultaneously, because the first N-type FET requires a relatively strong positive electrostatic discharge (ESD) pulse to conduct, when the ESD pulse strength is low, it will flow through the path formed by the second diode and the second N-type FET, as well as the path formed by the first resistor and the integrated circuit. Because the resistance of the path formed by the second diode and the second N-type FET is smaller than that of the integrated circuit, the intensity of the ESD pulse flowing through this path is greater than that flowing through the path formed by the first resistor and the integrated circuit. This causes most of the ESD pulse to flow through the path of the second diode and the second N-type FET and exit from the ground terminal, reducing the intensity of the ESD pulse flowing into the integrated circuit. Therefore, the ESD protection method can, to a certain extent, suppress ESD damage to the integrated circuit and can also suppress the flow of ESD pulses into the integrated circuit when the ESD pulse intensity is low, thus protecting integrated circuits with weak ESD tolerance.

[0053] When the positive electrostatic discharge (ESD) intensity is high, the ESD pulse will flow through the path formed by the second diode and the second N-type field-effect transistor, and also through the path formed by the first resistor and the first N-type field-effect transistor, and will flow out from the ground terminal. This allows the ESD protection method to achieve dual protection for the integrated circuit, further reducing the intensity of the ESD pulse flowing through the integrated circuit, and thus effectively suppressing ESD damage to the integrated circuit. It should be noted that, due to the small resistance of the diode (usually less than the resistance of the resistor in the circuit), the resistance of the path formed by the second diode and the second N-type field-effect transistor (FET) is less than the resistance of the path formed by the first resistor and the first N-type FET. Furthermore, since the resistance of the integrated circuit is greater than the resistance of the first N-type FET, the intensity of the positive electrostatic pulse is relatively large. When the pulse flows through the drain of the first N-type FET and is strong enough to turn it on, the intensity of the positive electrostatic pulse flowing through the path formed by the second diode and the second N-type FET is greater than the intensity flowing through the path formed by the first resistor and the first N-type FET. This results in most of the positive electrostatic pulse flowing out through both the path formed by the second diode and the second N-type FET and the path formed by the first resistor and the first N-type FET. Therefore, the path formed by the first resistor and the first N-type FET in the electrostatic protection circuit, along with the path formed by the second diode and the second N-type FET, provides dual protection for the integrated circuit, effectively preventing electrostatic damage.

[0054] When a negative electrostatic pulse flows in from the second input terminal, it is known that the negative terminal of the first diode is connected to the second input terminal, and the positive terminal is connected to the ground terminal. According to the forward conduction characteristic of the diode, the negative electrostatic pulse, after flowing in from the second input terminal, will flow through the first diode and out from the ground terminal. Furthermore, the integrated circuit input port is connected to the first input terminal, and the first input terminal is connected to the second input terminal through the first resistor. Simultaneously, the drain of the first N-type field-effect transistor is also connected to the first end of the first resistor. Therefore, the positive electrostatic pulse, after flowing in from the second input terminal, will also flow through the path formed by the first resistor and the first N-type field-effect transistor, as well as the path formed by the first resistor and the integrated circuit.

[0055] It should be noted that when the drain of an N-type field-effect transistor (FET) is connected to a negative voltage, the PN junction of the FET will conduct, making the FET function like a diode. Therefore, when the negative electrostatic pulse flows through the drain of the first N-type FET, the FET functions like a diode. Since the drain of the first N-type FET is connected to the first terminal of the first resistor, and the source is connected to the ground terminal, the first N-type FET functions like a diode with its negative terminal connected to the first terminal of the first resistor and its positive terminal connected to the ground terminal. This causes the electrostatic pulse to flow through the first N-type FET and exit from the ground terminal. When the negative electrostatic pulse flows through the drain of the first N-type field-effect transistor (FET) via the first resistor, the FET acts as a diode, making its resistance similar to that of the first diode. Consequently, the resistance of the first diode is less than the resistance of the path formed by the first resistor and the FET. Furthermore, since the integrated circuit has a larger resistance than the FET, the resistance of the path formed by the first resistor and the FET is less than the resistance of the path formed by the first resistor and the integrated circuit. Therefore, after the negative electrostatic pulse flows in from the second input port, the intensity flowing through the first diode is greater than the intensity flowing through the path formed by the first resistor and the first N-type field-effect transistor, and the intensity flowing through the path formed by the first resistor and the first N-type field-effect transistor is greater than the intensity flowing through the path formed by the first resistor and the integrated circuit. That is, after the positive electrostatic pulse flows in from the second input port, the intensity flowing through the first diode and the path formed by the first resistor and the first N-type field-effect transistor is greater than the intensity flowing through the path formed by the first resistor and the integrated circuit. This causes most of the intensity of the negative electrostatic pulse to flow out through the path formed by the first resistor and the first N-type field-effect transistor and the first diode, reducing the intensity of the electrostatic pulse flowing into the integrated circuit. As a result, the electrostatic protection method can, to a certain extent, suppress electrostatic damage to the integrated circuit and ensure the reliability of the integrated circuit.

[0056] Furthermore, the electrostatic discharge (ESD) protection circuit provided in this application, when a positive ESD pulse is applied to the second input / output port, increases the first resistance, reducing the potential of the drain of the first N-type field-effect transistor (FET). This helps prevent the FET from being damaged by thermal breakdown due to excessive power, thereby ensuring the reliability of the ESD protection circuit and enabling it to reliably protect the integrated circuit from ESD damage. Simultaneously, increasing the first resistance also reduces the potential of the integrated circuit's input port, helping to prevent the input port from burning out, further contributing to the reliability of the integrated circuit.

[0057] In addition, it should be noted that the above embodiments describe the situation where electrostatic pulses flow into the integrated circuit from the outside through the second input output port. There is another situation where electrostatic pulses exist inside the integrated circuit. The electrostatic protection circuit can also suppress electrostatic damage to the integrated circuit when electrostatic pulses exist inside the integrated circuit. Specifically, when an electrostatic pulse exists inside the integrated circuit and acts on the input port, if the electrostatic pulse is positive, since the integrated circuit input port is connected to the first input output port, and the first input output port is connected to the second input output port through the first resistor, if the positive electrostatic pulse is weak enough not to turn on the first N-type field-effect transistor, part of the positive electrostatic pulse remains inside the integrated circuit, and part flows through the first input output port connected to the integrated circuit input port. After flowing through the first input output port, it flows through the path formed by the first resistor, the second diode, and the second N-type field-effect transistor. Because integrated circuits include many electronic components, their resistance is relatively high, exceeding the resistance of the path formed by the first resistor, the second diode, and the second N-type field-effect transistor. Consequently, the intensity of the positive electrostatic pulse flowing out through the path formed by the first resistor, the second diode, and the second N-type field-effect transistor is greater than the intensity remaining inside the integrated circuit. This results in most of the positive electrostatic pulse flowing out through the path formed by the first resistor, the second diode, and the second N-type field-effect transistor, thereby enabling the electrostatic protection method to reduce the intensity of the electrostatic pulse inside the integrated circuit and, to a certain extent, suppress electrostatic damage to the integrated circuit.

[0058] If the electrostatic pulse is a positive electrostatic pulse and has a relatively high intensity, enough to turn on the first N-type field-effect transistor (FET), then after flowing through the first input / output port, it will flow through the first N-type FET in addition to the path formed by the first resistor, the second diode, and the second N-type FET, and exit from the ground port. This can further reduce the intensity of the electrostatic pulse inside the integrated circuit, thereby allowing the electrostatic protection method to suppress electrostatic damage to the integrated circuit to a certain extent. It should be noted that the intensity of the positive electrostatic pulse flowing through the path formed by the first resistor, the second diode, and the second N-type FET, and the intensity flowing through the first N-type FET, are related to the resistance of the path formed by the first resistor, the second diode, and the second N-type FET, and the resistance of the first N-type FET. A path with relatively high resistance will have a smaller electrostatic pulse intensity, and vice versa.

[0059] If the electrostatic pulse is negative, a portion of it remains inside the integrated circuit, while a portion flows into the electrostatic discharge (ESD) protection circuit through the first input port. After flowing into the ESD protection circuit, it passes through the first N-type field-effect transistor (FET) and exits from the ground port, and also passes through the first diode and exits from the ground port. Since the resistance of the first N-type FET and the resistance of the first diode are both less than the resistance of the integrated circuit, the intensity of the negative ESD pulse flowing into the ESD protection circuit is greater than the intensity remaining inside the integrated circuit. This allows the ESD protection method to reduce the intensity remaining inside the integrated circuit and suppress ESD damage to the integrated circuit.

[0060] Optionally, in one embodiment of this application, the first chip is a carbon-based chip and the second chip is a silicon-based chip. However, this application is not limited to this. In other embodiments of this application, the first chip may also be other chips that cannot achieve on-chip electrostatic protection design, depending on the specific circumstances.

[0061] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the integrated circuit also includes an output port 02, and the electrostatic discharge protection circuit also includes: an output port, a third diode 31, and a fourth diode 32;

[0062] The output ports include a first output port 311 and a second output port 312. The second output port 312 is connected to the first output port 311 through the anode of the third diode 31. That is, the anode of the third diode 31 is connected to both the second and first output ports 311. The cathode of the third diode 31 is connected to the second N-type field-effect transistor 16. The cathode of the fourth diode 32 is connected to the anode of the third diode 31, and the anode of the fourth diode 32 is connected to the ground port 20. Since the anode of the third diode 31 is connected to both the second and first output ports 311, and the cathode of the fourth diode 32 is connected to the anode of the third diode 31, the cathode of the fourth diode 32 is also connected to both the second and first output ports 311.

[0063] S4: Connect the first output port to the output port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

[0064] It should be noted that the first output port is connected to the output port of the integrated circuit by a wire bonding method, and the first output port is connected to the positive terminal of the third diode by a metal wire. Therefore, even if the first output port is connected to the input port of the integrated circuit and is also connected to the positive terminal of the third diode, the output port of the integrated circuit will not be directly connected to the positive terminal of the third diode.

[0065] It should also be noted that, in the embodiments of this application, the output port includes two output ports: a first output port and a second output port, and the integrated circuit includes one output port. However, this application does not limit this. In other embodiments of this application, the electrostatic protection circuit may also include one output port or at least three output ports, and the integrated circuit may include at least two output ports, depending on the specific circumstances.

[0066] Specifically, in this embodiment, the first output port of the electrostatic discharge protection circuit is connected to the output port of the integrated circuit, thereby connecting the electrostatic discharge protection circuit to the integrated circuit. This enables the electrostatic discharge protection method to protect the integrated circuit from electrostatic discharge, suppressing electrostatic pulses from flowing into the integrated circuit through its output port, thus helping to suppress electrostatic damage to the integrated circuit and promoting its development.

[0067] Based on the above embodiments, in this embodiment, when a positive electrostatic pulse flows in from the second output port, due to the forward conduction characteristic of the diode, the positive electrostatic pulse will not flow through the fourth diode, but will flow through the third diode. Since the negative terminal of the third diode is connected to the drain of the second N-type field-effect transistor, the positive electrostatic pulse will flow through the drain of the second N-type field-effect transistor, thus flowing through the path formed by the third diode and the second N-type field-effect transistor, and flowing out from the ground terminal. Furthermore, since the second output port is connected to the first output port through the positive terminal of the third diode, and the first output port is connected to the output port of the integrated circuit, the positive electrostatic pulse will also flow through the path formed by the first output port and the integrated circuit, flowing into the integrated circuit from the output port of the integrated circuit. Because the diode has a low resistance and the integrated circuit includes multiple field-effect transistors and other electronic devices, the resistance of the path formed by the third diode and the second N-type field-effect transistor is still relatively low compared to the resistance of the integrated circuit. Therefore, when the positive electrostatic pulse flows in from the second output port, the intensity of the pulse flowing through the path formed by the third diode and the second N-type field-effect transistor is greater than the intensity of the pulse flowing through the path formed by the first output port and the integrated circuit. This results in most of the positive electrostatic pulse's intensity flowing through the path formed by the third diode and the second N-type field-effect transistor and exiting from the ground port, effectively reducing the intensity of the electrostatic pulse flowing into the integrated circuit. Thus, the electrostatic protection method can, to a certain extent, suppress electrostatic damage to the integrated circuit and ensure its reliability. It should be noted that the principle of the positive electrostatic pulse flowing through the path formed by the third diode and the second N-type field-effect transistor is as follows: after the positive electrostatic pulse flows in from the second output port, it flows through the third diode and couples with the capacitor, causing the capacitor to release charge to the gate of the second N-type field-effect transistor, raising the gate potential of the second N-type field-effect transistor, causing the second N-type field-effect transistor to conduct, and thus allowing the positive electrostatic pulse to flow through the path formed by the third diode and the second N-type field-effect transistor and flow out from the ground terminal.

[0068] When a negative electrostatic pulse flows in from the second output port, due to the forward conduction characteristic of the diode, the negative electrostatic pulse will not flow through the third diode but will flow through the fourth diode. Furthermore, since the second output port is connected to the first output port, and the first output port is connected to the output port of the integrated circuit, the negative electrostatic pulse will also flow through the first output port and into the integrated circuit from the output port connected to the first output port. It is known that the diode resistance is smaller than the resistance of the integrated circuit. Therefore, after the negative electrostatic pulse flows in from the second output port, the intensity flowing through the fourth diode is greater than the intensity flowing into the integrated circuit. This causes most of the negative electrostatic pulse to flow through the fourth diode and exit from the ground terminal, thus enabling the electrostatic protection method to effectively reduce the intensity of the electrostatic pulse flowing into the integrated circuit and help suppress electrostatic damage to the integrated circuit.

[0069] Furthermore, when an electrostatic pulse (ESP) exists inside the integrated circuit and acts on its output port, if the ESP is positive, a portion of it will remain inside the integrated circuit. Since the output port of the integrated circuit is connected to the first output terminal, and the first output terminal is connected to the positive terminal of the third diode, a portion of the positive ESP will flow through the first output terminal connected to the integrated circuit's output port. After flowing through the first output terminal, according to the forward conduction characteristic of the diode, it will flow through the path formed by the third diode and the second N-type field-effect transistor, exiting from the ground terminal. Because the diode has a small resistance, the resistance of the path formed by the third diode and the second N-type field-effect transistor is still less than the resistance of the integrated circuit. This results in the intensity of the positive ESP flowing out through the path formed by the third diode and the second N-type field-effect transistor being greater than the intensity of the ESP inside the integrated circuit, reducing the intensity of the ESP inside the integrated circuit. Consequently, the ESP protection method can help suppress ESP damage to the integrated circuit and ensure its reliability.

[0070] When the electrostatic discharge (ESD) pulse is negative, a portion of it remains inside the integrated circuit (IC), while another portion flows through the first output port connected to the IC's output port. Due to the forward conduction characteristic of the diode, after flowing through the first output port, the negative ESD pulse passes through the fourth diode and exits from the ground port. Because the diode's resistance is lower than that of the IC, the intensity of the negative ESD pulse flowing through the fourth diode and exiting from the ground port is higher than the intensity of the portion remaining inside the IC. This allows the ESD protection method to reduce the intensity of the ESD pulse inside the IC, thereby suppressing ESD damage to the IC to a certain extent and helping to ensure the reliability of the IC.

[0071] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the integrated circuit also includes a power port 03, and the electrostatic discharge protection circuit also includes a power output port and a fifth diode 41;

[0072] The power output ports include a first power output port 411 and a second power output port 412. The first power output port 411 is connected to the drain of the second N-type field-effect transistor 16, and the second power output port 412 is connected to the cathode of the second diode 14. Since the cathode of the second diode 14 is connected to the drain of the second N-type field-effect transistor 16 through the first terminal of the capacitor 15, the second power output port 412 is connected to the first power output port in sequence through the cathode of the second diode 14, the first terminal of the capacitor 15, and the drain of the second N-type field-effect transistor 16. The cathode of the fifth diode 41 is connected to the first power output port 411, and the anode is connected to the ground output port 20. Since the second power output port 412 is connected to the first power output port in sequence through the cathode of the second diode 14, the first terminal of the capacitor 15, and the drain of the second N-type field-effect transistor 16, and the cathode of the fifth diode 41 is connected to the first power output port 411, the second power output port 412 is connected to the fifth diode 41 in sequence through the cathode of the second diode 14, the first terminal of the capacitor 15, the drain of the second N-type field-effect transistor 16, and the first power output port 411; the method further includes:

[0073] S5: Connect the first power output port to the power port of the integrated circuit, so that the electrostatic discharge protection circuit can be connected to the integrated circuit, so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

[0074] It should be noted that the first power output port is connected to the integrated circuit power port via a wire bonding method, and the first power output port is connected to the drain of the second N-type field-effect transistor via a metal wire. Furthermore, the first power output port is connected to the negative terminal of the fifth diode via a metal wire. Therefore, even if the first power output port is connected to the integrated circuit power port, and the first power output port is also connected to the drain of the second N-type field-effect transistor and the negative terminal of the fifth diode, the integrated circuit power port will not be directly connected to the drain of the second N-type field-effect transistor, nor will it be directly connected to the negative terminal of the fifth diode.

[0075] It should also be noted that, in the embodiments of this application, the power output port includes two power output ports: a first power output port and a second power output port. The integrated circuit includes one power port, but this application does not limit this. In other embodiments of this application, the electrostatic discharge protection circuit may also include one power output port or at least three power output ports, and the integrated circuit may include at least two power ports, depending on the specific circumstances.

[0076] Specifically, in this embodiment, the first power output port of the electrostatic discharge protection circuit is connected to the power port of the integrated circuit, thereby connecting the electrostatic discharge protection circuit to the integrated circuit. This enables the electrostatic discharge protection method to protect the integrated circuit from electrostatic discharge, suppressing electrostatic pulses from flowing into the integrated circuit through the power port of the integrated circuit, thus helping to suppress electrostatic damage to the integrated circuit and promoting the development of the integrated circuit.

[0077] Based on the above embodiments, in this embodiment, when a positive electrostatic pulse flows in from the second power output port, according to the forward conductivity of the diode, the positive electrostatic pulse will not flow through the second diode, the third diode, and the fifth diode. Since the second power output port is connected to the drain of the second N-type field-effect transistor through the first terminal of the capacitor, the positive electrostatic pulse will flow through the second N-type field-effect transistor and exit from the ground output port. Furthermore, the second power output port is connected to the first power output port through the negative terminal of the second diode, the first terminal of the capacitor, and the drain of the second N-type field-effect transistor. The first power output port is also connected to the integrated circuit power port, so the positive electrostatic pulse will also flow through the first power output port and into the integrated circuit from the integrated circuit power port connected to the first power output port. Because the integrated circuit has a larger resistance than the second N-type field-effect transistor, the intensity of the positive electrostatic pulse flowing into the first N-type field-effect transistor after flowing into the second power supply port is greater than the intensity flowing into the integrated circuit. As a result, most of the positive electrostatic pulse flows through the second N-type field-effect transistor and out from the ground port. This allows the electrostatic protection method to reduce the intensity of the electrostatic pulse flowing into the integrated circuit, thus protecting the integrated circuit from electrostatic damage and ensuring its reliability.

[0078] When a negative electrostatic pulse flows in from the second power output port, since the second power output port is connected to the first power output port through the negative terminal of the second diode, the first terminal of the capacitor, and the drain of the second N-type field-effect transistor, the negative electrostatic pulse will flow through the first power output port connected to the power port of the integrated circuit, and then flow into the integrated circuit from the power port of the integrated circuit. It will also flow through the drain of the first N-type field-effect transistor. It is known that a negatively charged drain of the field-effect transistor will cause the PN junction of the N-type field-effect transistor to conduct, making the N-type field-effect transistor equivalent to a diode. Since the drain of the second N-type field-effect transistor is connected to the second power output port, and the source is connected to the ground output port, when a negative electrostatic pulse flows in from the second power output port, the second N-type field-effect transistor acts as a diode with its negative terminal connected to the second power output port and its positive terminal connected to the ground output port. This causes the negative electrostatic pulse to flow through the second N-type field-effect transistor and out from the ground output port. Furthermore, since the electrostatic discharge (ESD) protection circuit also includes a fifth diode, the negative terminal of which is connected to the first power supply output port, and the positive terminal connected to the ground output port, the positive ESD pulse will also flow through the fifth diode and exit from the ground output port. It is known that when a negative ESD pulse flows in, the second N-type field-effect transistor (FET) acts as a diode. Therefore, when a negative ESD pulse flows in, the second N-type FET and the fifth diode have the same conduction capability. Considering the minute resistance present in the wires in the circuit, the intensity of the negative ESD pulse flowing through the second N-type FET and the fifth diode is related to the length of the wire between the second N-type FET and the fifth diode and the second power supply output port. A shorter wire results in a stronger path, and a longer wire results in a weaker path. Because the integrated circuit has a larger resistance than the diode, the intensity of the negative electrostatic pulse flowing into the integrated circuit is greater when it passes through the fifth diode and the second N-type field-effect transistor than when it flows into the integrated circuit itself. As a result, most of the negative electrostatic pulse can flow out from the ground terminal through the fifth diode and the second N-type field-effect transistor. This allows the electrostatic protection method to reduce the intensity of the electrostatic pulse flowing into the integrated circuit, thus protecting the integrated circuit from electrostatic discharge and ensuring its reliability.

[0079] In addition, based on the forward conduction characteristics of diodes, after the negative electrostatic pulse flows in, it will also flow through the path formed by the second diode and the first diode, the path formed by the second diode and the first N-type field-effect transistor, and the path formed by the third diode and the fourth diode. Since the second N-type field-effect transistor is equivalent to a diode at this time, and the resistance on the wire is very small, it cannot affect the resistance between the different paths formed by the circuit elements. Therefore, the resistance of the path formed by the second diode and the first diode, the path formed by the second diode and the first N-type field-effect transistor, and the path formed by the third diode and the fourth diode is greater than the resistance of the second N-type field-effect transistor. Furthermore, since the path formed by the second diode and the first diode includes two diodes, the path formed by the second diode and the first N-type field-effect transistor includes one diode and the first field-effect transistor, and the path formed by the third diode and the fourth diode... The circuit includes two diodes. Therefore, the resistance of the circuit formed by the second diode and the first diode, the circuit formed by the second diode and the first N-type field-effect transistor, and the circuit formed by the third diode and the fourth diode is greater than the resistance of the fifth diode. Consequently, the electrostatic pulse intensity flowing through the second N-type field-effect transistor and the fifth diode is greater than the electrostatic pulse intensity flowing through the circuits formed by the second diode and the first diode, the second diode and the first N-type field-effect transistor, and the third diode and the fourth diode. Furthermore, the electrostatic pulse intensity flowing through the circuits formed by the second diode and the first diode, the second diode and the first N-type field-effect transistor, and the third diode and the fourth diode is related to the resistance of each circuit; a higher resistance results in a lower electrostatic pulse intensity, and a lower resistance results in a higher electrostatic pulse intensity. This will not be elaborated further here.

[0080] Furthermore, when an electrostatic pulse (ESP) exists inside the integrated circuit and acts on its power port, if the ESP is positive, a portion of it will remain inside the integrated circuit. Since the first power output port is connected to the integrated circuit's power port, a portion of the ESP will flow through the first power output port connected to the integrated circuit's power port. After flowing through the first power output port, according to the forward conduction characteristic of the diode, it will flow through the drain of the second N-type field-effect transistor (FET) and couple with the capacitor, releasing charge to the second N-type FET, raising its gate potential, and turning it on. Thus, the positive ESP, after flowing through the first power output port, will flow through the second N-type FET and discharge from the ground port. Because the resistance of the integrated circuit is greater than the resistance of the second N-type FET, the intensity of the positive ESP flowing through the second N-type FET is greater than the intensity remaining inside the integrated circuit. Therefore, the ESP method can reduce the intensity of the ESP inside the integrated circuit, thereby suppressing ESP damage to the integrated circuit to a certain extent.

[0081] If the electrostatic pulse is negative, a portion of it will remain inside the integrated circuit, while the remainder will flow through the first power output port connected to the integrated circuit's power supply port. As previously mentioned, the second N-type field-effect transistor (FET) is essentially a diode with its negative terminal connected to the first power output port and its positive terminal connected to the ground output port. Due to the forward conduction characteristic of a diode, the negative electrostatic pulse will flow through the second N-type FET. Since the negative terminal of the fifth diode is connected to the first power output port, and its positive terminal is connected to the ground output port, the negative electrostatic pulse will also flow through the fifth diode. In this case, the fifth diode and the second N-type FET have the same conduction capability. Considering the minute resistance in the circuit's wires, the intensity of the negative electrostatic pulse flowing through the second N-type FET and the fifth diode depends on the length of the wire between the second N-type FET and the fifth diode and the second power output port. A shorter wire results in a stronger path, and a longer wire results in a weaker path. Because the integrated circuit has a larger resistance than the diode, the intensity of the negative electrostatic pulse flowing through the second N-type field-effect transistor and the fifth resistor is greater than the intensity remaining inside the integrated circuit. This allows the electrostatic protection method to reduce the intensity of the electrostatic pulse inside the integrated circuit, helping to suppress electrostatic damage to the integrated circuit.

[0082] Furthermore, since the second power output port is connected to the negative terminal of the second diode, and the second power output port is connected to the first power output port through the first terminal of the first capacitor and the drain of the first N-type field-effect transistor, the first power output port can be connected to the negative terminal of the second diode through the drain of the second N-type field-effect transistor and the first terminal of the capacitor. Also, since the negative terminal of the third diode is connected to the drain of the second N-type field-effect transistor, and the drain of the second N-type field-effect transistor is also connected to the first power output port, the negative terminal of the third diode is connected to the first power output port. According to the forward conduction characteristics of the diode, after the negative electrostatic pulse flows through the first power output port, it will also flow through the path formed by the second diode and the first diode, the path formed by the second diode and the first N-type field-effect transistor, and the path formed by the third diode and the fourth diode, and flow out from the ground output port. At the same time, the electrostatic pulse intensity on each path is related to the resistance of each path. The electrostatic pulse intensity is low when the resistance is high, and the electrostatic pulse intensity is high when the resistance is low. This will not be elaborated further here.

[0083] It should be noted that when an electrostatic pulse (ESP) exists inside the integrated circuit, after flowing through the first input port, first output port, or first power output port, it may flow through other ports of the ESP protection circuit. However, due to the low resistance and strong shunt capability of the ESP protection circuit, the intensity of the ESP flowing through these other ports will also be low. Therefore, even if the ESP flows through other ports of the ESP protection circuit, it will not affect the operation of those other ports. Similarly, when an ESP flows into the second input port, second output port, or second power output port of the ESP protection circuit, it may also flow through other ports. Likewise, due to the low resistance and strong shunt capability of the ESP protection circuit, the intensity of the ESP flowing through these other ports will also be low. Therefore, even if the ESP flows through other ports of the ESP protection circuit, it will not affect the operation of those other ports.

[0084] It should also be noted that, in this embodiment, to avoid affecting the normal operation of the integrated circuit, the turn-on voltage of the field-effect transistor in the electrostatic discharge (ESD) protection circuit is approximately 20% higher than the turn-on voltage of the integrated circuit. This ensures that when the integrated circuit is turned on, the field-effect transistor in the ESD protection circuit is in a closed state. This prevents the power signal from flowing through the ESD protection circuit's field-effect transistor and then exiting from the ground terminal after passing through the second power output port, thus preventing the integrated circuit from malfunctioning. Furthermore, according to... Figure 1 As can be seen, each diode in the electrostatic discharge protection circuit is in reverse connection with the second power output port. This ensures that after the power signal of the integrated circuit flows through the second power output port, the power signal will not flow through the diodes and out of the ground terminal, thus guaranteeing the normal operation of the integrated circuit.

[0085] Optionally, in one embodiment of this application, the first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode. However, this embodiment of the application does not limit this. In other embodiments of the application, the first diode, the second diode, the third diode, the fourth diode, and the fifth diode can also be commonly used ordinary diodes, depending on the specific circumstances.

[0086] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the electrostatic discharge protection circuit further includes: a second resistor 50; the method further includes:

[0087] S6: Connect the first end of the second resistor 50 to the gate of the second N-type field-effect transistor 16, and the second end to the ground terminal 20. Since the gate of the second N-type field-effect transistor 16 is connected to the second end of the capacitor 15, the first end of the second resistor 50 is connected to the second end of the capacitor 15 through the gate of the second N-type field-effect transistor 16. After the electrostatic pulse couples with the capacitor, the capacitor will discharge to the gate of the second N-type field-effect transistor, accumulating charge at the gate of the second N-type field-effect transistor, triggering the second N-type field-effect transistor to turn on. However, if too much charge accumulates at the gate of the second N-type field-effect transistor, it will cause damage to the second N-type field-effect transistor. The increase of the second resistor can share some of the electrical energy released by the capacitor, which helps to prevent excessive charge accumulation at the gate of the second N-type field-effect transistor from damaging the second N-type field-effect transistor. This helps to ensure the reliability of the electrostatic protection circuit, so that the electrostatic protection method can reliably reduce the possibility of electrostatic damage to the integrated circuit and ensure the reliability of the integrated circuit.

[0088] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the integrated circuit further includes a ground port, and the ground output port 20 includes a first ground output port 21 and a second ground output port 22; the method further includes:

[0089] S7: Connect the first ground output port 21 to the ground port 04 of the integrated circuit, connect the second ground output port 22 to the first ground output port 21, and ground the second ground output port 22, thereby grounding the ground port 04 of the integrated circuit, enabling the electrostatic discharge circuit to discharge electrostatic pulses from the second ground output port 22. The first ground output port and the ground port of the integrated circuit are connected by a wire bonding, and the first ground output port and the second ground output port are connected by a metal wiring. It should be noted that in this embodiment, the ground output port includes two ground output ports: a first ground output port and a second ground output port. The integrated circuit includes one ground port. However, this application is not limited to this. In other embodiments of this application, the electrostatic discharge circuit may also include one or more ground output ports, and the integrated circuit may include at least two ground ports, depending on the specific situation.

[0090] It should be noted that, continuing as Figure 2 As shown, the second power output port 412 of the electrostatic discharge (ESD) protection circuit is connected to an external power supply 61, the second input output port 112 is connected to an external input port 62, the second output output port 312 is connected to an external output port 63, and the second ground output port 22 is grounded to ground 64. This ensures that the integrated circuit can be connected to the outside world while being protected by the ESD protection circuit, guaranteeing the normal operation of the integrated circuit. Furthermore, the various output ports of the ESD protection circuit are connected to the various ports of the integrated circuit and the various external ports via wire bonding, but this application does not limit this connection; it depends on the specific circumstances.

[0091] To gain a clearer understanding of the electrostatic discharge (ESD) protection capability of the circuit, a TLP (ThinPrep) device was used to test its protection capability. The ESD protection capability of the circuit will be described below based on the test results from the TLP device.

[0092] Specifically, when a positive electrostatic pulse (ESP) is applied to the second input output port, in order to test the ESP protection capability of the ESP protection circuit, a TLP device is used to monitor the positive ESP flowing into the second input output port and the leakage current between the second input output port and the ground output port. The results are as follows: Figure 3 As shown, curve 1 is the IV curve of the electrostatic pulse at the second input output port, and curve 2 is the leakage current curve between the second input output port and the ground port. Figure 3It can be seen that when the positive electrostatic pulse intensity increases to 8V or slightly higher, the leakage current is small. As the positive electrostatic pulse intensity continues to increase, the leakage current rises rapidly, at which point electrostatic damage occurs to the integrated circuit. This indicates that the electrostatic protection circuit can withstand a positive electrostatic pulse of 8V or slightly higher flowing into the second input output port. When a negative electrostatic pulse acts on the second input output port, the TLP is also used to monitor the negative electrostatic pulse at the second input port and the leakage current between the second input port and the ground port. The results are as follows. Figure 4 As shown, curve 1 is the electrostatic pulse IV curve of the second input output port, and curve 2 is the leakage current curve between the second input output port and the ground port. Figure 4 It can be seen that when the intensity of the negative electrostatic pulse increases to 8V or slightly higher, the leakage current is small. As the electrostatic pulse continues to increase, the leakage current increases rapidly. At this time, electrostatic damage occurs to the integrated circuit, indicating that the electrostatic protection circuit can withstand a negative electrostatic pulse with an intensity of 8V or slightly higher flowing in from the second input output port.

[0093] When a positive electrostatic pulse (ESP) is applied to the second output port, in order to test the ESD protection capability of the ESD protection circuit, a TLP device is used to monitor the positive ESD pulse flowing into the second output port and the leakage current between the second output port and the ground port. The results are as follows: Figure 5 As shown, curve 1 is the positive electrostatic pulse (ESP) IV curve of the second output port, and curve 2 is the leakage current curve between the second output port and the ground port. According to... Figure 5 It can be seen that when the positive electrostatic pulse intensity increases to 10V or slightly higher, the leakage current is small, and the integrated circuit does not suffer electrostatic damage. However, as the positive electrostatic pulse continues to increase, the leakage current increases rapidly, and the integrated circuit suffers electrostatic damage. This indicates that the electrostatic protection circuit can withstand a positive electrostatic pulse of 10V or slightly higher flowing into the second output port. When a negative electrostatic pulse acts on the second output port, the TLP is also used to monitor the electrostatic pulse at the second output port and the leakage current between the second output port and the ground port. The results are then obtained as follows... Figure 4 As shown, the electrostatic discharge protection circuit can withstand negative electrostatic pulses with an intensity of 8V or slightly higher than 8V flowing in from the second output port.

[0094] When a positive electrostatic pulse is applied to the second power output port, a TLP device is used to monitor the positive electrostatic pulse flowing into the second power output port and the leakage current between the second power output port and the ground output port. The results are as follows: Figure 6As shown, curve 1 is the positive electrostatic pulse (ESP) IV curve of the second power output port, and curve 2 is the leakage current curve between the second power output port and the ground port. According to... Figure 6 It can be seen that when the positive electrostatic pulse intensity increases to 14V or slightly higher, the leakage current is small, and the integrated circuit is not damaged at this time. As the positive electrostatic pulse continues to increase, the leakage current increases rapidly, and electrostatic damage occurs in the integrated circuit. This indicates that the electrostatic protection circuit can withstand a positive electrostatic pulse of 14V or slightly higher flowing into the second power output port. When a negative electrostatic pulse acts on the second input output port, the TLP is also used to monitor the negative electrostatic pulse at the second power output port and the leakage current between the second power output port and the ground port. The results are then obtained as follows... Figure 4 As shown, the electrostatic discharge protection circuit can withstand negative electrostatic pulses with an intensity of 8V or slightly higher than 8V flowing in from the second power output port.

[0095] In summary, this application provides a novel electrostatic discharge (ESD) protection method for integrated circuits. The method includes: placing the integrated circuit on a first chip, the integrated circuit including an input port; and placing the ESD protection circuit on a second chip, the ESD protection circuit including an input output port, a first diode, a first resistor, a first N-type field-effect transistor (FET), and a ground output port, and further including a second diode, a capacitor, and a second N-type FET. The input output port includes a first input output port and a second input output port. The first input output port is connected to the input port of the integrated circuit, enabling the ESD protection circuit to connect to the integrated circuit, thereby providing ESD protection and helping to suppress ESD damage to the integrated circuit. Furthermore, the ESD protection circuit in the ESD protection method provided by this application includes an input output port, a first diode, a first resistor, a first N-type FET, and a ground output port, and also includes a second diode, a capacitor, and a second N-type FET, enabling the ESD protection circuit to achieve dual protection for the integrated circuit, possessing strong ESD protection capabilities, and more effectively suppressing ESD damage to the integrated circuit. Furthermore, the method places the electrostatic discharge (ESD) protection circuit on the second chip and the integrated circuit on the first chip, so that the integrated circuit and the ESD protection circuit are placed on different chips. This eliminates the need for ESD protection design on the first chip, i.e., it eliminates the need for ESD protection design on the chip where the integrated circuit is located. This avoids the problem of being unable to perform ESD protection design due to the limitations of the substrate material of the chip where the integrated circuit is located. It enables ESD protection for ESD-sensitive novel material integrated circuits and contributes to the development of novel material integrated circuits.

[0096] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0097] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for electrostatic protection, characterized in that, Electrostatic discharge (ESD) protection for integrated circuits is achieved using an ESD protection circuit. This method includes: A first chip is provided, and the integrated circuit is disposed on the first chip, the integrated circuit including an input port; A second chip is provided, on which the electrostatic discharge (ESD) protection circuit is disposed. The ESD protection circuit includes: an input / output port, a first diode, a first resistor, a first N-type field-effect transistor (FET), and a ground terminal. The input / output port includes a first input / output port and a second input / output port. The second input / output port is connected to the first input / output port through the first resistor. A first end of the first resistor is connected to the first input / output port, and a second end is connected to the second input / output port. The drain of the first N-type FET is connected to the first end of the first resistor, and the source is connected to the gate of the first N-type FET and the ground terminal. The ground terminal is grounded. The cathode of the first diode is connected to the second end of the first resistor, and the anode is connected to the ground terminal. The electrostatic discharge protection circuit further includes: a second diode, a capacitor, and a second N-type field-effect transistor; wherein, the positive terminal of the second diode is connected to the negative terminal of the first diode, the negative terminal is connected to the drain of the second N-type field-effect transistor through the first terminal of the capacitor, the gate of the second N-type field-effect transistor is connected to the second terminal of the capacitor, and the source is connected to the ground terminal. The first input output port is connected to the input port of the integrated circuit so that the electrostatic discharge protection circuit provides electrostatic protection for the integrated circuit.

2. The electrostatic protection method according to claim 1, characterized in that, The first chip is a carbon-based chip, and the second chip is a silicon-based chip.

3. The electrostatic protection method according to claim 1, characterized in that, The integrated circuit further includes an output port, and the electrostatic discharge protection circuit further includes: an output terminal, a third diode, and a fourth diode, wherein the output terminal includes a first output terminal and a second output terminal, the second output terminal is connected to the first output terminal through the positive terminal of the third diode, the negative terminal of the third diode is connected to the drain of the second N-type field-effect transistor, the negative terminal of the fourth diode is connected to the positive terminal of the third diode, and the positive terminal is connected to the ground terminal; the method further includes: Connect the first output port to the output port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

4. The electrostatic protection method according to claim 3, characterized in that, The integrated circuit further includes a power supply port, and the electrostatic discharge protection circuit further includes: a power output port and a fifth diode, wherein the power output port includes a first power output port and a second power output port, the first power output port is connected to the drain of the second N-type field-effect transistor, the second power output port is connected to the cathode of the second diode, the cathode of the fifth diode is connected to the first power output port, and the anode is connected to the ground output port; the method further includes: The first power output port is connected to the power port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

5. The electrostatic protection method according to claim 4, characterized in that, The first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode.

6. The electrostatic protection method according to claim 1, characterized in that, The electrostatic discharge protection circuit further includes a second resistor; the method further includes: The first end of the second resistor is connected to the gate of the second N-type field-effect transistor, and the second end is connected to the ground terminal.

7. The electrostatic protection method according to claim 1, characterized in that, The integrated circuit further includes a ground port, wherein the ground output port includes a first ground output port and a second ground output port; the method further includes: Connect the first ground output port to the ground port of the integrated circuit, connect the second ground output port to the first ground output port, and ground the second ground output port.

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