An electrostatic protection method for an integrated circuit

Abstract

The embodiment of the application discloses a static electricity protection method of an integrated circuit, which comprises the following steps: arranging the integrated circuit on a first chip, wherein the integrated circuit comprises an input port; arranging a static electricity protection circuit on a second chip, wherein the static electricity protection circuit comprises a first input output port, a second input output port, a first diode, a second diode, a capacitor, an N-type field effect transistor and a ground output port; connecting the first input output port with the input port, so that the static electricity protection circuit can be connected with the integrated circuit, thereby enabling the static electricity protection circuit to protect the integrated circuit from static electricity. Moreover, the integrated circuit and the static electricity protection circuit are arranged on different chips, thereby avoiding the static electricity protection design on the chip where the integrated circuit is arranged, and avoiding the problem that the static electricity protection design cannot be performed due to the limitation of the base material of the chip where the integrated circuit is arranged, and helping to realize the static electricity protection of the integrated circuit of a new material which is sensitive to static electricity.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an electrostatic discharge protection method for integrated circuits. Background Technology

[0002] With the development of integrated circuit technology, more and more new material integrated circuits have been or are about to be launched. The substrate materials of these new material integrated circuits are different from those of traditional silicon-based integrated circuits. They have superior performance compared to traditional silicon-based integrated circuits, becoming a new generation of stars that can improve computer speed and reduce the power consumption of electronic devices.

[0003] However, these novel material integrated circuits are typically highly sensitive to electrostatic pulses and prone to electrostatic damage. Furthermore, limitations in the properties of their substrate materials prevent the implementation of existing electrostatic protection designs for integrated circuits, hindering effective electrostatic protection and making these circuits susceptible to malfunction due to electrostatic damage in practical applications. Therefore, providing an electrostatic protection method for these novel material integrated circuits has become a key research focus for those skilled in the art. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides an electrostatic discharge (ESD) protection method for integrated circuits. This ESD protection method can provide ESD protection for ESD-sensitive novel material integrated circuits, effectively suppressing ESD damage to such integrated circuits and helping to ensure the reliability of integrated circuits.

[0005] To address the above problems, the embodiments of this application provide the following technical solutions:

[0006] An electrostatic discharge (ESD) protection method for integrated circuits, comprising an ESD protection circuit for the integrated circuits, the method comprising:

[0007] A first chip is provided, and the integrated circuit is disposed on the first chip, the integrated circuit including an input port;

[0008] A second chip is provided, on which the electrostatic discharge (ESD) protection circuit is disposed. The ESD protection circuit includes an input / output port, a first diode, a second diode, an N-type field-effect transistor (FET), a capacitor, and a ground terminal. The input / output port includes a first input / output port and a second input / output port. The second input / output port is connected to the first input / output port through the anode of the first diode. The cathode of the first diode is connected to the drain of the N-type FET through the first terminal of the capacitor. The gate of the N-type FET is connected to the second terminal of the capacitor, and its source is connected to the ground terminal. The ground terminal is grounded. The cathode of the second diode is connected to the anode of the first diode, and its anode is connected to the ground terminal.

[0009] Connect the first input output port to the input port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

[0010] Optionally, the first chip is a carbon-based chip, and the second chip is a silicon-based chip.

[0011] Optionally, the integrated circuit further includes an output port, and the electrostatic discharge protection circuit further includes: an output terminal, a third diode, and a fourth diode, wherein the output terminal includes a first output terminal and a second output terminal, the second output terminal is connected to the first output terminal through the positive terminal of the third diode, the negative terminal of the third diode is connected to the drain of the N-type field-effect transistor, the negative terminal of the fourth diode is connected to the positive terminal of the third diode, and the positive terminal is connected to the ground terminal; the method further includes:

[0012] Connect the first output port to the output port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

[0013] Optionally, the integrated circuit further includes a power supply port, and the electrostatic discharge protection circuit further includes: a power output port and a fifth diode, wherein the power output port includes a first power output port and a second power output port, the first power output port is connected to the drain of the N-type field-effect transistor, the second power output port is connected to the cathode of the first diode, the cathode of the fifth diode is connected to the first power output port, and the anode is connected to the ground output port; the method further includes:

[0014] The first power output port is connected to the power port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

[0015] Optionally, the first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode.

[0016] Optionally, the electrostatic discharge protection circuit further includes a resistor; the method further includes:

[0017] The first end of the resistor is connected to the gate of the N-type field-effect transistor, and the second end is connected to the ground terminal.

[0018] Optionally, the integrated circuit further includes a ground port, the ground output port including a first ground output port and a second ground output port; the method further includes:

[0019] Connect the first ground output port to the ground port of the integrated circuit, connect the second ground output port to the first ground output port, and ground the second ground output port.

[0020] Compared with existing technologies, the above technical solution has the following advantages:

[0021] The technical solution provided in this application embodiment provides electrostatic discharge (ESD) protection for integrated circuits via an ESD protection circuit. The method includes: providing a first chip and mounting the integrated circuit on the first chip, the integrated circuit including an input port; providing a second chip and mounting the ESD protection circuit on the second chip, the ESD protection circuit including an input output port, a first diode, a second diode, a capacitor, an N-type field-effect transistor, and a ground output port; wherein the input output port includes a first input output port and a second input output port, the first input output port is connected to the input port of the integrated circuit, enabling the ESD protection circuit to connect to the integrated circuit, thereby allowing the ESD protection circuit to provide ESD protection for the integrated circuit, helping to suppress ESD damage to the integrated circuit and ensuring the reliability of the integrated circuit. Furthermore, the electrostatic discharge (ESD) protection method provided in this application embodiment places the ESD protection circuit on the second chip and the integrated circuit on the first chip, so that the integrated circuit and the ESD protection circuit are placed on different chips. This eliminates the need for ESD protection design on the first chip, i.e., it eliminates the need for ESD protection design on the chip where the integrated circuit is located. This avoids the problem of being unable to perform ESD protection design due to the limitations of the substrate material of the chip where the integrated circuit is located. It enables ESD protection for ESD-sensitive novel material integrated circuits and contributes to the development of novel material integrated circuits. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart illustrating an electrostatic discharge protection method provided in this application embodiment;

[0024] Figure 2 This is a schematic diagram of the circuit structure in an electrostatic discharge protection method provided in an embodiment of this application;

[0025] Figure 3 A schematic diagram of the positive electrostatic pulse IV curve at the circuit input output port and the leakage current curve between the second input output port and the ground port in an embodiment of this application for an electrostatic protection method.

[0026] Figure 4 A schematic diagram of the negative electrostatic pulse IV curve of the circuit input / output / power output port and the leakage current curve between the input / output / power output port and the ground output port of an electrostatic protection method provided in this application embodiment.

[0027] Figure 5 A schematic diagram of the positive electrostatic pulse IV curve at the circuit output port and the leakage current curve between the second output port and the ground port of an electrostatic protection method provided in this application embodiment.

[0028] Figure 6 This is a schematic diagram of the positive electrostatic pulse (IV) curve at the power supply output port and the leakage current curve between the second power supply output port and the ground output port, which are provided in an embodiment of this application for an electrostatic protection method. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0031] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0032] To overcome the physical limitations of traditional silicon-based integrated circuits (ICs), researchers have focused on fabricating ICs on novel material chips to create novel material ICs. These novel material ICs use different substrate materials than traditional silicon-based ICs. Carbon-based ICs, in particular, exhibit superior performance due to their fabrication on carbon-based chips, making them one of the most widely studied novel material ICs. The core component of carbon-based ICs is the carbon-based transistor, which boasts a processing speed five times faster than a silicon-based transistor of the same size while consuming less than one-fifth the energy. This combination of higher processing speed and lower energy consumption makes carbon-based ICs a promising type of IC, attracting widespread research attention.

[0033] According to the inventors' research, most of these novel material integrated circuits are typically highly sensitive to electrostatic pulses and are referred to as electrostatic-sensitive novel material integrated circuits. They are prone to electrostatic damage. Furthermore, due to limitations in the properties of their substrate materials, these electrostatic-sensitive novel material integrated circuits cannot be directly designed for electrostatic protection on the chip where the integrated circuit is located. In other words, on-chip electrostatic protection design for integrated circuits is not possible. This makes it impossible for existing integrated circuit electrostatic protection designs to protect against electrostatic damage, thus failing to suppress electrostatic damage. As a result, in practical applications, these integrated circuits are prone to functional failure due to electrostatic damage, affecting the application and development of novel material integrated circuits.

[0034] For example, carbon-based integrated circuits suffer from problems such as thin carbon film, low conductivity, and poor heat dissipation. As a result, it is impossible to directly complete the electrostatic discharge (ESD) protection design for the carbon-based integrated circuit on the chip itself. In other words, it is impossible to achieve on-chip ESD protection for the integrated circuit, and thus it is impossible to effectively suppress ESD damage to the carbon-based integrated circuit, affecting its application.

[0035] Therefore, in order to support the development of integrated circuits and achieve electrostatic protection for electrostatic-sensitive novel material integrated circuits, providing an electrostatic protection method that can achieve electrostatic protection for the aforementioned electrostatic-sensitive novel material integrated circuits has become a research focus for those skilled in the art.

[0036] Based on this, this application provides an electrostatic discharge (ESD) protection method that can reduce the intensity of electrostatic discharge (ESD) pulses flowing through integrated circuits, helping to suppress ESD damage to integrated circuits to a certain extent. The integrated circuit mentioned above is an ESD-sensitive novel material integrated circuit, but this application does not limit it. The method provided in this application can also be applied to ESD protection of silicon-based integrated circuits and other integrated circuits disposed on traditional substrate materials, depending on the specific circumstances. Figure 1 As shown, the electrostatic discharge protection method includes:

[0037] S1: As Figure 2 As shown, a first chip 100 is provided, and the integrated circuit is disposed on the first chip 100 to complete the fabrication of an integrated circuit chip with a specific function. The integrated circuit includes an input port 01.

[0038] S2: Continue as follows Figure 2 As shown, a second chip 200 is provided, and the electrostatic discharge protection circuit is laid on the second chip 200 to complete the fabrication of an electrostatic discharge protection circuit with protection capability. The electrostatic discharge protection circuit includes: an input output port, a first diode 11, a second diode 12, an N-type field-effect transistor 13, a capacitor 14, and a ground output port 20.

[0039] The input / output ports include a first input / output port 111 and a second input / output port 112. The second input / output port 112 is connected to the first input / output port 111 through the anode of the first diode 11, i.e., the anode of the first diode 11 is connected to both the first input / output port 111 and the second input / output port 112. The cathode of the first diode 11 is connected to the drain of the N-type field-effect transistor 13 through the first terminal of the capacitor 14. The gate of the N-type field-effect transistor 13 is connected to the second terminal of the capacitor 14, and its source is connected to the ground terminal output port 20, which is grounded. The cathode of the second diode 12 is connected to the anode of the first diode, and its anode is connected to the... The ground terminal output port 20 is connected; since the positive terminal of the first diode is connected to the first input output port and the second input output port respectively, the negative terminal of the second diode is connected to the first input output port and the second input output port respectively; it should be noted that the first input output port of the electrostatic protection circuit is connected to the input port of the integrated circuit by a wire bonding method, and the first input output port is connected to the positive terminal of the first diode by a metal wire, so even if the first input output port is connected to the input port of the integrated circuit, and the first input output port is also connected to the positive terminal of the first diode, the input port of the integrated circuit and the positive terminal of the first diode will not be directly connected;

[0040] S3: Connect the first input output port to the input port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

[0041] It should be noted that, in the embodiments of this application, the input output port includes two input output ports: a first input output port and a second input output port. The integrated circuit includes one input port. However, this application does not limit this. In other embodiments of this application, the electrostatic discharge protection circuit may also include one input output port or at least three input output ports, and the integrated circuit may include at least two input ports, depending on the specific circumstances.

[0042] Specifically, in this embodiment, the integrated circuit is disposed on the first chip, the electrostatic discharge (ESD) protection circuit is disposed on the second chip, and the input port of the integrated circuit is connected to the first input / output port of the ESD protection circuit. This allows the ESD protection circuit to be connected to the integrated circuit, thereby enabling the ESD protection method to protect the integrated circuit from electrostatic discharge, which in turn helps to suppress ESD damage to the integrated circuit and ensure the reliability of the integrated circuit.

[0043] Furthermore, due to the limitations of the substrate material, on-chip electrostatic protection (ESP) designs for known ESD-sensitive novel material integrated circuits are impossible. This prevents existing ESP designs from effectively protecting these circuits from ESD damage, hindering their practical application. However, the ESP protection method provided in this application places the ESP protection circuit on a second chip and the integrated circuit on a first chip. This separates the integrated circuit and the ESP protection circuit from the ESP protection circuit, eliminating the need for ESP design on the first chip. This avoids the problem of ESP protection limitations caused by the substrate material of the integrated circuit chip, enabling ESP protection for ESD-sensitive novel integrated circuits. This, in turn, improves the reliability of novel material integrated circuits and promotes their development.

[0044] Furthermore, the electrostatic discharge (ESD) protection method provided in this application embodiment places the ESD protection circuit on the second chip and the integrated circuit on the first chip, that is, places the integrated circuit and the ESD protection circuit on different chips, so that the ESD protection circuit can achieve off-chip ESD protection for the integrated circuit. This allows the ESD protection circuit to also be applied to integrated circuits with high on-chip ESD protection design costs, which is beneficial to saving ESD protection costs for integrated circuits and promoting the development of integrated circuits.

[0045] Based on the above embodiments, in this embodiment, when a positive electrostatic pulse flows in from the second input output port, it is known that the anode of the first diode is connected to the second input output port, and the cathode of the second diode is connected to the second input output port. According to the forward conduction characteristic of the diode, the positive electrostatic pulse will not flow through the second diode, but will flow through the path formed by the first diode and the N-type field-effect transistor, and will flow out from the ground output port. Furthermore, since the first input output port is connected to the second input output port, the positive electrostatic pulse will also flow through the first input output port. Because the first input output port is connected to the input port of the integrated circuit, after the electrostatic pulse flows through the first input output port, it will also flow into the integrated circuit through the input port of the integrated circuit. The principle of the positive electrostatic pulse flowing through the path formed by the first diode and the N-type field-effect transistor is as follows: the positive electrostatic pulse flows through the first diode, and after flowing through the first diode, it couples with the capacitor, releases charge to the gate of the N-type field-effect transistor, pulls up the gate potential of the N-type field-effect transistor, and turns on the N-type field-effect transistor, so that the positive electrostatic pulse flows through the N-type field-effect transistor and flows out from the ground terminal, thereby making the positive electrostatic pulse flow through the path formed by the first diode and the N-type field-effect transistor.

[0046] It should be noted that integrated circuits typically include multiple field-effect transistors (FETs), resistors, capacitors, and other electronic devices. Since diodes have relatively low resistance, the overall resistance of the integrated circuit is greater than the resistance of the path formed by the diode and the FET. This results in the integrated circuit's resistance being greater than the resistance of the path formed by the first diode and the N-type FET. When parallel branches exist in the circuit, the current intensity flowing into each branch is related to the resistance of that branch; branches with higher resistance have lower current intensity, and branches with lower resistance have higher current intensity. Therefore, in this embodiment, after the positive electrostatic pulse flows in from the second input output port, the pulse intensity flowing through the path formed by the first diode and the N-type FET is greater than the intensity flowing into the integrated circuit. This causes most of the positive electrostatic pulse to flow out from the ground output port through the path formed by the first diode and the N-type FET, effectively reducing the intensity of the electrostatic pulse flowing into the integrated circuit. This allows the electrostatic protection circuit to suppress electrostatic damage to the integrated circuit to a certain extent, ensuring the reliability of the integrated circuit.

[0047] When a negative electrostatic discharge (ESD) pulse flows in from the second input output port, according to the forward conduction characteristic of the diode, the ESD pulse will not flow through the first diode, but will flow through the second diode and exit from the ground output port. Since the first input output port is connected to the second input output port and the first input output port is connected to the input port of the integrated circuit, the negative ESD pulse will also flow into the integrated circuit through the input port of the integrated circuit. It is known that the integrated circuit has a large resistance and the diode has a small resistance. Therefore, the resistance of the path formed by the first input output port and the integrated circuit is greater than the resistance of the second diode. This means that after the negative ESD pulse flows in from the second input output port, the intensity of the negative ESD pulse flowing through the second diode is greater than the intensity of the path flowing into the integrated circuit. Consequently, most of the negative ESD pulse flows through the second diode and into the ground output port. This allows the ESD protection circuit to effectively reduce the intensity of the ESD pulse flowing into the integrated circuit, thereby enabling the ESD protection circuit to suppress ESD damage to the integrated circuit to a certain extent. Thus, the ESD protection method can protect the integrated circuit from ESD, helping to ensure the reliability of the integrated circuit.

[0048] Additionally, it should be noted that the above embodiments describe the situation where electrostatic pulses flow into the integrated circuit from the outside through the second input output port. There is another situation where electrostatic pulses exist inside the integrated circuit. The electrostatic protection method can also suppress electrostatic damage to the integrated circuit when electrostatic pulses exist inside the integrated circuit. Specifically, when an electrostatic pulse (ESP) exists inside an integrated circuit and acts on its input port, if the ESP is a positive ESP, since the first input output port of the ESP protection circuit is connected to the input port of the integrated circuit, part of the positive ESP will remain inside the integrated circuit, and part will flow into the ESP protection circuit through the first input output port. Because the first input output port is connected to the anode of the first diode, part of the positive ESP, after flowing into the ESP protection circuit through the first input output port, will flow through the path formed by the first diode and the N-type field-effect transistor (FET) and exit from the ground output port. It is known that the resistance of the integrated circuit is greater than the resistance of the path formed by the first diode and the N-type FET. Therefore, the intensity of the positive ESP flowing through the path formed by the first diode and the N-type FET is greater than the intensity remaining inside the integrated circuit, causing part of the positive ESP to flow out through the ESP protection circuit. This allows the ESP protection method to reduce the intensity of the ESP remaining inside the integrated circuit, which can, to a certain extent, suppress ESP damage to the integrated circuit and help ensure its reliability.

[0049] If the electrostatic pulse is negative, similarly, a portion of the negative electrostatic pulse remains inside the integrated circuit, while a portion flows into the electrostatic discharge protection circuit through the first input output port. Since the negative terminal of the second diode is connected to the first input output port, according to the forward conduction characteristic of the diode, after a portion of the negative electrostatic pulse flows into the electrostatic discharge protection circuit through the first input output port, it will flow through the second diode and then out through the ground output port. It is known that the resistance of the integrated circuit is greater than the resistance of the diode, making the resistance of the integrated circuit greater than the resistance of the second diode. Therefore, the electrostatic pulse intensity of the negative electrostatic pulse flowing into the electrostatic discharge protection circuit is greater than the electrostatic pulse intensity remaining inside the integrated circuit. This allows the electrostatic discharge protection method to reduce the electrostatic pulse intensity inside the integrated circuit, which can suppress electrostatic damage to the integrated circuit to a certain extent and help ensure the reliability of the integrated circuit.

[0050] Optionally, in one embodiment of this application, the first chip is a carbon-based chip and the second chip is a silicon-based chip. However, this application is not limited to this. In other embodiments of this application, the first chip may also be other chips that cannot achieve on-chip electrostatic protection design, depending on the specific circumstances.

[0051] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2As shown, the integrated circuit also includes an output port 02. The electrostatic discharge protection circuit further includes: an output port, a third diode 31, and a fourth diode 32. The output port includes a first output port 311 and a second output port 312. The second output port 312 is connected to the first output port 311 through the positive terminal of the third diode 31, meaning the positive terminal of the third diode 31 is connected to the second output port 312, and the positive terminal of the third diode 31 is also connected to the first output port 311. The negative terminal of the third diode 31 is connected to the first terminal of the capacitor 14. It is known that the negative terminal 11 of the first diode is connected to the drain of the N-type field-effect transistor 13 through the first terminal of the capacitor 14, indicating that the first terminal of the capacitor 14 is connected to the drain of the N-type field-effect transistor 13. Therefore, the negative terminal of the third diode 31 can be connected to the N-type field-effect transistor 13 through the first terminal of the capacitor 14. The fourth diode 32... The negative terminal of diode 32 is connected to the positive terminal of the third diode 31, and the positive terminal is connected to the ground terminal 20. Since the positive terminal of the third diode 31 is connected to the second output terminal 312, and the positive terminal of the third diode 31 is also connected to the first output terminal 311, and the negative terminal of the fourth diode 32 is connected to the positive terminal of the third diode, the negative terminal of the fourth diode 32 is connected to the second output terminal 312, and the negative terminal of the fourth diode 32 is also connected to the first output terminal 311. It should be noted that the first output terminal is connected to the integrated circuit input port by a wire bonding method, and the first output terminal is connected to the positive terminal of the third diode by a metal wire connection. Therefore, even if the first output terminal is connected to the integrated circuit input port and is also connected to the positive terminal of the third diode, the integrated circuit input port is not directly connected to the positive terminal of the first diode.

[0052] This electrostatic protection method also includes:

[0053] S4: Connect the first output port to the output port of the integrated circuit, so that the electrostatic discharge protection circuit can be connected to the integrated circuit, so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

[0054] It should be noted that, in the embodiments of this application, the output port includes two output ports: a first output port and a second output port. The integrated circuit includes one output port, but this application does not limit this. In other embodiments of this application, the electrostatic protection circuit may also include one or more output ports, and the integrated circuit may include at least two output ports, depending on the specific circumstances.

[0055] Specifically, in this embodiment, the first output port of the electrostatic discharge (ESD) protection circuit is connected to the output port of the integrated circuit, thereby connecting the ESD protection circuit to the integrated circuit. This allows the ESD protection circuit to provide ESD protection to the integrated circuit, suppressing electrostatic pulses from flowing into the integrated circuit through its output port. Consequently, the ESD protection method can suppress ESD damage to the integrated circuit, thus contributing to the development of the integrated circuit.

[0056] Based on the above embodiments, in this embodiment, when a positive electrostatic pulse flows in from the second output port, the anode of the third diode is connected to the second output port, and the cathode of the fourth diode is connected to the second output port. According to the forward conduction characteristics of the diode, after the positive electrostatic pulse flows in from the second output port, it will flow through the path formed by the third diode and the N-type field-effect transistor and flow out from the ground port. Furthermore, since the second output port is connected to the first output port through the anode of the third diode, and the first input port is also connected to the output port of the integrated circuit, the positive electrostatic pulse will also flow into the integrated circuit after flowing in from the second output port. It is known that the resistance of the integrated circuit is greater than the resistance of the path formed by the diode and the field-effect transistor. Therefore, the resistance of the integrated circuit is greater than the resistance of the path formed by the third diode and the N-type field-effect transistor. This causes the positive electrostatic pulse flowing into the second output port to have a greater pulse intensity flowing through the path formed by the third diode and the N-type field-effect transistor than the pulse intensity flowing into the integrated circuit. Consequently, most of the positive electrostatic pulse flows through the path formed by the third diode and the N-type field-effect transistor and exits from the ground port, reducing the pulse intensity flowing into the integrated circuit. This allows the electrostatic protection circuit to suppress electrostatic damage to the integrated circuit to a certain extent. Therefore, the electrostatic protection method can protect the integrated circuit from electrostatic discharge, helping to ensure the reliability of the integrated circuit. The principle of the positive electrostatic pulse flowing through the path formed by the third diode and the N-type field-effect transistor is as follows: after the positive electrostatic pulse flows through the third diode, it couples with the capacitor, releases charge to the gate of the N-type field-effect transistor, pulls up the gate potential of the N-type field-effect transistor, turns on the N-type field-effect transistor, allows the positive electrostatic pulse to flow through the N-type field-effect transistor, and flows out from the ground terminal, thus allowing the positive electrostatic pulse to flow through the path formed by the third diode and the N-type field-effect transistor.

[0057] When a negative electrostatic pulse flows in from the second input port, according to the forward conduction characteristic of the diode, the negative electrostatic pulse will flow through the fourth diode after entering from the second input port, and then exit from the ground port. Since the negative terminal of the fourth diode is connected to both the second and first output ports, the negative electrostatic pulse will also flow through the first output port and then into the integrated circuit through its output port. It is known that the resistance of the integrated circuit is greater than the resistance of the diode, and therefore the resistance of the integrated circuit is greater than the resistance of the fourth diode. This means that the intensity of the negative electrostatic pulse flowing through the fourth diode after entering from the second input port is greater than the intensity flowing into the integrated circuit. Consequently, most of the negative electrostatic pulse flows through the fourth diode and exits from the ground port, reducing the pulse intensity flowing through the integrated circuit. This allows the electrostatic protection circuit to suppress electrostatic damage to the integrated circuit to a certain extent, thus enabling the electrostatic protection method to protect the integrated circuit from electrostatic discharge and helping to ensure its reliability.

[0058] Furthermore, when an electrostatic pulse (ESP) exists inside the integrated circuit and acts on its output port, if the ESP is positive, the first output port of the ESP protection circuit is connected to the output port of the integrated circuit. This causes a portion of the positive ESP to remain inside the integrated circuit, while a portion flows into the ESP protection circuit through the first output port. Since the anode of the third diode is connected to the first output port, and the cathode of the fourth diode is also connected to the first output port, based on the forward conduction characteristics of diodes, a portion of the positive ESP will flow into the ESP protection circuit through the first output port, then through the path formed by the third diode and the N-type field-effect transistor, and exit from the ground port. It is known that the resistance of the integrated circuit is greater than the resistance of the path formed by the third diode and the N-type field-effect transistor. Therefore, the strength of the positive electrostatic pulse flowing through the path formed by the third diode and the N-type field-effect transistor is greater than the strength remaining inside the integrated circuit. This causes most of the positive electrostatic pulse to flow out through the electrostatic protection short circuit, enabling the electrostatic protection circuit to reduce the intensity of the electrostatic pulse inside the integrated circuit. Consequently, the electrostatic protection method can protect the integrated circuit from electrostatic damage, thus helping to ensure the reliability of the integrated circuit.

[0059] If the electrostatic pulse is negative, similarly, a portion of the negative electrostatic pulse remains inside the integrated circuit, while another portion flows into the electrostatic discharge (ESD) protection circuit through the first output port. Based on the forward conduction characteristic of the diode, after flowing into the ESD protection circuit through the first input port, the portion of the negative ESD pulse will flow through the fourth diode and exit from the ground port. Since the resistance of the integrated circuit is greater than the diode resistance, the resistance of the integrated circuit is greater than the resistance of the fourth diode. Therefore, the intensity of the negative ESD pulse flowing into the ESD protection circuit is greater than the intensity of the ESD pulse remaining inside the integrated circuit. This allows the ESD protection circuit to reduce the intensity of the ESD pulse inside the integrated circuit, thereby enabling the ESD protection method to protect the integrated circuit from ESD damage to a certain extent and helping to ensure the reliability of the integrated circuit.

[0060] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2As shown, the integrated circuit also includes a power port 03, and the electrostatic discharge protection circuit also includes a power output port and a fifth diode 41. The power output port 40 includes a first power output port 411 and a second power output port 412. The first power output port 411 is connected to the drain of the N-type field-effect transistor 13, and the second power output port 412 is connected to the cathode of the first diode 11. Since the cathode of the first diode 11 is connected to the drain of the N-type field-effect transistor 13 through the first terminal of the capacitor 14, the second power output port 412 is sequentially connected to the drain of the N-type field-effect transistor 13 through the cathode of the first diode 11 and the first terminal of the capacitor 14. Furthermore, the second power output port 412 is also sequentially connected to the first power output port through the first terminal of the capacitor 14 and the drain of the N-type field-effect transistor 13. The cathode of the fifth diode 41 is connected to the first power output port 411, and its anode is connected to the ground output port 20. Since the second power output port is connected to the first power output port through the first terminal of the capacitor and the drain of the N-type field-effect transistor, and the negative terminal of the fifth diode is connected to the first power output port, the second power output port is sequentially connected to the first terminal of the capacitor, the drain of the N-type field-effect transistor, and the negative terminal of the fifth diode through the first power output port. It should be noted that the first power output port is connected to the integrated circuit power port via a wire bonding method, the first power output port is connected to the drain of the N-type field-effect transistor via a metal wire, and the first power output port is connected to the negative terminal of the fifth diode via a metal wire. Therefore, even if the first power output port is connected to the integrated circuit power port, and the first power output port is also connected to the drain of the N-type field-effect transistor and the negative terminal of the fifth diode, the integrated circuit input port will not be directly connected to the drain of the N-type field-effect transistor, nor will it be directly connected to the negative terminal of the fifth diode.

[0061] This electrostatic protection also includes:

[0062] S5: Connect the first power output port to the power port of the integrated circuit, so that the electrostatic discharge protection circuit can be connected to the integrated circuit, so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

[0063] It should be noted that, in the embodiments of this application, the power output port includes two power output ports: a first power output port and a second power output port. The integrated circuit includes one power port, but this application does not limit this. In other embodiments of this application, the electrostatic discharge protection circuit may also include one or more power output ports, and the integrated circuit may include at least two power ports, depending on the specific circumstances.

[0064] Specifically, in this embodiment, the first power output port of the electrostatic discharge (ESD) protection circuit is connected to the power port of the integrated circuit, thereby connecting the ESD protection circuit to the integrated circuit. This allows the ESD protection circuit to provide ESD protection to the integrated circuit, suppressing electrostatic pulses from flowing into the integrated circuit through its power port. Consequently, the ESD protection method helps to suppress ESD damage to the integrated circuit and contributes to the development of the integrated circuit.

[0065] Based on the above embodiments, in this embodiment, when a positive electrostatic pulse flows in from the second power output port, the cathode of the first diode is connected to the second power output port, the cathode of the fifth diode is connected to the first power output port, and the cathode of the third diode is connected to the drain of the N-type field-effect transistor. According to the forward conduction characteristics of the diodes, after the positive electrostatic pulse flows in from the second output port, it will not flow through the first diode, the third diode, and the fifth diode. Since the second power output port is connected to the drain of the N-type field-effect transistor through the first terminal of the capacitor, the positive electrostatic pulse will flow through the N-type field-effect transistor and out from the ground output port. Furthermore, since the second power output port is connected to the first power output port in sequence through the first terminal of the capacitor and the drain of the N-type field-effect transistor, the positive electrostatic pulse will also flow through the first power output port and into the integrated circuit through the power port of the integrated circuit. It is known that the resistance of the integrated circuit is greater than that of the N-type field-effect transistor (FET). Therefore, when the positive electrostatic pulse flows in from the second output port, the pulse intensity flowing through the N-type FET is greater than the pulse intensity flowing into the integrated circuit. This causes most of the positive electrostatic pulse to flow out through the N-type FET, enabling the electrostatic protection circuit to reduce the pulse intensity flowing into the integrated circuit. Consequently, the electrostatic protection method can protect the integrated circuit from electrostatic damage to a certain extent, helping to ensure the reliability of the integrated circuit. Specifically, the process of the positive electrostatic pulse flowing through the N-type FET is as follows: after flowing in from the second power output port, the positive electrostatic pulse couples with the capacitor, releasing charge to the gate of the N-type FET, raising the gate potential of the N-type FET, causing the N-type FET to conduct, allowing the positive electrostatic pulse to flow through the N-type FET and out from the ground output port.

[0066] When a negative electrostatic pulse flows in from the second power output port, it is known that the second power output port is connected to the first power output port through the first terminal of the capacitor and the drain of the second N-type field-effect transistor. After the negative electrostatic pulse flows in from the second power output port, it will flow through the first power output port connected to the power port of the integrated circuit and the drain of the N-type field-effect transistor. Since the first power output port is connected to the power port of the integrated circuit, the electrostatic pulse will flow into the integrated circuit after flowing through the first power output port. It is known that connecting the drain of a field-effect transistor (FET) to a negative terminal will cause the PN junction of the N-type FET to conduct, making the N-type FET function like a diode. Since the drain of the N-type FET is connected to the first terminal of the capacitor, and the source is connected to the ground terminal, when the negative electrostatic pulse flows through the drain of the N-type FET, the N-type FET functions like a diode with its negative terminal connected to the first terminal of the capacitor and its positive terminal connected to the ground terminal. Therefore, the negative electrostatic pulse, after flowing in from the second power supply terminal, will also flow through the N-type FET and out from the ground terminal. Furthermore, since the negative terminal of the fifth diode is connected to the first power supply terminal and its positive terminal is connected to the ground terminal, the positive electrostatic pulse will also flow through the fifth diode and out from the ground terminal. It is known that when a negative electrostatic pulse flows in, the N-type field-effect transistor (FET) acts as a diode. Therefore, when the negative electrostatic pulse flows in, the N-type FET and the fifth diode have the same conduction capability. Considering the minute resistance of the wires in the circuit, the intensity of the negative electrostatic pulse flowing through the N-type FET and the fifth diode is related to the length of the wire between the N-type FET and the fifth diode and the second power output port. A shorter wire results in a stronger path, and a longer wire results in a weaker path. Since the integrated circuit has a larger resistance than the diode, the intensity of the negative electrostatic pulse flowing through the fifth diode and the N-type FET is greater than the intensity flowing into the integrated circuit. This allows most of the negative electrostatic pulse to flow out from the ground port through the fifth diode and the N-type FET, enabling the electrostatic protection circuit to reduce the intensity of the electrostatic pulse flowing into the integrated circuit. Consequently, the electrostatic protection method helps to suppress electrostatic damage to the integrated circuit.

[0067] In addition, based on the forward conduction characteristics of the diode, after the negative electrostatic pulse flows in, it will also flow through the path formed by the second diode and the first diode, as well as the path formed by the third diode and the fourth diode. Since the N-type field-effect transistor is equivalent to a diode at this time, and the resistance on the wire is very small, it cannot affect the resistance between the different paths formed by the circuit elements. Therefore, the resistance of the path formed by the second diode and the first diode, as well as the path formed by the third diode and the fourth diode, is greater than the resistance of the second N-type field-effect transistor. Furthermore, since the path formed by the second diode and the first diode includes two diodes, and the path formed by the third diode and the fourth diode also includes two diodes, the resistance of the path formed by the second diode and the first diode, as well as the resistance of the path formed by the third diode and the fourth diode, is greater than the resistance of the fifth diode. Consequently, the intensity of the positive electrostatic pulse flowing through the second N-type field-effect transistor and the fifth diode is greater than the intensity of the pulse flowing through the path formed by the second diode and the first diode, as well as the intensity of the pulse flowing through the path formed by the third diode and the fourth diode. The electrostatic pulse intensity flowing through the path formed by the second diode and the first diode, as well as the path formed by the third diode and the fourth diode, is related to the resistance of each path. The electrostatic pulse intensity is low when the resistance is high and high when the resistance is low. This will not be elaborated further here.

[0068] Furthermore, when an electrostatic pulse exists inside the integrated circuit and acts on the power port of the integrated circuit, if the electrostatic pulse is a positive electrostatic pulse, a portion of the electrostatic pulse will remain inside the integrated circuit. Since the first power output port is connected to the power port of the integrated circuit, a portion of the electrostatic pulse will flow through the first power output port and into the electrostatic protection circuit. According to the forward conduction characteristic of the diode, after the portion of the electrostatic pulse flows into the electrostatic protection circuit, it will flow through the drain of the N-type field-effect transistor and couple with the capacitor, releasing charge to the N-type field-effect transistor and raising the gate potential of the N-type field-effect transistor, causing the N-type field-effect transistor to conduct. Thus, after the positive electrostatic pulse flows through the first power output port, it will flow through the N-type field-effect transistor and be discharged from the ground output port. Since the resistance of the integrated circuit is greater than that of the N-type field-effect transistor, the intensity of the positive electrostatic pulse flowing through the N-type field-effect transistor is greater than the intensity remaining inside the integrated circuit. As a result, the electrostatic pulse circuit can reduce the intensity of the electrostatic pulse inside the integrated circuit, thereby enabling the electrostatic protection method to protect the integrated circuit from electrostatic damage to a certain extent.

[0069] If the electrostatic pulse is negative, a portion of it will remain inside the integrated circuit, while another portion will flow through the first power output port connected to the integrated circuit's power supply port and through the drain of the N-type field-effect transistor (FET). As previously mentioned, the N-type FET is essentially a diode with its negative terminal connected to the first power output port and its positive terminal connected to the ground output port. Due to the forward conduction characteristic of a diode, the negative electrostatic pulse will flow through the N-type FET and exit from the ground output port. Since the negative terminal of the fifth diode is connected to the first power output port and its positive terminal is connected to the ground output port, the negative electrostatic pulse will also flow through the fifth diode. In this case, the fifth diode and the N-type FET have the same conduction capability. Considering the minute resistance in the circuit's wires, the intensity of the negative electrostatic pulse flowing through the N-type FET and the fifth diode depends on the length of the wire between the N-type FET and the fifth diode and the second power output port. Shorter wires result in a stronger path, while longer wires result in a weaker path. Because the integrated circuit has a larger resistance than the diode, the intensity of the negative electrostatic pulse flowing through the N-type field-effect transistor and the fifth resistor is greater than the intensity remaining inside the integrated circuit. This allows the electrostatic protection circuit to reduce the intensity of the electrostatic pulse inside the integrated circuit, thereby enabling the electrostatic protection method to protect the integrated circuit from electrostatic damage.

[0070] In addition, based on the forward conduction characteristics of the diode, after the negative electrostatic pulse flows into the electrostatic protection circuit, it will also flow through the path formed by the second diode and the first diode, as well as the path formed by the third diode and the fourth diode. Since the N-type field-effect transistor is equivalent to a diode at this time, and the resistance on the wire is very small, it cannot affect the resistance between the different paths formed by the circuit elements. Therefore, the resistance of the path formed by the second diode and the first diode, as well as the path formed by the third diode and the fourth diode, is greater than the resistance of the second N-type field-effect transistor. Furthermore, since the path formed by the second diode and the first diode includes two diodes, and the path formed by the third diode and the fourth diode also includes two diodes, the resistance of the path formed by the second diode and the first diode, as well as the path formed by the third diode and the fourth diode, is greater than the resistance of the fifth diode. Consequently, the intensity of the positive electrostatic pulse flowing through the second N-type field-effect transistor and the fifth diode is greater than the intensity of the pulse flowing through the path formed by the second diode and the first diode, as well as the intensity of the pulse flowing through the path formed by the third diode and the fourth diode. The electrostatic pulse intensity flowing through the path formed by the second diode and the first diode, as well as the path formed by the third diode and the fourth diode, is related to the resistance of each path. The electrostatic pulse intensity is low when the resistance is high and high when the resistance is low. This will not be elaborated further here.

[0071] It should be noted that when an electrostatic pulse (ESP) exists inside the integrated circuit, after flowing through the first input port, first output port, or first power output port, it may flow through other ports of the ESP protection circuit. However, due to the low resistance and strong shunt capability of the ESP protection circuit, the intensity of the ESP flowing through these other ports will also be low. Therefore, even if the ESP flows through other ports of the ESP protection circuit, it will not affect the operation of those other ports. Similarly, when an ESP flows into the second input port, second output port, or second power output port of the ESP protection circuit, it may also flow through other ports. Likewise, due to the low resistance and strong shunt capability of the ESP protection circuit, the intensity of the ESP flowing through these other ports will also be low. Therefore, even if the ESP flows through other ports of the ESP protection circuit, it will not affect the operation of those other ports.

[0072] It should also be noted that, in this embodiment, to avoid affecting the normal operation of the integrated circuit, the turn-on voltage of the field-effect transistor in the electrostatic discharge (ESD) protection circuit is approximately 20% higher than the turn-on voltage of the integrated circuit. This ensures that when the integrated circuit is turned on, the field-effect transistor in the ESD protection circuit is in a closed state. This prevents the power signal from flowing through the ESD protection circuit's field-effect transistor and then exiting from the ground terminal after passing through the second power output port, thus preventing the integrated circuit from malfunctioning. Furthermore, according to... Figure 1 As can be seen, each diode in the electrostatic discharge protection circuit is in reverse connection with the second power output port. This ensures that after the power signal of the integrated circuit flows through the second power output port, the power signal will not flow through the diodes and out of the ground terminal, thus guaranteeing the normal operation of the integrated circuit.

[0073] Optionally, in one embodiment of this application, the first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode. However, this application does not limit this, and it depends on the specific circumstances. In other embodiments of this application, the first diode, the second diode, the third diode, the fourth diode, and the fifth diode can also be commonly used ordinary diodes, depending on the specific circumstances.

[0074] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the electrostatic discharge (ESD) protection circuit further includes: a resistor 50Ω; the ESD protection method further includes:

[0075] S6: Connect the first end of the resistor 50 to the gate of the N-type field-effect transistor 13, and connect the second end to the ground terminal 20. Since the gate of the N-type field-effect transistor 13 is connected to the second end of the capacitor 14, the first end of the resistor 50 is also connected to the second end of the capacitor 14 through the gate of the N-type field-effect transistor 13.

[0076] In this embodiment, after the electrostatic pulse couples with the capacitor, the capacitor discharges to the gate of the N-type field-effect transistor (FET), accumulating charge at the FET gate and turning on the FET. However, if too much charge accumulates at the FET gate, it can damage the FET. The increase in resistance can share some of the energy released by the capacitor, helping to prevent excessive charge accumulation at the FET gate and damage to the FET. This helps ensure the reliability of the electrostatic protection circuit, enabling it to reliably reduce the possibility of electrostatic damage to the integrated circuit and guarantee its reliability.

[0077] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the integrated circuit includes a ground port, and the ground output port 20 includes a first ground output port 21 and a second ground output port 22; the electrostatic discharge protection method includes:

[0078] S7: Connect the first ground output port 21 to the ground port 04 of the integrated circuit, connect the second ground output port 22 to the first ground output port 21, and ground the second ground output port 22 so that the ground port 04 of the integrated circuit can be grounded, thereby enabling the electrostatic discharge circuit to discharge electrostatic pulses from the second ground output port 22. The first ground output port and the ground port of the integrated circuit are connected by a wire bonding, and the first ground output port and the second ground output port are connected by a metal wiring. It should be noted that in this embodiment, the ground output port includes two ground output ports: a first ground output port and a second ground output port. The integrated circuit includes one ground port. However, this application is not limited to this. In other embodiments of this application, the electrostatic discharge circuit may also include one or more ground output ports, and the integrated circuit may include at least two ground ports, depending on the specific situation.

[0079] It should also be noted that, continuing as Figure 2 As shown, the second power output port 412 of the electrostatic discharge protection circuit is connected to the external power supply 61, the second input output port 112 is connected to the external input port 62, the second output output port 312 is connected to the external output port 63, and the second ground output port 22 is grounded to the ground 64, so that the integrated circuit can be connected to the outside under the premise of the electrostatic discharge protection circuit, and the normal operation of the integrated circuit can be guaranteed.

[0080] To gain a clearer understanding of the electrostatic discharge (ESD) protection capability of the circuit, a TLP (ThinPrep) device was used to test its protection capability. The ESD protection capability of the circuit will be described below based on the test results from the TLP device.

[0081] Specifically, when a positive electrostatic pulse (ESP) is applied to the second input output port, in order to test the ESP protection capability of the ESP circuit, a TLP device is used to monitor the positive ESP flowing into the second input output port and the leakage current between the second input output port and the ground output port. The results are as follows: Figure 3 As shown, curve 1 is the IV curve of the electrostatic pulse at the second input output port, and curve 2 is the leakage current curve between the second input output port and the ground port. Figure 3It can be seen that when the positive electrostatic pulse intensity increases to 6V or slightly higher, the leakage current is small. As the positive electrostatic pulse intensity continues to increase, the leakage current rises rapidly, at which point electrostatic damage occurs to the integrated circuit. This indicates that the electrostatic protection circuit can withstand a positive electrostatic pulse of 6V or slightly higher flowing into the second input output port. When a negative electrostatic pulse acts on the second input output port, the TLP is also used to monitor the negative electrostatic pulse at the second input port and the leakage current between the second input port and the ground port. The results are as follows: Figure 4 As shown, curve 1 is the electrostatic pulse IV curve of the second input output port, and curve 2 is the leakage current curve between the second input output port and the ground port. Figure 3 It can be seen that when the intensity of the negative electrostatic pulse increases to 8V or slightly higher, the leakage current is small. As the electrostatic pulse continues to increase, the leakage current increases rapidly. At this time, electrostatic damage occurs to the integrated circuit, indicating that the electrostatic protection circuit can withstand a negative electrostatic pulse with an intensity of 8V or slightly higher flowing in from the second input output port.

[0082] When a positive electrostatic pulse (ESP) is applied to the second output port, in order to test the ESD protection capability of the ESD protection circuit, a TLP device is used to monitor the positive ESD pulse flowing into the second output port and the leakage current between the second output port and the ground port. The results are as follows: Figure 5 As shown, curve 1 is the positive electrostatic pulse (ESP) IV curve of the second output port, and curve 2 is the leakage current curve between the second output port and the ground port. According to... Figure 5 It can be seen that when the positive electrostatic pulse intensity increases to 6V or slightly higher, the leakage current is small, and the integrated circuit does not suffer electrostatic damage. However, as the positive electrostatic pulse continues to increase, the leakage current increases rapidly, and electrostatic damage occurs in the integrated circuit. This indicates that the electrostatic protection circuit can withstand a positive electrostatic pulse of 6V or slightly higher flowing into the second output port. When a negative electrostatic pulse acts on the second output port, the TLP is also used to monitor the electrostatic pulse at the second output port and the leakage current between the second output port and the ground port. The results are then obtained as follows... Figure 4 As shown, the electrostatic discharge protection circuit can withstand negative electrostatic pulses with an intensity of 8V or slightly higher than 8V flowing in from the second output port.

[0083] When a positive electrostatic pulse is applied to the second power output port, a TLP device is used to monitor the positive electrostatic pulse flowing into the second power output port and the leakage current between the second power output port and the ground output port. The results are as follows: Figure 6As shown, curve 1 is the positive electrostatic pulse (ESP) IV curve of the second power output port, and curve 2 is the leakage current curve between the second power output port and the ground port. According to... Figure 6 It can be seen that when the positive electrostatic pulse intensity increases to 14V or slightly higher, the leakage current is small, and the integrated circuit is not damaged at this time. As the positive electrostatic pulse continues to increase, the leakage current increases rapidly, and electrostatic damage occurs in the integrated circuit. This indicates that the electrostatic protection circuit can withstand a positive electrostatic pulse of 14V or slightly higher flowing into the second power output port. When a negative electrostatic pulse acts on the second input output port, the TLP is also used to monitor the negative electrostatic pulse at the second power output port and the leakage current between the second power output port and the ground port. The results are then obtained as follows... Figure 4 As shown, the electrostatic discharge protection circuit can withstand negative electrostatic pulses with an intensity of 8V or slightly higher than 8V flowing in from the second power output port.

[0084] In summary, the electrostatic discharge (ESD) protection method for integrated circuits provided in this application embodiment protects the integrated circuit from ESD through an ESD protection circuit. The method includes: providing a first chip and distributing the integrated circuit on the first chip, the integrated circuit including an input port; providing a second chip and distributing the ESD protection circuit on the second chip, the ESD protection circuit including an input output port, a first diode, a second diode, a capacitor, an N-type field-effect transistor, and a ground output port; wherein the input output port includes a first input output port and a second input output port, the first input output port is connected to the input port of the integrated circuit, enabling the ESD protection circuit to connect to the integrated circuit, thereby allowing the ESD protection circuit to protect the integrated circuit from ESD, helping to suppress ESD damage to the integrated circuit and ensuring the reliability of the integrated circuit. Furthermore, the electrostatic discharge (ESD) protection method provided in this application includes placing the ESD protection circuit on a second chip and placing the integrated circuit on a first chip. This allows the integrated circuit and the ESD protection circuit to be placed on different chips, eliminating the need for ESD protection design on the first chip. In other words, it eliminates the need for ESD protection design on the chip containing the integrated circuit, thereby avoiding the problem of being unable to perform ESD protection design due to limitations in the substrate material of the chip containing the integrated circuit. This enables ESD protection for ESD-sensitive novel material integrated circuits and contributes to the development of novel material integrated circuits.

[0085] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0086] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for electrostatic discharge protection of integrated circuits, characterized in that, Electrostatic discharge (ESD) protection for integrated circuits is achieved through an ESD protection circuit. This method includes: A first chip is provided, and the integrated circuit is disposed on the first chip, the integrated circuit including an input port; A second chip is provided, on which the electrostatic discharge (ESD) protection circuit is disposed. The ESD protection circuit includes an input / output port, a first diode, a second diode, an N-type field-effect transistor (FET), a capacitor, and a ground terminal. The input / output port includes a first input / output port and a second input / output port. The second input / output port is connected to the first input / output port through the anode of the first diode. The cathode of the first diode is connected to the drain of the N-type FET through the first terminal of the capacitor. The gate of the N-type FET is connected to the second terminal of the capacitor, and its source is connected to the ground terminal. The ground terminal is grounded. The cathode of the second diode is connected to the anode of the first diode, and its anode is connected to the ground terminal. Connect the first input output port to the input port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit. The first chip is a carbon-based chip, and the second chip is a silicon-based chip.

2. The electrostatic protection method according to claim 1, characterized in that, The integrated circuit further includes an output port, and the electrostatic discharge protection circuit further includes: an output terminal, a third diode, and a fourth diode, wherein the output terminal includes a first output terminal and a second output terminal, the second output terminal is connected to the first output terminal through the positive terminal of the third diode, the negative terminal of the third diode is connected to the drain of the N-type field-effect transistor, the negative terminal of the fourth diode is connected to the positive terminal of the third diode, and the positive terminal is connected to the ground terminal; the method further includes: Connect the first output port to the output port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

3. The electrostatic protection method according to claim 2, characterized in that, The integrated circuit further includes a power supply port, and the electrostatic discharge protection circuit further includes: a power output port and a fifth diode, wherein the power output port includes a first power output port and a second power output port, the first power output port is connected to the drain of the N-type field-effect transistor, the second power output port is connected to the cathode of the first diode, the cathode of the fifth diode is connected to the first power output port, and the anode is connected to the ground output port; the method further includes: The first power output port is connected to the power port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

4. The electrostatic protection method according to claim 3, characterized in that, The first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode.

5. The electrostatic protection method according to claim 1, characterized in that, The electrostatic discharge protection circuit further includes a resistor; the method further includes: The first end of the resistor is connected to the gate of the N-type field-effect transistor, and the second end is connected to the ground terminal.

6. The electrostatic protection method according to claim 1, characterized in that, The integrated circuit further includes a ground port, wherein the ground output port includes a first ground output port and a second ground output port; the method further includes: Connect the first ground output port to the ground port of the integrated circuit, connect the second ground output port to the first ground output port, and ground the second ground output port.

Images