A frequency configurable bandpass filter circuit

Abstract

The present invention is a frequency-configurable bandpass filter circuit, comprising a crystal oscillator module, counter chips U4 and U5 for filtering high-frequency signals, counter chips U1, U2 and U3 for filtering low-frequency signals, counter chip U6, NOT gate logic modules U9A and U10A, and AND gate logic modules U7A and U8A, which can filter out high-frequency signals above the high-frequency cutoff frequency set by the counter, and can filter out low-frequency signals whose input frequency is lower than the set low-frequency cutoff frequency through another counter module, and finally obtain frequency signals within the corresponding range. Compared with the existing circuits, the circuit of the present invention has strong configurability and high practicality, and can filter frequency signals within a specific frequency range.

Description

Technical Field

[0001] The present invention relates to hardware signal filtering, belonging to the field of hardware signal processing, and specifically to a frequency-configurable bandpass frequency filtering circuit. Background Art

[0002] Wave filtering is the operation of filtering out specific frequency bands in a signal. It is an important measure to suppress and prevent interference.

[0003] Signal processing is a general term for the processing of various types of electrical signals according to various expected purposes and requirements. The processing of analog signals is called analog signal processing, and the processing of digital signals is called digital signal processing. The so-called "signal processing" is the process of processing signals recorded on a certain medium in order to extract useful information. It is a general term for the processing of signal extraction, transformation, analysis, and synthesis.

[0004] With the development of hardware circuit design, although the simple first-order and second-order filtering methods can effectively reduce the response outside the signal bandwidth, there is also attenuation for the frequency response within the bandwidth, and the signal filter needs to be calculated using formulas, which is relatively complicated. Therefore, there is an urgent need for a digital circuit with simple calculation, feasible circuit principle, and configurable bandpass filtering frequency to realize the circuit's configurable frequency bandpass filtering. Summary of the invention

[0005] The purpose of the present invention is to provide a frequency-configurable bandpass filter circuit to address the above technical problems. The counter and crystal oscillator module set in the circuit are used in conjunction with a logic gate circuit to filter the frequency signal, filter out high-frequency signals above the specified frequency and low-frequency signals below the specified frequency, thereby achieving filtering of the input signal and outputting a frequency signal in a specified frequency range.

[0006] Technical solution of the present invention:

[0007] A frequency-configurable bandpass filter circuit includes a crystal oscillator module, counter chips U4 and U5 for filtering high-frequency signals, counter chips U1, U2 and U3 for filtering low-frequency signals, a counter chip U6, NOT gate logic modules U9A and U10A, and AND gate logic modules U7A and U8A;

[0008] The crystal oscillator module Y1 outputs a clock signal, which is used to provide a stable clock signal source for the bandpass filter circuit, and the clock frequency is F; the crystal oscillator module Y2 outputs a clock signal, which is used to provide a stable clock signal source for the bandpass filter circuit, and the clock frequency is f; the counter chip is a decimal counter, which is used to count according to the input clock signal when the counting condition is met, and outputs the corresponding counting signal through the counting output pin Qn, where n is a natural number, and the carry output pin TC for processing by the subsequent circuit; the NOT gate logic module is used for non-logical processing during signal transmission; the AND gate logic module is used for AND logic processing during signal transmission;

[0009] It is characterized in that the crystal oscillator module includes a crystal oscillator Y1, a capacitor C1 and a resistor R1, a crystal oscillator Y2, a capacitor C2, and a resistor R2. The VCC power supply end of the crystal oscillator Y1 is connected to a power supply and is grounded through the capacitor C1 for filtering. After the clock signal output end CLK of the crystal oscillator Y1 is connected to the matching resistor R1, the clock signal CLK-1 is output to the subsequent circuit; the VCC power supply end of the crystal oscillator Y2 is connected to the power supply and is grounded through the capacitor C2 for filtering. After the clock signal output end CLK of the crystal oscillator Y2 is connected to the matching resistor R2, the clock signal CLK-2 is output to the subsequent circuit;

[0010] The clock signal CLK-1 output by the crystal oscillator Y1 enters the CLK terminal of the counter chips U1, U2, and U3. The enable terminal CET and the enable terminal CEP of the counter chip U1 are connected to the power supply, so that the counter chip U1 performs cumulative counting every time it receives the clock signal CLK-1. The carry output pin TC of the counter chip U1 is connected to the enable terminal CET and the enable terminal CEP of the counter chip U2. When the cumulative count of the counter chip U1 reaches the rated count value, a high level is output to the counter chip U2 to enable the counter chip U2. The counter chip U2 Receive the clock signal CLK-1, and perform cumulative counting each time the clock signal CLK-1 is received. The carry output pin TC of the counter chip U2 is connected to the enable terminal CET and the enable terminal CEP of the counter chip U3. When the cumulative count of the counter chip U2 reaches the rated count value, a high level is output to the counter chip U3 to enable the counter chip U3. The counter chip U3 receives the clock signal CLK-1. The carry output pin TC of the counter chip U3 is connected to an input terminal of the AND gate logic module U7A through the NOT gate logic module U10A.

[0011] The input signal INPUT_SIGNAL to be filtered is input to the CLK terminal, the reset terminal MR of the counter chip U4 and the reset terminal MR of the counter chip U5, the enable terminal CET and the enable terminal CEP of the counter chip U4 are both connected to the power supply, the first counting output pin Q0 of the counter chip U4 is connected to an input terminal of the AND gate logic module U8A, the output terminal of the AND gate logic module U8A is connected to the enable terminal CEP of the counter chip U5, the enable terminal CET of the counter chip U5 is connected to the power supply, the CLK terminal input of the counter chip U5 is the clock signal CLK-2 output by the crystal oscillator Y2, the first counting output pin Q0 of the counter chip U5 is simultaneously connected to the input terminal of the NOT gate logic module U9A, the CLK terminal of the counter chip U6 and the other input terminal of the AND gate logic module U7A, the first counting output pin Q0 of the counter chip U5 outputs the signal SIGNAL, and the output terminal of the NOT gate logic module U9A is connected to the other input terminal of the AND gate logic module U8A;

[0012] The reset terminal MR of the counter chip U6 is connected to the output terminal of the AND gate logic module U7A, the enable terminal CET and the enable terminal CEP of the counter chip U6 are both connected to the power supply, and the first counting output terminal Q0 of the counter chip U6 outputs the final filtered OUTPUT_SIGNAL signal.

[0013] It is characterized in that when the high-frequency signal in the input signal INPUT_SIGNAL is input to the counter chip U4, the counter chip U4 starts counting. When the counter chip U4 counts to 1, the Q0 output pin of the counter chip U4 outputs a high-level signal, and the output counting signal of the counter chip U5 after the non-logic enters the AND gate logic module U8A for AND logic to control the enablement of the counter chip U5. After the counter chip U5 is enabled, the counter chip U5 can only output a high-level signal when the clock signal CLK-2 output by the crystal oscillator Y2 changes from a low level to a high level. When the input signal INPUT_SIGNAL signal is a low level, the counters U4 and U5 are reset, and U5 outputs a low level. Therefore, when the frequency of the high-frequency signal in the input signal INPUT_SIGNAL is higher than the frequency f of the clock signal output by the crystal oscillator Y2, the counter chip U5 cannot count normally, the high-frequency signal is filtered out, and the output signal SIGNAL is a signal that has been filtered through high-frequency filtering.

[0014] It is characterized in that when the clock signal CLK-1 output by the crystal oscillator Y1 is input to the counter chip U1, the counter chip U1 starts to count, when the count reaches 10, the carry output pin TC of the counter chip U1 starts to output a high level, enabling the counter chip U2, and the counter chip U2 starts to count, when the count reaches 10, the carry output pin TC of the counter chip U2 starts to output a high level, enabling the counter chip U3, and the counter chip U3 starts to count, when the count reaches 10, the carry output pin TC of the counter chip U3 outputs a high level, after passing through the NOT gate logic module, the counter chip U6 is reset, and after the delay of the crystal oscillator Y1 and the counter chips U1, U2, and U3, the final low-frequency cutoff frequency of the band-pass voltage filter circuit is F / 1000, realizing the low-frequency filtering function.

[0015] It is characterized in that the signal SIGNAL after high-frequency filtering is input into the CLK terminal of the counter chip U6 and the other input terminal of the AND gate logic module U7A. When the SIGNAL frequency is higher than F / 1000 and the carry output pin TC of the counter chip U3 outputs a low level, U6 starts to count the SIGNAL signal. When SIGNAL is at a high level, the counting output terminal Q0 of the counter chip U6 outputs a high level. When SIGNAL is at a low level, U7A outputs a low level, resets the counter U6, and the counting output terminal Q0 of the counter chip U6 outputs a low level, thereby filtering out the signal with a frequency lower than F / 1000, and finally outputs OUTPUT_SIGNAL filtered by the bandpass filter circuit.

[0016] The characteristic is that the signal OUTPUT_SIGNAL finally output by the bandpass filter circuit has a filtering frequency range of F / 1000 to f.

[0017] The invention is characterized in that, by setting the counter chip and the crystal oscillator specifications, the frequency signal is filtered, and the high-frequency signal above the specified frequency is filtered out to form a frequency signal after high-frequency filtering.

[0018] It is characterized in that the number of counter chips, the number of counting pins and the frequency of the crystal oscillator Y2 used to filter out high-frequency signals are determined according to the high-frequency cut-off frequency required by the band-pass voltage filter circuit.

[0019] It is characterized in that the number of counter chips, the number of counting pins, the base of the counter, and the frequency of the crystal oscillator Y1 used to filter out low-frequency signals are determined according to the low-frequency cutoff frequency required by the band-pass voltage filter circuit.

[0020] Beneficial effects of the invention:

[0021] The present invention discloses a frequency-configurable bandpass filter circuit, which filters out high-frequency signals above the high-frequency cutoff frequency set by the counters by arranging multiple counters and AND and NOT gate logic circuits, and can filter out low-frequency signals whose input frequency is lower than the set low-frequency cutoff frequency by another counter module, and output the final filtered frequency signal. Compared with the existing circuits, the circuit of the present invention has strong configurability and high practicality, and can filter frequency signals within a specific frequency range. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a frequency configurable bandpass filter circuit diagram DETAILED DESCRIPTION

[0023] The connection structure of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0024] like Figure 1 As shown, the frequency-configurable bandpass filter circuit includes a crystal oscillator module, counter chips U4 and U5 for filtering high-frequency signals, counter chips U1, U2, and U3 for filtering low-frequency signals, counter chip U6, NOT gate logic modules U9A and U10A, and AND gate logic modules U7A and U8A. The crystal oscillator module Y1 outputs a clock signal, which is used to provide a stable clock signal source for the bandpass filter circuit, and the clock frequency is F; the crystal oscillator module Y2 outputs a clock signal, which is used to provide a stable clock signal source for the bandpass filter circuit, and the clock frequency is f; the counter chip is a decimal counter, which is used to count according to the input clock signal when the counting condition is met, and outputs the corresponding counting signal through the counting output pin Qn, where n is a natural number, and the carry output pin TC for processing by the subsequent circuit; the NOT gate logic module is used for non-logical processing during signal transmission; the AND gate logic module is used for AND logic processing during signal transmission;

[0025] The crystal oscillator module includes a crystal oscillator Y1, a capacitor C1 and a resistor R1, a crystal oscillator Y2, a capacitor C2, and a resistor R2. The VCC power supply end of the crystal oscillator Y1 is connected to a power supply and is grounded through the capacitor C1 for filtering. After the clock signal output end CLK of the crystal oscillator Y1 is connected to the matching resistor R1, the clock signal CLK-1 is output to the subsequent circuit; the VCC power supply end of the crystal oscillator Y2 is connected to the power supply and is grounded through the capacitor C2 for filtering. After the clock signal output end CLK of the crystal oscillator Y2 is connected to the matching resistor R2, the clock signal CLK-2 is output to the subsequent circuit.

[0026] The clock signal CLK-1 output by the crystal oscillator Y1 enters the CLK terminal of the counter chips U1, U2, and U3. The enable terminal CET and the enable terminal CEP of the counter chip U1 are connected to the power supply, so that the counter chip U1 performs cumulative counting every time it receives the clock signal CLK-1. The carry output pin TC of the counter chip U1 is connected to the enable terminal CET and the enable terminal CEP of the counter chip U2. When the cumulative count of the counter chip U1 reaches the rated count value, a high level is output to the counter chip U2 to enable the counter chip U2. The counter chip U2 It receives the clock signal CLK-1 and performs cumulative counting each time it receives the clock signal CLK-1. The carry output pin TC of the counter chip U2 is connected to the enable terminal CET and the enable terminal CEP of the counter chip U3. When the cumulative count of the counter chip U2 reaches the rated count value, a high level is output to the counter chip U3 to enable the counter chip U3. The counter chip U3 receives the clock signal CLK-1. The carry output pin TC of the counter chip U3 is connected to an input terminal of the AND gate logic module U7A through the NOT gate logic module U10A.

[0027] The input signal INPUT_SIGNAL to be filtered is input to the CLK terminal, reset terminal MR of the counter chip U4 and the reset terminal MR of the counter chip U5. The enable terminal CET and enable terminal CEP of the counter chip U4 are both connected to the power supply. The first counting output pin Q0 of the counter chip U4 is connected to an input terminal of the AND gate logic module U8A. The output terminal of the AND gate logic module U8A is connected to the enable terminal CEP of the counter chip U5. The enable terminal CET of the counter chip U5 is connected to the power supply. The CLK terminal input of the counter chip U5 is the clock signal CLK-2 output by the crystal oscillator Y2. The first counting output pin Q0 of the counter chip U5 is simultaneously connected to the input terminal of the NOT gate logic module U9A, the CLK terminal of the counter chip U6 and the other input terminal of the AND gate logic module U7A. The first counting output pin Q0 of the counter chip U5 outputs the signal SIGNAL. The output terminal of the NOT gate logic module U9A is connected to the other input terminal of the AND gate logic module U8A.

[0028] The reset terminal MR of the counter chip U6 is connected to the output terminal of the AND gate logic module U7A, the enable terminal CET and the enable terminal CEP of the counter chip U6 are both connected to the power supply, and the first counting output terminal Q0 of the counter chip U6 outputs the final filtered OUTPUT_SIGNAL signal.

[0029] The working principle of the bandpass filter circuit of the present invention is:

[0030] When the input frequency signal (INPUT_SIGNAL) is input to counter U4, U4 starts to work, the timing output pin Q0 outputs a high level, U7A outputs a high level, and counter U5 is enabled. Therefore, U5 starts to count the CLK-2 signal output by crystal oscillator Y2, and the Q0 pin of U5 outputs a high level. At the same time, the high-level signal output by counter U5 is input to the U8A AND gate circuit through the NOT gate U9A, prohibiting the counter U5 from being enabled, ensuring that the QO pin of U5 continues to output a high-level signal. When the INPUT_SIGNAL output becomes a low level, U4 and U5 are reset, and the Q0 pin of U5 outputs a low level.

[0031] When the input signal frequency is greater than f, the counter can output a high-level signal when the signal is input to counter U4. However, after counter U5 is enabled, CLK needs to change from low level to high level before Q0 of counter U5 can output a high-level signal. However, U5 will be frequently reset by INPUT SIGNAL, and the output SIGNAL is mostly low level, filtering out the high-frequency signal. When the input signal frequency is less than f, U5 counts the CLK-2 signal output by the crystal oscillator, and the Q0 pin of U5 outputs a high level. The high-level signal output by counter U5 is input to the U8A AND gate circuit through the NOT gate U9A, prohibiting the counter U5 from being enabled, ensuring that the QO pin of U5 continues to output a high-level signal. When the INPUT_SIGNAL output changes to a low level, U4 and U5 are reset, and the Q0 pin of U5 outputs a low level, ensuring that the signal output SIGNAL frequency is consistent with the original signal.

[0032] When the CLK-1 signal output by the active crystal oscillator Y1 is input to the counter U1, the counter starts counting. When the count reaches 10, the TC pin of the counter U1 starts to output a high level, enabling the counter U2, and U2 starts counting. Similarly, when the count of U2 reaches 10, the counter U3 starts counting. When the count reaches 10, the TC pin of the counter U3 outputs a high level, that is, the frequency of the high level output by the TC pin of U3 is F / (10×10×10)=F / 1000. When the TC pin outputs high, it passes through the NOT gate U10A and the AND gate U7A to reset U6.

[0033] When the signal SIGNAL frequency after high-frequency filtering is input into the counter U6, if the SIGNAL signal frequency is lower than F / 1000, U6 will be reset by the frequency of F / 1000. Only when the SIGNAL signal has a rising edge in each reset time period of U6, the Q0 pin of U6 will output a high-level signal. Because the reset frequency is higher than the signal frequency, the output of the Q0 pin of U6 is basically low-level. In this way, the low-frequency cutoff frequency filtering of the circuit can be realized, and the low-frequency cutoff frequency is F / 1000.

Claims

1. A frequency-configurable bandpass filter circuit, comprising a crystal oscillator module, counter chips U4 and U5 for filtering high-frequency signals, counter chips U1, U2 and U3 for filtering low-frequency signals, a counter chip U6, NOT gate logic modules U9A and U10A, and AND gate logic modules U7A and U8A; The crystal oscillator module Y1 outputs a clock signal, which is used to provide a stable clock signal source for the bandpass filter circuit, and the clock frequency is F; the crystal oscillator module Y2 outputs a clock signal, which is used to provide a stable clock signal source for the bandpass filter circuit, and the clock frequency is f; the counter chip is a decimal counter, which is used to count according to the input clock signal when the counting condition is met, and outputs the corresponding counting signal through the counting output pin Qn, where n is a natural number, and the carry output pin TC for processing by the subsequent circuit; the NOT gate logic module is used for non-logical processing during signal transmission; the AND gate logic module is used for AND logic processing during signal transmission; It is characterized in that The crystal oscillator module includes a crystal oscillator Y1, a capacitor C1 and a resistor R1, a crystal oscillator Y2, a capacitor C2, and a resistor R2. The VCC power supply end of the crystal oscillator Y1 is connected to a power supply and is grounded through the capacitor C1 for filtering. After the clock signal output end CLK of the crystal oscillator Y1 is connected to the matching resistor R1, the clock signal CLK-1 is output to the subsequent circuit; the VCC power supply end of the crystal oscillator Y2 is connected to the power supply and is grounded through the capacitor C2 for filtering. After the clock signal output end CLK of the crystal oscillator Y2 is connected to the matching resistor R2, the clock signal CLK-2 is output to the subsequent circuit; The clock signal CLK-1 output by the crystal oscillator Y1 enters the CLK terminal of the counter chips U1, U2, and U3. The enable terminal CET and the enable terminal CEP of the counter chip U1 are connected to the power supply, so that the counter chip U1 performs cumulative counting every time it receives the clock signal CLK-1. The carry output pin TC of the counter chip U1 is connected to the enable terminal CET and the enable terminal CEP of the counter chip U2. When the cumulative count of the counter chip U1 reaches the rated count value, a high level is output to the counter chip U2 to enable the counter chip U2. The counter chip U2 Receive the clock signal CLK-1, and perform cumulative counting each time the clock signal CLK-1 is received. The carry output pin TC of the counter chip U2 is connected to the enable terminal CET and the enable terminal CEP of the counter chip U3. When the cumulative count of the counter chip U2 reaches the rated count value, a high level is output to the counter chip U3 to enable the counter chip U3. The counter chip U3 receives the clock signal CLK-1. The carry output pin TC of the counter chip U3 is connected to an input terminal of the AND gate logic module U7A through the NOT gate logic module U10A. The input signal INPUT_SIGNAL to be filtered is input to the CLK terminal, the reset terminal MR of the counter chip U4 and the reset terminal MR of the counter chip U5, the enable terminal CET and the enable terminal CEP of the counter chip U4 are both connected to the power supply, the first counting output pin Q0 of the counter chip U4 is connected to an input terminal of the AND gate logic module U8A, the output terminal of the AND gate logic module U8A is connected to the enable terminal CEP of the counter chip U5, the enable terminal CET of the counter chip U5 is connected to the power supply, the CLK terminal input of the counter chip U5 is the clock signal CLK-2 output by the crystal oscillator Y2, the first counting output pin Q0 of the counter chip U5 is simultaneously connected to the input terminal of the NOT gate logic module U9A, the CLK terminal of the counter chip U6 and the other input terminal of the AND gate logic module U7A, the first counting output pin Q0 of the counter chip U5 outputs the signal SIGNAL, and the output terminal of the NOT gate logic module U9A is connected to the other input terminal of the AND gate logic module U8A; The reset terminal MR of the counter chip U6 is connected to the output terminal of the AND gate logic module U7A, the enable terminal CET and the enable terminal CEP of the counter chip U6 are both connected to the power supply, and the first counting output terminal Q0 of the counter chip U6 outputs the final filtered OUTPUT_SIGNAL signal.

2. A frequency configurable bandpass filter circuit as claimed in claim 1, characterized in that: When the high-frequency signal in the input signal INPUT_SIGNAL is input to the counter chip U4, the counter chip U4 starts counting. When the counter chip U4 counts to 1, the Q0 output pin of the counter chip U4 outputs a high-level signal, and the output counting signal of the counter chip U5 after the non-logic enters the AND gate logic module U8A for AND logic to control the enablement of the counter chip U5. After the counter chip U5 is enabled, the counter chip U5 can output a high-level signal only when the clock signal CLK-2 output by the crystal oscillator Y2 changes from a low level to a high level. When the input signal INPUT_SIGNAL is at a low level, the counters U4 and U5 are reset, and U5 outputs a low level. Therefore, when the frequency of the high-frequency signal in the input signal INPUT_SIGNAL is higher than the frequency f of the clock signal output by the crystal oscillator Y2, the counter chip U5 cannot count normally, and the high-frequency signal is filtered out. The output signal SIGNAL is a signal that has been filtered through high-frequency filtering.

3. A frequency configurable bandpass filter circuit as claimed in claim 2, characterized in that: When the clock signal CLK-1 output by the crystal oscillator Y1 is input to the counter chip U1, the counter chip U1 starts counting. When the count reaches 10, the carry output pin TC of the counter chip U1 starts to output a high level, enabling the counter chip U2. The counter chip U2 starts counting. When the count reaches 10, the carry output pin TC of the counter chip U2 starts to output a high level, enabling the counter chip U3. The counter chip U3 starts counting. When the count reaches 10, the carry output pin TC of the counter chip U3 outputs a high level. After passing through the NOT gate logic module, the counter chip U6 is reset. After the delay of the crystal oscillator Y1 and the counter chips U1, U2, and U3, the final low-frequency cutoff frequency of the passband voltage filter circuit is F / 1000, realizing the low-frequency filtering function.

4. A frequency configurable bandpass filter circuit as claimed in claim 3, characterized in that: The signal SIGNAL after high-frequency filtering is input to the CLK terminal of the counter chip U6 and the other input terminal of the AND gate logic module U7A. When the SIGNAL frequency is higher than F / 1000 and the carry output pin TC of the counter chip U3 outputs a low level, U6 starts to count the SIGNAL signal. When SIGNAL is a high level, the count output terminal Q0 of the counter chip U6 outputs a high level. When SIGNAL is a low level, U7A outputs a low level, resetting the counter U6. The count output terminal Q0 of the counter chip U6 outputs a low level, thereby filtering out signals with frequencies lower than F / 1000, and finally outputting OUTPUT_SIGNAL filtered by the bandpass filter circuit.

5. A frequency configurable bandpass filter circuit as claimed in claim 4, characterized in that: The final output signal of the bandpass filter circuit is OUTPUT_SIGNAL, and the filtering frequency range is F / 1000~f.

6. A frequency configurable bandpass filter circuit as claimed in claim 5, characterized in that: By setting the counter chip and crystal oscillator specifications, the frequency signal is filtered to filter out high-frequency signals above the specified frequency, thereby forming a frequency signal after high-frequency filtering.

7. A frequency configurable bandpass filter circuit as claimed in claim 6, characterized in that: The number of counter chips, the number of counting pins and the frequency of the crystal oscillator Y2 used to filter out high-frequency signals are determined according to the high-frequency cutoff frequency required by the band-pass voltage filter circuit.

8. A frequency configurable bandpass filter circuit as claimed in claim 7, characterized in that: The number of counter chips, the number of counting pins, the base of the counter, and the frequency of the crystal oscillator Y1 used to filter out low-frequency signals are determined according to the low-frequency cutoff frequency required by the band-pass voltage filter circuit.

Images