Chip testing method, device, equipment and readable storage medium

Abstract

The present application discloses a chip testing method, device, equipment and readable storage medium. The present application divides the chip to be tested into multiple subsystems; divides each subsystem into multiple modules, and divides all modules into multiple sets; for any set, based on the physical position of each module in the set in the chip to be tested, selects the nearest test pin for each module in the set, and tests each module in the set in parallel based on the selected test pin, so as to test modules with smaller granularity, shorten the scan path, reduce the difficulty of physical wiring, and realize time-sharing multiplexing of chip pins, thereby reducing testing overhead. Correspondingly, the chip testing device, equipment and readable storage medium provided by the present application also have the above-mentioned technical effects.

Description

Technical Field

[0001] The present application relates to the field of computer chip testing technology, and in particular to a chip testing method, device, equipment and readable storage medium. Background Art

[0002] At present, the number of transistors integrated on a single chip has increased from millions to tens of millions, and even to billions. The chip functions are becoming more and more powerful, and the number of modules that need to be tested is also increasing.

[0003] Currently, tens of thousands of scan chains in a chip can be compressed into a few or dozens based on EDT compression scan chain technology to alleviate the shortage of chip test pins. However, in a scan chain, the input test pins and output test pins span multiple modules, so the scan path is long, which not only brings great challenges to test timing convergence and reduces test efficiency, but also makes the physical wiring required for testing very difficult.

[0004] Therefore, how to shorten the scan path and reduce the difficulty of physical wiring is a problem that those skilled in the art need to solve. Summary of the invention

[0005] In view of this, the purpose of this application is to provide a chip testing method, device, equipment and readable storage medium to shorten the scanning path and reduce the difficulty of physical wiring. The specific scheme is as follows:

[0006] In a first aspect, the present application provides a chip testing method, comprising:

[0007] Divide the chip under test into multiple subsystems;

[0008] Divide each subsystem into multiple modules, and divide all modules into multiple sets;

[0009] For any set, based on the physical position of each module in the set in the chip to be tested, select a nearby test pin for each module in the set, and test each module in the set in parallel based on the selected test pin;

[0010] The total number of test pins required by all modules in any set is not greater than the total number of pins of the chip to be tested.

[0011] Preferably, the chip to be tested and each subsystem are divided according to logical independence.

[0012] Preferably, the testing of the modules in the set in parallel based on the selected test pins comprises:

[0013] If there are modules with the same function in the set, the same test stimulus is input in parallel to the modules with the same function.

[0014] Preferably, the parallel input of the same test stimulus to the modules with the same functions comprises:

[0015] A broadcast structure is used to input the same test stimulus to the modules with the same functions in parallel.

[0016] Preferably, before the parallel testing of the modules in the set based on the selected test pins, the method further comprises:

[0017] Configure the interface registers of each module based on the internal test mode of the wrapper chain to isolate different modules.

[0018] Preferably, the testing of the modules in the set in parallel based on the selected test pins comprises:

[0019] The modules in the set are tested in parallel by controlling the selected test pins using a multiplexer.

[0020] Preferably, for any set, based on the physical position of each module in the set in the chip to be tested, selecting a test pin nearby for each module in the set, and testing each module in the set in parallel based on the selected test pin, further comprises:

[0021] Determine at least two modules in the set whose module connection boundaries need to be tested, and configure interface registers of the at least two modules using an external test mode of a wrapper chain to connect the at least two modules;

[0022] The module connection boundary is tested based on a module test pin of any one of the at least two modules that are connected.

[0023] In a second aspect, the present application provides a chip testing device, comprising:

[0024] A first division module is used to divide the chip to be tested into multiple subsystems;

[0025] A second partitioning module is used to partition each subsystem into multiple modules and to partition all modules into multiple sets;

[0026] A test module, for selecting, for any set, a test pin for each module in the set based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pin;

[0027] The total number of test pins required by all modules in any set is not greater than the total number of pins of the chip to be tested.

[0028] In a third aspect, the present application provides an electronic device, including:

[0029] Memory for storing computer programs;

[0030] The processor is used to execute the computer program to implement the chip testing method disclosed above.

[0031] In a fourth aspect, the present application provides a readable storage medium for storing a computer program, wherein the computer program implements the aforementioned disclosed chip testing method when executed by a processor.

[0032] It can be seen from the above scheme that the present application provides a chip testing method, including: dividing the chip to be tested into multiple subsystems; dividing each subsystem into multiple modules, and dividing all modules into multiple sets; for any set, based on the physical position of each module in the set in the chip to be tested, selecting test pins for each module in the set nearby, and testing each module in the set in parallel based on the selected test pins; wherein the total number of test pins required for all modules in any set is not greater than the total number of pins of the chip to be tested.

[0033] It can be seen that the present application divides the chip to be tested into multiple subsystems; divides each subsystem into multiple modules, and divides all modules into multiple sets; for any set, based on the physical position of each module in the set in the chip to be tested, selects test pins for each module in the set nearby, and tests each module in the set in parallel based on the selected test pins, so as to test modules with smaller granularity. Since the test pins are selected nearby for each module, the scan path when testing each module is shorter, reducing the difficulty of physical wiring. At the same time, the total number of test pins required for all modules in a set is not greater than the total number of pins of the chip to be tested, and each module is tested in parallel, which can not only improve the test efficiency, but also make full use of all the pins of the chip to be tested. Each set is tested accordingly, and time-sharing multiplexing of chip pins can be achieved, reducing test overhead.

[0034] Correspondingly, a chip testing device, equipment and readable storage medium provided by the present application also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0036] Figure 1 A flow chart of a chip testing method disclosed in this application;

[0037] Figure 2 A schematic diagram of a scanning path disclosed in this application;

[0038] Figure 3 for Figure 2 Schematic diagram of scan chain corresponding to the scan path shown;

[0039] Figure 4 A schematic diagram of a scanning path across different modules disclosed in this application;

[0040] Figure 5 A schematic diagram of a subsystem-based chip pin multiplexing disclosed in this application;

[0041] Figure 6 This is another schematic diagram of subsystem-based chip pin multiplexing disclosed in this application;

[0042] Figure 7 A schematic diagram of a scan chain included in a single module disclosed in this application;

[0043] Figure 8 A schematic diagram of a chip testing device disclosed in this application;

[0044] Fig. 9 This is a schematic diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] To facilitate the introduction of this application, the background technology involved in this application is first introduced as follows.

[0047] With the sharp increase in demand for large-scale chips in industries such as artificial intelligence and data storage, the scale of SoC has shown exponential growth. The number of transistors integrated on a single chip has increased from millions to tens of millions, and even to billions. However, the size requirements for chips have become smaller and smaller, which has brought severe challenges to the testing of chips after manufacturing. With the steady improvement of semiconductor processes, the possible defects in the manufacturing process have become more diverse and complex. It is necessary to develop more targeted test vectors based on physical manufacturing defects and corresponding fault models to ensure chip quality.

[0048] Chip testing connects ATE (automatic test equipment) to the pins of the chip, injects test stimuli into the chip, and reads the response results after the chip responds, and compares them with the expected results to screen the quality of the chip. However, the increase in the number of chip pins is far less than the growth scale of the chip's internal logic. On the other hand, the number of chip pins is affected by physical implementation. Under the premise of meeting functional requirements, the fewer the number of pins, the better, so as not to design additional pins specifically for chip testing. Therefore, the pins used in chip testing are mostly digital pins defined by multiplexing functions.

[0049] The compressed scan chain technology provided by EDT (Embedded Deterministic Test) can compress thousands of scan chains into a few to dozens, effectively alleviating the problem of insufficient number of chip test pins. However, as the chip scale continues to increase, the chip's functional pins can no longer meet current testing needs.

[0050] Moreover, in a scan chain, the input test pins and the output test pins span multiple modules, so the scan path is long, which not only brings great challenges to the test timing convergence and reduces the test efficiency, but also makes the physical wiring required for the test very difficult. To this end, the present application provides a chip testing solution that can shorten the scan path and reduce the difficulty of physical wiring.

[0051] See also Figure 1 As shown, the embodiment of the present application discloses a chip testing method, including:

[0052] S101, dividing the chip to be tested into multiple subsystems.

[0053] S102, dividing each subsystem into multiple modules, and dividing all modules into multiple sets.

[0054] It should be noted that the division of a chip to be tested needs to consider the independence and interconnectivity of each functional module in the chip. If the function of a module is independent, it means that the module can be tested separately. If the functions of two modules are interrelated, in addition to testing the two modules separately, it is also necessary to test whether the interrelated logic can run smoothly.

[0055] Correspondingly, different subsystems also need to follow such rules. Therefore, in a specific implementation, the chip to be tested and each subsystem are divided according to logical independence.

[0056] Among them, each subsystem and each module is divided based on the logical function of the chip, and corresponds to the corresponding physical devices on the chip. Therefore, each module on the chip to be tested is to test the data processing logic between the corresponding physical devices that implement the module.

[0057] S103 . For any set, based on the physical position of each module in the set in the chip to be tested, select a nearby test pin for each module in the set, and test each module in the set in parallel based on the selected test pin.

[0058] Since each module on the chip to be tested is essentially testing the data processing logic between the corresponding physical devices that implement the module, it is necessary to connect the corresponding pins of the chip to test the data processing logic between these physical devices. In order to shorten the scan path, this embodiment selects the test pins nearby for each module, thereby reducing the difficulty of physical wiring required for the test. Figure 2 As shown, the test pins of module A (including input pins and output pins) are all near module A, and the test pins of module B are all near module B, so the physical wiring difficulty is low.

[0059] After a chip to be tested is divided into modules in this embodiment, the number of pins required to test each module can be determined based on the test requirements of each module. However, since the number of pins on a chip to be tested is limited, it is necessary to test in batches. To this end, this embodiment divides all modules into several sets, and performs a test process in parallel for each module in a set.

[0060] The total number of test pins required by all modules in any set is not greater than the total number of pins of the chip to be tested.

[0061] In order to make every test process use all the pins of the chip to be tested as much as possible, all modules can be divided into sets according to the total number of pins of the chip to be tested. That is, the total number of test pins required for all modules in any set is equal to the total number of pins of the chip to be tested. Of course, it is also possible that the total number of test pins required for all modules in any set is less than the total number of pins of the chip to be tested, but there are idle chip pins when testing the corresponding set, which is not conducive to improving test efficiency.

[0062] For example: a chip to be tested has 10 pins, and the chip to be tested is divided into 5 modules: A, B, C, D, and E. Among them, module A requires 2 test pins, module B requires 4 test pins, module C requires 6 test pins, module D requires 8 test pins, and module E requires 10 test pins. Then A and D can be divided into a set X, B and C can be divided into a set Y, and E can be separated into a set Z. In this way, when testing sets X, Y, and Z separately, all the pins of the chip are used, realizing the maximum utilization of the chip pins; at the same time, the test processes corresponding to sets X, Y, and Z respectively realize the time-sharing multiplexing of chip pins.

[0063] Generally, a chip may not provide pins specifically used for testing. In this case, when testing the chip, it is sufficient to define each functional pin of the chip as a test pin.

[0064] In a specific embodiment, each module in the set is tested in parallel based on the selected test pins, including: if there are modules with the same function in the set, the same test stimulus is input in parallel to the modules with the same function. Wherein, the same test stimulus is input in parallel to the modules with the same function using a broadcast structure. Modules with the same function are: modules that are completely identical. The test stimulus is: input data designed for testing the corresponding module. The input data is input through the input pin, and the module's response to the input data is obtained from the corresponding output pin, so that it can be determined whether the response meets expectations.

[0065] It can be seen that the present embodiment divides the chip to be tested into multiple subsystems; divides each subsystem into multiple modules, and divides all modules into multiple sets; for any set, based on the physical position of each module in the set in the chip to be tested, selects a test pin for each module in the set nearby, and tests each module in the set in parallel based on the selected test pins, thereby testing modules with smaller granularity. Since the test pins are selected nearby for each module, the scan path when testing each module is shorter, reducing the difficulty of physical wiring. At the same time, the total number of test pins required for all modules in a set is not greater than the total number of pins of the chip to be tested, and each module is tested in parallel, which can not only improve the test efficiency, but also make full use of all the pins of the chip to be tested. Each set is tested accordingly, and time-sharing multiplexing of chip pins can be achieved, reducing test overhead.

[0066] Based on the above embodiments, it should be noted that, in a specific implementation, before testing the modules in the set in parallel based on the selected test pins, it also includes: configuring the interface register of each module based on the internal test mode of the Wrapper chain to isolate different modules.

[0067] Based on the above embodiment, it should be noted that, in a specific implementation, the modules in the set are tested in parallel based on the selected test pins, including: using a multiplexer to control the selected test pins to test the modules in the set in parallel. The multiplexer is used to control the test pins (including input pins and output pins) corresponding to each module, so as to determine which module is tested with which pins. For details, please refer to Figure 3 .

[0068] Will Figure 2 The scanning path corresponding to module A is expanded to obtain Figure 3 .Depend on Figure 3 It can be seen that when testing each module, a decompressor and a compressor need to be set accordingly. Among them, multiple modules can reuse the same set of decompressors and compressors, or one module can use a set of decompressors and compressors. The use of decompressors and compressors can be specifically referred to the existing related technologies, and will not be repeated here.

[0069] At the same time, there can be multiple scan chains in a module, and each scan chain runs through N registers. The first register of a scan chain is called the chain head register, and the last register is called the chain tail register. The scan path is used to indicate the direction of the scan chain.

[0070] Based on the above embodiments, it should be noted that, in a specific implementation manner, for any set, based on the physical position of each module in the set in the chip to be tested, a test pin is selected nearby for each module in the set, and after each module in the set is tested in parallel based on the selected test pin, it also includes: determining at least two modules in the set that need to test the module connection boundary, and configuring the interface registers of at least two modules using the external test mode of the wrapper chain to connect at least two modules; testing the module connection boundary based on the test pin of any module in the at least two connected modules.

[0071] For details, please see Figure 4 ,Depend on Figure 4 It can be seen that the connection boundary between module C and module D, and the connection boundary between module D and module E need to be tested. In the prior art, the scanning path generally spans modules C, D, and E, and the input pins are selected near module C, while the output pins are selected near module E. Since modules C and E are physically far away on the chip, it is not easy to connect the test circuits.

[0072] To this end, this application uses the external test mode of the Wrapper chain to connect module C and module D, and uses the pins near module C as input pins and output pins to first test the connection boundary between module C and module D; then, the external test mode of the Wrapper chain is used to connect module D and module E, and uses the pins near module E as input pins and output pins to test the connection boundary between module D and module E, thereby completing the boundary test between modules. This not only shortens the scan path, but also reduces the difficulty of wiring. Correspondingly, different subsystems can also be tested in this way.

[0073] It should be noted that since the current EDT compression ratio has reached one hundred or even two hundred, an excessively high compression ratio will lead to a decrease in the efficiency of ATPG (Automated Test Pattern Generation) in generating vectors, and the number of generated test vectors will also increase sharply, which will in turn affect the vector generation time and chip testing costs.

[0074] Therefore, this embodiment uses time-division multiplexing technology to time-division multiplex the functional pins. In a certain time period, only the implementation logic of a part of the chip subsystem or a single module is tested. In another time period, the logic of other subsystems of the chip is tested. This is equivalent to doubling the available test pins, effectively solving the current problem of insufficient test pins.

[0075] like Figure 5 As shown, the system on chip is divided into two subsystems, and the control register is selected by the multiplexer selector. In the first test period, the input pins and output pins are multiplexed to subsystem 1, and the scan test of subsystem 1 is completed first; in the second test period, the input pins and output pins are multiplexed to subsystem 2, and the scan test of subsystem 2 is completed. Of course, the pins used in any test process should not exceed the total number of chip pins.

[0076] If the whole chip is divided into three subsystems, namely subsystem 1, subsystem 2 and subsystem 3, then in the first test period, two subsystems can be selected for parallel testing. After these two subsystems are tested in parallel, the remaining subsystems can be tested. Of course, the pins used in any test process should not exceed the total number of chip pins.

[0077] Since there are many modules in a subsystem, testing a subsystem may need to span multiple modules, resulting in a longer scan chain and inability to flexibly select the pins used for testing.

[0078] In this regard, this embodiment divides the entire chip into subsystems and then into submodules for group testing, achieving the goal of high coverage and fewer test pins while meeting the test requirements. This embodiment further divides the standard logic units of the subsystem into different modules according to the requirements of function and physical implementation, takes the modules as test units, and performs time-sharing tests on different modules of the subsystem.

[0079] Specifically, the scan chain of the module is used as the compression object, a compressor and a decompressor are added to each module, and the scan channel formed between the compressor and the decompressor is connected to the pins near the module. Figure 2 As shown, the scan path is only within a single module and does not cross different submodules. If you need to test module boundaries, refer to Figure 4 And the corresponding introduction above.

[0080] If a chip has pins 1, 2, 3, and 4, and the chip is Figure 6 As shown, it is divided into subsystem 1 (including module AB), subsystem 2 (including module CDE), and subsystem 3 (including module FG). Then, in the first test, these pins are used for scan path 1 and scan path 2 of subsystem 1, and scan path 7 and scan path 8 of subsystem 3. After the test is completed, scan path 3, scan path 4, scan path 5, and scan path 6 of subsystem 2 reuse these pins. In this way, the maximum utilization and reuse of pins are achieved.

[0081] It should be noted that when dividing subsystems and modules, it is necessary to fully consider the independence and interactivity of each subsystem or submodule test, and try to balance the test requirements of each subsystem and submodule, so that when time-sharing functional pins are reused, the effective reuse rate of the pins can be maximized. Figure 6 As shown, in each test process, all pins are used as much as possible; and in different test processes, all pins are reused as much as possible to maximize the pin reuse rate.

[0082] Therefore, the interface timing logic unit (ie, interface register) of the subsystem or submodule is configured in a Wrapperchain manner.

[0083] by Figure 6 Taking the module D shown in the figure as an example, when designing the scan chain, the timing logic of the interface part of the module D is separately connected into one or several input and output wrapper chains, so that the wrapper chain plays the role of isolating each subsystem or submodule.

[0084] like Figure 7As shown, the sequential logic units related to the module D interface are strung together into input and output scan chains. When testing inside the module, the wrapper chain is used only as a shift register or capture register by controlling the internal test mode of the wrapper chain. When testing the boundaries of different modules or different subsystems, only the wrapper chain can be checked by controlling the external test mode of the wrapper chain, which is beneficial for vector generation and testing of large-scale chips.

[0085] This embodiment can flexibly configure and reuse test pins, and the test scale and test unit division are smaller, which can shorten the scan path and reduce the difficulty of timing convergence. For chips with large logic scale and area, the scan path can be shortened by almost half, and the timing improvement effect is particularly significant. The use of wrapper chain can effectively improve test coverage and reduce test time.

[0086] It can be seen that this embodiment can not only realize the compression of the scan chain, but also has the most important function of planning the optimal compressed scan channel length for complex and large-scale designs according to the physical placement of the chip pins, using time-sharing multiplexing technology, alleviating the bottleneck between the number of chip pins and the test time, reducing the compression ratio, and alleviating the problems of EDT internal winding blockage and chip top-level wiring difficulties. At the same time, the test grouping of the subsystem is further refined, the reused pins are reasonably configured, the scan path is optimized, and the difficulty of timing convergence is reduced.

[0087] In addition, for sub-modules or sub-systems that are reused multiple times, shared data channels can be considered when formulating a test pin reuse plan, that is, using a broadcast structure to test these same sub-modules or sub-systems simultaneously with the same stimulus to meet the requirements for the number of pins used.

[0088] A chip testing device provided in an embodiment of the present application is introduced below. The chip testing device described below and the chip testing method described above can be referenced to each other.

[0089] See also Figure 8 As shown, the embodiment of the present application discloses a chip testing device, including:

[0090] The first division module 801 is used to divide the chip to be tested into multiple subsystems;

[0091] The second division module 802 is used to divide each subsystem into multiple modules and divide all modules into multiple sets;

[0092] The testing module 803 is used for selecting a test pin for each module in any set based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pin;

[0093] The total number of test pins required by all modules in any set is not greater than the total number of pins of the chip to be tested.

[0094] In a specific implementation, the test module is specifically used to:

[0095] If there are modules with the same function in the set, the same test stimulus is input to the modules with the same function in parallel.

[0096] In a specific implementation, the test module is specifically used to:

[0097] The broadcast structure is used to input the same test stimulus to modules with the same function in parallel.

[0098] In a specific embodiment, it also includes:

[0099] The first configuration module is used to configure the interface register of each module based on the internal test mode of the wrapper chain to isolate different modules.

[0100] In a specific implementation, the test module is specifically used to:

[0101] The modules in the set are tested in parallel by controlling the selected test pins using a multiplexer.

[0102] In a specific embodiment, it also includes:

[0103] The second configuration module is used to determine at least two modules in the set whose module connection boundaries need to be tested, and use the external test mode of the wrapper chain to configure the interface registers of the at least two modules to connect the at least two modules; based on the test pin of any one of the at least two connected modules, the module connection boundary is tested.

[0104] Among them, for more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0105] It can be seen that this embodiment provides a chip testing device, which tests modules with smaller granularity, has a shorter scanning path, reduces the difficulty of physical wiring, and can also realize time-sharing multiplexing of chip pins, thereby reducing testing overhead.

[0106] An electronic device provided in an embodiment of the present application is introduced below. The electronic device described below and the chip testing method and device described above can be referenced to each other.

[0107] See also Fig. 9 As shown, the embodiment of the present application discloses an electronic device, including:

[0108] Memory 901, used for storing computer programs;

[0109] The processor 902 is used to execute the computer program to implement the method disclosed in any of the above embodiments.

[0110] A readable storage medium provided in an embodiment of the present application is introduced below. The readable storage medium described below and the chip testing method, device and apparatus described above can be referenced to each other.

[0111] A readable storage medium is used to store a computer program, wherein the computer program, when executed by a processor, implements the chip testing method disclosed in the above embodiment. The specific steps of the method can refer to the corresponding contents disclosed in the above embodiment, and will not be repeated here.

[0112] The "first", "second", "third", "fourth", etc. (if any) referred to in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods or devices.

[0113] It should be noted that the descriptions involving "first", "second", etc. in this application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0114] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0115] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of readable storage medium known in the art.

[0116] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A chip testing method, characterized in that: include: Divide the chip under test into multiple subsystems; Each subsystem is divided into multiple modules, and all modules are divided into multiple sets; wherein, when dividing a chip to be tested, the independence and interconnection of each functional module in the chip are considered; if the function of a module is independent, the module is tested separately; if the functions of two modules are interrelated, in addition to testing the two modules separately, the logic of the interrelated parts is also tested to see whether they can run smoothly; the chip to be tested and each subsystem are divided specifically according to the logic independence; For any set, based on the physical position of each module in the set in the chip to be tested, select the nearest test pin for each module in the set, and test each module in the set in parallel based on the selected test pin; if no pin is provided specifically for testing, each functional pin is a test pin; when testing each module, a decompressor and a compressor are set accordingly; multiple modules reuse the same set of decompressors and compressors; The total number of test pins required by all modules in any set is not greater than the total number of pins of the chip to be tested; Wherein, for any set, based on the physical position of each module in the set in the chip to be tested, selecting a test pin nearby for each module in the set, and testing each module in the set in parallel based on the selected test pin, further comprising: Determine at least two modules in the set whose module connection boundaries need to be tested, and configure interface registers of the at least two modules using an external test mode of a wrapper chain to connect the at least two modules; The module connection boundary is tested based on a module test pin of any one of the at least two modules that are connected.

2. The chip testing method according to claim 1, characterized in that: The step of testing each module in the set in parallel based on the selected test pins comprises: If there are modules with the same function in the set, the same test stimulus is input in parallel to the modules with the same function.

3. The chip testing method according to claim 2, characterized in that: The parallel input of the same test stimulus to the modules with the same functions comprises: A broadcast structure is used to input the same test stimulus to the modules with the same functions in parallel.

4. The chip testing method according to claim 1, characterized in that: Before the modules in the set are tested in parallel based on the selected test pins, the method further includes: Configure the interface registers of each module based on the internal test mode of the wrapper chain to isolate different modules.

5. The chip testing method according to claim 1, characterized in that: The step of testing each module in the set in parallel based on the selected test pins comprises: The modules in the set are tested in parallel by controlling the selected test pins using a multiplexer.

6. A chip testing device, characterized in that: include: A first division module is used to divide the chip to be tested into multiple subsystems; The second division module is used to divide each subsystem into multiple modules and divide all modules into multiple sets; wherein, the division of a chip to be tested takes into account the independence and interconnection of each functional module in the chip; if the function of a module is independent, the module is tested separately; if the functions of two modules are interrelated, in addition to testing the two modules separately, the interrelated logic is also tested to see whether it can run smoothly; the chip to be tested and each subsystem are divided according to the logic independence; The test module is used to select a test pin for each module in the set based on the physical position of each module in the set in the chip to be tested, and test each module in the set in parallel based on the selected test pin; if no pin is provided specifically for testing, each functional pin is a test pin; when testing each module, a decompressor and a compressor are set accordingly; multiple modules reuse the same set of decompressors and compressors; The total number of test pins required by all modules in any set is not greater than the total number of pins of the chip to be tested; Wherein, for any set, based on the physical position of each module in the set in the chip to be tested, selecting a test pin nearby for each module in the set, and testing each module in the set in parallel based on the selected test pin, further comprising: Determine at least two modules in the set whose module connection boundaries need to be tested, and configure interface registers of the at least two modules using an external test mode of a wrapper chain to connect the at least two modules; The module connection boundary is tested based on a module test pin of any one of the at least two modules that are connected.

7. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the chip testing method according to any one of claims 1 to 5.

8. A readable storage medium, characterized in that: Used to store a computer program, wherein the computer program, when executed by a processor, implements the chip testing method according to any one of claims 1 to 5.

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