Brightness Compensation Method, Brightness Compensation System, and Display System

Abstract

A brightness compensation method, comprising: generating brightness compensation data based on test image data, each of the test image data corresponding to a gray level, and each of the brightness compensation data including a compensation value corresponding to a gray level; generating in-plane data based on the brightness compensation data, one of the in-plane data being generated based on one of the brightness compensation data; generating inter-plane flow data based on the in-plane data, one of the inter-plane flow data being generated based on a data block included in the in-plane data and arranged at the same position within the in-plane data; and sequentially storing the inter-plane flow data in a memory.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2020 - 0093654, filed on Jul. 28, 2020, with the Korean Intellectual Property Office (KIPO), the subject matter of which is incorporated herein by reference. Technical field

[0003] Embodiments of the inventive concept generally relate to semiconductor integrated circuits, and more particularly, to a method of compensating for luminance, a luminance compensation system, and a display system that performs luminance compensation. Background art

[0004] Display devices - such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting displays (OLEDs) - are commonly used in many types of electronic devices. Various types of display panels including a plurality of pixels may be included in a display device. In response to the same input data (e.g., the same gray level), pixels should exhibit similar brightness (or the same luminance). However, defects in the design of the display panel or variations in the (multiple) manufacturing processes may cause luminance deviation between pixels. Therefore, luminance compensation should be performed. Summary of the invention

[0005] Various embodiments of the inventive concept provide a luminance compensation method, a luminance compensation system, and a related display system that can reduce the hardware cost and complexity associated with reading luminance compensation data.

[0006] In one embodiment, the inventive concept provides a luminance compensation method, including: generating luminance compensation data based on test image data, each of the test image data corresponding to a gray level, and each of the luminance compensation data including a compensation value corresponding to a gray level; generating intra - plane data based on the luminance compensation data, one of the intra - plane data being generated based on one of the luminance compensation data; generating inter - plane flow data based on the intra - plane data, one of the inter - plane flow data being generated based on a data block included in and disposed at the same position within the intra - plane data; and sequentially storing the inter - plane flow data in a memory.

[0007] In another embodiment, the inventive concept provides a brightness compensation system, including: a circuit configured to provide test image data to a display panel, wherein each of the test image data corresponds to a gray level; an image capture device configured to generate brightness data by capturing a panel image displayed on the display panel in response to the test image data; and a brightness compensation circuit. The brightness compensation circuit may be configured to generate brightness compensation data based on the brightness data, wherein each of the brightness compensation data includes a compensation value corresponding to a gray level, generate in-plane data based on the brightness compensation data, generate each of the inter-plane flow data based on data blocks included in and disposed at the same positions within each of the in-plane data, and sequentially store the inter-plane flow data in a memory.

[0008] In another embodiment, the inventive concept provides a display system, including: a display device including a brightness compensation circuit and a host processor configured to control the display device. The brightness compensation circuit may include: a brightness compensation data memory configured to store the inter-plane flow data, an in-plane data generator configured to sequentially read the inter-plane flow data and generate data blocks based on the inter-plane flow data to generate in-plane data, wherein the data blocks are included in the in-plane data and disposed at the same positions within each of the in-plane data, a brightness compensation data generator configured to generate the brightness compensation data based on the in-plane data, and a brightness compensation image data generator configured to generate output image data by compensating input image data based on the brightness compensation data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the present disclosure will be understood more clearly through the following detailed description in conjunction with the accompanying drawings.

[0010] Figure 1 is a flowchart outlining a brightness compensation method according to an embodiment of the inventive concept.

[0011] Figure 2 is a conceptual diagram showing a first brightness compensation system according to an embodiment of the inventive concept.

[0012] Figure 3 is further shown in one example Figure 2 a block diagram of the first brightness compensation circuit 110.

[0013] Figure 4 is a conceptual diagram showing an example of brightness compensation data, Figure 5 is a conceptual diagram showing an example of in-plane data, and Figure 6 is a conceptual diagram showing an example of inter-plane flow data.

[0014] Figure 7Aand Figure 7B is a corresponding conceptual diagram showing a method of storing inter-plane flow data in an embodiment of the inventive concept.

[0015] Figure 8 is a block diagram showing a second brightness compensation system according to an embodiment of the inventive concept.

[0016] Figure 9 further shows in one example Figure 8 a block diagram of the display device 210.

[0017] Figure 10 and Figure 11 is a diagram showing Figure 8 and Figure 9 a corresponding block diagram of an example of a second brightness compensation circuit.

[0018] Figure 12A and Figure 13A is a diagram showing Figure 11 the operations of a first decoder and a second decoder, and Figure 12B and 13B is a related timing diagram further illustrating Figure 11 the operations of the first decoder and the second decoder.

[0019] Figure 14 is a flowchart outlining a method of sequentially storing inter-plane flow data in a memory in an embodiment of the inventive concept.

[0020] Figure 15 is a block diagram showing a first brightness compensation circuit according to an embodiment of the inventive concept in another example.

[0021] Figure 16 is a block diagram showing a display mobile device including a second brightness compensation circuit according to an embodiment of the inventive concept. Detailed Description

[0022] Certain embodiments of the inventive concept will be described with some additional details with reference to the accompanying drawings. Throughout the written description and the drawings, the same reference numerals denote the same or similar elements.

[0023] Figure 1 is a flowchart outlining a brightness compensation method according to an embodiment of the inventive concept.

[0024] In this method, brightness compensation data is generated based on test image data (S1000). Here, each of the test image data may correspond to a gray level, and each of the brightness compensation data may include a compensation value corresponding to a gray level.

[0025] Generate in - plane data based on luminance compensation data (S2000). Here, each in - plane data can be generated based on one of the luminance compensation data.

[0026] Generate inter - plane flow data based on a plurality of in - plane data (S3000). Here, each inter - plane flow data can be generated based on data blocks that are included in the in - plane data and are arranged at the same positions within the in - plane data.

[0027] Once the inter - plane flow data has been sequentially stored in the memory (S4000), if necessary, the inter - plane flow data can be sequentially read from the memory (S5000).

[0028] In - plane data can be generated by generating data blocks based on the inter - plane flow data. The data blocks are included in each of the in - plane data and are arranged at the same positions within the in - plane data.

[0029] Generate luminance compensation data based on the in - plane data, and generate output image data for displaying an image by compensating input image data based on the luminance compensation data (S8000).

[0030] In some embodiments, the first luminance compensation system 100 (examples of which will be referred to later Figure 2 for description) can be used to perform Figure 1 method steps S1000, S2000, S3000, and S4000. The second luminance compensation system 200 (examples of which will be referred to Figure 8 for description) can be used to perform method steps S5000, S6000, S7000, and S8000.

[0031] Figure 2 is a block diagram showing a first luminance compensation system according to an embodiment of the inventive concept in one example.

[0032] Refer to Figure 2 , the first luminance compensation system 100 can be used to generate luminance compensation data for a manufactured display panel. In this regard, the luminance compensation data can be used to compensate for defects in the design and / or manufacture of the display panel before the display panel is incorporated into (or configured as) a display device. For example, when the display panel manufacturer is different from the manufacturer of the display device that includes the display panel, the luminance compensation data can be generated by the display panel manufacturer and then communicated to the display device manufacturer.

[0033] The luminance compensation data can be transmitted to and stored in the second luminance compensation system 200 (as described with respect to Figure 8in one of the descriptions provided herein and can subsequently be used to compensate the input image data received by the second luminance compensation system 200. Thus, Figure 2 the first luminance compensation system 100 can be used to generate luminance compensation data associated with the display panel, and Figure 8 the second luminance compensation system 200 can subsequently use the luminance compensation data to compensate the input image data received by a display device including the display panel.

[0034] Figure 2 The first luminance compensation system 100 can include a circuit configured to provide test image data to the display panel 150 (where each of the test image data corresponds to a gray level), a first luminance compensation circuit (LCC1) 110, and an image capture (e.g., photographing) device 190. In some embodiments, the circuit providing the test image data can be provided in the first luminance compensation circuit 110 such that the first luminance compensation circuit 110 can provide the test image data TD to the display panel 150.

[0035] In some embodiments, the test image data TD can correspond to a gray level. For example, the test image data TD can respectively correspond to K gray levels, where "K" is an integer greater than 1. Thus, the test image data TD can be respectively generated according to one of a first gray level, a second gray level, a third gray level, and a fourth gray level (hereinafter referred to as "the first to fourth gray levels"), where the first to fourth gray levels can be respectively (for example) 31, 63, 127, and 255, but the scope of the inventive concept is not limited thereto.

[0036] The display panel 150 can display a panel image based on the test image data TD, and the image capture (e.g., photographing) device 190 can capture (e.g., photograph) the panel image and generate corresponding luminance data LD.

[0037] The first luminance compensation circuit 110 generates luminance compensation data based on the luminance data LD. For example, the first luminance compensation circuit 110 can generate in-plane data based on the luminance compensation data and generate inter-plane flow data based on the in-plane data. In this regard, the first luminance compensation circuit 110 can store the inter-plane flow data in the first luminance compensation data memory (LCM1). This method will be described in some additional details hereinafter.

[0038] Figure 3 is shown in an example Figure 2 a block diagram of the first luminance compensation circuit 110.

[0039] Referring to Figure 2 and Figure 3, the first brightness compensation circuit 110 may include a luminance compensation data generator (LCG) 131, a controller 132, a test image data provider (TDP) 133, a luminance compensation data processor 134, and a first luminance compensation memory (LCM1) 137. The luminance compensation data processor 134 includes an in-plane data generator (LPG) 135 and an inter-plane flow data generator (LSG) 136.

[0040] The controller 132 may be generally used to control the operations and interoperability of the components 131, 133, 134, 135, 136, and 137 of the first brightness compensation circuit 110. The controller 132 may provide test image data TD to the test image data provider 133, where the test image data provider 133 temporarily stores the test image data TD and provides it to the display panel 150.

[0041] The luminance compensation data generator 131 receives luminance data LD from the image capture device 190 and a control signal CTRA from the controller 132. The luminance compensation data generator 131 may generate luminance compensation data LC in response to the control signal CTRA and based on the luminance data LD and reference luminance data. Here, the reference luminance data may be data corresponding to each of the test image data TD, and may indicate (or represent) the ideal brightness value of the panel image displayed based on the test image data TD.

[0042] In some embodiments, the reference luminance data may be included in the control signal CTRA. In some embodiments, the luminance compensation data generator 131 may compare the test luminance value included in the luminance data LD with the reference luminance value included in the reference luminance data. The luminance compensation data generator 131 may generate the luminance compensation data LC by performing negative compensation when the test luminance value is greater than the reference luminance value and positive compensation when the test luminance value is less than the reference luminance value.

[0043] In some embodiments, each of the luminance compensation data LC has the same resolution as the display panel 150, and may be data having a defined size (e.g., (W*H), where "W" is the width of the display panel and "H" is the height of the display panel). That is, the size of the luminance compensation data LC may be 1920*1080 in a full HD display panel, 3840*2160 in a 4K UHD display panel, and 7680*4320 in an 8K UHD display panel.

[0044] Figure 4 is a conceptual diagram showing an example of luminance compensation data.

[0045] In Figure 4Among them, the luminance compensation data LC includes first to fourth luminance compensation data LC[1] to LC[4]. Each luminance compensation data may be 6*8 data with a height of 6 and a width of 8. However, this quantity and size of the luminance compensation data LC are merely examples. In some embodiments, the luminance compensation data LC may have a quantity and size corresponding to the test image data TD.

[0046] Reference Figure 4 , the first luminance compensation data LC[1] includes a plurality of data P1C11 to P1C68, where the number "1" after the letter P representing each data indicates that the data corresponds to the first luminance compensation data among the plurality of luminance compensation data, and the number "11" after the letter C indicates that the data is arranged in the first row and the first column. In the illustrated example, the second luminance compensation data LC[2] includes data P2C11 to P2C68, the third luminance compensation data LC[3] includes data P3C11 to P3C68, and the fourth luminance compensation data LC[4] includes data P4C11 to P4C68. Hereinafter, various data generated based on the luminance compensation data LC will be described in the context of the luminance compensation data LC shown in Figure 4 the context of the luminance compensation data LC shown.

[0047] Referring back to Figure 2 and Figure 3 , the in-plane data generator 135 receives the luminance compensation data LC from the luminance compensation data generator 131, receives the control signal CTR A from the controller 132, and generates in-plane data LP based on the luminance compensation data LC.

[0048] In some embodiments, the in-plane data generator 135 may generate one in-plane data LP based on one of the luminance compensation data LC. In some embodiments, the in-plane data generator 135 may generate one in-plane data LP based on data blocks generated by dividing one of the luminance compensation data LC into a predetermined size. The method will be described in some additional details hereinafter.

[0049] Figure 5 is a conceptual diagram further showing the generation of in-plane data in an example.

[0050] In Figure 5 it is shown that Figure 4The luminance compensation data LC and the corresponding in-plane data LP. That is, the luminance compensation data LC including the first to fourth luminance compensation data LC[1] to LC[4] and the in-plane data LP including the corresponding first to fourth in-plane data LP[1] to LP[4] are shown. In some embodiments, the number (or grouping) of the in-plane data LP may be the same as the number of the luminance compensation data LC. For example, in the illustrated example, the size of each in-plane data may be 3*4 (e.g., having a height of 3 and a width of 4). However, the number and size of the in-plane data LP may vary according to the design.

[0051] Therefore, referring to Figure 5 , the first in-plane data LP[1] is generated based on the first luminance compensation data LC[1], the second in-plane data LP[2] is generated based on the second luminance compensation data LC[2], the third in-plane data LP[3] is generated based on the third luminance compensation data LC[3], and the fourth in-plane data LP[4] is generated based on the fourth luminance compensation data LC[4]. That is, by dividing the first luminance compensation data LC[1], a plurality of first data blocks are generated, and each of the plurality of first data blocks has a first size. Information about the first size may be included in the control signal CTR A.

[0052] The first in-plane data LP[1] is generated based on the first data block. For example, the in-plane value P1P11 included in the first in-plane data LP[1] may be generated based on the luminance compensation values P1C11, P1C12, P1C21, and P1C22 included in one of the first data blocks generated by dividing the first luminance compensation data LC[1] into a 2*2 size (grouping). The in-plane value P1P12 included in the first in-plane data LP[1] may be generated based on the luminance compensation values P1C13, P1C14, P1C23, and P1C24 included in one of the first data blocks. The in-plane values P1P13 to P1P33 included in the first in-plane data LP[1] may be generated in a similar manner, and the in-plane value P1P34 included in the first in-plane data LP[1] may be generated based on the luminance compensation values P1C57, P1C58, P1C67, and P1C68 included in one of the first data blocks. In addition, the second in-plane data LP[2], the third in-plane data LP[3], and the fourth in-plane data LP[4] may also be generated in a manner similar to the first in-plane data LP[1].

[0053] In some embodiments, an in - plane value (e.g., P1P11) included in each of the in - plane data may be generated as a representative value of the luminance compensation values (e.g., P1C11, P1C12, P1C21, and P1C22) included in one of the first data blocks. For example, the representative value may be the average of the luminance compensation values included in the first data block, but the scope of the inventive concept is not limited thereto.

[0054] Referring back Figure 2 and Figure 3 , the inter - plane flow data generator 136 receives the in - plane data LP from the in - plane data generator 135, receives the control signal CTR A from the controller 132, and generates the inter - plane flow data LS based on the in - plane data LP. In some embodiments, the inter - plane flow data generator 136 may generate the inter - plane flow data LS based on the in - plane data LP. That is, the inter - plane flow data generator 136 may generate one of the inter - plane flow data LS based on the data blocks included in the in - plane data LP and arranged at the same positions within the in - plane data LP. In some embodiments, the inter - plane flow data generator 136 may generate the first inter - plane flow data among the inter - plane flow data based on the selected second data blocks among the plurality of second data blocks generated by dividing the in - plane data into a predetermined size. The selected second data blocks may be included in different in - plane data and may be arranged at a first position within the in - plane data. Here, each of the second data blocks may have a second size.

[0055] Figure 6 is a conceptual diagram showing the concept of inter - plane flow data in one example.

[0056] In Figure 6 , the in - plane data LP and the corresponding inter - plane flow data LS are shown. Here, the in - plane data LP includes the first to fourth in - plane data LP[1] to LP[4], and the inter - plane flow data LS includes the first to sixth inter - plane flow data LS[1] to LS[6]. Figure 6 The in - plane data LP shown in Figure 5 is the same as the in - plane data LP shown in

[0057] Referring Figure 6, one of the inter-plane flow data LS[1] to LS[6] in the inter-plane flow data LS can be generated based on the second data block. Here, the second data block can be included in the first to fourth in-plane data LP[1] to LP[4], and can be arranged at the same position within the first to fourth in-plane data LP[1] to LP[4]. That is, a plurality of second data blocks can be generated by dividing the first to fourth in-plane data LP[1] to LP[4]. Each of the second data blocks can have a second size, and information about the second size can be included in the control signal CTR A.

[0058] For example, the first inter-plane flow data LS[1] can be generated based on the selected second data blocks PmP11, PmP12, PmP21, and PmP22 among the plurality of second data blocks, where "m" is a natural number greater than 0 and less than 5. The selected second data blocks can be included in different in-plane data and are arranged at the first position within the in-plane data. In a similar manner, the second inter-plane flow data LS[2] can be generated based on the selected second data blocks PmP12, PmP13, PmP22, and PmP23, the third inter-plane flow data LS[3] can be generated based on the selected second data blocks PmP13, PmP14, PmP23, and PmP24, and the same applies to Figure 6 the fourth, fifth, and sixth inter-plane flow data LS[4], LS[5], and LS[6] in the working example.

[0059] The order in which each of the inter-plane flow data LS is generated can be related to the writing order for storage or the reading order for retrieving the inter-plane flow data LS from the memory. Alternatively or additionally, the order in which each of the described inter-plane flow data LS is generated can be related to the order in which the luminance compensation data is used during decoding, rearrangement, and / or interpolation of the inter-plane flow data LS. Alternatively or additionally, the order in which the inter-plane flow data LS is generated can be related to the display scanning method of the display device included in the second luminance compensation system 200 (as will be described in Figure 8 more detail below).

[0060] In some embodiments, the inter-plane flow value included in each of the inter-plane flow data LS can be generated as a representative value of the selected second data block. For example, the representative value can be generated by applying an encoding algorithm to the selected data block. The encoding algorithm can be one of the advanced encryption standard (AES) algorithm and the lightweight encryption algorithm (LEA), but the scope of the inventive concept is not limited thereto.

[0061] Reference return Figure 2 and Figure 3 As shown in Figure 3 and , the controller 132 may control the inter-plane flow data generator 136 and the first luminance compensation data memory 137 to sequentially store the inter-plane flow data LS in the first luminance compensation data memory 137.

[0062] Figure 7A and Figure 7B are corresponding conceptual diagrams showing an example method of storing inter-plane flow data.

[0063] In Figure 7A and Figure 7B the inter-plane flow data LS of the first luminance compensation data memory 137 and the physical spaces PS1 and PS2 are shown.

[0064] Here, it is assumed that the controller 132 stores the inter-plane flow data LS in the first luminance compensation data memory 137 according to the order in which the inter-plane flow data LS is generated (e.g., LS[1]->LS[2]->…->LS[6]).

[0065] Reference Figure 7A As shown in Figure 7A , the inter-plane flow data LS is sequentially stored in the direction from the first address to the second address of the first luminance compensation data memory 137. In some embodiments, the first address may be higher than the second address. In some embodiments, the controller 132 may generate information representing a start address SADDR1 and an offset OFS1, and store the information in a special function register included in the first luminance compensation data memory 137. The start address SADDR1 may represent the address at which a plurality of inter-plane flow data starts to be stored in the first luminance compensation data memory 137, and the offset OFS1 may represent the size of each inter-plane flow data.

[0066] Reference Figure 7B As shown in Figure 7B , the inter-plane flow data LS is sequentially stored in the direction from the third address to the fourth address of the first luminance compensation data memory 137. In some embodiments, the third address may be lower than the fourth address. In some embodiments, the controller 132 may generate information representing a start address SADDR2 and an offset OFS2, and store the information in a special function register included in the first luminance compensation data memory 137. In this case, the offset OFS2 has the same size as the offset OFS1, but may have a different sign.

[0067] Figure 8 is a block diagram showing a second luminance compensation system 200 according to an embodiment of the inventive concept.

[0068] Reference Figure 8, the second brightness compensation system 200 generally includes a host processor 300 and a display device 210, where the display device 210 includes a display panel 230 and a display driver IC 250.

[0069] The second brightness compensation system 200 can be a display system that receives input image data IMG and generates output image data for displaying an image on the display panel 230.

[0070] The host processor 300 controls the overall operation of the second brightness compensation system 200. In some embodiments, the host processor 300 can be implemented as an application processor (AP), a baseband processor (BBP), a micro-processing unit (MPU), etc.

[0071] The host processor 300 provides the input image data IMG, the clock signal CLK, and the control signal CTRB required for the operation of the display device 210. In some embodiments, the input image data IMG can include RGB pixel values and have a defined resolution (e.g., a specific W*H).

[0072] The control signal CTRB can include a command signal, a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal. In some embodiments, the input image data IMG and the control signal CTRB can be provided to the display driver 250 as one or more data packets. The command signal can include signals for controlling image processing performed by the display driver 250, image information, and display environment setting information.

[0073] In some embodiments, the signals that generally control image processing can include signals for controlling the second brightness compensation circuit (LCC2) 270 to compensate the input image data IMG during the generation of the output data. In some embodiments, the image information can be information about the input image data IMG input to the display driver 250 and can include the resolution of each of the input image data IMG. In some embodiments, the display environment setting information can include panel information, a brightness setting value, etc.

[0074] The display driver 250 drives the display panel 230 based on the input image data IMG and in response to the control signal CTRB received from the host processor 300. In this regard, the display driver 250 converts the digital input image data IMG into a corresponding analog signal and drives the display panel 230 with the analog signal. The display driver 250 includes a second brightness compensation circuit 270. The second brightness compensation circuit 270 includes a second brightness compensation data memory (LCM2) 280.

[0075] Accordingly, the second luminance compensation circuit 270 can generate output image data for displaying an image by compensating input image data IMG using luminance compensation data, and then provide the compensated output image data to the display panel 230.

[0076] The second luminance compensation data memory 280 can be used to store, for example, luminance compensation data generated by Figure 2 and Figure 3 the first luminance compensation circuit 110 of Figure 7A and Figure 7B . That is, the luminance compensation data can be data that has been converted into inter-plane flow data LS using one of the methods shown in

[0077] and stored in the first luminance compensation data memory 137.

[0078] In some embodiments, the first luminance compensation data memory 137 and the second luminance compensation data memory 280 can be the same. In this case, the start addresses SADDR1 and SADDR2 and the offsets OFS1 and OFS2 can be stored in a specified area of the first luminance compensation data memory 137.

[0079] When the manufacturers of the display panel 230 and the display device 210 are different in some embodiments, the first luminance compensation data memory 137 can be transferred from the manufacturer of the display panel 230 to the manufacturer of the display device 270. In this case, the manufacturer of the display device 270 can copy the content of the first luminance compensation data memory 137 and store the content in the second luminance compensation data memory 280.

[0080] The display panel 230 is a panel capable of displaying an image, and can include an LCD panel (liquid crystal display panel), an electrophoretic display panel, an OLED panel (organic light emitting diode panel), an LED panel (light emitting diode panel), an inorganic EL panel (electroluminescent display panel), an FED panel (field emission display panel), an SED panel (surface conduction electron emission display panel), a PDP (plasma display panel), and a CRT (cathode ray tube) display panel.

[0080] The display system 200 can be implemented as a component of a mobile phone, a smart phone, a tablet personal computer, a personal digital assistant (PDA), a wearable electronic device, or a portable multimedia player (PMP) having an image display function. In addition, the display system 200 can be implemented with various electronic devices, such as a TV, a notebook computer, a desktop PC, and a navigation device.

[0081] Figure 9 is a block diagram of the display device 210 further shown in one example Figure 8 .

[0082] Reference Figure 9 , the display device 210 includes a display panel 230 and a display driver 250 that drives the display panel 230. The display panel 230 includes a plurality of pixel rows 231.

[0083] The display driver 250 includes a data driver 251, a scan driver 255, a timing controller 253, a power supply unit 257, a second luminance compensation circuit (LCC2) 270, and a gamma circuit 259.

[0084] The display panel 230 can be connected to the data driver 251 of the display driver 250 through data lines and can be connected to the scan driver 255 of the display driver 250 through scan lines. The display panel 230 can include pixel rows 231. The display panel 230 can include pixels PX arranged in a matrix of rows and columns. One pixel row 231 refers to a row of pixels PX that can be connected to the same scan line.

[0085] In some embodiments, each pixel PX included in the display panel 230 can have various configurations according to (for example) a driving method. For example, according to the method of representing gray levels, the driving method can be classified into analog driving or digital driving. The luminance compensation method according to an embodiment of the inventive concept can be applied to both analog driving and digital driving.

[0086] The data driver 251 can apply data signals to the display panel 230 through data lines, and the scan driver 255 can apply scan signals to the display panel 230 through scan lines. The timing controller 253 can control the operation of the display device 210. The timing controller 253 can control the operation of the display device 210 by providing predetermined control signals to the data driver 251 and the scan driver 255.

[0087] In some embodiments, the data driver 251, the scan driver 255, and the timing controller 253 can be implemented as a single integrated circuit (IC). In some embodiments, the data driver 251, the scan driver 255, and the timing controller 253 can be implemented using two or more ICs. A driving module in which at least the timing controller 253 and the data driver 251 are integrally formed can be referred to as a timing controller embedded data driver (TED).

[0088] The timing controller 253 receives from a host device (e.g., Figure 8The host processor 300) receives a plurality of input image data IMG and control signals CTRB. For example, the input image data IMG may include red image data R, green image data G, and blue image data B. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data.

[0089] The control signal CTRB may include a main clock signal and a data enable signal. In addition, the control signal CTRB may further include a vertical synchronization signal and a horizontal synchronization signal.

[0090] The power supply unit 257 may supply a power supply voltage and a ground voltage to the display panel 230. In some embodiments, the power supply voltage may correspond to a high power supply voltage and the ground voltage may correspond to a low power supply voltage. In addition, the power supply unit 257 may supply a regulator voltage to the gamma circuit 259. The gamma circuit 259 may generate a plurality of gamma reference voltages based on the regulator voltage. For example, the regulator voltage may be a power supply voltage or a voltage generated by a separate regulator voltage based on the power supply voltage.

[0091] The second brightness compensation circuit 270 may be used to compensate the input image data IMG based on brightness compensation data generated according to a brightness compensation method according to an embodiment of the inventive concept. Accordingly, the second brightness compensation circuit 270 may generate compensated image data CIMG from the input image data IMG. The brightness compensation data may be stored in the second brightness compensation data memory 280.

[0092] In Figure 9 the second brightness compensation circuit 270 is shown as being disposed between the data driver 251 and the timing controller 253, but the scope of the inventive concept is not limited thereto. In some embodiments, the second brightness compensation circuit 270 may be included in the timing controller 253 or may be disposed in front of the timing controller 253.

[0093] Figure 10 and Figure 11 is a Figure 8 and Figure 9 corresponding block diagram showing examples of the second brightness compensation circuits 270 and 270a.

[0094] Refer to Figure 8 、 Figure 9 and Figure 10The second brightness compensation circuit 270 may include a compensated image data generator (CDG) 272, a second brightness compensation data provider 274, and a second brightness compensation data memory (LCM2) 280. The second brightness compensation data provider 274 includes an in-plane data generator (LPG) 276 and a brightness compensation data generator (LCG) 278.

[0095] The second brightness compensation circuit 270 performs the same operation as that of the timing controller 253 based on the control signal CTRB received from the timing controller 253. Figure 3 The second brightness compensation circuit 270 performs a function opposite to that of the first brightness compensation circuit 110. That is, the second brightness compensation circuit 270 generates the brightness compensation data LC based on the inter-plane stream data LS.

[0096] The host processor 300 controls the overall operation of the components 272, 274, 276, 278 and 280 of the second brightness compensation circuit 270 through the timing controller 253. In some embodiments, the host processor 300 may control the components 272, 274, 276, 278 and 280 of the brightness compensation circuit 270 using the control signal CTRB.

[0097] The in-plane data generator 276 sequentially reads the inter-plane stream data LS from the second brightness compensation data memory 280. The in-plane data generator 276 generates the in-plane data by generating a data block based on the inter-plane stream data LS. The data block may be included in each of the in-plane data and may be arranged at the same position in the in-plane data. The in-plane data generator 276 provides the in-plane data LP to the brightness compensation data generator 278.

[0098] The brightness compensation data generator 278 receives the in-plane data LP from the in-plane data generator 276. The brightness compensation data generator 278 generates brightness compensation data LC based on the in-plane data LP. The compensated image data generator 272 generates output image data CIMG for displaying an image by compensating the input image data IMG based on the brightness compensation data LC.

[0099] refer to Figure 8 , Figure 9 and Figure 11 The second brightness compensation circuit 270a includes a compensated image data generator 272, a second brightness compensation data provider 274a and a second brightness compensation data memory 280a. The second brightness compensation data provider 274a includes an in-plane data generator 276a and a brightness compensation data generator 278a. The in-plane data generator 276a includes a demultiplexer (DEMUX) 276-1 and a plurality of decoders. The number of decoders may be based on the above reference Figure 2 The gray level described is determined by the number of brightness compensation data LC corresponding to the gray level described.

[0100] In some embodiments, the number of decoders may be less than the number of luminance compensation data LC. For example, as referred to above Figure 4 when the luminance compensation data LC includes first through fourth luminance compensation data LC[1] to LC[4], the number of decoders may be only two or half the number of luminance compensation data LC. Hereinafter, an embodiment in which the number of decoders is 2 is assumed when the number of luminance compensation data LC is 4. That is, it is assumed that only the first decoder 277-1 and the second decoder 277-2 are used as decoders to implement the in-plane data generator 276a. However, the scope of the inventive concept is not limited thereto.

[0101] The luminance compensation data generator 278a may include a line memory 278-1, and the second luminance compensation data memory 280a may include a special function register (SFR) 280-1.

[0102] The second luminance compensation data memory 280a may be used to store the inter-plane stream data LS. The special function register 280-1 stores the start addresses SADDR1 and SADDR2 and the offsets OFS1 and OFS2 referred to above Figure 7A and Figure 7B The in-plane data generator 276a sequentially reads the inter-plane stream data LS from the second luminance compensation data memory 280a. In some embodiments, when power is applied (e.g., turned on) to the second luminance compensation system 200, the inter-plane stream data may be sequentially read based on the start addresses SADDR1 and SADDR2 and the offsets OFS1 and OFS2 stored in the special function register 280-1 and in response to a control signal CTRB received from the timing controller 253.

[0103] The demultiplexer 276-1 may be used to distribute the read inter-plane stream data LS between the first decoder 277-1 and the second decoder 277-2. For example, assuming that the inter-plane stream data LS is sequentially read from inter-plane stream data LS[1] to inter-plane stream data LS[6], the demultiplexer 276-1 may distribute the first read inter-plane stream data LS[1] to the first decoder 277-1, and then distribute the second read inter-plane stream data LS[2] to the second decoder 277-2, and so on until the inter-plane stream data LS[3] to LS[6] have been distributed between the first decoder 277-2 and the second decoder 277-2.

[0104] In this way, for example, the first decoder 277-1 and the second decoder 277-2 may be used to respectively decode the distributed inter-plane stream data LS[1] to LS[6] to generate corresponding in-plane data LP[1] to LP[4].

[0105] The luminance compensation data generator 278 a receives the in-plane data LP from the first decoder 277 - 1 and the second decoder 277 - 2 and may rearrange and / or interpolate the in-plane data LP to generate luminance compensation data LC.

[0106] The brightness compensation data generator 278a communicates the brightness compensation data LC to the compensated image data generator 272. In some embodiments, the brightness compensation data generator 278a may temporarily store a portion of the in-plane data LP1 and LP2 in the line memory 278-1.

[0107] Therefore, the compensated image data generator 272 receives the input image data IMG from the timing controller 253 and receives the brightness compensation data LC from the brightness compensation data generator 278a. Therefore, the compensated image data generator 272 can generate the compensated image data CIMG by appropriately compensating the input image data IMG using the brightness compensation data LC. The compensated image data generator 272 can then communicate the compensated image data CIMG to the data driver 251.

[0108] Figure 12A and Figure 13A It is shown Figure 11 A conceptual diagram of an example of operations of the first decoder 277 - 1 and the second decoder 277 - 2 , and Figure 12B and Figure 13B It is further shown that Figure 11 1 and 2. A timing diagram showing the operation of the first decoder 277-1 and the second decoder 277-2.

[0109] exist Figure 12A In FIG. 1 , first exemplary input image data IMG is shown and is assumed to include pixels D(x)(y), D(x)(y+1), D(x)(y+2), and D(x)(y+3). Figure 12B In FIG. 1 , the clock signal DCLK, the validity signal IV1 and the in-plane data LP1 and LP2 are shown.

[0110] In order to compensate each of the pixels D(x)(y), D(x)(y+1), D(x)(y+2), and D(x)(y+3), the brightness compensation data LC is required. Therefore, the brightness compensation data LC may be generated based on the in-plane data LP. Figure 12BIn , the indication of the pixels D(x)(y), D(x)(y+1), D(x)(y+2), and D(x)(y+3) included in the input image data IMG shown on each of the in-plane data LP1 and LP2 represents the in-plane data output from the first decoder 277-1 and the second decoder 277-2 for compensating each of the pixels D(x)(y), D(x)(y+1), D(x)(y+2), and D(x)(y+3).

[0111] Reference Figure 11 、 Figure 12A and Figure 12B , the in-plane data LP1 and LP2 corresponding to the pixels D(x)(y), D(x)(y+1), D(x)(y+2), and D(x)(y+3) can be output from each of the first decoder 277-1 and the second decoder 277-2 in the (multiple) time periods corresponding to the clock signals C1 to C8. In some embodiments, the in-plane data corresponding to the pixels D(x)(y) and D(x)(y+1) can be output from each of the first decoder 277-1 and the second decoder 277-2 in the time periods corresponding to the clock signals C1 and C2. The in-plane data corresponding to the pixels D(x)(y+2) and D(x)(y+3) can be output from each of the first decoder 277-1 and the second decoder 277-2 in the time periods corresponding to the clock signals C4 and C5. The in-plane data corresponding to the pixels D(x)(y+4) and D(x)(y+5) can be output from each of the first decoder 277-1 and the second decoder 277-2 in the time periods corresponding to the clock signals C7 and C8. In some embodiments, when the validity signal IV1 transitions to a logic low level in the time periods corresponding to the clock signals C3 and C6, the outputs of the first decoder 277-1 and the second decoder 277-2 can be ignored.

[0112] In Figure 13AIn FIG., a second exemplary input image data IMG is shown and it is assumed that it includes pixels D(x-1)(y-1), D(x-1)(y), D(x-1)(y+1), D(x-1)(y+2), D(x)(y), D(x)(y+1), D(x)(y+2) and D(x)(y+3). It is further assumed that the luminance compensation data LC corresponding to the pixels D(x)(y) and D(x)(y+1) needs to be generated from the pixels D(x-1)(y-1), D(x-1)(y), D(x-1)(y+1) and D(x-1)(y+2) of the previous row. In some embodiments, the luminance compensation data LC corresponding to the multiple pixels D(x-1)(y-1), D(x-1)(y), D(x-1)(y+1) and D(x-1)(y+2) may be temporarily stored in the line memory 278-1.

[0113] In Figure 13B FIG., a clock signal DCLK, validity signals IV1 and IV2, line memory data LPU1, LPU2, LPU3 and LPU4 corresponding to the multiple pixels D(x-1)(y-1), D(x-1)(y), D(x-1)(y+1), D(x-1)(y+2), D(x)(y), D(x)(y+1), D(x)(y+2) and D(x)(y+3), and in-plane data LP1 and LP2 are shown.

[0114] Referring to Figure 11 , Figure 13A and Figure 13B, the line memory data LPU1, LPU2, LPU3, and LPU4, and the in-plane data LP1 and LP2 corresponding to the pixels D(x-1)(y-1), D(x-1)(y), D(x-1)(y+1), D(x-1)(y+2), D(x)(y), D(x)(y+1), D(x)(y+2), and D(x)(y+3) can be output from each of the first decoder 277-1 and the second decoder 277-2 during time periods corresponding to the clock signals C1 to C8. In some embodiments, the in-plane data corresponding to the pixels D(x-1)(y-1), D(x-1)(y), D(x-1)(y+1), and D(x-1)(y+2) can be output from the line memory 278-1 during the time periods corresponding to the clock signals C1 and C2. The in-plane data corresponding to the pixels D(x)(y) and D(x)(y+1) can be output from each of the first decoder 277-2 and the second decoder 277-2 during the time periods corresponding to the clock signals C3 and C4. The in-plane data corresponding to the pixels D(x-1)(y+1), D(x-1)(y+2), D(x-1)(y+3), and D(x-1)(y+4) can be output from the line memory 278-1 during the time periods corresponding to the clock signals C4 and C5. The in-plane data corresponding to the pixels D(x)(y+2) and D(x)(y+3) can be output from each of the first decoder 277-2 and the second decoder 277-2 during the time periods corresponding to the clock signals C6 and C7. The in-plane data corresponding to the pixels D(x-1)(y+3), D(x-1)(y+4), D(x-1)(y+5), and D(x-1)(y+6) can be output from the line memory 278-1 during the time periods corresponding to the clock signals C7 and C8. In some embodiments, when the validity signal IV2 transitions to a logic low level during the time periods corresponding to the clock signals C3 and C6, the output of the line memory 278-1 can be ignored. In some embodiments, when the validity signal IV1 transitions to a logic low level during the time periods corresponding to the clock signals C2, C5, and C8, the outputs of the first decoder 277-1 and the second decoder 277-2 can be ignored.

[0115] Figure 14 is a flowchart outlining an example of sequentially storing inter-plane stream data in a memory, and Figure 15 is, in another example, a block diagram of a first luminance compensation circuit 110a similar to Figure 3 the luminance compensation circuit 110 of

[0116] Reference Figure 14 , receives display scan method information (S6100) indicating a scan method for a display device. As referenced aboveFigure 6 As described, for example, the display scan method information may be related to (or defined in whole or in part by) the generation order, storage order, read order, generation order of the luminance compensation data, generation order of the inter-plane flow data, etc. Thereafter, the inter-plane flow data may be sequentially stored in the memory based on the display scan method information (S6300).

[0117] Common reference Figure 2 、 Figure 3 、 Figure 14 and Figure 15 , Figure 15 The first luminance compensation circuit 110a of Figure 15 may include a luminance compensation data generator (LCG) 131, a controller 132a, a test image data provider (TDP) 133, a luminance compensation data processor 134a, and a first luminance compensation data memory (LCM1) 137. The luminance compensation data processor 134a may include an in-plane data generator (LPG) 135 and an inter-plane flow data generator (LSG) 136a. Except that the controller 132a and the inter-plane flow data generator 136a further receive the display scan method information DSCI, Figure 15 the first luminance compensation circuit 110a of Figure 15 may perform (a plurality of) functions similar to those described previously for the first luminance compensation circuit 110 of Figure 3 . Figure 3

[0118] The controller 132a may be used to control the overall operation of the components 131, 133, 134a, 135, 136a, and 137 of the first luminance compensation circuit 110a in Figure 15 . Here, the controller 132a further receives the display scan method information DSCI from an external source. The display scan method information DSCI may include information identifying a method of generating the compensated image data CIMG by compensating the input image data IMG of Figure 9 . In some embodiments, the display scan method information DSCI may include information about one of the progressive scan type and the interlaced scan type as a raster scan scheme, but the scope of the inventive concept is not limited thereto. In some embodiments, the display scan method information DSCI may include information about a method of displaying a plurality of compensated image data CIMG on the display panel in various ways such as a continuous raster type, a diagonal scan type, and a block scan type. Figure 15 Figure 9

[0119] ​​​The controller 132a may control the inter-plane flow data generator 136a and the first luminance compensation data memory 137 to sequentially store the inter-plane flow data LS in the first luminance compensation data memory LCM1. In some embodiments, the controller 132a may sequentially store the inter-plane flow data LS in the first luminance compensation data memory LCM1 based on the display scan method information DSCI.

[0120] Figure 16 is a block diagram of a display mobile device including a second luminance compensation circuit according to an embodiment of the inventive concept.

[0121] Reference Figure 16 , the display mobile device 700 may include a system-on-chip 710 and functional modules 740, 750, 760, and 770. The display mobile device 700 may further include a memory device 720, a storage device 730, and a power management device 780.

[0122] The system-on-chip 710 may control the overall operations of the display mobile device 700 and its constituent components (e.g., the memory device 720, the storage device 730, and the functional modules 740, 750, 760, and 770). In some embodiments, the system-on-chip 710 may be an application processor (AP) provided in the display mobile device 700.

[0123] The system-on-chip 710 may include a central processing unit 712 and a power management system 714. The memory device 720 and the storage device 730 may store data required for the operations of the display mobile device 700. For example, the memory device 720 may correspond to a volatile memory device, such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc., and the storage device 730 may correspond to a non-volatile memory device, such as an EPROM (erasable programmable read-only memory) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a NFGM device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, or a ferroelectric random access memory (FRAM) device. In some embodiments, the storage device 730 may further include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.

[0124] The functional modules 740, 750, 760, and 770 can respectively perform various functions of the display mobile device 700. For example, the display mobile device 700 may include a communication module 740 for performing communication functions (e.g., a Code Division Multiple Access (CDMA) module, a Long Term Evolution (LTE) module, a Radio Frequency (RF) module, an Ultra-Wideband (UWB) module, a Wireless Local Area Network (WLAN) module, a Worldwide Interoperability for Microwave Access (WIMAX) module, etc.), a camera module 750 for performing a camera function, a display module 760 for performing a display function, a touch panel module 770 for performing a touch input function, etc. In some embodiments, the display mobile device 700 may further include a Global Positioning System (GPS) module, a microphone module, a speaker module, a gyroscope module, etc. However, those skilled in the art will recognize that many different functional modules 740, 750, 760, and 770 may be included in the display mobile device 700.

[0125] The power management device 780 can respectively provide driving voltages to the system-on-chip 710, the memory device 720, the storage device 730, and the functional modules 740, 750, 760, and 770.

[0126] According to an embodiment of the inventive concept, the display module 760 may include a second luminance compensation circuit (LCC2), such as the second luminance compensation circuit (e.g., 270 and 270A) described with respect to Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 12B , Figure 13A and Figure 13B as described above.

[0127] As described above, a method of luminance compensation, a luminance compensation system, and a display system performing luminance compensation may store luminance compensation data and data differently converted from such data in a memory. That is, the luminance compensation data may be converted into in-plane data, and the obtained in-plane data may be converted into inter-plane stream data that is sequentially stored in the memory. In addition, a luminance compensation method, a luminance compensation system, and a display system according to an embodiment of the inventive concept may sequentially read and decode the inter-plane stream data in the stored order to read the luminance compensation data. In addition, by reducing the number of decoders required during the reading process, the hardware cost and hardware complexity associated with the reading process may be reduced.

[0128] The foregoing is a description of embodiments of the inventive concept. Although certain embodiments have been described herein, those skilled in the art will readily appreciate that many modifications may be made to the illustrated embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Accordingly, such modifications are included within the scope of the inventive concept as defined by the appended claims.

Claims

1. A brightness compensation method, comprising: generating brightness compensation data based on test image data, each of the test image data corresponding to a gray level, and each of the brightness compensation data including a compensation value corresponding to a gray level; generating in-plane data based on the brightness compensation data, one of the in-plane data being generated based on one of the brightness compensation data; generating inter-plane flow data based on the in-plane data, a first inter-plane flow data among the inter-plane flow data being generated based on data blocks that are included in different in-plane data and are arranged at the same positions within the different in-plane data; and sequentially storing the inter-plane flow data in a memory.

2. The method according to claim 1, wherein the generation of the in-plane data includes: generating first in-plane data among the in-plane data based on a plurality of first data blocks generated by dividing first brightness compensation data among the brightness compensation data, and each of the plurality of first data blocks has a first size.

3. The method according to claim 2, wherein one of the in-plane data included in the first in-plane data includes an average value of at least a part of the plurality of first data blocks.

4. The method according to claim 1, wherein the generation of the inter-plane flow data includes: generating the first inter-plane flow data based on selected data blocks among the data blocks generated by dividing the in-plane data, the selected data blocks are included in the different in-plane data and are arranged at the same positions within the different in-plane data, and each of the data blocks has the same size.

5. The method according to claim 4, wherein the first inter-plane flow data is generated by encoding the selected data blocks.

6. The method according to claim 5, wherein a starting address of the memory storing the inter-plane flow data and an offset representing the size of each of the inter-plane flow data are stored in a special function register included in the memory.

7. The method according to claim 1, wherein the inter-plane flow data is sequentially stored in a direction from a first address to a second address in the memory.

8. The method according to claim 1, wherein sequentially storing the inter-plane flow data in the memory includes: receiving display scan method information indicating a scan method for a display device; and sequentially storing the inter-plane flow data in the memory based on the display scan method information.

9. The method according to claim 8, wherein the display scan method information includes one of a progressive scan type and an interlaced scan type.

10. The method according to claim 1, further comprising: sequentially reading the inter-plane flow data from the memory; Generating second in-plane data by generating the data blocks based on the read inter-plane flow data, wherein each of the data blocks is included in each of the second in-plane data and is arranged at the same position within the second in-plane data; Generating second luminance compensation data based on the second in-plane data; and Generating output image data for displaying an image by compensating input image data based on the second luminance compensation data.

11. A luminance compensation system, comprising: a circuit configured to provide test image data to a display panel, wherein each of the test image data corresponds to a gray level; an image capture device configured to generate luminance data by capturing a panel image displayed on the display panel in response to the test image data; and a luminance compensation circuit configured to: generate luminance compensation data based on the luminance data, wherein each of the luminance compensation data includes a compensation value corresponding to a gray level, generate in-plane data based on the luminance compensation data, generate first inter-plane flow data among a plurality of inter-plane flow data based on data blocks included in different in-plane data and arranged at the same position within each of the different in-plane data, and sequentially store the inter-plane flow data in a memory.

12. The luminance compensation system according to claim 11, wherein, the luminance compensation circuit is further configured to: generate a plurality of first data blocks by dividing first luminance compensation data among the luminance compensation data into a first size, and generate first in-plane data among the in-plane data based on the plurality of first data blocks.

13. The luminance compensation system according to claim 11, wherein, the luminance compensation circuit is further configured to: generate the data blocks by dividing the in-plane data into the same size, and generate the first inter-plane flow data based on the data blocks included in the different in-plane data and arranged at the same position.

14. The luminance compensation system according to claim 11, wherein, the luminance compensation circuit is further configured to sequentially store the inter-plane flow data in a direction from a lower address to a higher address of the memory.

15. The luminance compensation system according to claim 14, wherein, the memory includes a special function register, and the luminance compensation circuit is further configured to store information indicating a start address of the memory for the inter-plane flow data and an offset indicating a size of each inter-plane flow data in the special function register.

16. A display system, comprising: a display device including a luminance compensation circuit; and a host processor configured to control the display device, wherein the luminance compensation circuit includes: a luminance compensation data memory configured to store inter-plane flow data; An in-plane data generator, configured to sequentially read the inter-plane stream data and generate data blocks based on the inter-plane stream data to generate a plurality of in-plane data, wherein the data blocks are included in each of different in-plane data among the plurality of in-plane data and are arranged at the same position within each of different in-plane data among the plurality of in-plane data; A luminance compensation data generator, configured to generate luminance compensation data based on the plurality of in-plane data; and A luminance compensation image data generator, configured to generate output image data by compensating input image data based on the luminance compensation data.

17. The display system according to claim 16, wherein, the in-plane data generator includes a demultiplexer and a plurality of decoders, and the number of the plurality of decoders is half of the number of the luminance compensation data.

18. The display system according to claim 17, wherein, the demultiplexer distributes the inter-plane stream data among the plurality of decoders.

19. The display system according to claim 18, wherein, the plurality of decoders respectively decode the inter-plane stream data distributed by the demultiplexer to generate the in-plane data.

20. The display system according to claim 16, wherein, the luminance compensation data memory includes a special function register that stores a starting address of the luminance compensation data memory for the inter-plane stream data and an offset indicating the size of each of the inter-plane stream data.

Images