A semiconductor device and a method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, including a substrate, a stacked layer located on the substrate, the stacked layer sequentially including a first gate layer, a first insulating layer, a second gate layer, and a second insulating layer from top to bottom, a first channel structure longitudinally penetrating the first gate layer and the first insulating layer perpendicular to the substrate, and a second channel structure longitudinally penetrating the second gate layer. The top of the second channel structure is connected to the bottom of the first channel structure, and the cross-sectional area of the second channel structure in a cross-section perpendicular to the longitudinal direction is larger than the cross-sectional area of the first channel structure in a cross-section perpendicular to the longitudinal direction. Since the cross-sectional area of the first channel structure is small, the gating rate of the first gate layer is faster, and thus the gate control ability of the semiconductor device can be improved. At the same time, since the cross-sectional area of the second channel structure is large, the second channel structure can support a higher hole storage capacity, and thus the storage ability of the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention generally relates to electronic devices, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the continuous growth of the semiconductor market demand, semiconductor memory technologies have developed rapidly. In particular, the dynamic random access memory (DRAM) technology has witnessed a rapid development and occupies the most important position in the memory market. A common DRAM cell consists of a transistor and a capacitor to form a 1T1C structure, and the logical state is distinguished by whether there is charge stored on the capacitor.

[0003] Currently, the size scaling of traditional 1T1C DRAM has approached the process limit. For example, in small-size nodes, the capacitor manufacturing process is more complex, and the leakage becomes more significant, resulting in a reduced retention time, an increased static power consumption, a degraded operating voltage margin, etc.

[0004] How to improve the DRAM, such as the gating speed and storage capacity of the dynamic flash memory (DFM), is an urgent problem to be solved currently. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, aiming to improve the gate control ability and hole storage ability of the semiconductor device.

[0006] On the one hand, the present invention provides a semiconductor device, including:

[0007] A substrate;

[0008] A stacked layer located on the substrate, the stacked layer sequentially includes a first gate layer, a first insulating layer, a second gate layer, and a second insulating layer from top to bottom;

[0009] A first channel structure longitudinally penetrating the first gate layer and the first insulating layer perpendicular to the substrate;

[0010] A second channel structure longitudinally penetrating the second gate layer, the top of the second channel structure is connected to the bottom of the first channel structure, and the cross-sectional area of the second channel structure in a cross-section perpendicular to the longitudinal direction is larger than the cross-sectional area of the first channel structure in a cross-section perpendicular to the longitudinal direction.

[0011] Further preferably, the thickness of the second gate layer in the longitudinal direction is greater than the thickness of the first gate layer in the longitudinal direction.

[0012] Further preferably, the semiconductor device further includes:

[0013] A first gate insulating layer located between the outer sidewall of the first channel structure and the first gate layer;

[0014] A second gate insulating layer located between the outer sidewall of the second channel structure and the second gate layer.

[0015] Further preferably, the semiconductor device further includes:

[0016] A source electrode located between the second channel structure and the substrate;

[0017] A drain electrode located on top of the first channel structure.

[0018] Further preferably, the source electrode and the drain electrode are made of N-type single crystal silicon.

[0019] Further preferably, the material of the first gate layer includes polysilicon, and the first gate layer is connected to a word line, and the second gate layer is connected to a plate line and is applied with a fixed voltage.

[0020] Further preferably, the first channel structure and the second channel structure are cylindrical, and the diameter of the second channel structure is larger than the diameter of the first channel structure.

[0021] On the other hand, the present invention provides a method for manufacturing a semiconductor device, including:

[0022] Providing a substrate;

[0023] Forming a stacked layer on the substrate, the stacked layer sequentially includes a first gate layer, a first insulating layer, a second gate layer, and a second insulating layer from top to bottom;

[0024] Forming a first channel structure penetrating through the first gate layer and the first insulating layer along a longitudinal direction perpendicular to the substrate;

[0025] Forming a second channel structure penetrating through the second gate layer along the longitudinal direction, the top of the second channel structure is connected to the bottom of the first channel structure, and the cross-sectional area of the second channel structure in a cross-section perpendicular to the longitudinal direction is larger than the cross-sectional area of the first channel structure in a cross-section perpendicular to the longitudinal direction.

[0026] Further preferably, the step of forming the stacked layer on the substrate includes:

[0027] Forming the second insulating layer on the substrate;

[0028] Forming the second gate layer on the second insulating layer;

[0029] The first insulating layer is formed on the second gate layer;

[0030] The first gate layer is formed on the first insulating layer, and the thickness of the second gate layer in the longitudinal direction is greater than the thickness of the first gate layer in the longitudinal direction.

[0031] Further preferably, the step of forming the first channel structure penetrating the first gate layer and the first insulating layer along the longitudinal direction perpendicular to the substrate includes:

[0032] Forming a first channel hole penetrating the first gate layer and the first insulating layer along the longitudinal direction;

[0033] Filling a channel material in the first channel hole to form the first channel structure.

[0034] Further preferably, the step of forming the second channel structure penetrating the second gate layer along the longitudinal direction includes:

[0035] Before filling the channel material, forming a first through hole penetrating the second gate layer along the longitudinal direction, and the first through hole is communicated with the first channel hole;

[0036] Etching the second gate layer based on the first through hole to form a second channel hole penetrating the second gate layer, and the cross-sectional area of the second channel hole in the cross-section perpendicular to the longitudinal direction is greater than the cross-sectional area of the first channel hole in the cross-section perpendicular to the longitudinal direction;

[0037] Filling the channel material in the first channel hole and the second channel hole to form a first channel structure and the second channel structure located at the bottom of the first channel structure.

[0038] Further preferably, before the step of filling the channel material in the first channel hole and the second channel hole, the method for manufacturing the semiconductor device further includes:

[0039] Forming a first gate insulating layer located between the first channel hole and the first gate layer;

[0040] Forming a second gate insulating layer located between the second channel hole and the second gate layer.

[0041] Further preferably, the step of forming the first gate insulating layer located between the first channel hole and the first gate layer includes:

[0042] Partially oxidizing the first gate layer on the sidewall of the first channel hole to form a first gate insulating layer located between the first channel hole and the first gate layer;

[0043] The step of forming a second gate insulating layer between the second channel hole and the second gate layer includes:

[0044] Partially oxidize the second gate layer on the sidewall of the second channel hole to form a second gate insulating layer between the second channel hole and the second gate layer.

[0045] Partially oxidize the second gate layer on the sidewall of the second channel hole to form a second gate insulating layer between the second channel hole and the second gate layer.

[0046] Further preferably, the method for manufacturing the semiconductor device further includes:

[0047] After forming the first through hole, form a second through hole penetrating the second insulating layer along the longitudinal direction, and the second through hole communicates with the first through hole;

[0048] Before filling the channel material in the first channel hole and the second channel hole, form an N-type doped source in at least part of the second through hole.

[0049] Further preferably, the method for manufacturing the semiconductor device further includes:

[0050] Before forming the first channel hole, form a third insulating layer on the stacked layer;

[0051] Before forming the first channel hole, form a third through hole penetrating the third insulating layer along the longitudinal direction, and the third through hole communicates with the first channel hole;

[0052] After filling the channel material, form an N-type doped drain in the third through hole, and the drain is located at the top of the first channel structure.

[0053] Further preferably, the material of the first gate layer includes polysilicon, and the first gate layer is connected to a word line, and the second gate layer is connected to a plate line and is applied with a fixed voltage.

[0054] Further preferably, the first channel structure and the second channel structure are cylindrical, and the diameter of the second channel structure is larger than the diameter of the first channel structure.

[0055] The beneficial effects of the present invention are as follows: A semiconductor device and a preparation method thereof are provided, including a substrate, and a stacked layer located on the substrate. The stacked layer sequentially includes a first gate layer, a first insulating layer, a second gate layer, and a second insulating layer from top to bottom, as well as a first channel structure longitudinally penetrating the first gate layer and the first insulating layer perpendicular to the substrate, and a second channel structure longitudinally penetrating the second gate layer. The top of the second channel structure is connected to the bottom of the first channel structure, and the cross-sectional area of the second channel structure in a cross-section perpendicular to the longitudinal direction is larger than the cross-sectional area of the first channel structure in a cross-section perpendicular to the longitudinal direction. Since the cross-sectional area of the first channel structure is small, the gating rate of the first gate layer corresponding to the first channel structure is faster, thereby improving the gate control ability of the semiconductor device. At the same time, since the cross-sectional area of the second channel structure is large, the second channel structure can support a higher hole storage capacity, thereby improving the storage ability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The following, in conjunction with the drawings, through a detailed description of the specific embodiments of the present invention, will make the technical solutions and other beneficial effects of the present invention obvious.

[0057] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0058] Figure 2 is a schematic flow diagram of a preparation method of a semiconductor device provided by an embodiment of the present invention;

[0059] Figures 3a - 3l is a schematic structural diagram during the preparation process of a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0060] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0061] It should be understood that although terms such as first and second can be used here to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, the first component can be called the second component, and similarly, the second component can be called the first component without departing from the scope of the present invention.

[0062] It should be understood that when a component is referred to as being "on" another component or "connected" to another component, it can be directly on the other component or connected to the other component, or there can also be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0063] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively closer to the substrate, and the top side is relatively farther from the substrate. The layer can extend over the entire underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically, and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and contact layers (wherein contacts, interconnect lines, and one or more dielectric layers are formed).

[0064] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.

[0065] It should be noted that the diagrams provided in the embodiments of the present invention only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the diagrams and are not drawn according to the number, shape, and size of the components in actual implementation, the type, quantity, and ratio of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0066] Please refer to Figure 1 , Figure 1 , which is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention. The semiconductor device 100 includes a substrate 10, and a stacked layer 11 located on the substrate 10. The stacked layer 11 sequentially includes a top insulating layer 115, a first gate layer 114, a first insulating layer 113, a second gate layer 112, and a second insulating layer 111 from top to bottom. The substrate 10 can be a semiconductor substrate, for example, it can be silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI), etc. The semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, and can also be a stacked layer, such as Si / SiGe, etc.

[0067] The materials of the top insulating layer 115, the first insulating layer 113, and the second insulating layer 111 may include silicon oxide and / or other suitable insulating materials. The materials of the first gate layer 114 and the second gate layer 112 may include polysilicon or metal silicide, such as metal silicide selected from cobalt (Co), nickel (Ni), hafnium (Hf), platinum (Pt), W, and titanium (Ti).

[0068] The semiconductor device 100 further includes a first channel structure 101 that penetrates the first gate layer 114 and the first insulating layer 113 along a longitudinal direction perpendicular to the substrate 10, and a second channel structure 102 that penetrates the second gate layer 112 along the longitudinal direction. The top of the second channel structure 102 is connected to the bottom of the first channel structure 101. The materials of the first channel structure 101 and the second channel structure 102 may include single crystal silicon.

[0069] Wherein, the cross-sectional area of the second channel structure 102 in a cross-section perpendicular to the longitudinal direction is larger than the cross-sectional area of the first channel structure 101 in a cross-section perpendicular to the longitudinal direction. When the first channel structure 101 and the second channel structure 102 are cylindrical, the diameter of the second channel structure 102 is larger than the diameter of the first channel structure 101.

[0070] Furthermore, the height of the second channel structure 102 in the longitudinal direction is greater than the height of the first channel structure 101 in the longitudinal direction. The thickness of the second gate layer 112 corresponding to the second channel structure 102 in the longitudinal direction is greater than the thickness of the first gate layer 114 corresponding to the first channel structure 101 in the longitudinal direction. Therefore, the storage capacity of the second channel structure 102 controlled by the second gate layer 112 can be improved.

[0071] In a variant, the height of the second channel structure 102 in the longitudinal direction may be equal to the height of the first channel structure 101 in the longitudinal direction. Correspondingly, the thickness of the second gate layer 112 in the longitudinal direction is equal to the thickness of the first gate layer 114 in the longitudinal direction.

[0072] In this embodiment, a first channel structure 101 and a second channel structure 102 are connected to form a channel structure. The semiconductor device 100 takes multiple channel structures as an example to illustrate the specific structure of the channel structure. In a channel structure, the first gate layer 114 is connected to the word line. Its main function is that when a certain voltage is applied to the first gate layer 114 through the word line, the channel structure will be turned on, that is, the gating function is realized. The second gate layer 112 is connected to the Plate Line (PL). Its main function is to apply a fixed voltage (less than the voltage of the first gate layer 114) to the second gate layer 112 through the plate line, so that during the storage (write) operation, holes can be kept in the channel structure (mainly in the second channel structure 102), and hole leakage can be reduced when the voltage of the first gate layer 114 changes. In this embodiment, the cross-sectional area of the second channel structure 102 is set to be larger than that of the first channel structure 101, which can not only improve the gating rate of the first gate layer 114, thereby improving the gate control ability of the first gate layer 114, but also increase the hole storage capacity of the second channel structure 102 to improve the storage capacity of the semiconductor device 100.

[0073] The semiconductor device 100 further includes: a first gate insulating layer 31 located between the outer sidewall of the first channel structure 101 and the first gate layer 114; a second gate insulating layer 42 located between the outer sidewall of the second channel structure 102 and the second gate layer 112. In this embodiment, the materials of the first channel structure 101 and the second channel structure 102 may include intrinsic (undoped) single crystal silicon or P-type single crystal silicon, and the materials of the first gate insulating layer 31 and the second gate insulating layer 42 may be oxides.

[0074] The semiconductor device 100 may further include: a source electrode 60 located between the second channel structure 102 and the substrate 10; a drain electrode 70 located on the top of the first channel structure 101. The source electrode 60 can extend into the substrate 10. The materials of the source electrode 60 and the drain electrode 70 may include N-type single crystal silicon, and the material of the substrate 10 may include N-type single crystal silicon.

[0075] In this embodiment, the stacked layer 11 can be etched to form a stepped structure. The semiconductor device 100 may further include a third insulating layer 12 covering the stepped structure, and the third insulating layer 12 covers the surface of the top insulating layer 115. The main function of the top insulating layer 115 is to protect the first gate layer 114 when the stepped structure is etched. The third insulating layer 12 covering the stepped structure is mainly to fill the steps to make the surface of the structure flat. Therefore, the first channel structure 101 can also penetrate the top insulating layer 115 and part of the third insulating layer 12, and the height of the first channel structure 101 can still be less than the height of the second channel structure 102.

[0076] The semiconductor device 100 may further include a fourth insulating layer 13 covering the third insulating layer 12, a source lead contact 81 connected to the substrate 10 (serving as a common source layer), a first gate lead contact 82 connected to the first gate layer 114, a second gate lead contact 83 connected to the second gate layer 112, and a drain lead contact 84 connected to the drain 70. The source lead contact 81 is connected to a source line, the first gate lead contact 82 is connected to a word line, the second gate lead contact 83 is connected to a plate line, and the drain lead contact 84 is connected to a bit line to implement read, write, and erase operations.

[0077] Among them, the source lead contact 81 penetrates through the fourth insulating layer 13 and the third insulating layer 12, the first gate lead contact 82 penetrates through the fourth insulating layer 13, the third insulating layer 12, and the top insulating layer 115, the second gate lead contact 83 penetrates through the fourth insulating layer 13, the third insulating layer 12, and the first insulating layer 113, and the drain lead contact 84 penetrates through the fourth insulating layer 13.

[0078] The semiconductor device 100 provided by an embodiment of the present invention includes a substrate 10, a stacked layer 11 located on the substrate 10. The stacked layer 11 sequentially includes a first gate layer 114, a first insulating layer 113, a second gate layer 112, and a second insulating layer 111 from top to bottom, a first channel structure 101 longitudinally penetrating through the first gate layer 114 and the first insulating layer 113 perpendicular to the substrate 10, and a second channel structure 102 longitudinally penetrating through the second gate layer 112. The top of the second channel structure 102 is connected to the bottom of the first channel structure 101, and the cross-sectional area of the second channel structure 102 in a cross-section perpendicular to the longitudinal direction is larger than the cross-sectional area of the first channel structure 101 in a cross-section perpendicular to the longitudinal direction. Since the cross-sectional area of the first channel structure 101 is small, the gating rate of the first gate layer 114 corresponding to the first channel structure 101 is faster, and thus the gate control ability of the semiconductor device 100 can be improved. At the same time, since the cross-sectional area of the second channel structure 102 is large, the second channel structure 102 can support a higher hole storage capacity, and thus the storage ability of the semiconductor device 100 can be improved.

[0079] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of a manufacturing method of the semiconductor device 100 provided by an embodiment of the present invention. Please also refer to Figures 3a - 3l , Figures 3a - 3l which is a schematic structural diagram during the manufacturing process of the semiconductor device 100 provided by an embodiment of the present invention. Taking the manufacturing of the above semiconductor device 100 as an example, the manufacturing method of the semiconductor device 100 is described below. The manufacturing method of the semiconductor device 100 includes the following steps S1 - S6.

[0080] Please refer to Figure 2 steps S1 - S2 in Figures 3a - 3b .

[0081] Step S1: Provide a substrate 10.

[0082] Step S2: Form a stacked layer 11 on the substrate 10. The stacked layer 11 includes, from top to bottom, a first gate layer 114, a first insulating layer 113, a second gate layer 112, and a second insulating layer 111 in sequence.

[0083] In this embodiment, the substrate 10 can be single - crystal silicon and have N - type doping ions. The steps of forming the stacked layer 11 may include: 1) form the second insulating layer 111 on the substrate 10; 2) form the second gate layer 112 on the second insulating layer 111; 3) form the first insulating layer 113 on the second gate layer 112; 4) form the first gate layer 114 on the first insulating layer 113, and the thickness of the second gate layer 112 in the longitudinal direction is greater than the thickness of the first gate layer 114 in the longitudinal direction; 5) form a top insulating layer 115 on the first gate layer 114.

[0084] After forming the stacked layer 11, the manufacturing method may further include: etching the stacked layer 11 to form a stepped structure as Figure 3b shown; forming a third insulating layer 12 covering the stepped structure.

[0085] In a variant, after forming the stepped structure, a dielectric layer (the dielectric may include a relatively thin first dielectric layer and a relatively thick second dielectric layer) covering the stepped structure can be formed, and then the dielectric layer is subjected to chemical - mechanical polishing to make the dielectric layer flush with the top insulating layer 115. Then the third insulating layer 12 is formed on the horizontal surface. Regardless of which process, the third insulating layer 12 is located on the top insulating layer 115.

[0086] Please refer to Figure 1 steps S3 in Figures 3c - 3f .

[0087] Step S3: Form a first channel hole 30 that penetrates the first gate layer 114 and the first insulating layer 113 along the longitudinal direction.

[0088] Specifically, 1) as Figure 3cAs shown, the third insulating layer 12, the top insulating layer 115, and the first gate layer 114 are etched in sequence to form a third through hole 20 penetrating through the third insulating layer 12 and the top insulating layer 115, and then a first channel hole 30 penetrating through the first gate layer 114. The third through hole 20 communicates with the first channel hole 30, and the third through hole 20 and the first channel hole 30 can be formed in a single etching process; 2) As Figure 3d shown, a first gate insulating layer 31 is formed between the first channel hole 30 and the first gate layer 114. Specifically, the first gate layer 114 on the sidewall of the first channel hole 30 can be partially oxidized to form the first gate insulating layer 31 between the first channel hole 30 and the first gate layer 114; 3) As Figure 3e shown, a protective layer 32 is formed on the inner walls of the third through hole 20 and the first channel hole 30. The material of the protective layer 32 can include polysilicon; 4) As Figure 3f shown, the bottom of the protective layer 32 and the first insulating layer 113 are etched to make the first channel hole 30 penetrate through the first gate layer 114 and the first insulating layer 113. The function of the protective layer 32 is to protect the first gate insulating layer 31 from being etched when etching the first insulating layer 113 and subsequent etching of the second gate layer 112 and the second insulating layer 111. The protective layer 32 will be removed in subsequent processes.

[0089] Please refer to Figure 2 step S4 in Figure 3g and

[0090] Step S4: A first through hole 40 is formed to penetrate through the second gate layer 112 along the longitudinal direction, and the first through hole 40 communicates with the first channel hole 30.

[0091] As Figure 3g shown, the second gate layer 112 is etched further downward to form a first through hole 40 penetrating through the second gate layer 112. In this embodiment, the manufacturing method may further include: after forming the first through hole 40, a second through hole 50 is formed to penetrate through the second insulating layer 111 along the longitudinal direction, and the second through hole 50 communicates with the first through hole 40, and the second through hole 50 can extend through a part of the substrate 10.

[0092] Please refer to Figure 2 step S5 in Figure 3h and

[0093] Step S5: The second gate layer 112 is etched based on the first through hole 40 to form a second channel hole 41 penetrating through the second gate layer 112. The cross-sectional area of the second channel hole 41 in a cross-section perpendicular to the longitudinal direction is larger than the cross-sectional area of the first channel hole 30 in a cross-section perpendicular to the longitudinal direction.

[0094] As shown Figure 3h in the figure, after etching the second gate layer 112 on the sidewall of the first through hole 40, a second channel hole 41 with a pore diameter larger than that of the first channel hole 30 can be formed, that is, the cross-sectional area of the second channel hole 41 in the cross-section perpendicular to the longitudinal direction is larger than the cross-sectional area of the first channel hole 30 in the cross-section perpendicular to the longitudinal direction. In the process of etching the second gate layer 112, the protective layer 32 is also removed, and at the same time, the first insulating layer 113 directly below the protective layer 32 is also removed, so that the vertical (longitudinal) dimensions of the first channel hole 30 penetrating through the first gate layer 114 and the first insulating layer 113 are uniform. Similarly, the second insulating layer 111 directly below the protective layer 32 is also removed, so that the pore diameter of the second through hole 50 is the same as the pore diameter of the first channel hole 30.

[0095] After step S5, the preparation method may further include: 1) As shown Figure 3i in the figure, a second gate insulating layer 42 is formed between the second channel hole 41 and the second gate layer 112. Specifically, the second gate layer 112 on the sidewall of the second channel hole 41 can be partially oxidized to form a second gate insulating layer 42 between the second channel hole 41 and the second gate layer 112; 2) As shown Figure 3j in the figure, an N-type doped source electrode 60 is formed in at least part of the second through hole 50, and the source electrode 60 is located at the bottom of the second through hole 50. Since the second through hole 50 extends through part of the substrate 10, an N-type single crystal silicon epitaxial process can be used to form the source electrode 60 on the surface of the substrate 10 of the second through hole 50. The formed source electrode 60 may not fill the second through hole 50, that is, the top surface of the source electrode 60 is lower than the top of the second through hole 50.

[0096] Please refer to Figure 2 step S6 in Figure 3k .

[0097] Step S6: Fill the first channel hole 30 and the second channel hole 41 with channel material to form a first channel structure 101 and a second channel structure 102 located at the bottom of the first channel structure 101.

[0098] Specifically, a single crystal silicon epitaxial growth process can be performed on the source electrode 60 until the second channel hole 41, the first channel hole 30, and the third through hole 20 are filled with single crystal silicon. It should be noted that since the source electrode 60 does not fill the second through hole 50, single crystal silicon will be formed in the unfilled part of the second through hole 50 by the source electrode 60.

[0099] After step S6, the preparation method may further include: Please combine Figure 1 and Figure 3l, N-type ion implantation is performed on the single-crystalline silicon located in the third through-hole 20 to form an N-type doped drain 70 in the third through-hole 20, and the drain 70 is located at the top of the third through-hole 20. It should be noted that since the height of the drain 70 is less than the height of the third through-hole 20, the first channel structure 101 penetrates not only the first gate layer 114 and the first insulating layer 113, but also the top insulating layer 115 and a part of the third insulating layer 12. In Figure 1 , the height of the second channel structure 102 can still be greater than the height of the first channel structure 101.

[0100] In this embodiment, the manufacturing method may further include: as Figure 3l shown, an isolation structure 80 is formed that penetrates the stacked layer 11, the third insulating layer 12, and a part of the substrate 10. The isolation structure 80 separates the gate layers of two adjacent channel structures, that is, separates the first gate layers 114 of two adjacent first channel structures 101, and separates the second gate layers 112 of two adjacent second channel structures 102.

[0101] The manufacturing method of the semiconductor device 100 provided by the embodiment of the present invention first forms a second gate layer 112 with a thickness greater than that of the first gate layer 114, then forms a second channel structure 102 with a cross-sectional area greater than that of the first channel structure 101, and also forms a source 60 at the bottom of the second channel structure 102 and a drain 70 at the top of the first channel structure 101, thereby forming a semiconductor device 100 with high gate control ability and storage ability.

[0102] The description of the above embodiments is only used to help understand the technical solution and its core idea of the present invention; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, comprising: a substrate; a stacked layer located on the substrate, the stacked layer sequentially including a first gate layer, a first insulating layer, a second gate layer, and a second insulating layer from top to bottom; a first channel structure penetrating the first gate layer and the first insulating layer along a longitudinal direction perpendicular to the substrate; a second channel structure penetrating the second gate layer along the longitudinal direction, a top of the second channel structure being connected to a bottom of the first channel structure, and a cross-sectional area of the second channel structure in a cross-section perpendicular to the longitudinal direction being larger than a cross-sectional area of the first channel structure in a cross-section perpendicular to the longitudinal direction.

2. The semiconductor device according to claim 1, characterized in that, a thickness of the second gate layer in the longitudinal direction is greater than a thickness of the first gate layer in the longitudinal direction.

3. The semiconductor device according to claim 1, characterized in that, the semiconductor device further comprises: a first gate insulating layer located between an outer sidewall of the first channel structure and the first gate layer; a second gate insulating layer located between an outer sidewall of the second channel structure and the second gate layer.

4. The semiconductor device according to claim 1, characterized in that, the semiconductor device further comprises: a source electrode located between the second channel structure and the substrate; a drain electrode located at a top of the first channel structure.

5. The semiconductor device according to claim 4, characterized in that, the source electrode and the drain electrode are made of N-type single-crystalline silicon.

6. The semiconductor device according to claim 1, characterized in that, a material of the first gate layer includes polysilicon, the first gate layer is connected to a word line, the second gate layer is connected to a plate line and is applied with a fixed voltage.

7. The semiconductor device according to claim 1, characterized in that, the first channel structure and the second channel structure are cylindrical, and a diameter of the second channel structure is larger than a diameter of the first channel structure.

8. A method for manufacturing a semiconductor device, characterized in that, comprising: providing a substrate; forming a stacked layer on the substrate, the stacked layer sequentially including a first gate layer, a first insulating layer, a second gate layer, and a second insulating layer from top to bottom; forming a first channel structure penetrating the first gate layer and the first insulating layer along a longitudinal direction perpendicular to the substrate; forming a second channel structure penetrating the second gate layer along the longitudinal direction, a top of the second channel structure being connected to a bottom of the first channel structure, and a cross-sectional area of the second channel structure in a cross-section perpendicular to the longitudinal direction being larger than a cross-sectional area of the first channel structure in a cross-section perpendicular to the longitudinal direction.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, the step of forming the stacked layer on the substrate includes: forming the second insulating layer on the substrate; forming the second gate layer on the second insulating layer; forming the first insulating layer on the second gate layer; forming the first gate layer on the first insulating layer, a thickness of the second gate layer in the longitudinal direction being greater than a thickness of the first gate layer in the longitudinal direction.

10. The method for manufacturing a semiconductor device according to claim 8, wherein, the step of forming a first channel structure that penetrates the first gate layer and the first insulating layer along a longitudinal direction perpendicular to the substrate includes: forming a first channel hole that penetrates the first gate layer and the first insulating layer along the longitudinal direction; filling a channel material in the first channel hole to form the first channel structure.

11. The method for manufacturing a semiconductor device according to claim 10, wherein, the step of forming a second channel structure that penetrates the second gate layer along the longitudinal direction includes: before filling the channel material, forming a first through hole that penetrates the second gate layer along the longitudinal direction, and the first through hole communicates with the first channel hole; etching the second gate layer based on the first through hole to form a second channel hole that penetrates the second gate layer, and the cross-sectional area of the second channel hole in a cross-section perpendicular to the longitudinal direction is larger than the cross-sectional area of the first channel hole in a cross-section perpendicular to the longitudinal direction; filling the channel material in the first channel hole and the second channel hole to form a first channel structure and the second channel structure located at the bottom of the first channel structure.

12. The method for manufacturing a semiconductor device according to claim 11, wherein, before the step of filling the channel material in the first channel hole and the second channel hole, the method for manufacturing the semiconductor device further includes: forming a first gate insulating layer between the first channel hole and the first gate layer; forming a second gate insulating layer between the second channel hole and the second gate layer.

13. The method for manufacturing a semiconductor device according to claim 12, wherein, the step of forming a first gate insulating layer between the first channel hole and the first gate layer includes: partially oxidizing the first gate layer on the sidewall of the first channel hole to form a first gate insulating layer between the first channel hole and the first gate layer; the step of forming a second gate insulating layer between the second channel hole and the second gate layer includes: partially oxidizing the second gate layer on the sidewall of the second channel hole to form a second gate insulating layer between the second channel hole and the second gate layer.

14. The method for manufacturing a semiconductor device according to claim 11, wherein, the method for manufacturing the semiconductor device further includes: after forming the first through hole, forming a second through hole that penetrates the second insulating layer along the longitudinal direction, and the second through hole communicates with the first through hole; before filling the channel material in the first channel hole and the second channel hole, forming an N-type doped source in at least part of the second through hole.

15. The method for manufacturing a semiconductor device according to claim 10, wherein, the method for manufacturing the semiconductor device further includes: before forming the first channel hole, forming a third insulating layer on the stacked layer; Before forming the first channel hole, a third through hole is formed that penetrates the third insulating layer along the longitudinal direction, and the third through hole communicates with the first channel hole; After filling the channel material, an N-type doped drain is formed in the third through hole, and the drain is located on top of the first channel structure.

16. The method for manufacturing a semiconductor device according to claim 8, wherein, the material of the first gate layer includes polysilicon, and the first gate layer is connected to a word line, and the second gate layer is connected to a plate line and is applied with a fixed voltage.

17. The method for manufacturing a semiconductor device according to claim 8, wherein, the first channel structure and the second channel structure are cylindrical, and the diameter of the second channel structure is greater than the diameter of the first channel structure.

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