Method for preparing semiconductor device and semiconductor device

Abstract

The present invention discloses a method for preparing a semiconductor device and a semiconductor device, comprising forming a substrate, forming a first gate and a second gate located on the substrate, and forming a first sidewall and a second sidewall on the sidewalls of the first gate and the second gate, respectively. A high-voltage well region and a low-voltage well region are formed in the substrate, the first gate and the second gate correspond to the high-voltage well region and the low-voltage well region, respectively, and the height of the first gate is greater than the height of the second gate, and the width of the first sidewall is greater than the width of the second sidewall. Since the height of the first gate and the width of the first sidewall corresponding to the high-voltage well region are larger, the performance of the device can be improved, such as reducing damage to the gate oxide layer and hot carrier effects. At the same time, since the height of the second gate and the width of the second sidewall corresponding to the low-voltage well region are smaller, the speed of the device can be increased and the area of ​​the device can be reduced.

Description

Technical Field

[0001] The present invention generally relates to electronic devices, and more particularly, to a method for preparing a semiconductor device and the semiconductor device. Background Art

[0002] In complementary metal oxide semiconductors (CMOS), there are both low voltage metal oxide semiconductor transistors (LVMOS) and high voltage metal oxide semiconductor transistors (HVMOS).

[0003] Because the ion implantation energy used to form the low-doped structure of HVMOS is relatively high, if the gate height does not meet certain requirements, the gate will be punched through, thereby damaging the gate oxide layer. At the same time, if the width of the sidewalls on both sides of the gate does not meet certain requirements, it will cause hot carrier injection (HCI) effects, thereby damaging the performance of the device. However, for LVMOS, a gate that is too thick will reduce the speed of the device, and a sidewall that is too wide will also reduce the speed of the device. Since the sidewalls of LVMOS need to be separated from the contact points on the gate by a certain distance, the wider the sidewalls, the more limited the space for the contact points is when the device area is fixed. If the sidewalls are to be kept a certain distance from the contact points and the sidewall width is increased, the area of ​​the device will increase. Therefore, if the sidewall width of LVMOS is too wide, it will result in a loss of device area.

[0004] However, for memory, as storage density increases, reducing the area of ​​CMOS is an inevitable requirement. Summary of the Invention

[0005] The object of the present invention is to provide a method for preparing a semiconductor device and a semiconductor device, aiming to form double gates with different heights and double sidewalls with different widths, so as to take into account the gate height and sidewall width of HVMOS and LVMOS, thereby improving the performance of the device and reducing the area of ​​the device.

[0006] In one aspect, the present invention provides a method for preparing a semiconductor device, comprising:

[0007] Providing a substrate, wherein a high-voltage well region and a low-voltage well region are formed in the substrate;

[0008] forming a first gate and a second gate located on the substrate, wherein the first gate corresponds to the high-voltage well region, the second gate corresponds to the low-voltage well region, and the height of the first gate is greater than that of the second gate;

[0009] A first sidewall spacer is formed on the first gate sidewall and a second sidewall spacer is formed on the second gate sidewall. The width of the first sidewall spacer in a direction away from the first gate sidewall is greater than the width of the second sidewall spacer in a direction away from the second gate sidewall.

[0010] Further preferably, the step of forming a first gate and a second gate located on the substrate includes:

[0011] forming a gate layer on the substrate, wherein the gate layer is located above the high-voltage well region and the low-voltage well region;

[0012] removing a portion of the gate layer located above the low-voltage well region, so that a height of the gate layer above the low-voltage well region is smaller than a height of the gate layer above the high-voltage well region;

[0013] The first gate corresponding to the high-voltage well region and the second gate corresponding to the low-voltage well region are formed by a photolithography process, and the height of the first gate is greater than that of the second gate.

[0014] Further preferably, the width of the first gate is greater than the width of the second gate.

[0015] Further preferably, the step of forming a first sidewall spacer located on the sidewall of the first gate and a second sidewall spacer located on the sidewall of the second gate includes:

[0016] forming an insulating layer covering the first gate, the second gate and the substrate;

[0017] The insulating layer is etched to form a first insulating layer located on the sidewall of the first gate and a second insulating layer located on the sidewall of the second gate, wherein the first sidewall includes the first insulating layer, and the second sidewall includes the second insulating layer.

[0018] Further preferably, the widths of the first sidewall spacer and the second sidewall spacer gradually decrease in a direction away from the substrate.

[0019] Further preferably, the step of forming a first sidewall spacer located on the sidewall of the first gate and a second sidewall spacer located on the sidewall of the second gate further includes:

[0020] Before the step of forming the insulating layer, forming a first oxide layer and a second oxide layer covering the first gate and the second gate respectively;

[0021] forming a first nitride layer on the sidewall of the first gate and located on the outer surface of the first oxide layer, and forming a second nitride layer on the sidewall of the second gate and located on the outer surface of the second oxide layer;

[0022] The first sidewall spacer includes the first oxide layer, the first nitride layer and the first insulating layer located on the sidewall of the first gate, and the second sidewall spacer includes the second oxide layer, the second nitride layer and the second insulating layer located on the sidewall of the second gate.

[0023] Further preferably, the step of forming a first sidewall spacer located on the sidewall of the first gate and a second sidewall spacer located on the sidewall of the second gate further includes:

[0024] forming a third oxide layer, a third nitride layer, and a fourth oxide layer in sequence to cover the horizontal surfaces and sidewalls of the first and second gates;

[0025] removing the fourth oxide layer located on horizontal surfaces of the first gate and the second gate;

[0026] removing the fourth oxide layer located on the sidewall of the second gate;

[0027] removing the third nitride layer located on horizontal surfaces of the first gate and the second gate;

[0028] Among them, the first side wall includes the first oxide layer, the first nitride layer, the third oxide layer, the third nitride layer, the fourth oxide layer and the first insulating layer located in sequence on the side wall of the first gate, and the second side wall includes the second oxide layer, the second nitride layer, the third oxide layer, the third nitride layer and the second insulating layer located in sequence on the side wall of the second gate.

[0029] More preferably, it also includes:

[0030] forming a first source region and a first drain region in the high-voltage well region;

[0031] forming a second source region and a second drain region in the low voltage well region;

[0032] After the step of forming the first gate and the second gate, a first lightly doped region and a second lightly doped region are formed in the high-voltage well region and are adjacent to the first source region and the first drain region respectively.

[0033] In another aspect, the present invention provides a semiconductor device comprising:

[0034] a substrate having a high-voltage well region and a low-voltage well region formed therein;

[0035] a first gate and a second gate located on the substrate, wherein the first gate corresponds to the high-voltage well region, the second gate corresponds to the low-voltage well region, and the height of the first gate is greater than that of the second gate;

[0036] A first sidewall spacer located on the first gate sidewall and a second sidewall spacer located on the second gate sidewall, wherein the width of the first sidewall spacer in a direction away from the first gate sidewall is greater than the width of the second sidewall spacer in a direction away from the second gate sidewall.

[0037] Further preferably, the width of the first gate is greater than the width of the second gate.

[0038] Further preferably, the first side wall includes a first insulating layer located on the side wall of the first gate, the second side wall includes a second insulating layer located on the side wall of the second gate, and the widths of the first side wall and the second side wall respectively gradually decrease in a direction away from the substrate.

[0039] Further preferably, the first side wall includes a first oxide layer, a first nitride layer and the first insulating layer sequentially located on the side wall of the first gate, and the second side wall includes a second oxide layer, a second nitride layer and the second insulating layer sequentially located on the side wall of the first gate.

[0040] Further preferably, the first side wall includes the first oxide layer, the first nitride layer, the third oxide layer, the third nitride layer, the fourth oxide layer and the first insulating layer sequentially located on the side wall of the first gate, and the second side wall includes the second oxide layer, the second nitride layer, the third oxide layer, the third nitride layer and the second insulating layer sequentially located on the side wall of the second gate.

[0041] More preferably, it also includes:

[0042] a first source region and a first drain region located in the high-voltage well region;

[0043] a second source region and a second drain region located in the low voltage well region;

[0044] A first lightly doped region and a second lightly doped region are located in the high-voltage well region and are adjacent to the first source region and the first drain region respectively.

[0045] The beneficial effects of the present invention are as follows: a method for preparing a semiconductor device and a semiconductor device are provided, comprising forming a substrate, forming a first gate and a second gate located on the substrate, and forming a first sidewall and a second sidewall on the sidewalls of the first gate and the second gate, respectively. A high-voltage well region and a low-voltage well region are formed in the substrate, the first gate and the second gate correspond to the high-voltage well region and the low-voltage well region, respectively, the height of the first gate is greater than the height of the second gate, and the width of the first sidewall is greater than the width of the second sidewall. Since the height of the first gate and the width of the first sidewall corresponding to the high-voltage well region are larger, the performance of the device can be improved, such as reducing damage to the gate oxide layer and hot carrier effects. At the same time, since the height of the second gate and the width of the second sidewall corresponding to the low-voltage well region are smaller, the speed of the device can be increased and the area of ​​the device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0047] Figure 1 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

[0048] Figures 2a-2i is a schematic structural diagram of a semiconductor device during the manufacturing process provided by the first embodiment of the present invention;

[0049] Figure 3 1 is a schematic diagram of a process for forming a first sidewall and a second sidewall provided by a second embodiment of the present invention;

[0050] Figures 4a-4e 1 is a schematic structural diagram of the process of forming the first sidewall and the second sidewall provided by the second embodiment of the present invention. DETAILED DESCRIPTION

[0051] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0052] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of the present invention.

[0053] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0054] As used herein, the term "layer" refers to a material portion comprising an area with a height. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. A layer can extend over the entire lower or upper structure, or can have a range that is smaller than the range of the lower or upper structure. In addition, a layer can be an area of ​​a uniform or non-uniform continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnect lines and one or more dielectric layers are formed).

[0055] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.

[0056] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed at will, and the component layout type may also be more complicated.

[0057] See also Figure 1 , Figure 1 This is a flow chart of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. Figures 2a-2i , Figures 2a-2i 1 is a schematic diagram of the structure of a semiconductor device during the manufacturing process provided by the first embodiment of the present invention. The manufacturing method of the semiconductor device includes the following steps S1-S3.

[0058] See Figure 1 Step S1 and Figure 2a .

[0059] Step S1: providing a substrate 10 , wherein a high-voltage well region 101 and a low-voltage well region 102 are formed in the substrate 10 .

[0060] The substrate 10 may be a semiconductor substrate, for example, a silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, and may also be a stacked structure, such as Si / SiGe.

[0061] In this embodiment, the substrate 10 can be first etched to form an isolation trench, and then an insulating material can be filled into the isolation trench to form an isolation structure 103. Then, ion implantation can be performed on the substrate 10 using a suitable mask to form a high-voltage well region 101 and a low-voltage well region 102 spaced apart. The isolation structure 103 is used to separate the high-voltage well region 101 from the low-voltage well region 102. The device operating voltage corresponding to the high-voltage well region 101 is higher, while the device operating voltage corresponding to the low-voltage well region 102 is lower. The order in which the high-voltage well region 101, the low-voltage well region 102, and the isolation structure 103 are prepared is not limited by this embodiment.

[0062] See Figure 1 Steps S2-S4 and Figures 2a-2e .

[0063] Step S2 : forming a gate layer 12 on the substrate 10 , wherein the gate layer 12 is located above the high-voltage well region 101 and the low-voltage well region 102 .

[0064] In a specific embodiment, if Figure 2a As shown, step S2 may include: first forming a gate insulating layer 11 on the substrate 10 using a suitable deposition process; then depositing a gate layer 12 on the gate insulating layer 11, where the gate insulating layer 11 may include silicon oxide, and the gate layer 12 may include polysilicon.

[0065] Step S3 : removing a portion of the gate layer 12 located above the low-voltage well region 102 , so that the height of the gate layer 12 above the low-voltage well region 102 is smaller than the height of the gate layer 12 above the high-voltage well region 101 .

[0066] In a specific embodiment, if Figure 2b As shown, a photoresist is spin-coated on the gate layer 12; and then the photoresist is patterned using a mask to form a pattern as shown in FIG. Figure 2b The patterned photoresist layer 13 shown in FIG. 1 corresponds to the top of the high-voltage well region 101; Figure 2cAs shown, the patterned photoresist layer 13 is then used to etch the gate layer 12 to remove a portion of the gate layer 12 located above the low-voltage well region 102, so that the height of the gate layer 12 above the low-voltage well region 102 is smaller than the height of the gate layer 12 above the high-voltage well region 101. Specifically, the etching depth can be controlled by controlling the etching rate and time, thereby precisely controlling the height of the gate layer 12 above the low-voltage well region 102.

[0067] Among them, when the photoresist is a positive photoresist, the mask has an opening above the corresponding low-voltage well area 102 and the isolation structure 103. After exposure and development, the portion of the photoresist above the corresponding low-voltage well area 102 and the isolation structure 103 is removed, thereby forming a patterned photoresist layer 13 above the corresponding high-voltage well area 101.

[0068] Step S4 : forming the first gate 121 corresponding to the high-voltage well region 101 and the second gate 122 corresponding to the low-voltage well region 102 by a photolithography process, wherein the height of the first gate 121 is greater than that of the second gate 122 .

[0069] In a specific embodiment, if Figure 2d As shown, a composite hard mask layer 14 and a photoresist layer 15 are sequentially deposited on the etched gate layer 12. The composite hard mask layer includes an amorphous carbon layer (AC) 141 formed in sequence, and a silicon oxynitride (SiON) layer 142 formed on the surface of the amorphous carbon layer 141. The amorphous carbon layer 141 serves as a light absorbing layer, and the silicon oxynitride layer 142 serves as an anti-reflection layer. Figure 2e As shown, the photoresist layer 15 is exposed and developed using a mask, and then a patterned hard mask layer is formed using the photoresist layer 15. The gate layer 12 is then etched using the patterned hard mask layer to form a gate electrode 12. Figure 2e The first gate 121 and the second gate 122 are shown. Preferably, by changing the pattern of the mask, the width of the first gate 121 can be made larger than the width of the second gate 122. In this way, the process of forming the first gate 121 and the second gate 122 with different widths is simple and does not require additional process steps.

[0070] See Figure 1 Step S5 and Figure 2f-2i .

[0071] Step S5: Form a first side wall 1210 located on the side wall of the first gate 121 and a second side wall 1220 located on the side wall of the second gate 122, wherein the width of the first side wall 1210 in a direction away from the side wall of the first gate 121 is greater than the width of the second side wall 1220 in a direction away from the side wall of the second gate 122.

[0072] In a specific embodiment, step S5 may include:

[0073] 1) forming a first oxide layer 1211 and a second oxide layer 1221 covering the first gate 121 and the second gate 122 respectively. Specifically, the oxide layer may be deposited first, and then the oxide layer on the gate insulating layer 11 may be removed to form the following: Figure 2f A first oxide layer 1211 covering the first gate 121 and a second oxide layer 1221 covering the second gate are shown.

[0074] 2) forming a first nitride layer 1212 on the outer surface of the first oxide layer 1211 on the sidewall of the first gate 121, and forming a second nitride layer 1222 on the outer surface of the second oxide layer 1221 on the sidewall of the second gate 122. Specifically, the nitride layer can be deposited first, and then the nitride layer on the horizontal surface can be removed by dry etching (isotropic etching) to form the following: Figure 2f A first nitride layer 1212 and a second nitride layer 1222 are shown.

[0075] 3) If Figure 2h As shown, an insulating layer 16 is formed to cover the first gate 121, the second gate 122, and the substrate 10 (or the gate insulating layer 11). When depositing the insulating layer 16, more insulating layer 16 is deposited at the corners at the bottoms of the first gate 121 and the second gate 122, and the amount of insulating layer 16 gradually decreases as it moves away from the substrate 10. Because the height of the first gate 121 is greater than that of the second gate 122, in order to ensure that the insulating layer 16 covers the first gate 121, which is taller than the second gate 122, a thicker insulating layer 16 is formed on the sidewalls of the first gate 121 than on the second gate 122. Therefore, the width of the formed insulating layer 16 gradually decreases as it moves away from the substrate 10, and the insulating layer 16 on the sidewalls of the first gate 121 is wider than the insulating layer 16 on the sidewalls of the second gate 122 (comparing corresponding positions, for example, comparing the bottom of the first gate 121 with the bottom of the second gate 122).

[0076] 4) If Figure 2iAs shown, the insulating layer 16 is etched to form a first insulating layer 161 located on the sidewall of the first gate 121 as the first spacer 1210, and a second insulating layer 162 located on the sidewall of the second gate 122 as the second spacer 1220. The widths of the first spacer 1210 and the second spacer 1220 gradually decrease in a direction away from the substrate 10. Specifically, dry etching can be used to etch the insulating layer 16 in a direction perpendicular to the substrate 10 to remove the insulating layer 16 on the horizontal surface, leaving the first insulating layer 161 located on the sidewall of the first gate 121 and the second insulating layer 162 located on the sidewall of the second gate 122. The first spacer 1210 includes the first oxide layer 1211, the first nitride layer 1212, and the first insulating layer 161 located on the sidewall of the first gate 121. The second spacer 1220 includes the second oxide layer 1221, the second nitride layer 1222, and the second insulating layer 162 located on the sidewall of the second gate 122. During the etching process, since the insulating layer 16 on the side wall of the first gate 121 is thicker, the width of the first side wall 1210 formed after etching in the direction away from the side wall of the first gate 121 is greater than the width of the second side wall 1220 in the direction away from the side wall of the second gate 122. Moreover, since the width of the insulating layer 16 gradually decreases from the bottom to the top of the gate, the width of the first side wall 1210 and the second side wall 1220 formed gradually decreases in the direction away from the substrate 10.

[0077] In a modified embodiment, the insulating layer 16 can be directly formed, and then etched to form the first insulating layer 161 and the second insulating layer 162 as the first sidewall spacer 1210 and the second sidewall spacer 1220, respectively. This eliminates the need to form oxide and nitride layers. In this embodiment, the first oxide layer 1211 and the first nitride layer 1212 are formed between the first gate 121 and the first sidewall spacer 1210 to more effectively protect the first gate 121. The second oxide layer 1221 and the second nitride layer 1222 are formed between the second gate 122 and the second sidewall spacer 1220 to more effectively protect the second gate 122.

[0078] The method for manufacturing the semiconductor device provided in this embodiment may further include, after forming the high-voltage well region 101 and the low-voltage well region 102, forming a first source region and a first drain region (not shown in the figure) in the high-voltage well region 101, and forming a second source region and a second drain region (not shown in the figure) in the low-voltage well region 102. Further, after forming the first nitride layer 1212 and the second nitride layer 1222 ( Figure 2f ),like Figure 2gAs shown, a photoresist is formed covering the isolation structure 103 and the low-voltage well region 102, and a first lightly doped region 1011 and a second lightly doped region 1012 are formed in the high-voltage well region 101, adjacent to the first source region and the first drain region, respectively. Specifically, ion implantation is performed on the high-voltage well region 101 adjacent to the first source region to form the first lightly doped region 1011, and simultaneously ion implantation is performed on the high-voltage well region 101 adjacent to the first drain region to form the second lightly doped region 1012. The first lightly doped region 1011 and the second lightly doped region 1012 are formed in the high-voltage well region 101, so that the first lightly doped region 1011 and the second lightly doped region 1012 also bear partial voltage. This structure can prevent the HCl effect. Due to the high energy of the ion implantation, the thickness of the first gate 121 corresponding to the high-voltage well region 101 is set relatively thick in this embodiment, which can prevent the first gate 121 from being penetrated and damaging the gate insulation layer 11, thereby ensuring device performance.

[0079] The method for fabricating a semiconductor device provided in the first embodiment of the present invention first forms a substrate 10 having a high-voltage well region 101 and a low-voltage well region 102 spaced apart from each other. A first gate 121 and a second gate 122 are then formed on the substrate, corresponding to the high-voltage well region 101 and the low-voltage well region 102, respectively. A first spacer 1210 and a second spacer 1220 are then formed on the sidewalls of the first gate 121 and the second gate 122, respectively. The height of the first gate 121 is greater than the height of the second gate 122, and the width of the first spacer 1210 is greater than the width of the second spacer 1220. Because the height of the first gate 121 corresponding to the high-voltage well region 101 is higher, the first gate 121 is protected from being punched through and the gate oxide layer is protected from being damaged during the formation of the first lightly doped region 1011 and the second lightly doped region 1012. Furthermore, because the width of the first spacer 1210 on the sidewalls of the first gate 121 is greater, hot carrier injection effects are reduced. At the same time, the height of the second gate 122 and the width of the second sidewall spacer 1220 corresponding to the low-voltage well region 102 are relatively small, which can increase the speed of the device and reduce the area of ​​the device.

[0080] See also Figure 3 , Figure 3 This is a schematic diagram of the process of forming the first sidewall and the second sidewall provided by the second embodiment of the present invention. Figures 4a-4e , Figures 4a-4e FIG2 is a schematic diagram illustrating the process of forming the first and second sidewall spacers according to a second embodiment of the present invention. For ease of understanding, identical structures in this embodiment are numeraled as in the first embodiment. In this embodiment, the steps of forming the first and second sidewall spacers include the following steps S51-S56.

[0081] Step S51 : forming a first oxide layer 1211 and a second oxide layer 1221 covering the first gate 121 and the second gate 122 respectively.

[0082] Step S52 : forming a first nitride layer 1212 on the sidewall of the first gate 121 and located on the outer surface of the first oxide layer 1211 , and forming a second nitride layer 1222 on the sidewall of the second gate 122 and located on the outer surface of the second oxide layer 1221 .

[0083] In this embodiment, step S51 is the same as step 1) of step S5 in the first embodiment, and step S52 is the same as step 2) of step S5 in the first embodiment. The processes of step S51 and step S52 are not described in detail in this embodiment. The completed structure is the same as that in the first embodiment. Figure 2f shown.

[0084] Step S53 : forming a third oxide layer 17 , a third nitride layer 18 and a fourth oxide layer 19 in sequence to cover the horizontal surfaces and sidewalls of the first gate 121 and the second gate 122 .

[0085] exist Figure 2f On the basis of, a third oxide layer 17, a third nitride layer 18 and a fourth oxide layer 19 are sequentially deposited, such as Figure 4a As shown, the third oxide layer 17 , the third nitride layer 18 and the fourth oxide layer 19 cover the horizontal surfaces and sidewalls of the first gate 121 and the second gate 122 and the gate insulating layer 11 .

[0086] Step S54 : removing the fourth oxide layer 19 located on the horizontal surfaces of the first gate 121 and the second gate 122 .

[0087] In this embodiment, a dry etching process can be used to etch the fourth oxide layer 19 along a direction perpendicular to the substrate 10 to form a fourth oxide layer 191 located on the sidewall of the first gate 121 and a fourth oxide layer 192 located on the sidewall of the second gate 122 (e.g., Figure 4b shown).

[0088] Step S55: removing the fourth oxide layer 192 (such as Figure 4c shown).

[0089] In this embodiment, the mask used in step S3 of the first embodiment can be used. Since both step S55 and step S3 etch the device in the low voltage well region 102, using the same mask as step S3 can save the number of masks and save costs.

[0090] Step S56 : removing the third nitride layer 18 located on the horizontal surfaces of the first gate 121 and the second gate 122 .

[0091] In this embodiment, the third nitride layer 18 can be etched in a direction perpendicular to the substrate 10 by dry etching to remove the third nitride layer 18 located on the horizontal surfaces of the first gate 121 and the second gate 122, thereby forming a third nitride layer 181 located on the sidewall of the first gate 121 and a third nitride layer 182 located on the sidewall of the second gate 122 (e.g., Figure 4d shown).

[0092] In this embodiment, after step S56, the following step may further include: removing the oxide layer (including the first oxide layer 1211 and the third oxide layer 17) on the horizontal surfaces of the first gate 121 and the second gate 122. Specifically, dry etching may be used to remove the oxide layer on the top of the first gate 121 and the oxide layer on the top of the second gate 122, as well as the third oxide layer 17 on the surface of the gate insulating layer 11, leaving the third oxide layer 171 on the side wall of the first gate 121 and the third oxide layer 172 on the side wall of the second gate 122 (such as Figure 4e shown).

[0093] In this embodiment, continue Figure 4e On the basis of forming a first insulating layer located on the side wall of the first gate 121 and a second insulating layer located on the side wall of the second gate 122 (see the first embodiment) Figure 2i The first insulating layer 161 and the second insulating layer 162 are provided in the side wall of the first gate 121, so the first side wall 1210 provided in this embodiment includes the first oxide layer 1211, the first nitride layer 1212, the third oxide layer 171, the third nitride layer 181, the fourth oxide layer 191 and the first insulating layer located in sequence on the side wall of the first gate 121, and the second side wall 1220 includes the second oxide layer 1221, the second nitride layer 1222, the third oxide layer 172, the third nitride layer 182 and the second insulating layer located in sequence on the side wall of the second gate 122.

[0094] The second embodiment of the present invention provides a method for forming the first sidewall 1210 and the second sidewall 1220. Compared with the first embodiment, a third oxide layer 171, a third nitride layer 181, and a fourth oxide layer 191 are further formed between the first insulating layer and the first nitride layer 1212 on the sidewalls of the first gate 121. A third oxide layer 172 and a third nitride layer 182 are further formed between the second insulating layer and the second nitride layer 1222 on the sidewalls of the second gate 122. Therefore, not only can the first insulating layer and the second insulating layer increase the width difference between the first sidewall 1210 and the second sidewall 1220, but the first sidewall 1210 also has an additional fourth oxide layer 191 located on the sidewall of the first gate compared to the second sidewall 1220, further increasing the width difference between the first sidewall 1210 and the second sidewall 1220, thereby meeting the HCI requirements of the high-voltage well region 101 device and reducing the area of ​​the low-voltage well region 102 device. In addition, since the number of layers formed on the gate sidewall is relatively large, the sidewall can better protect the gate. However, the process steps of the first embodiment are less than those of the second embodiment.

[0095] The third embodiment of the present invention further provides a semiconductor device, such as Figure 2i As shown, the semiconductor device includes: a substrate 10, in which a high-voltage well region 101 and a low-voltage well region 102 are formed, spaced apart from each other; a first gate 121 and a second gate 122 located on the substrate 10, wherein the first gate 121 corresponds to the high-voltage well region 101, and the second gate 122 corresponds to the low-voltage well region 102, and the height of the first gate 121 is greater than the height of the second gate 122; and a first spacer 1210 located on the sidewall of the first gate 121 and a second spacer 1220 located on the sidewall of the second gate 122, wherein the width of the first spacer 1210 in a direction away from the sidewall of the first gate 121 is greater than the width of the second spacer 1220 in a direction away from the sidewall of the second gate 122. In this embodiment, the high-voltage well region 101, the first gate 121, and the first spacer 1210 are components of an HVMOS, and the low-voltage well region 102, the second gate 122, and the second spacer 1220 are components of an LVMOS.

[0096] Preferably, the width of the first gate 121 is greater than the width of the second gate 122 .

[0097] Optionally, the first side wall 1210 includes a first insulating layer 161 located on the side wall of the first gate 121, and the second side wall 1220 includes a second insulating layer 162 located on the side wall of the second gate 122, and the widths of the first side wall 1210 and the second side wall 1220 gradually decrease in the direction away from the substrate 10.

[0098] Furthermore, the first side wall 1210 includes a first oxide layer 1211, a first nitride layer 1212 and the first insulating layer 161 sequentially located on the side wall of the first gate 121, and the second side wall 1220 includes a second oxide layer 1221, a second nitride layer 1222 and the second insulating layer 162 sequentially located on the side wall of the second gate 122.

[0099] In a further embodiment, referring to Figure 4e The first side wall 1210 includes the first oxide layer 1211, the first nitride layer 1212, the third oxide layer 171, the third nitride layer 181, the fourth oxide layer 191 and the first insulating layer sequentially located on the side wall of the first gate 121, and the second side wall 1220 includes the second oxide layer 1221, the second nitride layer 1222, the third oxide layer 172, the third nitride layer 182 and the second insulating layer sequentially located on the side wall of the second gate 122.

[0100] The semiconductor device may further include: a first source region and a first drain region located in the high-voltage well region 101; a second source region and a second drain region located in the low-voltage well region 102; and a first lightly doped region 1011 and a second lightly doped region 1012 located in the high-voltage well region 101 and adjacent to the first source region and the first drain region, respectively. The semiconductor device is formed by the semiconductor device manufacturing method provided in the above embodiment, and thus has the same advantageous effects as the above embodiment, which will not be described in detail in this embodiment.

[0101] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, wherein a high-voltage well region and a low-voltage well region are formed in the substrate; forming a first gate and a second gate located on the substrate, wherein the first gate corresponds to the high-voltage well region, the second gate corresponds to the low-voltage well region, and the height of the first gate is greater than that of the second gate; forming an insulating layer covering the first gate, the second gate, and the substrate by a deposition process, wherein the width of the insulating layer formed by the deposition process gradually decreases in a direction away from the substrate, and the width of the insulating layer formed by the deposition process on the sidewall of the first gate is greater than the width of the insulating layer on the sidewall of the second gate; The insulating layer on the substrate surface, the top of the first gate and the top of the second gate is removed, leaving the first insulating layer located on the side wall of the first gate as a first side wall and the second insulating layer located on the side wall of the second gate as a second side wall, and the width of the first side wall in the direction away from the first gate side wall is greater than the width of the second side wall in the direction away from the second gate side wall.

2. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming a first gate and a second gate located on the substrate includes: forming a gate layer on the substrate, wherein the gate layer is located above the high-voltage well region and the low-voltage well region; removing a portion of the gate layer located above the low-voltage well region, so that a height of the gate layer above the low-voltage well region is smaller than a height of the gate layer above the high-voltage well region; The first gate corresponding to the high-voltage well region and the second gate corresponding to the low-voltage well region are formed by a photolithography process, and the height of the first gate is greater than that of the second gate.

3. The method for preparing a semiconductor device according to claim 2, wherein: The width of the first gate is greater than the width of the second gate.

4. The method for preparing a semiconductor device according to claim 1, wherein: The widths of the first sidewall spacer and the second sidewall spacer gradually decrease in a direction away from the substrate.

5. The method for preparing a semiconductor device according to claim 4, wherein: The step of forming a first sidewall spacer located on the sidewall of the first gate and a second sidewall spacer located on the sidewall of the second gate further includes: Before the step of forming the insulating layer, forming a first oxide layer and a second oxide layer covering the first gate and the second gate respectively; forming a first nitride layer on the sidewall of the first gate and located on the outer surface of the first oxide layer, and forming a second nitride layer on the sidewall of the second gate and located on the outer surface of the second oxide layer; The first sidewall spacer includes the first oxide layer, the first nitride layer and the first insulating layer located on the sidewall of the first gate, and the second sidewall spacer includes the second oxide layer, the second nitride layer and the second insulating layer located on the sidewall of the second gate.

6. The method for preparing a semiconductor device according to claim 5, wherein: The step of forming a first sidewall spacer located on the sidewall of the first gate and a second sidewall spacer located on the sidewall of the second gate further includes: forming a third oxide layer, a third nitride layer, and a fourth oxide layer in sequence to cover the horizontal surfaces and sidewalls of the first and second gates; removing the fourth oxide layer located on horizontal surfaces of the first gate and the second gate; removing the fourth oxide layer located on the sidewall of the second gate; removing the third nitride layer located on horizontal surfaces of the first gate and the second gate; Among them, the first side wall includes the first oxide layer, the first nitride layer, the third oxide layer, the third nitride layer, the fourth oxide layer and the first insulating layer located in sequence on the side wall of the first gate, and the second side wall includes the second oxide layer, the second nitride layer, the third oxide layer, the third nitride layer and the second insulating layer located in sequence on the side wall of the second gate.

7. The method for preparing a semiconductor device according to claim 1, wherein: Also includes: forming a first source region and a first drain region in the high-voltage well region; forming a second source region and a second drain region in the low voltage well region; After the step of forming the first gate and the second gate, a first lightly doped region and a second lightly doped region are formed in the high-voltage well region and are adjacent to the first source region and the first drain region respectively.

8. A semiconductor device, characterized in that: include: a substrate having a high-voltage well region and a low-voltage well region formed therein; a first gate and a second gate located on the substrate, wherein the first gate corresponds to the high-voltage well region, the second gate corresponds to the low-voltage well region, and the height of the first gate is greater than that of the second gate; A first sidewall spacer located on the sidewall of the first gate and a second sidewall spacer located on the sidewall of the second gate, wherein the width of the first sidewall in a direction away from the first gate sidewall is greater than the width of the second sidewall in a direction away from the second gate sidewall, and the widths of the first sidewall and the second sidewall gradually decrease in a direction away from the substrate, wherein the insulating layer deposited on the sidewall of the first gate serves as the first sidewall spacer, and the insulating layer deposited on the sidewall of the second gate serves as the second sidewall spacer.

9. The semiconductor device according to claim 8, wherein The width of the first gate is greater than the width of the second gate.

10. The semiconductor device according to claim 8, wherein The first spacer includes a first insulating layer located on a sidewall of the first gate, and the second spacer includes a second insulating layer located on a sidewall of the second gate.

11. The semiconductor device according to claim 10, wherein: The first sidewall spacer includes a first oxide layer, a first nitride layer and the first insulating layer sequentially located on the sidewall of the first gate, and the second sidewall spacer includes a second oxide layer, a second nitride layer and the second insulating layer sequentially located on the sidewall of the first gate.

12. The semiconductor device according to claim 11, wherein The first side wall includes the first oxide layer, the first nitride layer, the third oxide layer, the third nitride layer, the fourth oxide layer and the first insulating layer sequentially located on the side wall of the first gate, and the second side wall includes the second oxide layer, the second nitride layer, the third oxide layer, the third nitride layer and the second insulating layer sequentially located on the side wall of the second gate.

13. The semiconductor device according to claim 8, wherein Also includes: a first source region and a first drain region located in the high-voltage well region; a second source region and a second drain region located in the low voltage well region; A first lightly doped region and a second lightly doped region are located in the high-voltage well region and are adjacent to the first source region and the first drain region respectively.

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