Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: forming a semiconductor structure, the semiconductor structure comprising a substrate, a stack structure in a first direction of the substrate, a sacrificial layer between the substrate and the stack structure, and a channel structure extending through the stack structure and into the substrate, the channel structure comprising a functional layer, a channel layer, and an insulating layer, and the channel structure having a gap in the insulating layer at an end of the channel structure close to the sacrificial layer; removing the substrate; removing at least part of the sacrificial layer to expose the gap at the end of the channel structure; and forming an insulating filling block in the gap. By forming the insulating filling block in the gap, the material of a semiconductor layer formed subsequently can be prevented from entering the gap, thereby avoiding electrical interference and causing electrical failure of the device, and improving the yield and reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In recent years, the development of flash memory is particularly rapid. The main features of flash memory are that it can keep the stored information for a long time without power supply, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc., so it has been widely used in many fields such as microcomputer and automatic control. Under this background, in order to solve the difficulties encountered by planar flash memory and pursue lower production cost per storage unit, 3D NAND flash memory emerges as the times require. In the 3D NAND flash memory, multiple layers of data storage units are alternately stacked, which converts the planar structure into a three-dimensional structure to improve the storage density and integration of the 3D NAND flash memory. The 3D NAND flash memory can accommodate higher storage capacity in smaller space, thereby bringing great cost savings, energy consumption reduction, and substantial performance improvement to fully meet the needs of many consumer mobile devices and the most demanding enterprise deployments.

[0003] With the increase of the number of stacked layers of the 3D NAND flash memory, the process of forming the 3D NAND flash memory becomes more and more difficult, which leads to the reduction of the yield and reliability of the 3D NAND flash memory. Therefore, it is necessary to continuously optimize the process of forming the 3D NAND flash memory to continuously improve the yield and reliability of the device. SUMMARY

[0004] The purpose of the present application is to provide a semiconductor device and a manufacturing method thereof to improve the yield and reliability of the device.

[0005] In order to solve the above problems, the present application provides a manufacturing method of a semiconductor device, comprising: forming a semiconductor structure, the semiconductor structure comprising a substrate, a stack structure in a first direction of the substrate, a sacrificial layer between the substrate and the stack structure, and a channel structure penetrating the stack structure and extending into the substrate, the channel structure comprising a functional layer, a channel layer and an insulating layer formed in a radial direction from outside to inside in sequence, the channel structure having a gap in the insulating layer at an end portion of the channel structure close to the sacrificial layer; removing the substrate; removing at least part of the sacrificial layer to expose the gap at the end portion of the channel structure; forming an insulating filling block in the gap, the insulating filling block being located in at least part of the gap.

[0006] After forming the insulating filling block in the gap, the method further comprises:

[0007] removing part of the functional layer at the end portion of the channel structure to expose an end portion of the channel layer at the end portion of the channel structure;

[0008] Forming a semiconductor layer, wherein the stack structure comprises a front side and a back side opposite to each other, the back side is a side close to the substrate, the semiconductor layer is located at the back side of the stack structure, and the semiconductor layer covers the end part of the channel structure after the functional layer is removed.

[0009] Wherein, the insulating filling block is formed in the gap, and specifically includes:

[0010] The insulating filling block is formed in the gap by atomic layer deposition.

[0011] Wherein, the insulating filling block is formed in the gap, and specifically includes:

[0012] The insulating filling block is formed in the gap by deposition, etching back and deposition.

[0013] Wherein, the step of removing the part of the functional layer at the end part of the channel structure further includes:

[0014] The part of the insulating layer and the insulating filling block located in the end part of the channel layer are removed.

[0015] Wherein, the sacrificial layer comprises a first dielectric layer, a first stop layer and a second stop layer in sequence away from the substrate, and the step of removing at least part of the sacrificial layer to expose the gap at the end part of the channel structure specifically includes:

[0016] At least part of the sacrificial layer is removed by chemical mechanical polishing, and the remaining sacrificial layer is flush with the first stop layer in the first direction.

[0017] Wherein, the step of removing the part of the functional layer at the end part of the channel structure to expose the end part of the channel layer at the end part of the channel structure specifically includes:

[0018] The part of the functional layer at the end part of the channel structure is removed by dry etching process, and the remaining functional layer is flush with the second stop layer in the first direction.

[0019] Wherein, the material of the insulating filling block comprises an oxide.

[0020] To solve the above problems, the embodiment of the present application further provides a semiconductor device, comprising: a semiconductor layer; a stack structure comprising alternately stacked gate layers and interlayer insulating layers located on the semiconductor layer; a channel structure penetrating through the stack structure and extending into the semiconductor layer, the channel structure comprising functional layers, channel layers and insulating layers formed in a radial direction from outside to inside in sequence; wherein, the end part of the channel structure close to the sacrificial layer has a gap in the insulating layer, an insulating filling block is located in at least part of the gap, and the channel layer at the end part of the channel structure extends into the semiconductor layer and is directly connected with the semiconductor layer.

[0021] The semiconductor device further comprises a gate slit structure penetrating through the stack structure and dividing the stack structure into several parts, the gate slit structure comprises a second dielectric layer and a conductive layer formed in sequence from outside to inside, and part of the second dielectric layer is located between the conductive layer end and the semiconductor layer.

[0022] The semiconductor device further comprises a gate slit structure penetrating through the stack structure and dividing the stack structure into several parts, the gate slit structure comprises a second dielectric layer and a conductive layer formed in sequence from outside to inside, and part of the second dielectric layer is located between the conductive layer end and the semiconductor layer.

[0023] The application provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: forming a semiconductor structure, the semiconductor structure comprising a substrate, a stack structure in a first direction of the substrate, a sacrificial layer between the substrate and the stack structure, and a channel structure penetrating through the stack structure and extending into the substrate, the channel structure comprising a functional layer, a channel layer and an insulating layer formed in sequence from outside to inside in a radial direction, and the channel structure end close to the sacrificial layer having a gap in the insulating layer; removing the substrate; removing at least part of the sacrificial layer to expose the gap of the channel structure end; and forming an insulating filling block in the gap, the insulating filling block being located in at least part of the gap. By forming the insulating filling block in the gap, the material of the semiconductor layer is prevented from entering the gap when the semiconductor layer is formed subsequently, thereby avoiding electrical interference and causing electrical failure of the semiconductor device, and improving the yield and reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0024] The technical solutions and other beneficial effects of the application will be apparent from the following detailed description of the specific embodiments of the application, combined with the accompanying drawings.

[0025] Figure 1 The manufacturing method of the semiconductor device of the first embodiment of the application is shown in a flow chart.

[0026] Figures 2a to 2e The structure of each step of the manufacturing method of the semiconductor device of the first embodiment of the application is shown in a schematic diagram.

[0027] Figures 3a to 3d The structure of each step of the manufacturing method of the semiconductor device of the second embodiment of the application is shown in a schematic diagram.

[0028] Figure 4 The structure of the semiconductor device of some embodiments of the application is shown in a schematic diagram.

[0029] Figure 5 The structure of the semiconductor device of some embodiments of the application is shown in a schematic diagram. DETAILED DESCRIPTION

[0030] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of the present application.

[0031] It should be understood that although the terms first, second, etc. can be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present application.

[0032] It should be understood that when a component is referred to as being "on" or "connected to" another component, it can be directly on or connected to the other component, or intervening components can also be present. Other words used to describe the relationship between components should be interpreted in a like manner.

[0033] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively close to a substrate and the top side is relatively far from the substrate. A layer can extend over an entire underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any set of horizontal planes that are between and at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, where it can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more electrically conductive layers and contact layers (where contacts, interconnect lines, and one or more dielectric layers are formed).

[0034] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction that is perpendicular to the substrate.

[0035] It should be noted that the drawings provided in the embodiments of the present application only schematically illustrate the basic concepts of the present application, and although only the components related to the present application are shown in the drawings, the actual implementation is not drawn according to the number, shape and size of the components, the actual implementation of each component can be arbitrarily changed, and the component layout pattern can be more complex.

[0036] Please refer to Figure 1The flowchart of the method for manufacturing the semiconductor device according to the first embodiment of the present application is shown in FIG. 1, and the detailed flow is shown in FIG. 2. Figures 2a to 2e The structure diagram of the semiconductor device according to the first embodiment of the present application can include the following.

[0037] S101: Forming a semiconductor structure, which includes a substrate 110, a stack structure (not shown in the figure) located in the first direction of the substrate (e.g. the Z direction), a sacrificial layer 120 located between the substrate 110 and the stack structure, and a channel structure 130 extending through the stack structure and into the substrate 110, the channel structure 130 including a functional layer 131, a channel layer 132 and an insulating layer 133 formed in the radial direction from outside to inside in sequence, and the channel structure 130 having a void 140 located in the insulating layer 133 at the end of the channel structure 130 close to the sacrificial layer 120. Figure 2a

[0038] In addition, it should be noted that, Figures 2a to 2e Only the structures related to the first embodiment of the present application are shown, and the semiconductor device of the present application can further include other components and structures for realizing the complete functions of the device.

[0039] Figure 2a The structure formed in S101 is shown in FIG. 3, which includes the substrate 110, the sacrificial layer 120 and the channel structure 130, wherein the channel structure 130 includes the functional layer 131, the channel layer 132 and the insulating layer 133 formed in the radial direction from outside to inside in sequence, and the channel structure 130 has the void 140 located in the insulating layer 133 at the end of the channel structure 130 close to the sacrificial layer 120.

[0040] Specifically, in the semiconductor structure, the channel structure 130 serves as a data storage unit of the semiconductor device, for realizing the data storage function, the gate layer in the stack structure is used to control the conduction of the channel structure 130, and the interlayer insulating layer is used to separate the gate layers.

[0041] Specifically, the substrate 110 can be a semiconductor substrate 110, such as a silicon (Si), germanium (Ge), SiGe substrate 110, silicon on insulator (SOI) or germanium on insulator (GOI), etc. In other embodiments, the semiconductor substrate 110 can also be a substrate 110 including other elemental semiconductors or compound semiconductors, and can also be a laminated structure, such as Si / SiGe, etc.

[0042] ​The semiconductor structure can be formed by the following steps. After the substrate 110 is provided, a stack structure including alternately stacked interlayer sacrificial layers and interlayer insulating layers can be formed on the substrate 110 by a deposition process. The number of layers of the interlayer sacrificial layers and the interlayer insulating layers can be controlled, for example, by adjusting the parameters of the deposition process to form the interlayer sacrificial layers and the interlayer insulating layers with the desired number of layers. The interlayer insulating layers are used to separate the plurality of interlayer sacrificial layers, and the material of the interlayer insulating layers can be composed of an oxide, such as silicon oxide (SiO2), and the material of the interlayer sacrificial layers can be composed of a nitride, such as silicon nitride (SiN). Since the material of the interlayer sacrificial layers is mostly nitride, it is beneficial to simultaneously form the stack structure including alternately stacked interlayer sacrificial layers and interlayer insulating layers, and thus the stack structure including alternately stacked interlayer sacrificial layers and interlayer insulating layers can be formed by the deposition process.

[0043] Subsequently, a channel hole (not shown in the figure) extending through the stack structure and extending to the substrate 110 can be formed in the stack structure by an etching process, such as dry etching, and then the inner wall of the channel hole can be sequentially filled with one or more fill materials by a deposition process, so as to form a channel structure 130. The fill material can be an insulating material or a conductive material, etc. When the channel structure 130 is formed by sequentially filling the inner wall of the channel hole with one or more fill materials by the deposition process, the innermost insulating layer 133 at the end of the channel structure 130 can not be completely filled, resulting in a gap 140. The end of the channel structure 130 refers to the most terminal position of the channel structure 130 close to the substrate 110, and the same applies hereinafter and will not be repeated. Figure 2a As shown in the figure, the channel structure 130 has inconsistent depths. Since the number of layers of the stack structure is very large, and the alternately stacked gate layers and interlayer insulating layers cannot be directly formed at one time, the deposition process is used to form the alternately stacked interlayer sacrificial layers and interlayer insulating layers at one time, and then the wet etching process is used to remove the interlayer sacrificial layers to form the gate layers at the positions of the original interlayer sacrificial layers, so as to form the stack structure.

[0044] S102 step: removing the substrate 110.

[0045] Specifically, the substrate 110 can be removed by wet etching or dry etching, for example, by using a chemical solution with a certain selectivity, which has a high etching rate for the substrate 110 and a low etching rate for other film layers, so that the substrate 110 can be removed without damaging other film layers. In addition, it should be noted that before the substrate 110 is removed, other processes such as gate line slit, TSV connection structure, etc. can also be formed. Since these structures and the processes for forming these structures are not the focus of the present application, they are omitted.

[0046] S103: removing at least part of the sacrificial layer 120 to expose the gap 140 at the end of the channel structure 130.

[0047] In the embodiment, the sacrificial layer 120 includes a first dielectric layer 121, a first stop layer 122 and a second stop layer 123 in sequence away from the substrate 110. The step of removing at least part of the sacrificial layer 120 to expose the gap 140 at the end of the channel structure 130 includes:

[0048] The at least part of the sacrificial layer 120 is removed by chemical mechanical polishing, so that the remaining sacrificial layer 120 is flush with the first stop layer 122 in the first direction (Z direction).

[0049] Figure 2b The structure formed by the steps S102 and S103 includes the substrate 110, the sacrificial layer 120 and the channel structure 130. The sacrificial layer 120 includes the first dielectric layer 121, the first stop layer 122 and the second stop layer 123. The channel structure 130 has the gap 140 in the insulating layer 133 at the end of the channel structure close to the sacrificial layer 120, and the gap 140 at the end of the channel structure 130 is opened.

[0050] In addition, an intermediate film layer can also be formed between the first dielectric layer 121 and the first stop layer 122, and the material of the intermediate film layer can be polysilicon. As can be seen from the above, the depth of the formed channel hole is inconsistent, so it is necessary to form an intermediate film layer between the first dielectric layer 121 and the first stop layer 122 as a fault tolerance layer for the channel hole with inconsistent depth, for example, to make the channel hole with inconsistent depth at the same depth when the intermediate film layer is removed. The material of the intermediate film layer can be polysilicon (poly). The first dielectric layer 121 is used to form the intermediate film layer on the substrate 110 without changing the properties of the substrate 110, and is used as an isolation layer. The material of the first dielectric layer 121 is generally an oxide, such as silicon oxide.

[0051] Specifically, part of the sacrificial layer 120 can be removed by chemical mechanical polishing (CMP), wherein the sacrificial layer 120 comprises, in sequence from the direction close to the substrate 110 to the direction away from the substrate 110, the first dielectric layer 121, the intermediate film layer, the first stop layer 122 and the second stop layer 123, and the first stop layer 122 serves as a stop layer for chemical mechanical polishing, and when the first stop layer 122 is removed, the chemical mechanical polishing is stopped. At this time, at least part of the sacrificial layer 120 is removed, and the gap 140 at the end of the channel structure 130 is exposed. The material of the first stop layer 122 can be an oxide, such as silicon oxide.

[0052] S104: Forming an insulating filling block 1411 in the gap 140, wherein the insulating filling block 1411 is located in at least part of the gap 140.

[0053] Specifically, the forming of the insulating filling block 1411 in the gap 140 comprises:

[0054] The insulating filling block 1411 is formed in the gap 140 by atomic layer deposition.

[0055] Figure 2c The structure formed in the S104 step is shown, comprising the first stop layer 122, the second stop layer 123, the channel structure 130, and the insulating filling block 1411 located in at least part of the gap 140 at the end of the channel structure.

[0056] Specifically, atomic layer deposition (ALD) is a method of plating a substance on the surface of a substrate in a single-atom film layer by layer. Atomic layer deposition is similar to chemical deposition (CVD), but different from chemical deposition, in that in the process of atomic layer deposition, the chemical reaction of a new layer of atomic film is directly associated with the previous layer, which makes each reaction deposit only one layer of atoms. Therefore, the film layer of atomic layer deposition is more dense, and the insulating filling block 1411 can be formed in the gap 140 by atomic layer deposition. At the same time, the thickness and depth of the insulating filling block 1411 can be controlled by controlling the parameters of atomic layer deposition, such as the gas time of the reaction gas. By using atomic layer deposition in the gap 140, the insulating filling block 1411 with dense film layer and controllable film thickness can be formed, which can effectively block the material of the subsequently formed semiconductor layer 150 from entering the gap 140, avoid causing electrical interference, thereby causing the electrical failure of the device, and further improve the yield and reliability of the device.

[0057] Specifically, the material of the insulating filling block 1411 comprises an oxide.

[0058] Specifically, by forming the insulating filling block 1411 in the gap 140, the material of the semiconductor layer 150 is prevented from filling into the gap 140 when the semiconductor layer 150 is formed subsequently, so as to avoid electrical interference and thus cause the device to fail electrically. Therefore, the material of the insulating filling block 1411 can be an oxide, such as silicon oxide (SiO2).

[0059] In the step S104 of forming the insulating filling block 1411 in the gap 140, after the insulating filling block 1411 is located in at least part of the gap 140, the method further comprises:

[0060] The step S105 of removing part of the functional layer 131 at the end of the channel structure 130 to expose the end of the channel layer 132 at the end of the channel structure 130.

[0061] The step of removing part of the functional layer 131 at the end of the channel structure 130 to expose the end of the channel layer 132 at the end of the channel structure 130 comprises:

[0062] The part of the functional layer 131 at the end of the channel structure 130 is removed by a dry etching process, so that the remaining functional layer 131 is flush with the second stop layer 123 in the first direction (Z direction).

[0063] Figure 2d The structure formed in the step S105 comprises the second stop layer 123, the channel structure 130, and the insulating filling block 1412 located in at least part of the gap 140 at the end of the channel structure 130. Part of the channel layer 132 is higher than the functional layer 131.

[0064] Specifically, the part of the functional layer 131 at the end of the channel structure 130 can be removed by a dry etching process, and the second stop layer 123 can be used as a reaction stop layer for the dry etching process. When the second stop layer 123 is reached, the dry etching process is stopped. At this time, at least part of the functional layer 131 is removed, so that the end of the remaining functional layer 131 is flush with the surface of the second stop layer 123 in the first direction (Z direction), and the end of the channel layer 132 at the end of the channel structure 130 is exposed. In addition, when the dry etching process is performed to remove the functional layer 131, an etching reaction gas with a high selectivity to the material of the functional layer 131 can be selected. When the part of the functional layer 131 at the end of the channel structure 130 is removed, the film layer of the channel layer 132 is not damaged, and a structure as shown in Figure 2dThe partial channel layer 132 is shown higher than the functional layer 131. The material of the second stop layer 123 should be different from the material of the functional layer 131 to be removed, and the material of the second stop layer 123 can be polysilicon (poly). The end of the channel layer 132 refers to the endmost position of the channel layer 132 near one end of the substrate 110, and the same applies hereinafter.

[0065] The step of removing the partial functional layer 131 at the end of the channel structure 130 further comprises:

[0066] The partial insulating layer 133 and the insulating fill block 1412 at the end of the channel layer 132 are removed.

[0067] Please refer to Figure 2d Since the second stop layer 123 is selected as the stop layer of the dry etch process, when the partial functional layer 131 at the end of the channel structure 130 is removed, the partial insulating layer 133 and the insulating fill block 1412 higher than the second stop layer 123 and located at the end of the channel layer 132 are also removed. In addition, the insulating fill block 1412 on the surface of the second stop layer 123 is also removed.

[0068] In addition, it should be noted that when the second stop layer 123 is selected as the stop layer of the dry etch process, in the ideal case, when the etching reaches the second stop layer 123, the etching reaction stops immediately, and a structure as shown in FIG. 6A is formed. Figure 2dAs shown in the structure, the remaining insulating filling block 1412 is flush with the surface of the second stop layer 123 in the first direction (Z direction). In actual cases, when etching reaches the second stop layer 123, the etching reaction does not necessarily stop accurately and immediately, resulting in the possibility that part of the second stop layer 123 is removed or part of the film layer on the second stop layer 123 is not completely removed. When the second stop layer 123 is selected as the stop layer of the dry etching process and part of the second stop layer 123 is removed, at this time, part of the insulating filling block 1412 is also removed, and the remaining insulating filling block 1412 is flush with the surface of the second stop layer 123 in the first direction (Z direction). Since the insulating filling block 1412 still fills the gap, it can effectively isolate the subsequent semiconductor layer 150 material from entering. When the second stop layer 123 is selected as the stop layer of the dry etching process and part of the film layer on the second stop layer 123 is not completely removed, at this time, the surface of the insulating filling block 1412 in the first direction (Z direction) is higher than the surface of the second stop layer 123, and part of the insulating filling block 1412 is located on the surface of the second stop layer 123. Since the insulating filling block 1412 still fills the gap, it can effectively isolate the subsequent semiconductor layer 150 material from entering. In addition, in order to ensure that the channel layer 132 end portion is in communication with the semiconductor layer 150, the surface of the insulating filling block 1412 in the first direction (Z direction) must not be higher than the surface of the channel layer 132 end portion.

[0069] S106 step: forming a semiconductor layer 150, wherein the stack structure includes a front side and a back side facing away from each other, the back side is the side close to the substrate 110, the semiconductor layer 150 is located on the back side of the stack structure, and the semiconductor layer 150 covers the channel structure 130 end portion after removing part of the functional layer 131.

[0070] Figure 2e The structure shown in S106 step includes: substrate 110, second stop layer 123, channel structure 130, at least part of the insulating filling block 1412 in the gap 140 at the end of the channel structure 130, and the semiconductor layer 150 located above the insulating filling layer. Among them, the semiconductor layer 150 covers the channel structure 130 end portion after removing part of the functional layer 131, and is in communication with the channel layer 132.

[0071] Specifically, the semiconductor layer 150 can be a source region or a conductive film layer, without particular limitation. When the semiconductor layer 150 is a source region, the semiconductor layer 150 can be formed by forming one or more polysilicon layers above the second stop layer 123, i.e., at the position of the original substrate 110, and then performing one or more ion implantations on the polysilicon layers. The semiconductor layer 150 is used to provide carriers, which can be electrons or holes, for the semiconductor device. The channel layer 132 is used to provide a path for the movement of the carriers between the semiconductor layer 150 and the functional layer 131, and thus the material of the channel layer 132 needs to be a conductive material, such as polysilicon (poly). The functional layer 131 generally includes a tunneling layer 1311, a charge trap layer 1312, and a blocking layer 1313. By removing the substrate 110 and removing part of the functional layer 131 at the end of the channel structure 130, the poly channel layer 132 at the end of the channel structure 130 is exposed, and the semiconductor layer 150 covers the bottom of the channel structure 130 and the gate line gap structure, so that the semiconductor layer 150 is in direct contact with the poly channel layer 132 of the channel structure 130, and the carriers of the semiconductor layer 150 can move freely in the poly channel layer 132.

[0072] In addition, when the semiconductor layer is a conductive connection film layer, one or more conductive film layers can be formed above the second stop layer 123, i.e., at the position of the original substrate 110. By removing the substrate 110 and removing part of the functional layer 131 at the end of the channel structure 130, the poly channel layer 132 at the end of the channel structure 130 is exposed, and the semiconductor layer 150 covers the bottom of the channel structure 130 and the gate line gap structure, so that the semiconductor layer 150 is in direct contact with the poly channel layer 132 of the channel structure 130, and the semiconductor layer 150 is in communication with the poly channel layer 132.

[0073] The following describes a second embodiment according to the present application, which is different from the scheme of forming the insulating filling block 241 in the gap 240 by atomic layer deposition in the first embodiment. In the second embodiment, the S104 step of forming the insulating filling block 241 in the gap 240 specifically includes:

[0074] The insulating filling block 241 is formed in the gap 240 by deposition, etching back, and deposition.

[0075] It can be understood that the second embodiment is only different from the first embodiment in the forming method of the insulating fill block 241 formed in S104. The first embodiment adopts the atomic layer deposition method to form the insulating fill block 241, while the second embodiment adopts the deposition, etching and deposition method (also known as DED, dep etch dep) to form the insulating fill block 241.

[0076] In addition, it should be noted that, Figures 3a to 3d Only the structures related to the second embodiment of the present application are shown, and the semiconductor device of the present application can further include other components and structures for realizing the complete functions of the device.

[0077] Please refer to Figure 3a For the structure formed in S103 in the second embodiment, it includes the channel structure 230 and the gap 240, the channel structure 230 includes the functional layer 231, the channel layer 232 and the insulating layer 233 distributed in turn from outside to inside, and the width L1 of the gap 240 at the upper end of the channel structure 230 is smaller than the width L2 of the gap 240 at the lower end of the channel structure 230. The functional layer 231 generally includes the tunneling layer 2311, the charge trapping layer 2312 and the blocking layer 2313.

[0078] Please refer to Figures 3b to 3d The structures formed in S104 and S106 in the second embodiment are shown in FIG. 2B and FIG. 2C, respectively. Figure 3d As shown in FIG. 2B and FIG. 2C, it includes the second stop layer 223, the insulating fill block 241 in at least part of the gap 240 at the end of the channel structure 230, and the semiconductor layer 250 above the insulating fill block 241, the channel structure 230 includes the functional layer 231, the channel layer 232 and the insulating layer 233 distributed in turn from inside to outside, and part of the channel layer 232 is in the semiconductor layer 250 and communicates with the semiconductor layer 250. When at least part of the sacrificial layer (not shown in the figure) is removed, the first dielectric layer, the intermediate film layer and the first stop layer 222 in the sacrificial layer are removed, and only the second stop layer 223 as the reaction stop of the dry etching process is left.

[0079] Specifically, based on the characteristics of the etching process, generally, the deep hole formed is wider at the upper part and narrower at the lower part. Based on this, when a channel hole (not shown in the figure) is formed in the stack structure (not shown in the figure) through the etching process, such as dry etching, which penetrates the stack structure and extends to the substrate, the cross-sectional shape of the channel hole in the X direction and the Y direction plane is also wider at the upper part and narrower at the lower part, and then the material is filled in the inner wall of the channel hole multiple times through the deposition process, so as to form the channel structure 230, the cross-sectional shape of the channel structure 230 in the X direction and the Y direction plane is also wider at the upper part and narrower at the lower part. At this time, since the channel hole is not completely filled, there is a gap in the insulating layer at the end of the channel structure, and the channel structure 230 is upside down, correspondingly, the width L1 of the gap 240 at the upper end of the channel structure 230 is less than the width L2 of the gap 240 at the lower end of the channel structure 230.

[0080] Subsequently, when at least part of the sacrificial layer (not shown in the figure) is removed by chemical mechanical polishing to expose the gap 240 at the end of the channel structure, there may still be a remaining part of the gap 240 at the upper end of the channel structure 230, and the width L1 of the gap 240 at the lower end is less than the width L2. At this time, when the insulating filling block 241 is formed in the gap 240 by atomic layer deposition, since the opening at the upper end of the channel structure 230 is small, when atomic layer deposition is performed, it is easy to seal the upper part of the gap 240 completely before the gap 240 is completely filled, that is, to form an incomplete filling insulating filling block 241. When part of the functional layer 231 at the end of the channel structure 230 is removed subsequently, part of the insulating layer 233 and the insulating filling block 241 in the end of the channel layer 232 will also be removed. Since the insulating filling block 241 formed is not completely filled, when part of the insulating layer 233 and the insulating filling block 241 in the end of the channel layer 232 are removed, the insulating filling block 241 used to block the material of the semiconductor layer 250 formed subsequently from entering the gap 240 will be opened, resulting in that the insulating filling block 241 cannot be used to block the material of the semiconductor layer 250 from entering the gap 240, thereby causing the device to fail electrically.

[0081] Based on this, the second embodiment of the present application adopts the mode of deposition, etching back and deposition to form the insulating filling block 241 in the gap 240, that is, when the channel structure 230 with a smaller upper gap 240 is formed after the chemical mechanical polishing is performed to remove at least part of the sacrificial layer, the insulating filling block 241 is first formed in an incomplete filling mode by using the atomic layer deposition mode, then the insulating filling block 241 is opened by using the etching back mode, and then the insulating filling block 241 is formed in a complete filling mode by using the atomic layer deposition mode. The second embodiment of the present application adopts the mode of deposition, etching back and deposition to form the insulating filling block 241 in the gap 240, so as to improve the problem that the gap 240 cannot be completely filled by using the atomic layer deposition when the upper width of the formed gap 240 is small, and further improve the yield and reliability of the device by improving the process.

[0082] The material of the insulating filling block 241 includes an oxide.

[0083] Specifically, the insulating filling block 241 is formed in the gap 240 to block the material of the semiconductor layer 250 from filling into the gap 240 when the semiconductor layer 250 is subsequently formed, so as to cause the electrical interference and thus cause the electrical failure of the semiconductor device. Therefore, the material of the insulating filling block 241 can be an oxide, such as silicon oxide (SiO2). In addition, it should be noted that the steps S101 to S103 and the steps S105 to S106 are basically the same as those of the first embodiment, and thus will not be described herein.

[0084] Based on the manufacturing method of the semiconductor device described in the above embodiments, the embodiment of the present application further provides a semiconductor device, which includes: a semiconductor layer 150; a stack structure located on the semiconductor layer 150 and including alternately stacked gate layers and interlayer insulating layers; a channel structure 130 penetrating the stack structure and extending into the semiconductor layer 150, the channel structure 130 including, in a radial direction, a functional layer 131, a channel layer 132 and an insulating layer 133 formed in sequence from outside to inside; wherein the channel structure 130 has a gap 140 located in the insulating layer 133 at an end of the channel structure 130 close to the sacrificial layer 120, an insulating filling block 1412 is located in at least part of the gap 140, and the channel layer 132 at the end of the channel structure 130 extends into the semiconductor layer 150 and is directly connected with the semiconductor layer 150. The semiconductor layer 150 can be a source region (source) or a conductive film layer, and is not particularly limited. Since the above has been described in detail, it will not be described herein.

[0085] Please refer to Figure 2eFor the semiconductor device of the first embodiment, it comprises a substrate 110, a sacrificial layer 120, a channel structure 130, an insulating filling block 1412 in at least part of the void 140 at the end of the channel structure 130, and a semiconductor layer 150 above the insulating filling layer. The semiconductor layer 150 covers the end of the channel structure 130 after removing part of the functional layer 131 and is in communication with the channel layer 132. In the first embodiment, the insulating filling block 1412 is formed in the void 140 to avoid the material of the semiconductor layer 150 entering the void 140 when the semiconductor layer 150 is formed, causing electrical interference, thereby leading to electrical failure of the device, and further improving the yield and reliability of the device.

[0086] Referring to Figure 3d For the semiconductor device of the second embodiment, it comprises a channel structure 230, an insulating filling block 241 in at least part of the void 240 at the end of the channel structure 230, and a semiconductor layer 250 above the insulating filling block 241. The channel structure 230 comprises a functional layer 231, a channel layer 232, and an insulating layer 233 distributed in sequence from outside to inside. Part of the channel layer 232 is in the semiconductor layer 250 and is in communication with the semiconductor layer 250. In the second embodiment, the insulating filling block 241 is formed in the void 240 to avoid the material of the semiconductor layer 250 entering the void 240 when the semiconductor layer 250 is formed, causing electrical interference, thereby leading to electrical failure of the device, and further improving the yield and reliability of the device.

[0087] In some embodiments, the semiconductor device further comprises a gate slit structure 350 penetrating the stacked structure 320 and dividing the stacked structure 320 into several parts. The gate slit structure 350 comprises a second dielectric layer 351 and a conductive layer 352 formed in sequence from outside to inside. Part of the second dielectric layer 351 is between the end of the conductive layer 352 and the semiconductor layer 360.

[0088] Referring to Figure 4 For the semiconductor device of some embodiments of the present application, the structure schematic diagram comprises a stacked structure 320 comprising alternatingly stacked gate layers 321 and interlayer insulating layers 322, a channel structure 330, an insulating filling block 341 in a void 340, a gate slit structure 350, and a semiconductor layer 360 below the stacked structure 320. The channel structure 330 comprises a functional layer 331, a channel layer 332, and an insulating layer 333 formed in sequence from outside to inside in the radial direction. The gate slit structure 350 comprises a second dielectric layer 351 and a conductive layer 352 formed in sequence from inside to outside.

[0089] It can be understood that the conductive layer 352 is separated from the semiconductor layer by the partial second dielectric layer 351, that is, the gate slit gap structure 350 including the second dielectric layer 351 and the conductive layer 352 only plays a role of dividing the stack structure into several parts, and does not play a role of electrically connecting with the semiconductor layer 360. In some embodiments, by forming the insulating filling block 341 in the gap 340, it is avoided that the material of the semiconductor layer 360 enters into the gap 340 when the semiconductor layer 360 is formed, causing electrical interference, thereby causing the device to fail electrically, and further improving the yield and reliability of the device.

[0090] In addition, it needs to be noted that the second dielectric layer 351 of the gate slit gap structure 350 can be an oxide such as silicon oxide, and the material of the conductive layer 352 of the gate slit gap structure 350 can be polysilicon, which is the same as the following, and will not be repeated here.

[0091] In some embodiments, the semiconductor device further includes a gate slit gap structure 450 penetrating through the stack structure 420 and dividing the stack structure 420 into several parts, the gate slit gap structure 450 including a second dielectric layer 451 and a conductive layer 452 formed in turn from outside to inside, and the conductive layer 452 at the end of the gate slit gap structure 450 extending into the semiconductor layer 460 and communicating with the semiconductor layer 460.

[0092] Please refer to Figure 5 The structure of the semiconductor device of some embodiments is shown in the schematic view, which includes: the stack structure 420 including the gate layer 421 and the interlayer insulating layer 422 stacked alternately, the channel structure 430, the insulating filling block 441 located in the gap 440, the gate slit gap 450, the second dielectric layer 451 and the conductive layer 452 located on the inner wall of the gate slit gap 450, and the semiconductor layer 460 located below the stack structure 420. Among them, the conductive layer 452 extends into the semiconductor layer 460 and directly communicates with the semiconductor layer 460. Among them, the channel structure 430 includes the functional layer 431, the channel layer 432 and the insulating layer 433 formed in turn from outside to inside in the radial direction.

[0093] It can be understood that the conductive layer 452 extends into the semiconductor layer 460 and communicates with the semiconductor layer 460, thereby realizing the communication between the gate line slit gap 450 structure and the semiconductor layer 460, reducing the additional setting of other structures and processes communicating with the semiconductor layer 460, further simplifying the process flow, and greatly reducing the production cost. In the variant, by forming the insulating filling block 441 in the gap 440, it is avoided that the material of the semiconductor layer 460 enters into the gap 440 when the semiconductor layer 460 is formed, causing electrical interference, thereby causing the device to fail electrically, and further improving the yield and reliability of the device.

[0094] Different from the prior art, the semiconductor device and the manufacturing method thereof in the embodiment include: forming a semiconductor structure, the semiconductor structure includes a substrate, a stack structure including alternately stacked gate layers and interlayer insulating layers on the substrate, a sacrificial layer between the substrate and the stack structure, and a channel structure penetrating through the stack structure and extending into the substrate, the channel structure includes a functional layer, a channel layer and an insulating layer sequentially formed from outside to inside in a radial direction, and the channel structure has a gap in the insulating layer at an end of the channel structure close to the sacrificial layer; removing the substrate; removing at least part of the sacrificial layer to expose the gap at the end of the channel structure; and forming an insulating filling block in the gap, the insulating filling block being located in at least part of the gap. By forming the insulating filling block in the gap, the material of the semiconductor layer is prevented from entering the gap when the semiconductor layer is subsequently formed, thereby avoiding electrical interference and causing electrical failure of the semiconductor device, and thus improving the yield and reliability of the device.

[0095] The above description of the embodiments is only used to help understand the technical solutions of the present application and its core idea; those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: forming a semiconductor structure, the semiconductor structure comprising a substrate, a stack structure in a first direction of the substrate, a sacrificial layer between the substrate and the stack structure, and a channel structure extending through the stack structure and into the substrate, the channel structure comprising, in a radial direction, a functional layer, a channel layer, and an insulating layer formed in sequence from outside to inside, the channel structure having a channel structure end portion close to the sacrificial layer, the channel structure end portion having a void in the insulating layer; removing the substrate; removing at least part of the sacrificial layer to expose the void of the channel structure end portion; forming an insulating filling block in the void, the insulating filling block being located in at least part of the void.

2. The method of manufacturing a semiconductor device according to Claim 1, wherein After forming the insulating filling block in the void, the method further comprises: removing part of the functional layer of the channel structure end portion to expose a channel layer end portion of the channel structure end portion; forming a semiconductor layer, wherein the stack structure comprises a front side and a back side opposite to each other, the back side being a side close to the substrate, the semiconductor layer is located on the back side of the stack structure, and the semiconductor layer covers the channel structure end portion after the removal of part of the functional layer.

3. The method of manufacturing a semiconductor device according to Claim 1, wherein The forming of the insulating filling block in the void specifically comprises: forming the insulating filling block in the void by atomic layer deposition.

4. The method of manufacturing a semiconductor device according to Claim 1, wherein The forming of the insulating filling block in the void specifically comprises: forming the insulating filling block in the void by deposition, etching back, and deposition.

5. The method of manufacturing a semiconductor device according to Claim 1, wherein The step of removing part of the functional layer of the channel structure end portion further comprises: removing part of the insulating layer in the channel layer end portion and the insulating filling block.

6. The method of producing a semiconductor device according to Claim 1, wherein The sacrificial layer comprises a first dielectric layer, a first stop layer, and a second stop layer in sequence away from the substrate, and the step of removing at least part of the sacrificial layer to expose the void of the channel structure end portion specifically comprises: removing at least part of the sacrificial layer by chemical mechanical grinding so that the remaining sacrificial layer is flush with the first stop layer in the first direction.

7. The method of producing a semiconductor device according to Claim 6, wherein The step of removing part of the functional layer of the channel structure end portion to expose a channel layer end portion of the channel structure end portion specifically comprises: removing part of the functional layer of the channel structure end portion by a dry etching process so that the remaining functional layer is flush with the second stop layer in the first direction.

8. The method of producing a semiconductor device according to Claim 1, wherein The material of the insulating filling block comprises an oxide.

9. A semiconductor device, characterized by comprising: The semiconductor structure comprises: a semiconductor layer; a stack structure comprising alternately stacked gate layers and interlayer insulating layers on the semiconductor layer; a channel structure extending through the stack structure and into the semiconductor layer, the channel structure comprising, in a radial direction, a functional layer, a channel layer, and an insulating layer formed in sequence from outside to inside; wherein the channel structure has a channel structure end portion close to the gate layers, the channel structure end portion having a void in the insulating layer, at least part of the void having an insulating filling block, and the channel layer of the channel structure end portion extending into the semiconductor layer and directly connected to the semiconductor layer.

10. The semiconductor device of claim 9, wherein, The semiconductor device further comprises a gate slit structure penetrating through the stack structure and dividing the stack structure into several parts, the gate slit structure comprising a second dielectric layer and a conductive layer formed in sequence from outside to inside, and part of the second dielectric layer is located between the conductive layer end and the semiconductor layer.

11. The semiconductor device of claim 9, wherein, The semiconductor device further comprises a gate slit structure penetrating through the stack structure and dividing the stack structure into several parts, the gate slit structure comprising a second dielectric layer and a conductive layer formed in sequence from outside to inside, and the conductive layer at the end of the gate slit structure extends into the semiconductor layer and communicates with the semiconductor layer.

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