An ultrathin super-junction IGBT device and a preparation method thereof

Abstract

The application discloses an ultrathin super-junction IGBT device and a preparation method thereof, which comprises a metallized collector, a P-type collector region on the metallized collector, an N-type FS layer above the P-type collector region, an N-type FS isolation layer above the N-type FS layer, a first N-type epitaxial layer above the N-type FS isolation layer and a second N-type epitaxial layer above the first N-type epitaxial layer, and a MOS structure in the second N-type epitaxial layer. According to the application, the chip thickness is thinned, the forward conduction voltage drop and the switching loss of the device are reduced, the thermal resistance of the device is reduced, and the conduction current capacity is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductors, in particular to an ultrathin super-junction IGBT device and a preparation method thereof. BACKGROUND

[0002] Insulated Gate Bipolar Transistor (IGBT) devices are widely used in solar inverters, new energy vehicles, high-voltage direct current transmission systems, high-speed railways and other fields due to their high input resistance, high breakdown voltage, wide safe operating area, easy driving and other advantages similar to power MOS devices, as well as low on-state voltage of bipolar devices. Currently, Infineon IGBT technology has developed to the seventh generation, adopting Micro Pattern Trench (MPT), Field Stop (FS), Carrier Storage (CS), Injection Enhanced (IE) and other technologies to obtain a good compromise of on-state voltage drop, switching loss and safe operating area. However, limited by the silicon limit, the thickness of the voltage-resisting layer of a 650V IGBT is about 60μm, as shown in FIG. 1, which makes it difficult to further thin the device to reduce the on-state resistance and switching loss and improve the current capacity. Figure 1

[0003] ​Super junction IGBT device is a new type of power semiconductor device which is a new type of power semiconductor device based on the traditional IGBT device structure and adding repeated PN columns in the epitaxial layer. The super junction structure formed by the PN column has similar effect on the optimization of device withstand voltage and forward conduction voltage drop as the super junction MOS device. The introduction of the PN column makes the super junction IGBT device generate a transverse electric field through the mutual depletion of the PN column in addition to the longitudinal electric field of the Pbody-N-Drift junction when the device withstands voltage, which modulates the triangular electric field distribution of the traditional IGBT device into an approximately rectangular distribution, greatly improving the withstand voltage capability of the super junction IGBT device. Under the premise of ensuring a certain breakdown voltage of the device, the concentration of the N-Drift layer can be significantly increased, thereby significantly reducing the forward conduction voltage drop and helping the super junction IGBT device to significantly reduce the conduction loss in application. Under the same current specification, the area of the super junction IGBT device can be greatly reduced, and the chip cost can be reduced. At present, deep trench etching and filling process is one of the two manufacturing methods for manufacturing super junction IGBT devices. The deep trench etching and filling process has a relatively simple process flow, but it has high requirements for etching equipment. Due to the limitation of the etching equipment, the trench is not a perfect rectangular structure during deep trench etching, and the trench width will gradually decrease with the deepening of the reactive ion etching, forming a tapered structure with a wide upper part and a narrow lower part. After filling the P-type silicon single crystal, the narrow bottom of the P column and the N-Drift region are prone to form an electric field concentration when withstanding voltage, so for a 650V conventional SJ-IGBT, as shown in FIG. 1, the length of the entire P column is generally not less than 45μm to ensure the withstand voltage capability of the device, and in addition to the front MOS structure and the back collector structure, the total thickness is generally also not less than 60μm. These all limit the further reduction of the conduction voltage and switching loss of the IGBT device. Figure 2 SUMMARY

[0004] In view of the deficiencies in the prior art, the purpose of the present application is to provide a super-thin super junction IGBT device and a preparation method, which thins the chip thickness, reduces the forward conduction voltage drop and switching loss of the device, and at the same time reduces the thermal resistance of the device and improves the conduction current capability. In order to achieve the above-mentioned purposes and other advantages according to the present application, a super-thin super junction IGBT device is provided, comprising:

[0005] a metalized collector electrode;

[0006] a P-type collector region located on the metalized collector electrode;

[0007] an N-type FS layer located above the P-type collector region;

[0008] an N-type FS isolation layer located above the N-type FS layer;

[0009] ​A first N-type epitaxial layer above the N-type FS isolation layer and a second N-type epitaxial layer above the first N-type epitaxial layer; a MOS structure in the second N-type epitaxial layer.

[0010] Preferably, opposite two sides of the first N-type epitaxial layer are formed into P columns through a deep groove etching and backfilling process.

[0011] Preferably, the second N-type epitaxial layer includes grooves formed through a reactive ion etching, a thermally grown gate oxide layer arranged in the grooves, a heavily doped polysilicon deposited in the gate oxide layer, and P-type body regions formed through a self-alignment process, and the P columns are not connected with the P-type body regions.

[0012] Preferably, the IGBT device further includes mutually independent N-type emitter regions arranged in the P-type body regions on two sides of the grooves, boron phosphorus silicon glass deposited above the second N-type epitaxial layer, and a metallized emitter above the boron phosphorus silicon glass.

[0013] Preferably, the IGBT device further includes a substrate, which is of an N-type or a P-type with an arbitrary doping concentration, and the IGBT device can also be applicable to a P-type channel super-junction IGBT, a silicon carbide or a gallium nitride semiconductor material.

[0014] Preferably, the IGBT device does not include a substrate, and a zone-fusion single crystal silicon is used as the first N-type epitaxial layer.

[0015] Preferably, the N-type FS isolation layer of the back surface of the IGBT device can be implanted or not implanted, and the ions implanted are phosphorus, arsenic, hydrogen or helium.

[0016] Preferably, the second N-type epitaxial layer is formed through epitaxy or through a deep groove etching and backfilling to form P columns on a first N-type epitaxial layer structure, and then through N-type high-energy implantation to compensate the P columns at the top of the first N-type epitaxial layer to be N-type.

[0017] Preferably, the back surface of the IGBT device is ground to the bottom end of the P columns, and then ground for several microns, and then the N-type FS layer and the P-type collector region are implanted.

[0018] A preparation method of an ultrathin super-junction IGBT device, including the following steps:

[0019] S1, forming a first N-type epitaxial layer on an arbitrary substrate wafer, and forming deep grooves on the first N-type epitaxial layer through a reactive ion etching process, and forming P columns through a backfilling P-type silicon single crystal;

[0020] S2, a second N-type epitaxial layer is formed above the first N-type epitaxial layer, a trench is formed on the second N-type epitaxial layer by reactive ion etching, a gate oxide layer is formed in the trench by dry oxidation, heavily doped polysilicon is deposited in the gate oxide layer and is etched back to form a polysilicon gate;

[0021] S3, a P-type body region is formed by a self-alignment process, ion implantation and high-temperature push-trap, and an N-type emitter region is formed in the P-type body region by photolithography implantation;

[0022] S4, boron phosphorus silicon glass is deposited above the second N-type epitaxial layer, high-temperature reflow is performed, contact hole photolithography is performed above the boron phosphorus silicon glass, silicon with a thickness of 3000-5000A is etched, and a metalized emitter is formed by depositing a top surface metal;

[0023] S5, the substrate is flipped and thinned, ground to the bottom of the P column, and then ground for several microns, and a first N-type FS layer implantation is performed;

[0024] S6, a second N-type FS isolation layer implantation and impurity activation are continuously performed;

[0025] S7, a P-type collector region implantation and annealing are performed on one side of the P-type collector region;

[0026] S8, a metal layer is deposited on one side of the P-type collector region to form a metalized collector.

[0027] The present application has the beneficial effects compared with the prior art: a first N-type epitaxial layer is epitaxied on a substrate silicon wafer, a super junction structure is formed by deep trench etching and backfilling process, a surface MOS structure is formed by second epitaxy, and a floating P column is formed. The device is ground to the bottom of the P column by back thinning, and the P column is further thinned by several microns to remove the narrow bottom part, so as to reduce the electric field aggregation at this part when the device withstands voltage. An N-type impurity is injected on the back to form an FS layer, a P-type impurity is injected on the back to form a collector region, hydrogen ions are injected again to form an FS isolation layer, and the P column is compensated to N-type. The device is completed by back sputtering metal. The floating P column ensures that the device works in the conductance modulation mode, and reduces the forward conduction voltage drop of the device. The N-type FS isolation layer formed by hydrogen ion injection can reduce the switching loss when turned off. Thinning to remove part of the bottom of the P column can reduce the electric field aggregation when the device withstands voltage, so as to ensure that the device has sufficient breakdown voltage, and at the same time, the thickness of the N-Drift region is reduced, the forward conduction voltage drop of the device is reduced, and the switching loss is reduced. Thinner chip thickness reduces the thermal resistance of the device, and improves the current capacity of the device. The 650V-level ultra-thin super junction IGBT chip provided by the present application can be thinned to 45μm, the breakdown voltage is greater than 700V, the forward conduction voltage drop is reduced by at least 0.1V compared with the same type of conventional super junction IGBT, the switching loss and thermal resistance are reduced by more than 10%, and the current capacity of the super junction IGBT device is significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is a schematic diagram of a conventional Trench FS-IGBT device structure;

[0029] Figure 2 It is a schematic diagram of a conventional super junction IGBT device structure;

[0030] Figure 3 It is a schematic diagram of the structure of the ultra-thin super junction IGBT device and the preparation method according to the present application;

[0031] Figure 4 It is a schematic diagram of the structure of an embodiment of the ultra-thin super junction IGBT device and the preparation method according to the present application;

[0032] Figure 5-1-1 5 is a schematic diagram of the preparation steps of the ultra-thin super junction IGBT device and the preparation method according to the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0034] Reference Figure 1 -5, an ultra-thin super-junction IGBT device, comprising: a metallized collector 1;

[0035] a P-type collector region 2 located on the metallized collector 1;

[0036] an N-type FS layer 3 located above the P-type collector region 2;

[0037] an N-type FS isolation layer 4 located above the N-type FS layer 3;

[0038] a first N-type epitaxial layer 5 located above the N-type FS isolation layer 4 and a second N-type epitaxial layer 6 located above the first N-type epitaxial layer 5, a MOS structure located in the second N-type epitaxial layer, and an N-type FS isolation layer formed by hydrogen ion implantation, which can reduce switching loss when turned off.

[0039] Further, a P-column 101 is formed in the first N-type epitaxial layer 5 by a deep trench etching and backfilling process, which ensures that the device operates in a conductance modulation mode and reduces the forward conduction voltage drop of the device.

[0040] Further, the second N-type epitaxial layer 6 includes a trench 7 formed by a reactive ion etching, a thermally grown gate oxide layer 8 arranged in the trench 7, a heavily doped polysilicon 9 deposited in the gate oxide layer 8, and a P-type body region 10 formed by a self-alignment process, and the P-column 101 is not connected to the P-type body region 10.

[0041] Further, it also includes mutually independent N-type emitter regions 11 arranged on both sides of the trench 7 and in the P-type body region 10, a boron-phosphorus-silicon glass 12 deposited above the second N-type epitaxial layer 6, and a metallized emitter 13 located above the boron-phosphorus-silicon glass 12.

[0042] Further, it also includes a substrate, which can be of any doping concentration of N-type or of any doping concentration of P-type, and the IGBT device can also be applicable to a P-type channel super-junction IGBT, a silicon carbide or a gallium nitride semiconductor material.

[0043] Further, it does not include a substrate, and the first N-type epitaxial layer 5 is made of a zone-fused single crystal silicon.

[0044] Further, the N-type FS isolation layer 4 on the back of the IGBT device can be implanted or not implanted, and the ions implanted are phosphorus, arsenic, hydrogen or helium, and the back of the IGBT device is the side provided with the N-type FS isolation layer 4.

[0045] Further, the second N-type epitaxial layer 6 is formed by epitaxy or by forming P pillars 101 on the structure of the first N-type epitaxial layer 5 through deep trench etching and backfilling, and then compensating the P pillar part at the top of the first N-type epitaxial layer 5 to N-type through N-type high-energy injection.

[0046] Further, after the back surface of the IGBT device is ground to the bottom end of the P pillar 101, the back surface of the IGBT device is further ground for several microns, then N-type FS layer 3 and P-type collector region 2 injection is performed, after the back surface of the IGBT device is thinned, only one N-type FS layer injection is performed, the isolation of the P-type collector region 2 and the P pillar 101 can be achieved, and the thickness of the N-Drift region can be reduced when the device withstand voltage is reduced, the breakdown voltage of the device is ensured, and the thickness of the N-Drift region is reduced, the forward conduction voltage drop of the device is reduced, and the switching loss is reduced. The thinner chip thickness reduces the thermal resistance of the device and improves the current capacity of the device.

[0047] Reference Figure 5-1-1 5. A preparation method of an ultrathin super-junction IGBT device, comprising the following steps:

[0048] S1, forming a first N-type epitaxial layer 5 on an arbitrary substrate wafer, and forming a deep trench on the first N-type epitaxial layer 5 by using a reactive ion etching process, and forming a P pillar 101 by using backfilling P-type silicon single crystal;

[0049] S2, forming a second N-type epitaxial layer 6 above the first N-type epitaxial layer 5, and forming a groove 7 on the second N-type epitaxial layer 6 by using a reactive ion etching process, and then forming a gate oxide layer 8 in the groove 7 by using dry oxidation, and depositing heavily doped polysilicon in the gate oxide layer 8 and forming a polysilicon gate 9 by reverse etching;

[0050] S3, forming a P-type body region 10 by using ion implantation and high-temperature push well through a self-alignment process, and setting an N-type emitter region 11 in the P-type body region 10 by using photolithography injection;

[0051] S4, depositing boron phosphorus silicon glass 12 above the second N-type epitaxial layer 6, performing high-temperature reflow, performing contact hole photolithography above the boron phosphorus silicon glass 12, etching silicon with a thickness of 3000-5000 angstroms, and depositing upper surface metal to form a metallized emitter 13;

[0052] S5, after the substrate is turned over and thinned, the substrate is ground to the bottom of the P pillar 101, and then the substrate is further ground for several microns, and the first N-type FS layer 3 injection is performed;

[0053] S6, the second N-type FS isolation layer 4 injection and impurity activation are continuously performed;

[0054] S7. P-type collector region 2 implant and anneal on one side of P-type collector region 2.

[0055] S8. Metal layer deposition on one side of P-type collector region 2 to form a metalized collector 1.

[0056] The number of devices and processing steps described herein are intended to simplify the description of the application. Modifications and variations of the application that are obvious to those of skill in the art are intended to be within the scope of the application.

[0057] While embodiments of the application have been disclosed in connection with the specified embodiments, as illustrated and described, it will be readily apparent to those of ordinary skill in the art that modifications and / or improvements can be made thereto without departing from the spirit and scope of the application as set forth in the appended claims and equivalents thereof.

Claims

1. A method of fabricating an ultrathin super junction IGBT device, the ultrathin super junction IGBT device comprising: A metalized collector electrode (1); A P-type collector region (2) on the metalized collector electrode (1); An N-type FS layer (3) above the P-type collector region (2); An N-type FS isolation layer (4) above the N-type FS layer (3); A first N-type epitaxial layer (5) above the N-type FS isolation layer (4) and a second N-type epitaxial layer (6) above the first N-type epitaxial layer (5); a MOS structure in the second N-type epitaxial layer; a P-column (101) formed by deep groove etching and backfilling on opposite sides of the first N-type epitaxial layer (5). The preparation method comprises the following steps: S1, forming a first N-type epitaxial layer (5) on a substrate wafer, forming a deep groove on the first N-type epitaxial layer (5) by using a reactive ion etching process, and forming a P-column (101) by backfilling a P-type silicon single crystal; S2, forming a second N-type epitaxial layer (6) above the first N-type epitaxial layer (5), forming a groove (7) on the second N-type epitaxial layer (6) by using a reactive ion etching process, and then forming a gate oxide layer (8) by dry oxidation in the groove (7), and depositing heavily doped polysilicon in the gate oxide layer (8) and forming a polysilicon gate (9) by etching in reverse; S3, forming a P-type body region (10) by using ion implantation and high-temperature push well through a self-alignment process, and forming an N-type emitter region (11) in the P-type body region (10) by using photolithography implantation; S4, depositing boron phosphorus silicon glass (12) on the second N-type epitaxial layer (6), performing high-temperature reflow, performing contact hole photolithography on the boron phosphorus silicon glass (12), etching silicon with a thickness of 3000-5000A, and depositing an upper surface metal to form a metalized emitter (13); S5, after the substrate is turned over, thinning is performed, and after grinding to the bottom of the P-column (101), the substrate is further ground by several microns, and a first N-type FS layer (3) is implanted; S6, a second N-type FS isolation layer (4) is implanted and impurity activation is performed; S7, P-type collector region (2) implantation and annealing are performed on one side of the P-type collector region (2); S8, a metal layer is deposited on one side of the P-type collector region (2) to form a metalized collector electrode (1).

2. The method of claim 1, wherein the super-thin super-junction IGBT device is prepared by the steps of: The N-type FS isolation layer (4) on the back of the IGBT device can be implanted or not implanted, and the ions implanted are phosphorus, arsenic, hydrogen or helium.

3. The method of claim 2, wherein the method further comprises: The second N-type epitaxial layer (6) is formed by epitaxy or by forming a P-column (101) on the structure of the first N-type epitaxial layer (5) by deep groove etching and backfilling, and then compensating the P-column part at the top of the first N-type epitaxial layer (5) to N-type by N-type high-energy implantation.

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