Method, apparatus, and system for configuring NAND die

Abstract

Embodiments of the present application provide a method for configuring a NAND die, a NAND die, a NAND storage device, a host device, and a storage system. The method includes: receiving trim option information from a host device, wherein the trim option information includes a trim command, the trim command being used to indicate a desired trim option from a plurality of pre-set trim options; selecting a target trim profile from a plurality of trim profiles based on the trim option information, wherein the plurality of trim profiles are pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die; and configuring the NAND die using the target trim profile.

Description

Technical Field

[0001] In general, the present application relates to storage technology, and more particularly, to a method for configuring a NAND die, a NAND die, a NAND storage device, a host device, and a storage system. Background Art

[0002] NAND memory devices have experienced rapid growth in recent years due to their superior storage performance. Typically, NAND memory devices can retain stored data for an extremely long period of time without the need for applied voltage. Furthermore, NAND memory devices offer very high read rates, and stored data can be easily erased and rewritten. Consequently, NAND memory devices have become widely used in various devices, such as mobile computing devices and servers. Summary of the Invention

[0003] In view of the above problems in the prior art, embodiments of the present application provide a method for configuring a NAND die, a NAND die, a NAND storage device, a host device, and a storage system.

[0004] On the one hand, an embodiment of the present application provides a method for configuring a NAND die, comprising: receiving trim option information from a host device, wherein the trim option information includes a trim command, and the trim command is used to indicate an intended trim option from a plurality of pre-set trim options; based on the trim option information, selecting a target trim profile from a plurality of trim profiles, wherein the plurality of trim profiles are pre-stored in the NAND die, each trim option is associated with a trim profile, and each trim profile includes a set of operating parameters associated with the NAND die; and configuring the NAND die using the target trim profile.

[0005] On the other hand, an embodiment of the present application provides a method for configuring a NAND die, comprising: generating trim option information, wherein the trim option information includes a trim command, and the trim command is used to indicate an expected trim option from a plurality of pre-set trim options; sending the trim option information to the NAND die so that the NAND die selects a target trim profile from a plurality of trim profiles for configuration based on the trim option information, wherein the plurality of trim profiles are pre-stored in the NAND die, each trim option is associated with a trim profile, and each trim profile includes a set of operating parameters associated with the NAND die.

[0006] On the other hand, an embodiment of the present application provides a NAND die, comprising: a memory cell array; at least one peripheral circuit coupled to the memory cell array, wherein the at least one peripheral circuit is configured to: receive trimming option information from a host device, wherein the trimming option information includes a trimming command, and the trimming command is used to indicate an expected trimming option from a plurality of pre-set trimming options; based on the trimming option information, select a target trimming profile from a plurality of trimming profiles, wherein the plurality of trimming profiles are pre-stored in the NAND die, each trimming option is associated with a trimming profile, and each trimming profile includes a set of operating parameters associated with the NAND die; and configure the NAND die using the target trimming profile.

[0007] On the other hand, an embodiment of the present application provides a NAND memory device, comprising: at least one NAND die, wherein: each NAND die includes a memory cell array and at least one peripheral circuit coupled to the memory cell array; for any first NAND die among the at least one NAND die, the at least one peripheral circuit in the first NAND die is configured to: receive trim option information from a host device, wherein the trim option information includes a trim command, and the trim command is used to indicate an expected trim option from a plurality of pre-set trim options; based on the trim option information, select a target trim profile from a plurality of trim profiles, wherein the plurality of trim profiles are pre-stored in the first NAND die, each trim option is associated with a trim profile, and each trim profile includes a set of operating parameters associated with the first NAND die; and configure the first NAND die using the target trim profile.

[0008] On the other hand, an embodiment of the present application provides a host device, comprising: a processor; a memory configured to store executable code, wherein the executable code, when executed by the processor, causes the processor to perform the following operations: generate trimming option information, wherein the trimming option information includes a trimming command, and the trimming command is used to indicate an expected trimming option from a plurality of pre-set trimming options; and send the trimming option information to a NAND die so that the NAND die selects a target trimming profile from a plurality of trimming profiles for configuration based on the trimming option information, wherein the plurality of trimming profiles are pre-stored in the NAND die, each trimming option is associated with a trimming profile, and each trimming profile includes a set of operating parameters associated with the NAND die.

[0009] On the other hand, an embodiment of the present application provides a storage system, comprising: a NAND storage device comprising at least one NAND die; a host device coupled to the at least one NAND die, wherein: the host device is configured to: generate trim option information for a first NAND die among the at least one NAND die, wherein the trim option information comprises a trim command, the trim command being used to indicate an expected trim option among a plurality of pre-set trim options; send the trim option information to the first NAND die; the first NAND die is configured to: select a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the first NAND die, each trim option being associated with a trim profile, each trim profile comprising a set of operating parameters associated with the first NAND die; and configure the first NAND die using the target trim profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other purposes, features and advantages of the embodiments of the present application will become more apparent through a more detailed description of the embodiments of the present application in conjunction with the accompanying drawings, wherein the same figure marks generally represent the same elements in the embodiments of the present application.

[0011] Figure 1A is a schematic diagram of an application environment in which some embodiments of the present application can be applied.

[0012] Figure 1B Further shown is a schematic block diagram of a NAND die according to some embodiments.

[0013] Figure 2 is a schematic flow chart of a method for configuring a NAND die according to some embodiments.

[0014] Figure 3 An example of the storage format of trim commands and verification codes in a NAND die is shown according to some embodiments.

[0015] Figure 4 is a method for configuring a NAND die according to some embodiments.

[0016] Figure 5A and Figure 5B is a flow chart of an example of a method for configuring a NAND die.

[0017] Figure 6 is a schematic block diagram of a host device according to some embodiments. DETAILED DESCRIPTION

[0018] The subject matter described herein will now be discussed with reference to various embodiments. It should be understood that these embodiments are discussed solely to enable those skilled in the art to better understand and implement the subject matter described herein and are not intended to limit the scope, applicability, or examples set forth in the claims. The functions and arrangements of the elements discussed may be varied without departing from the scope of the claims. Various embodiments may omit, replace, or add various processes or components as needed.

[0019] As used herein, the term "including" and its variations are open-ended terms meaning "including but not limited to". The term "based on" means "based at least in part on". The terms "one embodiment" and "an embodiment" mean "at least one embodiment". The term "another embodiment" means "at least one other embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other definitions may be included below, whether explicit or implicit, and the definition of a term is consistent throughout the specification unless the context clearly indicates otherwise.

[0020] NAND storage devices typically include one or more NAND dies to implement storage functions. Generally, NAND dies can be divided into different grades based on their performance, and different grades can correspond to different application scenarios. For example, NAND dies are currently generally divided into enterprise, mobile, and client grades. For example, enterprise-grade NAND dies can typically be used in enterprise-level servers, mobile-grade NAND dies can be used in mobile phones, tablet devices, and client-grade NAND dies can be used in laptops, etc. Each grade of NAND dies may have different performance emphases. For example, enterprise-grade NAND dies may focus on fast response and good reliability, mobile-grade NAND dies may focus on fast response, and client-grade NAND dies may focus on low cost while meeting demand. Of course, as technology develops, market demand, and so on, NAND dies may be divided into other grades.

[0021] Different grades of NAND die usually have different trim settings. That is, different grades can correspond to different trim settings. Trim settings can be understood as a set of operating parameter settings for the NAND die, such as voltage, current, temperature compensation, power, etc. Through the trim settings, the NAND die can be configured to achieve the performance corresponding to the grade. Currently, after determining the grade of the NAND die, the corresponding trim settings are usually pre-configured in the NAND die. However, in some cases, the grade of the NAND die may need to be adjusted, then the corresponding trim settings need to be reconfigured or tested for the NAND die, and such a process may be time-consuming and complicated.

[0022] In view of this, embodiments of the present application provide a technical solution for configuring NAND dies, which will be described in detail below in conjunction with various embodiments.

[0023] Figure 1A is a schematic diagram of an application environment in which some embodiments of the present application can be applied.

[0024] exist Figure 1A In the example of FIG, the application environment 100 may include a host device 110 and a NAND storage device 120. It should be understood that, depending on the specific implementation, the application environment 100 may also include other devices, which are not shown here for clarity of illustration and are not limited herein.

[0025] The host device 110 may generally be any device configured to interact with a NAND memory device, such as a central processing unit (CPU), an application specific integrated circuit (ASIC), a microcontroller, and the like.

[0026] The NAND memory device 120 may include one or more NAND dies 130. For example, the NAND memory device 120 may be packaged with one NAND die, or may be packaged with multiple NAND dies, which is not limited herein.

[0027] Generally, the NAND storage device 120 can be applied in various scenarios. For example, the NAND storage device 120 can be applied to a solid-state drive (SSD), an embedded multi-media card (eMMC), a smartphone, a tablet device, etc. When the NAND storage device 120 is in different scenarios, the host device 110 can be implemented by different devices accordingly.

[0028] For example, when the NAND memory device 120 is applied to an SSD, the host device 110 may be implemented by a controller in the SSD. Figure 1A The application environment 100 may represent a schematic structure of an SSD. Of course, the examples herein are only for ease of understanding. In actual implementation, an SSD may also include other modules or units, which are not limited herein.

[0029] For example, when the NAND memory device 120 is applied to an eMMC, the host device 110 may be implemented by an eMMC controller in the eMMC. Figure 1A The application environment 100 may represent a schematic structure of an eMMC. Of course, the eMMC may also have other modules or units, which are not limited herein.

[0030] For another example, when the NAND storage device 120 is under test, the host device 110 may be implemented by a test platform. Figure 1A The application environment may represent a test environment for a NAND memory device.

[0031] Typically, a NAND die may be obtained by dicing a processed wafer, each NAND die having its own memory cell array and peripheral circuits. In some cases, a NAND die may be referred to as a NAND die or other names. Figure 1B Further shown is a schematic structural diagram of a NAND die according to some embodiments. Figure 1B As shown, NAND die 130 may include a memory cell array 131 and various appropriate peripheral circuits coupled to the memory cell array 131. In some implementations, the memory cell array 131 may be an array of 3D NAND memory cells, which may be in the form of vertically extending NAND memory strings.

[0032] Furthermore, the peripheral circuits may include various appropriate circuits, e.g. Figure 1B , a control logic unit 132, a page buffer / sense amplifier 133, a column decoder / bit line driver 134, an I / O circuit 135, a row decoder / word line driver 136, a register 137, an interface (I / F) 138, a data bus 139, etc. It should be understood that Figure 1B The various circuits shown in the figure are merely examples. In different implementation scenarios, the NAND die may include fewer or more peripheral circuits, which is not limited herein.

[0033] In addition, the functions of the aforementioned circuits are well known in the art and will not be described in detail here. For example, the control logic unit 132 can be coupled to various other peripheral circuits to implement control or management functions for the NAND die, such as controlling the peripheral circuits in the NAND die and thereby controlling the memory cell array 131. In different implementations, the control logic unit 132 may also have other names, such as a microcontroller unit (MCU), a state machine, etc.

[0034] As previously described, the host device 110 can interact with the NAND die 130. For example, Figure 1B From the above, the host device 110 can communicate with the control logic unit 132 through the interface 138, for example, by sending commands, information, etc. related to the embodiments of this document to the control logic unit 132 through the interface 138. Then, the control logic unit 132 can control or manage the NAND die 130 according to the commands, information, etc. of the host device.

[0035] Furthermore, as previously mentioned, the NAND memory device 120 may include multiple NAND dies. In this case, the host device 110 may interact with each NAND die individually, for example, to change its trimming settings. The following describes in detail the process of the host device interacting with a particular NAND die. In the case of multiple NAND dies, the host device's interaction process with each NAND die is similar.

[0036] Figure 2 is a schematic flow chart of a method for configuring a NAND die according to some embodiments. For example, a NAND die may be Figure 1A and Figure 1B NAND die 130, Figure 2 The method 200 may be performed by Figure 1B The control logic unit 132 in is executed.

[0037] like Figure 2 As shown, in step 202, trimming option information may be received from a host device. The trimming option information may include at least a trimming command. The trimming command may be used to indicate a desired trimming option from a plurality of pre-set trimming options.

[0038] In step 204 , a target trimming profile may be selected from a plurality of trimming profiles based on the trimming option information.

[0039] In some embodiments, multiple trimming options may be associated with multiple trimming profiles, respectively. Specifically, each trimming option may be associated with a trimming profile. The trimming profile may include trimming settings. Specifically, the trimming profile may include a set of operating parameters associated with the NAND die, such as current, voltage, power, temperature compensation, etc. For example, the trimming profile may include specific values ​​of each parameter, a range of values, a function for determining the parameter, etc. Multiple trimming profiles may be pre-stored in the NAND die. For example, multiple trimming profiles may be pre-stored in the configuration block of the NAND die. In addition, the correspondence between multiple trimming options and multiple trimming profiles may also be pre-stored in the NAND die, such as in the configuration block of each NAND die.

[0040] In step 206, the NAND die may be configured using the target trim configuration file.

[0041] As can be seen from the above, in the embodiments of the present application, multiple trimming options can be pre-set and multiple trimming profiles associated with the multiple trimming options can be pre-stored in the NAND die. In this way, the trimming settings for the NAND die can be simply and efficiently readjusted. For example, when the grade of the NAND die needs to be adjusted, an appropriate trimming profile can be directly selected from the multiple trimming profiles pre-stored in the NAND die to configure the NAND die, without having to temporarily load the trimming profile to be used into the NAND die, thereby enabling efficient trimming of the NAND die.

[0042] In some embodiments, multiple trimming options can be divided into default trimming options and non-default trimming options. For example, among multiple trimming options, one trimming option can be the default trimming option, and the remaining trimming options can be non-default trimming options. For example, in one implementation, four trimming options can be pre-set, namely trimming option 0, trimming option 1, trimming option 2, and trimming option 3. Trim option 0 can be designated as the default trimming option, while the remaining trimming options are non-default trimming options. In some cases, different trimming options can correspond to different levels of NAND die.

[0043] In this case, whether the expected trimming option is a default trimming option or a non-default trimming option may be determined in step 204. Then, a target trimming profile may be selected from a plurality of trimming profiles based on the determination result for the expected trimming option.

[0044] In some embodiments, when it is determined that the expected trimming option is the default trimming option, a trimming profile corresponding to the expected trimming option may be selected from a plurality of trimming profiles as a target trimming profile.

[0045] In some embodiments, the intended trimming option may be a non-default trimming option. In this case, security verification may be performed to prevent the host device from arbitrarily changing the trimming settings of the NAND die. For example, in some implementations, the host device may also send a verification code associated with the intended trimming option. In one implementation, the host device may send the trimming command and the verification code together. For example, in addition to the aforementioned trimming command, the aforementioned trimming option information may also include a verification code. In step 204, if it is determined that the intended trimming option is a non-default trimming option, a first preset security code associated with the intended trimming option from among multiple preset security codes may be obtained. Multiple preset security codes may be pre-stored in the NAND die. Each trimming option may be associated with a preset security code.

[0046] Then, it can be determined whether the received verification code matches the first preset security code.A target trimming profile can be selected based on the matching result of the verification code and the first preset security code.

[0047] For example, if it is determined that the received verification code matches the first preset security code, the host device may be deemed authorized to adjust the trim settings of the NAND die. Therefore, a trim profile associated with the desired trim options may be selected from the plurality of trim profiles as a target trim profile.

[0048] If it is determined that the received verification code does not match the first preset security code, it can be considered that the host device may not be authorized to adjust the trim settings of the NAND die. Therefore, a trim profile associated with the default trim option can be selected from multiple trim profiles as the target trim profile.

[0049] In this way, it is possible to ensure that the trim settings of the NAND die are changed when the host device is authorized, thereby effectively preventing potential problems caused by arbitrarily changing the trim settings of the NAND die.

[0050] In different embodiments, the verification code can be implemented in different ways.

[0051] For example, the verification code may be represented by a single value (eg, 8 bits), which can reduce signaling overhead.

[0052] For another example, to further improve security, the verification code can be represented by a combination of multiple values, each of which can have the same or different sizes. For example, each value can be 8 bits in size. In this case, the host device can send multiple values ​​to the NAND die at once, or send multiple values ​​to the NAND die separately. After receiving the multiple values, the NAND die can combine the multiple values ​​to form the verification code to be used.

[0053] In some implementations, after receiving the trimming option information from the host device, the control logic unit may store the trimming option information as a parameter at a designated location for subsequent command execution, recording, querying, and the like.

[0054] For example, a trim command can be represented by 2 bits. If a verification code is present and represented by a single value, the verification code can be represented by 8 bits. To prevent write errors or information loss, the verification code can be stored in a backup format. For example, the verification code can be stored as three backups, each of which occupies 8 bits.

[0055] For another example, a trim command can be represented by 2 bits. If a verification code exists and the verification code is represented by a combination of multiple values, each value can be represented by 8 bits. In this way, the entire verification code can occupy 3 bytes.

[0056] Figure 3 An example of the storage format of trim commands and verification codes in a NAND die is shown according to some embodiments.

[0057] The following will be combined Figure 1A and 1B Describe the application scenario Figure 3 For example, after the control logic unit 132 receives the trim command and the verification code from the host device 110 , the control logic unit 132 may write the information into a designated location.

[0058] exist Figure 3 In the example of , it is assumed that there are four trimming options: trimming option 0 which is the default option, and trimming options 1, 2, and 3 which are non-default options.

[0059] In addition, Figure 3 In the example of , bits 0-1 of parameter P1 can be used to store a trim command, specifically, a trim option. Bits 2-7 of parameter P1 can be reserved. Parameters P2, P3, and P4 can store a verification code received from the host device.

[0060] As mentioned above, the verification code can be represented by a single value or a combination of multiple values. For ease of understanding, examples will be given below.

[0061] (1) For implementations where the verification code is represented by a single value:

[0062] Parameters P2, P3, and P4 can store the same value to serve as a backup.

[0063] If the trim command indicates trim option 0, then a verification code is not required. In this case, bits 0-1 of parameter P1 may store a value representing trim option 0, such as 00. Since no verification code was received, parameters P2, P3, and P4 may be empty.

[0064] If the trim command indicates trim option 1, and the verification code associated with it is assumed to be value X, bits 0-1 of parameter P1 may store a value representing trim option 1, such as 01. Parameters P2, P3, and P4 may each use 8 bits to store value X.

[0065] If the trim command indicates trim option 2, and assume the verification code associated therewith is value Y.

[0066] In this case, bits 0-1 of parameter P1 may store a value representing pruning option 2, such as 10. Parameters P2, P3, and P4 may each use 8 bits to store the value Y.

[0067] If the trim command indicates trim option 3, and the verification code associated therewith is assumed to be value Z.

[0068] In this case, bits 0-1 of parameter P1 may store a value representing pruning option 3, such as 11. Parameters P2, P3, and P4 may each use 8 bits to store the value Z.

[0069] (2) For the implementation method where the verification code is represented by a combination of multiple values:

[0070] Here, it is assumed that the verification code is represented by a combination of three values.

[0071] If the trim command indicates trim option 0, then a verification code is not required. In this case, bits 0-1 of parameter P1 may store a value representing trim option 0, such as 00. Since no verification code was received, parameters P2, P3, and P4 may be empty.

[0072] If the trim command indicates trim option 1, and the verification code associated with it is ABC, that is, the verification code associated with trim option 1 consists of three values: A, B, and C. Combining these three values ​​can form the verification code associated with trim option 1, and ABC is used here to represent the combination of these three values. In this case, bits 0-1 of parameter P1 can store the value representing trim option 1, such as 01. Parameters P2, P3, and P4 can each store 8 bits of the values ​​A, B, and C, respectively. For example, ABC can be 24'h77696E.

[0073] If the trim command indicates trim option 2, and the verification code associated with it is DEF, then the verification code associated with trim option 1 consists of three values: D, F, and F. Combining these three values ​​forms the verification code associated with trim option 2, and DEF is used here to represent this combination of three values. In this case, bits 0-1 of parameter P1 can store a value representing trim option 2, such as 10. Parameters P2, P3, and P4 can each store 8 bits of the values ​​D, E, and F, respectively. For example, DEF can be 24'h676F64.

[0074] If the trim command indicates trim option 3, and the verification code associated with it is GHI, then the verification code associated with trim option 3 consists of three values: G, H, and I. Combining these three values ​​can form the verification code associated with trim option 3, and GHI is used here to represent this combination of three values. In this case, bits 0-1 of parameter P1 can store a value representing trim option 3, such as 11. Parameters P2, P3, and P4 can each store 8 bits of the values ​​G, H, and I, respectively. For example, GHI can be 24'h796D74.

[0075] In addition, multiple preset security codes can be pre-programmed in the configuration block of the NAND die. As can be seen from the above, the verification code and the preset security code can correspond. That is, the size of the verification code and the preset security code is the same. For example, for the previous example with four trimming options (one of which is the default option), three preset security codes are required. If each preset security code is represented by a combination of three values, these preset security codes can occupy a total of 3×3 bytes. If each preset security code is represented by a single value, these preset security codes can occupy a total of 3×1 byte. In actual operation, after the NAND die is powered on, these preset security codes can be loaded into the static random access memory (SRAM) in the NAND die. In this way, when the trimming option needs to be verified, the corresponding preset security code can be read directly from the SRAM.

[0076] Figure 4 is a method for configuring a NAND die according to some embodiments. Figure 4 The method 400 may be performed by a host device in communication with a NAND die, such as Figure 1A A host device 110 is shown. Figure 4 Method 400 with Figure 3 Therefore, some repeated descriptions will be omitted here.

[0077] like Figure 4 As shown, in step 402, trimming option information may be generated.

[0078] The trimming option information may include a trimming command. The trimming command may be used to indicate a desired trimming option among a plurality of preset trimming options.

[0079] In step 404, trim option information may be sent to the NAND die, so that the NAND die may select a target trim profile from a plurality of trim profiles for configuration based on the trim option information.

[0080] Multiple trim profiles can be pre-stored in the NAND die. Each trim option can be associated with a trim profile. Each trim profile can include a set of operating parameters associated with the NAND die.

[0081] In some embodiments, the plurality of trimming options may be divided into default trimming options and non-default trimming options.

[0082] In case the intended trimming option is a non-default trimming option, the trimming option information may also include a verification code associated with the intended trimming option.

[0083] In some embodiments, the trimming option information may include multiple values ​​that together constitute a verification code.

[0084] For ease of understanding, the following description will be given in conjunction with specific examples. It should be understood that the following examples do not limit the scope of this application.

[0085] Figure 5A and Figure 5B 1 is a flow chart of an example of a method for configuring a NAND die. Figure 5A and Figure 5B .

[0086] In step 501 , the host device 110 may send a power-up command sequence to the control logic unit 132 of the NAND die 130 .

[0087] In step 502 , the control logic unit 132 may control the NAND die 130 to power on according to a power-on command sequence of the host device 110 .

[0088] In step 503 , the host device 110 may send a device initialization command to the control logic unit 132 .

[0089] In step 504 , the control logic unit 132 may control the initialization of the NAND die 130 according to the device initialization command.

[0090] These operations are known in the art and therefore will not be described in detail here.

[0091] In step 505, the host device 110 may send trim option information to the control logic unit 132. As previously described, the trim option information may include a trim command indicating the intended trim option. Additionally, if the intended trim option is a non-default trim option, the trim option information may also include an associated verification code. The specific implementation of the trim command may depend on the specific application scenario. For example, if the NAND memory device 120 includes only a single NAND die, the trim command may be a set feature command, such as represented by EFh (hexadecimal). If the NAND memory device 120 includes multiple NAND dies, the trim command may be a set feature by LUN command, such as represented by D5h (hexadecimal), thereby indicating the trim option and the associated NAND die. Thus, in the embodiments herein, the trim settings can be flexibly changed for each NAND die of the NAND memory device, thereby meeting various application requirements.

[0092] In step 506, the host device 110 may send a hard reset command to the control logic unit 132. For example, the hard reset command may be denoted as FDh, which is used to initiate a process of modifying trim settings.

[0093] In step 507 , the control logic unit 132 may select a trimming configuration file based on the trimming option information.

[0094] In step 508, the control logic unit 132 may load the selected trim configuration file. For example, the control logic unit 132 may configure the NAND die 130 using the selected trim configuration file.

[0095] It should be understood that the above steps do not necessarily follow Figure 5A The execution order mainly depends on the specific implementation method.

[0096] For further understanding, the following Figure 5B The specific process of step 507 is described in the example of Figure 5B In the example shown in FIG, 4 , it is assumed that there are four trimming options, namely trimming options 0-3, and that trimming option 0 is the default trimming option. Furthermore, it is assumed that trimming options 0-3 are associated with trimming profiles 0-3, respectively. Furthermore, it is assumed that trimming option 1 is associated with a preset security code ABC, trimming option 2 is associated with a preset security code DEF, and trimming option 3 is associated with a preset security code GHI.

[0097] In step 507 , the control logic unit 132 may determine whether the desired trimming option is trimming option 0. If so, the control logic unit 132 may select trimming profile 0.

[0098] If the expected trimming option is not trimming option 0, control logic unit 132 may determine whether the expected trimming option is trimming option 1. If so, control logic unit 132 may determine whether the verification code in the trimming option information matches ABC. If so, control logic unit 132 may select trimming profile 1. If not, control logic unit 132 may select the default trimming profile 0.

[0099] If the expected trimming option is not trimming option 1, control logic unit 132 may determine whether the expected trimming option is trimming option 2. If so, control logic unit 132 may determine whether the verification code in the trimming option information matches DEF. If so, control logic unit 132 may select trimming profile 2. If not, control logic unit 132 may select the default trimming profile 0.

[0100] If the expected trimming option is not trimming option 2, control logic unit 132 may determine whether the expected trimming option is trimming option 3. If so, control logic unit 132 may determine whether the verification code in the trimming option information matches the GHI. If so, control logic unit 132 may select trimming profile 3. If not, control logic unit 132 may select the default trimming profile 0.

[0101] It can be seen that in this way, it is possible to ensure that the host device modifies the trimming settings of the NAND die under authorization, thereby avoiding potential risks caused by arbitrarily modifying the trimming settings of the NAND die.

[0102] Figure 6 is a schematic block diagram of a host device according to some embodiments. For example, Figure 6 The host device 600 may correspond to the host device 110 of FIG. 1 .

[0103] like Figure 6 As shown, host device 600 may include a processor 602 and a memory 604. Processor 602 and memory 604 may be connected together via a bus.

[0104] The memory 604 may store executable codes, which, when executed by the processor 602 , may enable the processor 602 to implement the specific processes described above with respect to the host device.

[0105] According to the above description, it can be seen that the embodiment of the present application can provide a NAND die, which can include a memory cell array and a peripheral circuit coupled thereto. For example, the peripheral circuit can include a control logic unit. For example, an example of a NAND die can be Figure 1B NAND die 130 is shown.

[0106] In addition, embodiments of the present application may provide a storage system that may include a host device and a NAND storage device. For example, an example of a storage system may be Figure 1A An application scenario 100 is provided. An example of a host device may be a host device 110, and an example of a NAND storage device may be a NAND storage device 120. For example, the storage system may be an SSD, an eMMC, or other similar storage systems.

[0107] Embodiments of the present application also provide a machine-readable storage medium. The machine-readable storage medium may store executable code. When executed, the executable code may cause a machine to implement the specific process described above with respect to the control logic unit of the NAND die.

[0108] Embodiments of the present application also provide a machine-readable storage medium. The machine-readable storage medium may store executable code. When executed, the executable code may enable a machine to implement the specific process described above with respect to the host device.

[0109] It should be noted that not all steps and units in the above processes and system structure diagrams are required, and some steps or units can be omitted according to actual needs. The execution order of each step is not fixed and can be determined as needed. The device structure described in the above embodiments can be a physical structure or a logical structure, that is, some units may be implemented by the same physical entity, or some units may be implemented by multiple physical entities, or may be implemented by certain components in multiple independent devices.

[0110] Each unit has been described in conjunction with various devices and methods. Each unit can be implemented using electronic hardware, computer software or any combination thereof. Whether each unit is implemented as hardware or software will depend on the specific application and the overall design constraints imposed on the system. As an example, each unit provided in this disclosure, any part of each unit or any combination of each unit can be implemented as a microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gate logic, a discrete hardware circuit and other suitable processing components configured to perform the various functions described in this disclosure.

[0111] The foregoing description of the present disclosure is provided to enable any person skilled in the art to implement or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is intended to be consistent with the widest range of principles and novel features disclosed herein.

Claims

1. A method for configuring a NAND die, comprising: receiving trimming option information from a host device, wherein the trimming option information includes a trimming command, and the trimming command is used to indicate a desired trimming option among a plurality of preset trimming options; selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die; configuring the NAND die using the target trim configuration file; wherein the plurality of trimming options are divided into default trimming options and non-default trimming options; Select the target trimming profile, including: determining that the expected trimming option is a non-default trimming option, wherein the trimming option information further includes a verification code associated with the expected trimming option; Perform security verification based on the verification code; The target trimming profile is selected from the plurality of trimming profiles based on a result of the security verification.

2. The method according to claim 1, wherein Select the target trimming profile to include: determining that the expected trimming option is a default trimming option; A trim profile associated with the desired trim option is selected from the plurality of trim profiles as the target trim profile.

3. The method according to claim 1, wherein Performing security verification based on the verification code includes: Obtaining a first preset security code associated with the desired trimming option from a plurality of preset security codes, wherein the plurality of preset security codes are pre-stored in the NAND die, each trimming option being associated with a preset security code; Determine whether the verification code matches the first preset security code.

4. The method according to claim 3, wherein: Selecting the target trimming profile from the plurality of trimming profiles based on a result of the security verification comprises: If it is determined that the verification code matches the first preset security code, selecting a trimming profile associated with the desired trimming option from the plurality of trimming profiles as the target trimming profile; If it is determined that the verification code does not match the first preset security code, a trimming profile associated with the default trimming option is selected from the plurality of trimming profiles as the target trimming profile.

5. The method according to claim 3 or 4, wherein: The trimming option information includes a plurality of values ​​that together constitute the verification code; Before determining whether the verification code matches the first preset security code, the method further includes: The multiple values ​​are combined to obtain the verification code.

6. A method for configuring a NAND die, comprising: generating trimming option information, wherein the trimming option information includes a trimming command, the trimming command being used to indicate a desired trimming option among a plurality of preset trimming options; sending the trim option information to a NAND die so that the NAND die selects a target trim profile from a plurality of trim profiles for configuration based on the trim option information, wherein the plurality of trim profiles are pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die, The plurality of trimming options are divided into default trimming options and non-default trimming options, and in the case that the expected trimming option is a non-default trimming option, the trimming option information further includes a verification code associated with the expected trimming option.

7. The method according to claim 6, wherein: The trimming option information includes a plurality of values ​​that together constitute the verification code.

8. A NAND die, comprising: memory cell array; at least one peripheral circuit coupled to the memory cell array, wherein the at least one peripheral circuit is configured to: receiving trimming option information from a host device, wherein the trimming option information includes a trimming command, and the trimming command is used to indicate a desired trimming option among a plurality of preset trimming options; selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die; configuring the NAND die using the target trim configuration file, wherein the plurality of trimming options are divided into default trimming options and non-default trimming options; Select the target trimming profile, including: determining that the expected trimming option is a non-default trimming option, wherein the trimming option information further includes a verification code associated with the expected trimming option; Perform security verification based on the verification code; The target trimming profile is selected from the plurality of trimming profiles based on a result of the security verification.

9. A NAND storage device, comprising: At least one NAND die, wherein: Each NAND die includes a memory cell array and at least one peripheral circuit coupled to the memory cell array; For any first NAND die among the at least one NAND die, at least one peripheral circuit in the first NAND die is configured as follows: receiving trimming option information from a host device, wherein the trimming option information includes a trimming command, and the trimming command is used to indicate a desired trimming option among a plurality of preset trimming options; selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the first NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the first NAND die; configuring the first NAND die using the target trim configuration file, wherein the plurality of trim options are divided into default trim options and non-default trim options; Select the target trimming profile, including: determining that the expected trimming option is a non-default trimming option, wherein the trimming option information further includes a verification code associated with the expected trimming option; Perform security verification based on the verification code; The target trimming profile is selected from the plurality of trimming profiles based on a result of the security verification.

10. A host device, comprising: processor; A memory configured to store executable code, which, when executed by the processor, causes the processor to perform the following operations: generating trimming option information, wherein the trimming option information includes a trimming command, and the trimming command is used to indicate a desired trimming option among a plurality of preset trimming options; sending the trim option information to a NAND die so that the NAND die selects a target trim profile from a plurality of trim profiles for configuration based on the trim option information, wherein the plurality of trim profiles are pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die, The plurality of trimming options are divided into default trimming options and non-default trimming options, and in the case that the expected trimming option is a non-default trimming option, the trimming option information further includes a verification code associated with the expected trimming option.

11. A storage system comprising: A NAND memory device comprising at least one NAND die; a host device coupled to the at least one NAND die, wherein: The host device is configured to: generating trim option information for a first NAND die of the at least one NAND die, wherein the trim option information includes a trim command, the trim command being used to indicate a desired trim option among a plurality of preset trim options; sending the trim option information to the first NAND die; The first NAND die is configured as: selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the first NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the first NAND die; configuring the first NAND die using the target trim configuration file, wherein the plurality of trim options are divided into default trim options and non-default trim options; Select the target trimming profile, including: determining that the expected trimming option is a non-default trimming option, wherein the trimming option information further includes a verification code associated with the expected trimming option; Perform security verification based on the verification code; The target trimming profile is selected from the plurality of trimming profiles based on a result of the security verification.

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