Silicon epitaxy method for FDSOI

Abstract

The present application relates to the field of semiconductor integrated circuit manufacturing technology, and specifically to a silicon epitaxial method for FDSOI. The method comprises the following steps: providing a semiconductor structure, forming a groove in the semiconductor structure; sequentially forming a first etching barrier layer and an etching reaction layer on the surface of the semiconductor structure; performing an etching operation on the etching reaction layer, wherein the etching stop surface of the etching operation is located in the first etching barrier layer covering the bottom surface of the groove, and in the etching reaction layer covering the side surface of the groove; making the etching reaction layers remaining on each side surface of the groove form sidewall structures respectively; making the space between the sidewall structures at the groove position be filled with a second etching barrier layer; etching the sidewall structure and the first etching barrier layer under the sidewall structure to form a groove structure; removing the second etching barrier layer and the remaining first etching barrier layer; making the silicon substrate at the position of the groove and the groove structure grow epitaxially upward to form epitaxial silicon, and the epitaxial silicon is flush with the top silicon layer.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a FDSOI silicon epitaxial growth method. Background Art

[0002] SOI (Silicon-On-Insulator) introduces a buried layer between the top silicon and the silicon substrate. The buried layer forms an insulator, and the top silicon is a semiconductor film located on the insulator, thereby reducing parasitic capacitance, improving the chip clock, and reducing chip current leakage.

[0003] FDSOI (Fully Depleted Silicon On Insulator) has become an option for SOI due to its superior gate control capability and lower leakage current.

[0004] Figure 1 The cross-sectional structure diagram of the FDSOI device manufactured by the related technology is shown. In the related technology, the FDSOI process will Figure 1 The buried layer 130 in the shown part is removed by photolithography and etching to form a trench 100 and expose the silicon substrate 120 under the buried layer 130. Then, a certain amount of silicon is grown through an epitaxial process to fill the trench 100, so that the epitaxial silicon 140 is connected to the top silicon 110 as a whole for use in the device.

[0005] However, since the bottom of the trench 100 is flat, and the top silicon 110 and the silicon substrate 120 grow silicon at the same time during the epitaxial process, the silicon on both sides of the trench 100 grows faster than the bottom, resulting in that after the epitaxial process is completed, the silicon growth on both sides of the trench 100 is greater than the silicon in the middle of the trench 100, resulting in the formation of silicon on the left and right sides of the trench 100. Figure 1 The protrusions shown make the silicon surface uneven, which is not conducive to subsequent processes. Summary of the invention

[0006] The present application provides a silicon epitaxial growth method for FDSOI, which can solve the problem of protrusions formed on the left and right sides of the groove and uneven silicon surface in the related art.

[0007] In order to solve the technical problem described in the background technology, the present application provides a silicon epitaxial method of FDSOI, and the silicon epitaxial method of FDSOI includes the following steps performed in sequence:

[0008] A semiconductor structure is provided, wherein a trench is formed in the semiconductor structure; the silicon substrate at the position of the trench is exposed, and the semiconductor structure other than the position of the trench comprises a silicon substrate, an insulating layer, a top silicon layer and an isolation dielectric layer stacked in sequence from bottom to top;

[0009] According to the surface morphology of the semiconductor structure, sequentially forming a first etching stop layer and an etching reaction layer on the surface of the semiconductor structure;

[0010] Performing an etching operation on the etching reaction layer, wherein an etching stop surface of the etching operation is located in the first etching barrier layer covering the bottom surface of the groove and in the etching reaction layer covering the side surface of the groove;

[0011] The etching reaction layers remaining on the sides of the grooves are respectively formed into sidewall structures;

[0012] So that at the position of the groove, the space between the sidewall structures is filled with a second etching stop layer;

[0013] Using the second etch barrier layer as a protective structure, etching the sidewall structure and the first etch barrier layer under the sidewall structure to form a groove structure, wherein the groove structure is recessed downward from the bottom surface of the trench;

[0014] removing the second etch stop layer and the remaining first etch stop layer;

[0015] The silicon substrate at the position of the trench and the recess structure is epitaxially grown upward to form epitaxial silicon until the epitaxial silicon is flush with the upper surface of the top silicon layer.

[0016] Optionally, a semiconductor structure is provided, wherein a trench is formed in the semiconductor structure; the silicon substrate at the position of the trench is exposed, and the semiconductor structure other than the position of the trench comprises a silicon substrate, an insulating layer, a top silicon layer and an isolation dielectric layer stacked sequentially from bottom to top, comprising:

[0017] Providing a semiconductor substrate, the semiconductor substrate comprising a silicon substrate, an insulating layer, a top silicon layer and an isolation dielectric layer stacked in sequence from bottom to top;

[0018] Defining a groove pattern on the isolation dielectric layer by a photolithography process;

[0019] Based on the groove pattern, the semiconductor substrate is etched to form a groove, so that the silicon substrate at the groove position is exposed, and the remaining semiconductor base layer forms a semiconductor structure.

[0020] Optionally, the step of sequentially forming a first etching stop layer and an etching reaction layer on the surface of the semiconductor structure according to the surface morphology of the semiconductor structure includes:

[0021] According to the surface morphology of the semiconductor structure with grooves, a first etching stop layer with a thickness ranging from 20Å to 100Å and an etching reaction layer with a thickness ranging from 50Å to 200Å are sequentially formed on the surface of the semiconductor structure.

[0022] Optionally, the material of the first etch stop layer is silicon dioxide.

[0023] Optionally, the material of the etching reaction layer is polysilicon or silicon nitride.

[0024] Optionally, the step of filling the space at the groove position except the sidewall structure with the second etch stop layer comprises:

[0025] Coating a protective medium on the semiconductor structure having the first etch stop layer and the sidewall structure, wherein the protective medium at least fills the trench having the sidewall structure;

[0026] The protective medium is etched to expose the upper end of the sidewall structure; the remaining protective medium is filled in the groove between the sidewall structures to form a second etching stop layer.

[0027] Optionally, the material of the protective medium is photoresist.

[0028] Optionally, the protective medium is etched so that the upper end of the sidewall structure is exposed; the remaining protective medium is filled in the groove between the sidewall structures, and in the step of forming a second etch barrier layer, the thickness of the formed second etch barrier layer ranges from 100Å to 1000Å.

[0029] Optionally, the side wall structure and the first etch barrier layer under the side wall structure are etched using the second etch barrier layer as a protective structure to form a groove structure, wherein the groove structure is recessed downward from the bottom surface of the groove, and the depth of the recessed groove structure from the bottom surface of the groove is 50Å to 500Å.

[0030] The technical solution of the present application includes at least the following advantages: the groove structure formed by the FDSOI silicon epitaxial method provided by the present application can offset the excessive growth of silicon on both sides of the groove during the subsequent epitaxial process, so that the upper surface of the formed epitaxial silicon is flush with the upper surface of the top silicon, which is beneficial to the subsequent process. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1A schematic cross-sectional structure diagram of a FDSOI device manufactured using a related technology is shown;

[0033] Figure 2 A flow chart of a FDSOI silicon epitaxial method provided by an embodiment of the present application is shown;

[0034] Figure 2a A schematic cross-sectional structure diagram of a semiconductor structure with a trench is shown;

[0035] Figure 2b Shown in Figure 2a Based on the structure shown, a schematic diagram of a cross-sectional structure of the device after completing step S22;

[0036] Figure 2c Shown in Figure 2b Based on the structure shown, a schematic diagram of a cross-sectional structure of the device after completing step S23;

[0037] Figure 2d Shown in Figure 2c Based on the structure shown, a schematic diagram of a cross-sectional structure of the device after completing step S24;

[0038] Figure 2e Shown in Figure 2d Based on the structure shown, a schematic diagram of a cross-sectional structure of the device after completing step S25;

[0039] Figure 2f Shown in Figure 2e Based on the structure shown, a schematic diagram of a cross-sectional structure of the device after completing step S26;

[0040] Figure 2g Shown in Figure 2f Based on the structure shown, a schematic diagram of the device cross-sectional structure after completing step S27 is shown. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0042] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0043] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0044] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0045] Figure 2 A flow chart of a FDSOI silicon epitaxial method provided in one embodiment of the present application is shown.

[0046] Reference Figure 2 The FDSOI silicon epitaxial growth method includes the following steps S21 to S27 performed in sequence, wherein:

[0047] S21: providing a semiconductor structure, in which a trench is formed; the silicon substrate at the position of the trench is exposed, and the semiconductor structure other than the position of the trench includes a silicon substrate, an insulating layer, a top silicon layer and an isolation dielectric layer stacked in sequence from bottom to top.

[0048] Reference Figure 2a , which shows a schematic cross-sectional structure diagram of a semiconductor structure with trenches.

[0049] The semiconductor structure 200 with the trench 210 includes a silicon substrate 201, an insulating layer 202, a top silicon layer 203 and an isolation dielectric layer 204 stacked in sequence from bottom to top, and the trench 210 extends downward from the upper surface of the isolation dielectric layer 204, so that the silicon substrate 201 is exposed from the trench 210. The bottom surface of the trench 210 is the upper surface of the silicon substrate 201, and the side surfaces of the trench 210 are, from bottom to top, the side surfaces of the insulating layer 202, the side surfaces of the top silicon layer 203 and the side surfaces of the isolation dielectric layer 204.

[0050] Optionally, the following steps S211 to S213 may be performed to obtain Figure 2a A semiconductor structure 200 is shown.

[0051] Step S211: providing a semiconductor substrate, wherein the semiconductor substrate comprises a silicon substrate, an insulating layer, a top silicon layer and an isolation dielectric layer stacked in sequence from bottom to top.

[0052] Step S212: defining a groove pattern on the isolation dielectric layer through a photolithography process.

[0053] Step S213: Based on the groove pattern, the semiconductor substrate is etched to form a groove, so that the silicon substrate at the groove position is exposed, and the remaining semiconductor base layer forms a semiconductor structure. Figure 2a The semiconductor structure 200 is shown, and a trench 210 is formed in the semiconductor structure 200 .

[0054] The insulating layer may be made of silicon dioxide, and the isolation dielectric layer may include a silicon dioxide layer and a silicon nitride layer stacked in sequence from bottom to top.

[0055] Step S22: forming a first etching stop layer and an etching reaction layer in sequence on the surface of the semiconductor structure according to the surface morphology of the semiconductor structure.

[0056] Reference Figure 2b , which shows that in Figure 2a Based on the structure shown, a schematic diagram of the device cross-sectional structure after completing step S22 is shown.

[0057] exist Figure 2a The surface of the semiconductor structure 200 is formed Figure 2b The first etch barrier layer 221 and the etch reaction layer 222 are shown, and the first etch barrier layer 221 and the etch reaction layer 222 cover the bottom surface and the side surface of the trench 210 and the upper surface of the isolation dielectric layer 204 .

[0058] The material of the first etch stop layer 221 may be silicon dioxide, and the thickness may be any thickness in the range of 20Å to 100Å. The material of the etch reaction layer 222 may be polysilicon or silicon nitride, and the thickness may be any thickness in the range of 50Å to 200Å.

[0059] Step S23: performing an etching operation on the etching reaction layer, wherein an etching stop surface of the etching operation is located in the first etching barrier layer covering the bottom surface of the groove and in the etching reaction layer covering the side surface of the groove; so that the etching reaction layers remaining on each side surface of the groove form sidewall structures respectively.

[0060] Reference Figure 2c , which shows that in Figure 2b Based on the structure shown, a schematic diagram of the device cross-sectional structure after completing step S23 is shown.

[0061] Due to the anisotropy of etching, the etching reaction layer 222 covering the front surface of the semiconductor structure 200 is completely etched away, and the etching reaction layer 222 covering the side surface of the semiconductor structure 200 remains.

[0062] The front side of the semiconductor structure 200 includes the bottom surface of the trench 210 and the upper surface of the isolation dielectric layer 204, that is, the two sides of the trench 210 retain the lower part of the etching reaction layer 222 to form Figure 2c Two sidewall structures 230 are shown.

[0063] In addition to the sidewall structure 230, the etching reaction layer 222 located at the bottom surface of the groove 210 is completely removed, and the etching reaction layer 222 located at the upper surface of the isolation dielectric layer 204 is also completely removed, so that except for the portion of the first etching barrier layer 221 located under the sidewall structure 230, the other first etching barrier layer 221 located at the bottom surface of the groove 210 is exposed, and the first etching barrier layer 221 located on the upper surface of the isolation dielectric layer 204 is exposed.

[0064] Step S24: filling the space between the sidewall structures at the groove position with a second etching stop layer.

[0065] Reference Figure 2d , which shows that in Figure 2c Based on the structure shown, a schematic diagram of the device cross-sectional structure after completing step S24 is shown.

[0066] The formed second etch stop layer 240 fills the trench space between the two sidewall structures 230 in the trench 210 , and the upper ends of the two sidewall structures 230 are exposed from the upper surface of the second etch stop layer 240 .

[0067] The second etch stop layer 240 may be a combination of any one or more of a photoresist, an anti-reflective coating (BARC), and an organic dielectric layer (ODL), and the thickness may be any thickness in the range of 100Å to 1000Å.

[0068] Among them, you can Figure 2c Based on the structure shown in FIG. 1 , through the following steps S241 to S242, a Figure 2d The device structure shown.

[0069] Step S241: Figure 2cAs shown, a protective medium is coated on the semiconductor structure 200 with the first etch stop layer 221 and the spacer structure 230 , and the protective medium at least fills the trench 210 with the spacer structure 230 .

[0070] Step S242: etching the protective dielectric formed after step S241 is completed, so that the upper end of the sidewall structure 230 is exposed; the remaining protective dielectric is filled in the groove 210 between the sidewall structures 230 to form Figure 2d A second etch stop layer 240 is shown.

[0071] Step S25: using the second etch barrier layer as a protection structure, etching the sidewall structure and the first etch barrier layer under the sidewall structure to form a groove structure, wherein the groove structure is recessed downward from the bottom surface of the trench.

[0072] Reference Figure 2e , which shows that in Figure 2d Based on the structure shown, a schematic diagram of the device cross-sectional structure after completing step S25 is shown.

[0073] Figure 2d The second etch stop layer 240 shown in the figure can protect the position covered by it during step S25, so that the first etch stop layer 221 and the bottom surface of the groove 210 covered by the second etch stop layer 240 are not etched, while the first etch stop layer 221 and the bottom surface of the groove 210 not covered by the second etch stop layer 240 are etched, forming Figure 2e The groove structure 250 is shown as being recessed downward from the bottom surface of the trench 210 .

[0074] The depth of the groove structure 250 that is recessed downward from the bottom surface of the groove 210 can be set according to needs. The depth of the groove structure 250 that is recessed downward from the bottom surface of the groove 210 can be set to any depth within the range of 50Å to 500Å.

[0075] Step S26: removing the second etch stop layer and the remaining first etch stop layer.

[0076] Reference Figure 2f , which shows that in Figure 2e Based on the structure shown, a schematic diagram of the device cross-sectional structure after completing step S26 is shown.

[0077] Removal Figure 2e After the second etch stop layer 240 and the remaining first etch stop layer 221 are etched, recess structures 250 are formed at the bottom of the trench 210 near the two sides of the trench 210 .

[0078] Step S27: causing the silicon substrate at the positions of the trench and the recess structure to grow epitaxially upward to form epitaxial silicon until the epitaxial silicon is flush with the upper surface of the top silicon layer.

[0079] Reference Figure 2g , which shows that in Figure 2f Based on the structure shown, a schematic diagram of the device cross-sectional structure after completing step S27 is shown.

[0080] Figure 2e and Figure 2f The groove structure 250 can offset the overgrown silicon on both sides of the trench 210 during the epitaxial growth process of step S27, so that the upper surface of the formed epitaxial silicon 260 is flush with the upper surface of the top silicon 203.

[0081] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A silicon epitaxial method of FDSOI, characterized in that: The silicon epitaxial growth method of the FDSOI comprises the following steps performed in sequence: A semiconductor structure is provided, wherein a trench is formed in the semiconductor structure; the silicon substrate at the position of the trench is exposed, and the semiconductor structure other than the position of the trench comprises a silicon substrate, an insulating layer, a top silicon layer and an isolation dielectric layer stacked in sequence from bottom to top; According to the surface morphology of the semiconductor structure, sequentially forming a first etching stop layer and an etching reaction layer on the surface of the semiconductor structure; Performing an etching operation on the etching reaction layer, wherein an etching stop surface of the etching operation is located in the first etching barrier layer covering the bottom surface of the groove and in the etching reaction layer covering the side surface of the groove; The etching reaction layers remaining on the sides of the grooves are respectively formed into sidewall structures; So that at the position of the groove, the space between the sidewall structures is filled with a second etching stop layer; Using the second etch barrier layer as a protective structure, etching the sidewall structure and the first etch barrier layer under the sidewall structure to form a groove structure, wherein the groove structure is recessed downward from the bottom surface of the trench; removing the second etch stop layer and the remaining first etch stop layer; The silicon substrate at the position of the trench and the recess structure is epitaxially grown upward to form epitaxial silicon until the epitaxial silicon is flush with the upper surface of the top silicon layer.

2. The FDSOI silicon epitaxial growth method according to claim 1, characterized in that: A semiconductor structure is provided, wherein a trench is formed in the semiconductor structure; a silicon substrate at the position of the trench is exposed, and the semiconductor structure other than the position of the trench comprises a silicon substrate, an insulating layer, a top silicon layer and an isolation dielectric layer stacked in sequence from bottom to top, including: Providing a semiconductor substrate, the semiconductor substrate comprising a silicon substrate, an insulating layer, a top silicon layer and an isolation dielectric layer stacked in sequence from bottom to top; Defining a groove pattern on the isolation dielectric layer by a photolithography process; Based on the groove pattern, the semiconductor substrate is etched to form a groove, so that the silicon substrate at the groove position is exposed, and the remaining semiconductor base layer forms a semiconductor structure.

3. The FDSOI silicon epitaxial growth method according to claim 1, characterized in that: The step of sequentially forming a first etching stop layer and an etching reaction layer on the surface of the semiconductor structure according to the surface morphology of the semiconductor structure comprises: According to the surface morphology of the semiconductor structure with the grooves, a first etching stop layer with a thickness ranging from 20Å to 100Å and an etching reaction layer with a thickness ranging from 50Å to 200Å are sequentially formed on the surface of the semiconductor structure.

4. The FDSOI silicon epitaxial growth method according to claim 1, characterized in that: The material of the first etch stop layer is silicon dioxide.

5. The FDSOI silicon epitaxial growth method according to claim 1, characterized in that: The material of the etching reaction layer is polysilicon or silicon nitride.

6. The FDSOI silicon epitaxial growth method according to claim 1, characterized in that: The step of filling the space at the groove position except the sidewall structure with the second etching stop layer comprises: Coating a protective medium on the semiconductor structure having the first etch stop layer and the sidewall structure, wherein the protective medium at least fills the trench having the sidewall structure; The protective medium is etched to expose the upper end of the sidewall structure; the remaining protective medium is filled in the groove between the sidewall structures to form a second etching stop layer.

7. The silicon epitaxial growth method of FDSOI according to claim 6, characterized in that The material of the protective medium is photoresist.

8. The FDSOI silicon epitaxial growth method according to claim 6, characterized in that: The protective medium is etched so that the upper end of the sidewall structure is exposed; the remaining protective medium is filled in the groove between the sidewall structures, and in the step of forming a second etch barrier layer, the thickness of the formed second etch barrier layer ranges from 100 Å to 1000 Å.

9. The FDSOI silicon epitaxial growth method according to claim 1, characterized in that: The second etch barrier layer is used as a protective structure to etch the side wall structure and the first etch barrier layer under the side wall structure to form a groove structure. In the step of the groove structure being recessed downward from the bottom surface of the groove, the depth of the groove structure recessed downward from the bottom surface of the groove is 50Å to 500Å.

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