Digital-to-analog conversion circuits and electronic equipment

Abstract

A digital-to-analog conversion circuit and electronic device, the circuit comprising: an R-2R ladder network module, comprising a plurality of first resistors, a second resistor, and control switches corresponding to the second resistors, wherein the plurality of first resistors are connected in series, and one end of the second resistor is sequentially connected to one end of the corresponding first resistor to form a node from low to high; one end of the control switch is connected to the other end of a second resistor, and the other end is grounded to form a ground path; one end of the remaining control switches is connected to the other ends of the remaining second resistors to form a resistance arm from low to high, and the other end responds to an input digital coding signal; and an impedance adjustment module, comprising an impedance element corresponding to the first resistor, the impedance element being connected between adjacent nodes, and the impedance value of the impedance element being equal to the impedance value of the control switch. The present invention can prevent resistance mismatch problems in the resistance arm during switching, thereby improving the conversion accuracy of the digital-to-analog converter.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a digital-to-analog conversion circuit and electronic equipment. Background Art

[0002] A DAC (digital-to-analog converter) is a device that converts digital signals into analog signals and is widely used in digital circuits. Commonly used inverted-T network DACs require dual power supplies, an inverter, and a large number of resistors of varying values, making them inconvenient and bulky. An R-2R architecture DAC is a simple resistor network that doesn't require an op amp. An n-bit R-2R resistor network DAC requires n-1 R resistors and n+1 2R resistors, requiring only two resistance values. This makes it easy to fabricate manually. In applications where precision is less critical, resistors can be used directly, reducing costs.

[0003] However, in the DAC with R-2R architecture, resistance mismatch problem will occur when the resistor arms are switched. Summary of the Invention

[0004] In view of this, the present application provides a digital-to-analog conversion circuit and an electronic device to solve the problem of resistance mismatch occurring in existing digital-to-analog conversion circuits when resistance arms are switched.

[0005] The present application provides a digital-to-analog conversion circuit, comprising: an R-2R ladder network module, comprising a plurality of first resistors, a second resistor, and control switches corresponding to the second resistors, wherein the plurality of first resistors are connected in series, and one end of the second resistors is sequentially connected to one end of the corresponding first resistor to form nodes from low to high; one end of one of the control switches is connected to the other end of one of the second resistors, and the other end of the control switch is grounded to form a ground path; one end of the remaining control switches is connected to the other end of the remaining second resistors to form resistance arms from low to high, and the other end of the control switch is responsive to an input digital coding signal to control the resistance arms to connect to a reference voltage or ground to achieve digital-to-analog conversion; an impedance adjustment module, comprising impedance elements corresponding to the first resistors, the impedance elements being connected between adjacent nodes, and the impedance value of the impedance elements being equal to the impedance value of the corresponding control switches.

[0006] The digital-to-analog conversion circuit of the present application achieves a fixed resistance value for the equivalent resistance seen from each node into the ground path by connecting an impedance element between adjacent nodes, with the impedance value of the impedance element being equal to the impedance value of the control switch, thereby preventing resistance mismatch problems in the resistor arms during switching and improving the conversion accuracy of the digital-to-analog converter.

[0007] Optionally, the equivalent resistance between each node and the ground path is the sum of the resistance value of the corresponding second resistor, the impedance value of the impedance element, and the impedance value of the control switch. By controlling the impedance value of the impedance element, the equivalent resistance between each node and the ground path can be achieved, that is, the sum of the resistance value of the corresponding second resistor, the impedance value of the impedance element, and the impedance value of the control switch is equal and fixed. This prevents resistance mismatch problems in the resistor arms during switching, thereby improving the conversion accuracy of the digital-to-analog converter.

[0008] Optionally, the impedance value of the impedance element is positively correlated with the number of control switches. When the number of control switches increases, the impedance value of the corresponding impedance element also increases accordingly. This impedance value may cause a significant resistance mismatch problem in the resistor arm during switching. To prevent this significant resistance mismatch problem in the resistor arm during switching, the impedance value of the corresponding impedance element is also increased accordingly to offset the impedance of the control switches.

[0009] Optionally, the control switch is an inverter or a path selector.

[0010] Optionally, the impedance element includes at least one of the following: a resistor, an inductor, a transmission gate device, and a switch device.

[0011] Optionally, when the control switch is an inverter; the inverter includes a first PMOS transistor and a first NMOS transistor; the gates of the first PMOS transistor and the first NMOS transistor are connected and serve as input ends, the drains are connected and serve as output ends, the source of the first PMOS transistor is connected to a high voltage, and the source of the first NMOS transistor is connected to a low voltage; the on-impedance and off-impedance of the inverter are equal.

[0012] By implementing the control switch through an inverter, the input data can be reversed, noise interference can be suppressed, and the equivalent resistance of the ground path formed by each node to the second resistor and the control switch can be fixed, which can prevent the resistance mismatch problem of the resistor arm during switching and improve the conversion accuracy of the digital-to-analog converter.

[0013] Optionally, when the impedance element is the transmission gate device, the transmission gate device includes a second PMOS transistor and a second NMOS transistor; the sources of the second PMOS transistor and the second NMOS transistor are connected and serve as the first end of the transmission gate, the drains are connected and serve as the second end of the transmission gate, the gate of the second PMOS transistor is connected to a low voltage, and the source of the second NMOS transistor is connected to a high voltage; the impedance of the transmission gate is the impedance of the second PMOS transistor and the second NMOS transistor connected in parallel. Due to the small size of the transmission gate device, using the transmission gate as the impedance element greatly reduces the chip area.

[0014] Optionally, the impedance value of the transmission gate is equal to the impedance value of the inverter.

[0015] By selecting a transmission gate with the same impedance value as the inverter as the impedance element, the classic R-2R structure DAC can achieve an unmatched R-(2R+R S ) structure to waste area structure, and then to [(R+R T )-(2R+R S +R T )]=[(R+R S )-(2R+2R S )]=[R-2R] structure conversion can achieve a fixed equivalent resistance from each node to the ground path formed by the second resistor and the control switch, which can prevent the resistance mismatch problem of the resistor arm during switching and improve the conversion accuracy of the digital-to-analog converter.

[0016] Optionally, the impedance of the transmission gate satisfies the following formula:

[0017]

[0018] Among them, R T is the impedance of the transmission gate, μ p 、μ n is the carrier mobility, C ox is the gate capacitance per unit area, W is the gate length, L is the gate width, VDD is the gate voltage, V THP 、V THN is the threshold voltage, R is the impedance of the first resistor, R s is the impedance of the inverter, Vref is the reference voltage, and || represents a parallel relationship.

[0019] An electronic device comprises the digital-to-analog conversion circuit.

[0020] The digital-to-analog conversion circuit and electronic device of the present application, by connecting an impedance element between adjacent nodes, and the impedance value of the impedance element is equal to the impedance value of the control switch, so as to achieve a fixed resistance value for the equivalent resistance seen from each node into the ground path, thereby preventing resistance mismatch problems from occurring in the resistor arm during switching and improving the conversion accuracy of the digital-to-analog converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A DAC circuit of an R-2R structure according to an embodiment;

[0023] Figure 2 Schematic diagram of the structure of the digital-to-analog conversion circuit according to an embodiment of the present invention;

[0024] Figure 3 Schematic diagram of the structure of the digital-to-analog conversion circuit according to an embodiment of the present invention;

[0025] Figure 4 Schematic diagram of the structure of the digital-to-analog conversion circuit according to an embodiment of the present invention;

[0026] Figure 5 is a circuit diagram of a control switch according to an embodiment of the present invention;

[0027] Figure 6 FIG. 4 is a circuit diagram of an impedance element according to an embodiment of the present invention.

[0028] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0029] While implementing the technical solution of the present application, the inventors discovered that the R-2R circuit structure of a classic R-2R architecture DAC circuit is fixed, and this fixed structure is typically used for overall circuit design. In a classic R-2R architecture DAC circuit, when the DAC resolution is low, the resistance values ​​of resistors R or 2R in the R-2R architecture are typically adjusted to ensure matching between the resistors to improve the DAC resolution, or the DAC resolution is improved through layout optimization without changing the R-2R architecture. However, the present application deviates from this norm and improves the classic R-2R architecture.

[0030] The following, in conjunction with the accompanying drawings, clearly and completely describes the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0031] See Figure 1 , is an R-2R structure DAC circuit of an embodiment.

[0032] Figure 1 The R-2R architecture DAC circuit includes two resistors with resistance values ​​of R and 2R and a control switch INV. Each 2R resistor and a control switch INV form a resistor arm. The control switch INV is used as a control switch to adjust the output voltage according to the input digital coding signal DA. <0> DA <1> to DA <9> The corresponding resistor arm is controlled to select the connection to the reference voltage VREF or the ground. Figure 1 The resistance value of each node a0, a1, a2...a7, a8 looking to the left is 2R (excluding the resistance arm of the node). Assume Figure 1 In the R-2R ladder network, the resistor arm corresponding to node a9 is connected to the reference voltage VREF, and the other resistor arms are connected to ground. The circuit then becomes a 2R-2R voltage divider for the reference voltage VREF, making the output voltage VDAC of node a9 = VREF / 2. If the resistor arm corresponding to node a8 controls the switch to connect to the reference voltage VREF, and the other resistor arms are connected to ground, the voltage of the corresponding node a8 is divided by the voltage divider network consisting of 2R and 6 / 5R: the voltage of node a8 is equal to 3VREF / 8, and the output voltage VOUT of node a8 is = VREF / 4. By analogy, the output voltage of node a7 is VOUT = VREF / 8. That is, Figure 1 The total output VOUT of the R-2R ladder network is the sum of the voltage division terms obtained by dividing VREF by 2. For an n-bit DAC,

[0033]

[0034] Figure 1 The R-2R architecture DAC solves the shortcoming of the resistor divider DAC that the number of resistors increases exponentially with the increase of the number of DAC bits. In the R-2R ladder network, one R-2R unit is used for each bit, and a 2R resistor is added to the total port. Therefore, the required resistance is reduced from 2 n The number of cells is reduced to about 3n.

[0035] but, Figure 1 The R-2R architecture DAC circuit in FIG. 1 also has a problem: the control switch INV connected to the control switch as a resistance arm has a certain impedance, which causes a resistance mismatch problem when the resistance arm is switched.

[0036] In order to solve the above problem, the present invention provides a digital-to-analog conversion circuit.

[0037] See Figure 2, a structural diagram of a digital-to-analog conversion circuit according to an embodiment of the present invention.

[0038] The digital-to-analog conversion circuit of this embodiment includes an R-2R ladder network module and an impedance adjustment module.

[0039] When the R-2R ladder network module is to realize n-bit digital-to-analog conversion, it needs to include n-1 first resistors, namely the first resistor R0, the first resistor R1 to the first resistor R(n-2) and n+1 second resistors, namely the second resistor 2R, the second resistor 2R0, the second resistor 2R1, 2R2 to the second resistor 2R(n-1), wherein the resistance values ​​of the first resistors R0, R1 to R(n-2) are all R, and the resistance values ​​of the second resistors 2R, 2R0, 2R1, 2R2 to 2R(n-1) are all 2R.

[0040] The impedance adjustment module includes the same number of impedance elements b0, b1 to b(n-2) as the first resistor, one end of the second resistor 2R is connected to one end of a control switch INV, the other end of the control switch INV is grounded to form a ground path, one end of the second resistor 2R0 is connected to one end of the first resistor R0 to form a node a0, and the other end is connected to one end of the control switch INV0, and the other end of the control switch INV0 is used to receive the input digital code signal DA <0> The second resistor 2R0 and the control switch INV0 form a resistor arm H <0> One end of the first resistor R0 is connected to the node a0 through the impedance element b0, and the other end is connected to one end of the second resistor 2R1 and one end of the first resistor R1 to form a node a1. The other end of the second resistor 2R1 is connected to one end of the control switch INV1, and the other end of the control switch INV1 is used to receive the input digital code signal DA <1> The second resistor 2R1 and the control switch INV1 form a resistor arm H <1> According to the same connection method, the remaining first resistor, the second resistor and the control switch are connected to form a resistor arm H from low to high <2> To H <n-1>The control switch is used to control the resistor arm to connect to the reference voltage VREF or ground according to the input digital coding signal to achieve digital-to-analog conversion, and the node is used to output the result VDAC after digital-to-analog conversion.

[0041] Impedance elements b0, b1, through b(n-2) are connected between adjacent nodes. The impedance values ​​of the impedance elements are equal to the impedance values ​​of the corresponding control switches, ensuring that the equivalent resistance between each node and the ground path is a fixed resistance value, thereby preventing resistance mismatch when switching the resistor arms. Optionally, the control switches are kept the same size, and the impedance values ​​of the impedance elements are equal to the impedance values ​​of the control switches, ensuring that the equivalent resistance from each node into the ground path is a fixed resistance value. Alternatively, the value of the impedance element is adjusted via a control signal to ensure that the equivalent resistance from each node into the ground path is a fixed resistance value.

[0042] The control switch includes a dip switch, a touch switch, a selection switch, a power switch, an inverter, a path selector, etc. When the control switch includes an inverter, the number of the inverters can be one, two or more.

[0043] The impedance elements b0, b1 to b(n-2) include at least one of the following: a resistor, an inductor, a transmission gate device, and a switch device.

[0044] In the digital-to-analog conversion circuit of this embodiment, the impedance value of the impedance element is equal to the impedance value of the corresponding control switch so that the equivalent resistance between each node and the ground path is a fixed resistance value, thereby preventing resistance mismatch problems in the resistor arm during switching and improving the conversion accuracy of the digital-to-analog converter.

[0045] In an optional implementation manner, the equivalent resistance between each node and the ground path is the sum of the resistance value of the corresponding second resistor, the impedance value of the impedance element, and the impedance value of the control switch.

[0046] By controlling the impedance value of the impedance element, an equivalent resistance can be achieved between each node and the ground path, that is, the sum of the corresponding resistance value of the second resistor, the impedance value of the impedance element and the impedance value of the control switch are equal, which is a fixed resistance value. This can prevent the resistance mismatch problem of the resistor arm during switching, thereby improving the conversion accuracy of the digital-to-analog converter.

[0047] In an optional embodiment, the impedance value of the impedance element is positively correlated with the number of the control switches. When multiple control switches are used in the resistor arm, such as two, three, or four control switches, as the number of control switches increases, the impedance value of the corresponding impedance element also increases accordingly. This impedance value may cause a significant resistance mismatch problem in the resistor arm during switching. To prevent this significant resistance mismatch problem in the resistor arm during switching, the impedance value of the corresponding impedance element is also increased accordingly to offset the impedance of the control switches.

[0048] In an optional embodiment, the control switch is an inverter or a path selector, which can facilitate circuit design.

[0049] See Figure 3 , a structural diagram of a digital-to-analog conversion circuit according to an embodiment of the present invention.

[0050] In the digital-to-analog conversion circuit of this embodiment, the control switch is an inverter, and the number of inverters is one. In other optional embodiments, the number of inverters can be two or more. The inverters are of the same size. Since the impedance value of the inverter is related to the size of the inverter, when the inverters are of the same size, the impedance values ​​of the inverters are also the same. Impedance element b0 is connected between node a0 and node a1, impedance element b1 is connected between node a1 and node a2, and impedance element b(n-2) is connected between node a(n-2) and VDAC. The impedance values ​​of impedance elements b0, b1, through b(n-2) are equal to the impedance values ​​of the inverters INV1, INV2, through INV(n-1).

[0051] In other optional embodiments, impedance element b0 is connected between the first resistor R0 and the second resistor 2R1, impedance element b1 is connected between the first resistor R1 and the second resistor 2R2, and impedance element b(n-2) is connected between the first resistor R(n-2) and the second resistor 2R(n-1). The impedance values ​​of impedance elements b0, b1, and b(n-2) are equal to the impedance values ​​of inverters INV1, INV2, and INV(n-1). This can achieve that the equivalent resistance between each node and the ground path is a fixed resistance value, that is, the equivalent resistance of the ground path formed by node a0 to the second resistor 2R and the control switch INV is a fixed value. The equivalent resistance of the ground path formed by node a1 to the second resistor 2R and the control switch INV is a fixed value. The equivalent resistance of the ground path formed by node a2 to the second resistor 2R and the control switch INV is a fixed value. Similarly, the equivalent resistance of the ground path formed by node VDAC to the second resistor 2R and the control switch INV is a fixed value. The fixed value is the sum of the second resistance value, the inverter impedance value and the impedance value of the impedance element. In other optional embodiments, the fixed value can be set to other values ​​according to actual conditions.

[0052] By implementing the control switch through an inverter, the input data can be reversed, noise interference can be suppressed, and the equivalent resistance of the ground path formed by each node to the second resistor and the control switch can be fixed, which can prevent the resistance mismatch problem of the resistor arm during switching and improve the conversion accuracy of the digital-to-analog converter.

[0053] See Figure 4 , a structural diagram of a digital-to-analog conversion circuit according to an embodiment of the present invention.

[0054] In the digital-to-analog conversion circuit of this embodiment, the ground path includes two inverters INV, H in the resistor arm <0> 、H <1> 、H <2> To H <n-1>They include two inverters, namely H in the resistor arm <0> It includes two inverters INV0, H in the resistor arm <n-1>The circuit includes two inverters INV(n-1). The two inverters can be of the same or different sizes, but the equivalent impedances of the two inverters in adjacent resistor arms are the same. The impedance element and the equivalent impedance of the two inverters in the corresponding resistor arm are the same, preventing resistance mismatch when switching the resistor arms. It can be seen that the impedance value of the impedance element is related to the number of control switches in the corresponding resistor arm. The greater the number of control switches, the greater the impedance value of the corresponding impedance element. At the same time, the use of two inverters can prevent the input digital code signal from being flipped, allowing direct digital-to-analog conversion of the signal, facilitating signal processing.

[0055] See Figure 5 , a circuit diagram of a control switch according to an embodiment of the present invention.

[0056] The control switch of the embodiment of the present invention is an inverter, and the on-impedance and off-impedance of the inverter are the same, that is, the on-state impedance and the off-state impedance are the same. The inverter includes a first PMOS transistor and a first NMOS transistor; in other optional embodiments, the number of the first PMOS transistor and the first NMOS transistor can be multiple, the gates of the first PMOS transistor and the first NMOS transistor are connected and serve as the input terminal VIN, the drains are connected and serve as the output terminal VOUT, the source of the first PMOS transistor is connected to the high voltage VH, and the source of the first NMOS transistor is connected to the low voltage VL; the on-impedance and off-impedance of the inverter are equal, the on-impedance is the state when the first signal is input to the input terminal, and the off-impedance is the state when the second signal is input to the input terminal; assuming that the first signal input to the input terminal VIN is a high-level signal, the inverter is closed at this time, and the corresponding impedance is the off-state impedance. The second signal input to the input terminal VIN is a low-level signal, and the inverter is turned on at this time, and the corresponding impedance is the on-state impedance. In other optional embodiments, the first signal and the second signal can be set to other level signals as needed.

[0057] The on-resistance or the off-resistance is the impedance of the first PMOS transistor and the first NMOS transistor in parallel. Specifically, the on-resistance or the off-resistance of the inverter is R S The following formula must be satisfied:

[0058] R S =R NMOS ||R PMOS

[0059] Among them, R NMOS represents the impedance of the first NMOS transistor, R PMOS represents the impedance of the first PMOS transistor, and || represents a parallel relationship.

[0060] When the input terminal VIN is at a low level, the first NMOS transistor is cut off, and the resistance of the first NMOS transistor is infinite, that is, R NMOS =+∞. Therefore, the impedance of the inverter R S ≈R PMOS .

[0061]

[0062] Among them, μ p is the carrier mobility, C ox is the gate capacitance per unit area, W is the gate length, L is the gate width, VDD is the gate voltage, V THP is the threshold voltage.

[0063] When the input terminal VIN is at a high level, the first PMOS transistor is cut off, and the resistance of the first PMOS transistor is infinite, that is, R PMOS =+∞. Therefore, the impedance of the inverter R S ≈R NMOS .

[0064]

[0065] Among them, μ p is the carrier mobility, C ox is the gate capacitance per unit area, W is the gate length, L is the gate width, VDD is the gate voltage, V THP is the threshold voltage.

[0066] Let R PMOS =R NMOS , the size of the first NMOS transistor and the first PMOS transistor in the inverter can be obtained, and the size includes the ratio of the transistor gate length to the gate width.

[0067] After obtaining the impedance and size of the inverter, a component with the same impedance as the inverter is selected as the control switch, which is easy to implement.

[0068] After obtaining the control switch, select the corresponding impedance element. The specific process is as follows:

[0069] See Figure 6 , a circuit diagram of an impedance element according to an embodiment of the present invention.

[0070] The impedance elements b0, b1, and b(n-2) of this embodiment are transmission gate devices. In the digital-to-analog conversion circuit of the present invention, the transmission gate device includes a second PMOS transistor PT and a second NMOS transistor NT. In other optional embodiments, the number of second PMOS transistors and second NMOS transistors can be multiple. The source of the second PMOS transistor PT and the second NMOS transistor NT are connected and serve as the first terminal A of the transmission gate, and the drain is connected and serves as the second terminal B of the transmission gate. The gate of the second PMOS transistor PT is connected to a low voltage VL, and the source of the second NMOS transistor NT is connected to a high voltage VH. When the first terminal A is at a high level, the second PMOS transistor PT is turned on, the second NMOS transistor NT is turned off, and the second terminal B outputs a high level. When the first terminal A is at a low level, the second NMOS transistor NT is turned on, the second PMOS transistor PT is turned off, and the second terminal B outputs a low level. It can be seen that all transmission gate devices are in the on state, and one of the second PMOS transistor PT and the second NMOS transistor NT is turned on. Assume that the impedance of the transmission gate device is R T , the following formula must be satisfied:

[0071] R T =R NMOST ||R PMOST

[0072] Among them, R NMOST represents the impedance of the second NMOS transistor, R PMOST represents the impedance of the second PMOS transistor, and || represents a parallel relationship.

[0073] Right now,

[0074]

[0075] Among them, R T is the impedance of the transmission gate, μ p is the carrier mobility of the second PMOS transistor, μ n is the carrier mobility of the second NMOS transistor, C ox is the gate capacitance per unit area, W is the gate length, L is the gate width, VDD is the gate voltage, V THP is the threshold voltage of the second PMOS transistor, V THN is the threshold voltage of the second NMOS transistor, R is the impedance of the first resistor, R s is the impedance of the control switch, that is, the impedance of the inverter, Vref is the reference voltage, and || represents a parallel relationship.

[0076] Since the transmission gate device is small in size, using the transmission gate as an impedance element greatly reduces the chip area.

[0077] The impedance value of the transmission gate is equal to the impedance value of the inverter, so R T =R S =R NMOS =R PMOS , we can get the same transmission gate device size as the inverter impedance, that is, we can achieve R T =R S .

[0078] Select the transmission gate of this size as the impedance element, and connect the impedance element and the control switch according to Figure 3 The circuit connection relationship is connected in the circuit. The impedance element, the control switch and the R between the resistor arm are added, so that the classic R-2R structure DAC can achieve the R-(2R+R S ) structure to waste area structure, and then to [(R+R T )-(2R+R S +R T )]=[(R+R S )-(2R+2R S )]=[R-2R] structure conversion can achieve a fixed equivalent resistance from each node to the ground path formed by the second resistor and the control switch, which can prevent the resistance mismatch problem of the resistor arm during switching and improve the conversion accuracy of the digital-to-analog converter.

[0079] In an optional embodiment, the first PMOS transistor and the first NMOS transistor in the inverter are directly used according to Figure 3 By connecting the circuit in the manner described above, a transmission gate device with the same impedance as the inverter can be obtained. Directly using the transmission gate device as an impedance element can prevent the resistance mismatch problem from occurring when the resistor arm is switched, thereby improving the conversion accuracy of the digital-to-analog converter.

[0080] In another optional embodiment, the impedance value of each control switch is obtained by measurement, thereby obtaining impedance elements with the same impedance value. The direct measurement method can eliminate the influence of parasitic parameters and improve accuracy.

[0081] The transmission gate device is used as impedance elements b0, b1, b2 to b(n-2), and according to Figure 3 The connection relationship in the figure is connected to the first resistors R0, R1, R2 to R(n-2) between the resistor arms. At this time, the resistance value of each node a0, a1, a2...a(n-2) looking to the left is [(R+R T )-(2R+R S +R T )]=[(R+R S )-(2R+2R S )]=[R-2R]. Therefore, it can be seen that by adding transmission gate type impedance elements b0, b1, b2 to b(n-2) between the first resistors, since the impedance of the transmission gate device is equal to the impedance of the inverters INV0 to INV(n-1), the influence of the inverter impedance can be eliminated when each resistor arm is switched. The impedance matching of each resistor arm is still maintained when switching, which reduces the deviation of the analog signal output by each digital coded signal and greatly improves the accuracy of the digital-to-analog conversion of each digital coded signal.

[0082] Since the size of the transmission gate device is very small, compared with the method of gradually increasing the area of ​​the inverter, the digital-to-analog conversion circuit of this embodiment greatly reduces the chip area, and can better ensure the matching of the circuit in terms of layout.

[0083] In this embodiment, the reason for selecting a transistor of the same size as the control switch to form the impedance element is that: in a digital-to-analog conversion circuit, when the circuit temperature, noise interference, and application environment change, the temperature drift and error generated by transistors of the same size are the same, and the corresponding impedance change is also the same. Therefore, the impedance of the control switch and the impedance change of the impedance element are the same, which improves the accuracy of the calculation results and effectively prevents the problem of impedance mismatch in the resistor arm.

[0084] For example, for a 10-bit DAC with an R-2R structure that multiplies the inverter size bit by bit by a factor of 2, the inverter area used for the MSB (most significant bit) resistor arm is 512 times that of the LSB (least significant bit), and the inverter area used for the entire DAC is 1024 times that of the LSB. This large inverter area results in significant waste of area. However, the digital-to-analog conversion circuit of this embodiment only requires 11 transmission gates with LSB resistor arms for a 10-bit DAC, significantly reducing chip area. Furthermore, the transmission gates and inverters have the same area and are smaller, thus ensuring better circuit compatibility in terms of layout.

[0085] It can be seen from the above description that the first resistor R between the transmission gate device and the resistor arm is added so that Figure 1 The R-2R structure DAC in the embodiment realizes the R-(2R+R S ) structure to waste area structure, and then to [(R+R T )-(2R+R S +R T )]=[(R+R S )-(2R+2R S The present invention can use inverters and transmission gate devices of the same fixed size, greatly optimizing the performance of the DAC and improving the convenience of circuit and layout design.

[0086] The present invention also provides an electronic device including the aforementioned digital-to-analog conversion circuit. The electronic device includes various smart terminals, such as mobile phones, computers, and various communication devices. The digital-to-analog conversion circuit prevents resistance mismatch during switching between resistor arms, thereby improving the conversion accuracy of the digital-to-analog converter.

[0087] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A digital-to-analog conversion circuit, characterized in that: include: An R-2R ladder network module includes a plurality of first resistors, a second resistor, and control switches corresponding to the second resistors, wherein the plurality of first resistors are connected in series, and one end of the second resistor is sequentially connected to one end of the corresponding first resistor to form nodes from low to high; One end of one of the control switches is connected to the other end of one of the second resistors, and the other end of the control switch is grounded to form a ground path; one end of the remaining control switches is connected to the other end of the remaining second resistors to form a resistance arm from a low position to a high position, and the other end of the control switch is responsive to an input digital coding signal and is used to control the resistance arm to be connected to a reference voltage or ground to achieve digital-to-analog conversion; the control switch is an inverter or a path selector; The impedance adjustment module includes an impedance element corresponding to the first resistor, the impedance element is connected between adjacent nodes, and the impedance value of the impedance element is equal to the impedance value of the corresponding control switch.

2. The digital-to-analog conversion circuit according to claim 1, wherein: The equivalent resistance between each node and the ground path is the sum of the resistance value of the corresponding second resistor, the impedance value of the impedance element, and the impedance value of the control switch.

3. The digital-to-analog conversion circuit according to claim 1 or 2, characterized in that: The impedance value of the impedance element is positively correlated with the number of the control switches.

4. The digital-to-analog conversion circuit according to claim 3, wherein: The impedance element includes at least one of the following: Resistors, inductors, transmission gates, and switches.

5. The digital-to-analog conversion circuit according to claim 1, wherein: When the control switch is an inverter; The inverter includes a first PMOS transistor and a first NMOS transistor; the gates of the first PMOS transistor and the first NMOS transistor are connected and serve as the input end of the inverter, the drains are connected and serve as the output end of the inverter, the source of the first PMOS transistor is connected to a high voltage, and the source of the first NMOS transistor is connected to a low voltage; the on-resistance and off-resistance of the inverter are equal.

6. The digital-to-analog conversion circuit according to claim 4, characterized in that: When the impedance element is the transmission gate device; The transmission gate device includes a second PMOS transistor and a second NMOS transistor; The sources of the second PMOS transistor and the second NMOS transistor are connected and serve as the first end of the transmission gate, the drains are connected and serve as the second end of the transmission gate, the gate of the second PMOS transistor is connected to a low voltage, and the source of the second NMOS transistor is connected to a high voltage; The impedance of the transmission gate is the impedance of the second PMOS transistor and the second NMOS transistor connected in parallel.

7. The digital-to-analog conversion circuit according to claim 6, wherein: The impedance value of the transmission gate is equal to the impedance value of the inverter.

8. The digital-to-analog conversion circuit according to claim 7, wherein: The impedance of the transmission gate satisfies the following formula: Among them, R T is the impedance of the transmission gate, μ p 、μ n is the carrier mobility, C ox is the gate capacitance per unit area, W is the gate length, L is the gate width, VDD is the gate voltage, V THP 、V THN is the threshold voltage, R is the impedance of the first resistor, R s is the impedance of the inverter, Vref is the reference voltage, and || represents a parallel relationship.

9. An electronic device, characterized in that: The digital-to-analog conversion circuit comprises the digital-to-analog conversion circuit according to any one of claims 1 to 8.

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