Apparatus and method for repairing defective memory cells based on specified error rates for certain memory cells

Abstract

Methods, apparatus, and systems are disclosed for repairing defective memory cells in a region of a memory array associated with a high or low priority. A repair address generator can be configured to generate a memory address map for repair (e.g., fusing a fuse at a fuse circuit) depending on whether certain applications can operate at a high priority indicating a low bit error rate or a low priority indicating a higher bit error rate. For example, a specified error rate associated with a low priority can correspond to a threshold error rate for certain applications, such as a neural network application storing trained weights. This neural network application can access trained weights that are partially stored in defective memory cells, where the least significant bits of such trained weights are stored in defective memory cells that are not repaired according to the memory address map.

Description

Background Technology

[0001] In semiconductor devices such as DRAM (Dynamic Random Access Memory), redundant memory cells are provided to replace defective memory cells in some cases. The address of the defective memory cell is stored in a fuse circuit. When such an address needs to be accessed, the fuse circuit activates a hit signal. After the hit signal becomes active, the redundant memory cell is accessed instead of the defective memory cell. For example, all defective memory cells can be replaced by redundant memory cells.

[0002] Meanwhile, high-speed memory access and reduced power consumption are required characteristics of semiconductor devices. In recent years, systems employing multi-core processors to execute applications have led to faster access patterns for memory devices acting as main memory (e.g., Dynamic Random Access Memory (DRAM)) or any such volatile memory. For example, a typical access pattern for DRAM involves sequentially repeating bank activation, read or write access, and bank pre-charging. Defective memory cells in this volatile memory need to be repaired for efficient access to such memory devices. The efficiency and performance of a computing device can be affected by the different memory devices and the extent to which said memory devices can be repaired, for example, by the fuses allocated to such defective memory cells in said memory devices.

[0003] Meanwhile, bit flips (e.g., charge changes at memory cells) occur in non-volatile memory devices. As the number of bits per memory cell increases, the raw bit error rate (RBER) indicates worse performance, while the demand for better throughput and latency continues to grow. Therefore, memory devices may operate with complex error correction techniques, which are increasingly demanding in terms of area and power; leading to higher silicon costs and longer firmware development times.

[0004] Neural networks are used in computer vision and natural language processing technologies, as well as various other signal processing applications. While the computational and memory requirements of neural networks continue to grow as they are applied to solve complex computational problems, there is still a need to reduce the complexity (e.g., computational and memory footprint) of such neural networks for some resource-constrained devices, ranging from Internet of Things (IoT) devices and embedded devices to large computing clusters (e.g., graphics processing unit (GPU) clusters). When utilizing this neural network, machine learning models can be trained on GPUs using volatile memory devices. The weights generated from this training can be stored on volatile memory devices (e.g., DRAM memory devices) or non-volatile memory devices (e.g., NAND flash memory devices). Attached Figure Description

[0005] Figure 1 This is a block diagram of a computing system arranged according to the example described in this article.

[0006] Figure 2 This is a block diagram of a memory device arranged according to the examples described herein.

[0007] Figure 3 This is a block diagram of a memory device arranged according to the examples described herein.

[0008] Figure 4 This is a flowchart of the method for arranging the examples described in this article.

[0009] Figure 5 This is a flowchart of the method for arranging the examples described in this article.

[0010] Figure 6 This is a block diagram of a computing system arranged according to the example described in this article.

[0011] Figure 7 This is a block diagram of a neural network arranged according to the example described in this article. Summary of the Invention

[0012] This document discloses example methods. In embodiments of this disclosure, one method includes: obtaining a plurality of memory commands associated with a plurality of memory access operations, at least a portion of the plurality of memory access operations being associated with a specified error rate; generating a memory address mapping for the plurality of memory access operations, in part based on the specified error rate; and providing the memory address mapping to a memory data register of a memory cell, the memory data register being accessible by the memory cell for repairing areas of the memory cell.

[0013] Additionally or alternatively, it further includes: accessing a first region of the memory cell based on the memory address mapping to implement at least one of the plurality of memory commands, the first region of the memory being characterized by the specified error rate for at least the portion of the plurality of memory access operations; and accessing a second region of the memory cell to implement another of the plurality of memory commands.

[0014] Alternatively or additionally, the memory data register accessible by the memory cell may correspond to a register or local cache of the memory cell.

[0015] Alternatively or additionally, the specified error rate corresponds to the threshold error rate used to store the weights of the neural network.

[0016] Alternatively or additionally, the threshold error rate used to store the weights of the neural network is based on the bit-flip tolerance of the neural network.

[0017] Additionally or alternatively, the method further includes: obtaining a memory access pattern associated with the plurality of memory access operations, the memory access pattern indicating which areas of the memory cells are accessed more frequently than other areas of the memory cells; in the memory address pattern, identifying a first portion of the memory address associated with the areas of the memory cells that are accessed more frequently than other areas of the memory cells as high priority of the memory address mapping; and in the memory address pattern, identifying a second portion of the memory address associated with the areas of the memory cells that are not accessed more frequently than other areas of the memory cells as low priority of the memory address mapping.

[0018] Additionally or alternatively, it further includes: identifying the most significant bit of each memory address in the first portion of the memory address, which is the high-priority memory address; and aligning each memory address in the first portion of the memory address with a memory identifier of the memory address in the memory address mapping.

[0019] Alternatively or additionally, the memory identifier corresponds to a page of the memory cell or a block of the memory cell.

[0020] Alternatively or additionally, the memory cell corresponds to at least one of DRAM, SRAM, NAND, resistive memory, or phase-change memory, or any combination thereof.

[0021] This document discloses example devices. In embodiments of this disclosure, a device includes: a memory array comprising a plurality of memory cells, the plurality of memory cells including at least one defective memory cell, each defective memory cell having a defective memory address; a register configured to store a memory address mapping, the memory address mapping including a plurality of memory addresses and indicating which of the plurality of memory addresses are associated with high priority and which are associated with low priority; a memory controller coupled to the memory array and configured to: provide the memory address mapping to the repair register; compare the defective memory address of the defective memory cell with the memory address mapping; and repair some of the memory addresses associated with the high priority and the memory addresses associated with the low priority; and a fuse circuit configured to store the defective memory address.

[0022] Alternatively or additionally, the fuse circuit includes a plurality of fuse elements, each corresponding to a bit among a plurality of bits of the defect address.

[0023] Alternatively or additionally, the memory controller is further configured to identify defective memory addresses stored in the fuse circuit.

[0024] Additionally or alternatively, the memory controller is further configured to: determine that a portion of the repair of the memory address associated with the high priority is performed in a first region of the memory array; and repair some of the memory addresses associated with the low priority in a second region of the memory array having a specified bit error rate for certain memory access operations.

[0025] Additionally or alternatively, each of the certain memory access operations includes an instruction for a corresponding address of a memory cell among the plurality of memory cells.

[0026] Additionally or alternatively, the memory controller is further configured to: determine that a fuse element threshold has been exceeded when repairing some of the memory addresses associated with the low priority; and repair an additional portion of the memory addresses associated with the high priority in the third region of the memory array.

[0027] Additionally or alternatively, the memory controller is further configured to: determine that a portion of the repair of the memory address associated with the high priority was not completed in the first region of the memory array; and invalidate the first region of the memory array.

[0028] Additionally or alternatively, the system further includes a processor device coupled to the memory controller. The memory controller is configured to receive memory commands from the processor or host device.

[0029] Additionally or alternatively, the system further includes a memory interface coupled to the memory controller and configured to communicate with the memory array. The memory controller is configured to provide the memory mapping to the memory array via the memory interface.

[0030] In another aspect of this disclosure, a method includes: providing a memory address mapping to a register accessible by a memory cell; comparing one or more addresses of defective memory cells of the memory cell with the memory address mapping comprising a plurality of memory addresses, and indicating which of the plurality of memory addresses are associated with high priority and which are associated with low priority, the low priority indicating which memory addresses will be accessed for a plurality of memory access operations associated with a specified error rate; and repairing at least in part based on the comparison a portion of the memory addresses associated with the high priority and a portion of the memory addresses associated with the low priority.

[0031] Alternatively or additionally, the specified error rate corresponds to the threshold error rate used to store the weights of the neural network.

[0032] Alternatively or additionally, the memory address indicating the most significant bit of the weights in the weights of the neural network is repaired.

[0033] Additionally or alternatively, it further includes: fusing the fuse element of the plurality of fuse elements that corresponds to the most significant bit of the weight.

[0034] Alternatively or additionally, the plurality of memory addresses correspond to physical memory addresses or virtual memory addresses.

[0035] Additionally or alternatively, it further includes: in response to a memory access operation in one of the plurality of memory access operations, accessing a plurality of memory cells according to a repaired memory address indicating the portion of the memory address associated with the low priority.

[0036] In another aspect of this disclosure, an apparatus includes: a memory array comprising a plurality of memory cells, the plurality of memory cells including at least one defective memory cell from a plurality of defective memory cells having a specified error rate; and a non-transitory computer-readable medium encoded with executable instructions that, when executed, cause the apparatus to identify weights for use in a neural network and store the weights in the at least one defective memory cell from the plurality of defective memory cells having the specified error rate. One or more least significant bits of the weights are stored in the at least one defective memory cell.

[0037] Alternatively or additionally, the specified error rate corresponds to a first threshold error rate for storing the weights of the neural network associated with access operations at the memory array.

[0038] Alternatively or additionally, the first threshold error rate used to store the weights of the neural network is different from the second threshold error rate associated with additional access operations.

[0039] Additionally or alternatively, the non-transitory computer-readable medium is further encoded with executable instructions that, when executed, cause the neural network to repair a portion of the memory address associated with the access operation and to repair the memory address associated with the additional access operation. Detailed Implementation

[0040] Neural networks can be implemented using memory with a higher bit error rate than is acceptable in many other applications, such as data storage. For example, the performance of a neural network may be slightly invariant to memory errors. For instance, if some bits in the weights used in the neural network operation contain bit errors (e.g., due to bit flips), the neural network's performance may still be acceptable. Therefore, memory with a higher bit error rate than is generally acceptable can still be used for neural network applications. For memory that can be used in neural network applications (e.g., memory for storing neural network weights), the bit error rate requirement can be relaxed.

[0041] In neural network applications that utilize memory to store neural network weights, bits stored for a particular training weight may be 'flipped' or altered (e.g., from '0' to '1', or '1' to '0') due to defective memory cells erroneously storing charges for specific positions. While such bit flips can affect the neural network's output (e.g., predictions / probabilities) and may cause the network to misclassify the output (e.g., due to weight degradation in memory), some neural networks may be less susceptible to bit flips, such as recurrent neural network (RNN)-based networks (e.g., Long Short-Term Memory (LSTM) neural networks or Gated Recurrent Unit (GRU) neural networks). These RNN-based neural networks may exhibit a higher tolerance for bit flips and may be able to maintain higher bit error rates. For example, some neural networks trained for image classification can tolerate bit error rates of up to 10^-7 due to memory degradation of training weights. As another example, some neural networks trained for object detection can tolerate bit error rates of up to 10^-8 due to memory degradation of training weights.

[0042] This document describes methods, apparatus, and systems for repairing defective memory cells. For example, to repair defective memory cells, a memory address map may be provided to a repair register of a memory device. The memory address map may indicate which memory address memory cells to repair based on a specified error rate for certain memory cells, such as the address of a memory cell in a low-priority region compared to memory addresses in a high-priority region. Therefore, a processor and / or memory controller implementing this memory address map may compare the address of the defective memory cell of the memory device with the memory address map, which indicates which memory addresses are associated with high priority and which with low priority. Low priority may indicate which memory addresses are required to be accessed for a plurality of memory access operations associated with a specified error rate. For example, a memory access operation associated with a specified error rate may be an operation accessing trained weights of a neural network. The bit error rate requirement for this trained weight of the neural network for the neural network application may not be as stringent as the bit error rate that might be utilized or required for other memory access operations associated with high priority (e.g., accessing other data stored in volatile or non-volatile memory). For example, memory operations (e.g., DRAM operations) may typically require low bit error rates, such as 10^-19 to 10^-21 BER. However, in some instances, neural network applications can operate efficiently at higher bit error rates, such as from 10^-10 BER to 10^-4 BER, or even down to 10^-3 BER. Therefore, a memory controller and / or processor that repairs defective memory cells can repair memory addresses associated with high priority to achieve a low bit error rate; while only repairing a portion of memory addresses associated with low priority, because applications accessing data from low-priority memory cells (e.g., neural network applications) may be able to tolerate higher bit error rates.

[0043] As described herein, it is advantageous that a repair operation performed or implemented in a processor or memory controller may include identifying certain memory addresses as high priority, including the most significant bit (MSB) of each memory address. Using this identification, a memory address map can be generated by aligning the most significant bit of each memory address in the memory address map, for example, as indicated by a memory identifier. For example, a memory identifier may be a page of a memory device (e.g., a DRAM page) or a block of a memory device (e.g., a NAND non-volatile block). Thus, the memory address of the memory device may correspond to a physical memory address or a virtual memory address. In various embodiments, the memory identifier can be used for various memory devices, such as DRAM, SRAM, NAND, resistive, or phase-change memory devices.

[0044] Repair operations can also be performed on addresses associated with low priority in the memory map, such as when fuses in the memory device are available for repair. Therefore, some addresses associated with low priority—those associated with a specified error rate, such as memory access operations used in various neural network applications—can be left unrepaired. In this case, advantageously, one or more least significant bits (LSBs) of the trained weights can be stored in some unrepaired defective memory cells. Storing the bits of trained weights for neural network applications in some defective memory cells allows for efficient use of the memory device because, for example, some memory devices may not be discarded after repair or after manufacturing, as the bit error rate requirement may not be so high. Therefore, such memory devices containing some defective memory cells (e.g., for neural network applications) can still be utilized. In contrast to typical manufacturing scenarios or post-repair evaluations, such memory devices still containing defective memory cells might be discarded, thereby increasing semiconductor device waste. Therefore, the devices and methods described herein can facilitate the efficient use of memory devices with low-priority regions designated for use by applications that tolerate higher bit error rates than other memory access operations (e.g., operations requiring DRAM bit error rates of 10^-19 to 10^-21 BER). Additionally or alternatively, such systems and methods can be used to implement IoT devices that may have lower computational requirements and utilize and / or require a smaller memory footprint than other electronic devices.

[0045] Figure 1 This is a schematic diagram of a computing system 100 arranged according to the examples described herein. The computing system 100 includes a processor 105 coupled to memory cells 140, which may also be referred to as memory devices. For example, one of the memory cells 140 may be an SRAM memory device, and the other memory cell 140 may be a NAND flash memory device. The processor may implement a repair address generator (RAG) that generates memory address maps to repair certain memory cells associated with memory addresses utilized by various memory access operations, some of which are based on a specified error rate for a particular memory application (e.g., a neural network application). A memory controller 110 may be coupled to the memory cells 140 via a memory interface 135. The processor 105 may implement memory commands received from various data sources or from processes executing on the processor 105. For example, the processor 105 may receive memory access requests (e.g., read or write commands) from processes executing on the processor 105. In this case, the memory controller 110 can process memory access requests implemented by the processor 105 to access one or more of the memory cells 140.

[0046] Processor 105 can be used to implement the memory system of computing system 100 using memory controller 110. In some instances, processor 105 may be a multi-core processor containing multiple cores. For example, multiple cores may be implemented using processing circuitry that independently reads and executes program instructions. Memory controller 110 can handle communication with a memory system that may be external to processor 105. For example, memory controller 110 may provide access commands from multiple cores of processor 105 to memory cells 140. Memory controller 110 may provide such access commands via memory interface 135. For example, memory interface 135 may provide clock signals, command signals, and / or address signals to any of memory cells 140.

[0047] In a typical memory access scheme, memory controller 110 provides instructions to write data to memory cell 140 based on a write command. Similarly, for a read command, memory controller 110 provides instructions based on the read command and receives data from memory cell 140. As described herein, in some cases, repair address generator 120 generates memory maps for memory access operations—some memory access operations are associated with high priority, and other memory access operations with a specified error rate are associated with low priority. For example, to generate memory maps for repairing certain memory addresses, RAG 120 can obtain memory access patterns associated with both high and low priority memory access operations.

[0048] The memory access pattern obtained by RAG 120 indicates which areas of a memory cell are accessed more frequently than other areas of the memory cell. Areas of a memory cell may contain memory cells and may contain defective memory cells. RAG 120 may associate areas of memory cells accessed more frequently than other areas of the memory cell as areas associated with high priority, while other areas of the memory cell are associated with low priority. Therefore, RAG 120 may identify a first portion of the memory address associated with areas of memory cells accessed more frequently than other areas of the memory cell as high priority in the memory address pattern; and may identify a second portion of the memory address not associated with areas of memory cells accessed more frequently than other areas of the memory cell as low priority. Once the memory address mapping is generated, the memory controller 110 may send repair registers or caches (e.g., described below) to one or more of the memory cells 140. Figure 2 The repair register 214 provides memory address mapping.

[0049] The memory controller 110 may be implemented using a circuitry that controls memory access operations to / from memory cells 140. The memory controller 110 may be a separate chip or integrated circuit coupled to or implemented on the processor 105, for example, as a core of the processor 105 used to control the memory system of the computing system 100. In some embodiments, the memory controller 110 may be integrated into the processor 105 and referred to as an integrated memory controller (IMC).

[0050] Memory controller 110 can communicate with multiple memory cells to implement a memory system having processor 105. For example, memory cell 140 can communicate with memory controller 110 simultaneously. Therefore, memory controller 110 can access memory cell 140a based on a generated memory map indicating which certain memory cells are associated with certain memory addresses. For example, memory controller 110 can access a first region of memory cell 140 to implement memory commands, wherein the first region of memory cell 140 is characterized by a specified error rate for some memory access operations (e.g., neural network access operations). The specified error rate may correspond to a threshold error rate used to store the weights of the neural network. In an example implementation, the threshold error rate used to store the weights of the neural network is based on the bit flip tolerance of the neural network. In this example, for a resistive memory device (e.g., a 3D cross-point memory device), the threshold error rate may be a raw bit error rate in the range of 10^-6 to 10^-2 BER; or in a single-level cell memory device, it may be a raw bit error rate of 10^-8. Various raw bit error rates can be threshold error rates determined for various applications. In examples, three-level cell (TLC) or four-level cell (QLC) NAND memory devices can have different or the same threshold error rates. Continuing with the example, the memory controller 110 can access a second region of the memory cell 140 to execute another memory command, wherein the second region of the memory cell 140 is not characterized by a specified error rate or has a default error rate (e.g., a default error rate for a high-priority region). For example, the default error rate could be another threshold error rate typically associated with other memory access operations different from those associated with memory access operations related to the weights of a stored neural network.

[0051] Although Figure 1The example depicts three memory cells 140, but it is contemplated that the memory controller 110 can interact with any number of memory cells. For example, eight memory cells may be included, and each memory cell may include a data bus with an eight-bit width, thus the memory system implemented by the processor 105 may have a sixty-four-bit width. The memory cells 140 may be dynamic random access memory (DRAM) or non-volatile random access memory (RAM), such as ferroelectric RAM (FeRAM), spin-transfer torque RAM (STT-RAM), phase-change RAM (PCRAM), resistance-changing RAM (ReRAM), or the like. In various embodiments, such memory cells may be referred to as memory chips, memory modules, memory dies, memory cards, memory devices, memory arrays, and / or memory cells. Physically, the memory cells 140 may be arranged and positioned as a single layer, or may be positioned as a stacked layer. In some embodiments, the memory cells 140 may be positioned as multiple layers on top of each other to form a vertical memory, such as a 3D NAND flash memory (e.g., a 3D cross-point memory device).

[0052] In some instances where memory cell 140 is implemented using DRAM or non-volatile RAM integrated into a single semiconductor chip, memory cell 140 may be mounted on a memory module substrate, motherboard, or the like. For example, memory cell 140 may be referred to as a memory chip. Memory cell 140 may include a memory cell array region and a peripheral circuit region. The memory cell array region includes an array of memory cells having multiple banks, each bank including multiple word lines, multiple bit lines, and multiple memory cells arranged at the intersections of the multiple word lines and multiple bit lines. Bit line selection may be performed by multiple column decoders, and word line selection may be performed by multiple row decoders.

[0053] The memory controller 110 can interact with the memory interface 135 to provide memory commands, clock signals, command signals, and / or address signals to any of the memory cells 140 for performing various memory access operations. For example, a corresponding peripheral circuit area of ​​the memory cell 140 may include clock terminals, address terminals, command terminals, and data input / output (I / O) terminals (DQ). For example, the data I / O terminals can handle eight-bit data communication. Data input / output (I / O) buffers may be coupled to the data input / output terminals (DQ) for data access, such as memory read and write access. Address terminals may receive address signals and bank address signals. Bank address signals can be used to select a bank among multiple banks. Row and column addresses may be provided as address signals. Command terminals may include a chip select ( / CS) pin, a row address strobe ( / RAS) pin, a column address strobe ( / CAS) pin, a write enable ( / WE) pin, and / or the like. The command decoder decodes command signals received from the memory controller 110 via the memory interface 135 at the command terminal to receive various commands, including read and / or write commands. This command decoder can provide control signals corresponding to the received commands to control the memory cell array area. An external clock signal, such as from the memory interface 135, can be supplied to the clock terminal. (About...) Figure 2 Describe the implementation plan for the example.

[0054] Advantageously, in some instances, the systems and methods described herein can be used as memory access schemes when processing memory commands for applications that may have a specified error rate (e.g., neural network applications). Neural network-based processing may involve training and associated computation of various weights. In some applications, trained weights can be stored in regions of memory device 140 such that the LSBs of the trained weights are stored in unrepaired defective memory cells as indicated in the memory address mapping. For example, in a page of DRAM memory device 140, trained weights can be aligned with their corresponding MSBs such that the remaining LSBs are stored in defective memory cells.

[0055] While the repair address generator 120 has been described as part of the memory controller in the context of the implementation of processor 105, it is contemplated that the repair address generator 120 may be implemented differently in other embodiments. For example, the repair address generator 120 may be coupled to processor 105 as a separate circuit, such as an application-specific integrated circuit (ASIC), a digital signal processor (DSP) implemented as part of a field-programmable gate array (FPGA), or a system-on-a-chip (SoC). As another example, the repair address generator 120 may be coupled to memory controller 110 implemented by processor 105 as a series of switches determining the sequence of instructions to be provided to the repair register or local cache of memory cell 140. For example, the local cache of memory cell 140 may be an L2 cache. The switches may be multiplexers, such as those having selected lines coupled to memory controller 110.

[0056] Figure 2 This is a block diagram of a memory cell 240 arranged according to the example described herein. The memory cell 240 includes a memory cell array 211, which includes multiple word lines WL, each assigning a different memory address thereto, and multiple bit lines BL, each assigning a different memory address thereto. The memory cell array 211 also includes memory cells MC, located at the intersections of the word lines WL and the bit lines BL. The word lines WL are selected by a row decoder 212. The bit lines BL are selected by a column decoder 213. The memory cell array 211 also includes redundant word lines RWL. Redundant memory cells RMC are located at the intersections of the redundant word lines RWL and the bit lines BL. The redundant word lines RWL are spare word lines, each of which can replace a defective word line WL or a word line WL connected to a defective memory cell MC. Although Figure 2 A redundant word line (RWL) is depicted, but the memory cell array 211 may contain any number of redundant word lines, such as 178 RWLs.

[0057] Continue to refer to Figure 2 The memory cell 240 includes external terminals, including an address terminal 221, a command terminal 222, a clock terminal 223, a data terminal 224, a data strobe terminal 225, and a power supply terminal 226. For example, power can be supplied to the address terminal 221 from a memory controller (e.g., Figure 1 The address signal ADD of the memory controller 110 is input to the address terminal 221. The address signal ADD is supplied to the address latch circuit 232 via the address input circuit 231. The address signal ADD can be latched by the address latch circuit 232. The address signal ADD latched by the address latch circuit 232 is supplied to the row decoder 212, the column decoder 213, the repair register 214, and / or the fuse circuit 250.

[0058] Repair register 214 may receive a memory address from the address signal ADD. For example, repair register 214 may receive a memory mapping indicating memory cells to be repaired for high-priority areas and certain low-priority areas of memory array 211, such that the low-priority areas of memory array 211 are operable according to a specified error rate. In some instances, the repair register may be a memory data register (MDR). Repair register 214 may receive this memory mapping from a repair address generator of the memory controller (e.g., RAG 120 of memory controller 110). In some embodiments, fuse circuit 250 may provide the memory controller with a lookup table and / or list indicating which fuses of fuse circuit 250 have blown. In such embodiments, the memory controller may use this lookup table to determine whether all high-priority repairs have been completed (e.g., as described in decision block 520 regarding method 500). Based on this determination, an updated memory mapping may be generated by the repair address generator and provided to the local cache or repair register of memory cell 240 (e.g., repair register 214).

[0059] Supplying command to terminal 222 from memory controller (e.g., Figure 1 The memory controller 110) sends a command signal CMD. The command signal CMD may include multiple signals, such as the row address strobe signal / RAS, the column address strobe signal / CAS, and the write enable signal / WE. Signal names beginning with a forward slash ( / ) indicate that the signal is a corresponding signal or an inverted version of a low-active signal. The command signal CMD input to command terminal 222 is supplied to command decoder 234 via command input circuitry 233. Command decoder 234 generates various internal commands by decoding command signal CMD. Internal commands may include the active signal IACT, the column signal ICOL, and a repair signal to be provided to repair register 214.

[0060] When the command signal CMD indicates a row access (active command), the valid signal IACT is activated. After the valid signal IACT becomes active, the address signal ADD, latched by the address latch circuit 232, is supplied to the row decoder 212. Therefore, the word line WL specified by the address signal ADD is selected. When the command signal CMD indicates a column access (read command or write command), the column signal ICOL is activated. After the column signal ICOL becomes active, the address signal ADD, latched by the address latch circuit 232, is supplied to the column decoder 213. Therefore, the bit line BL specified by the address signal ADD is selected.

[0061] If the active command and read command are entered in this order, and the row address and column address are entered synchronously with the command, then read data can be read from the memory cell MC specified by the row and column addresses. The read data DQ is output from the data terminal 224 synchronously via the input / output circuit 215 and the data strobe signal DQS output from the data strobe terminal 225. If the active command and write command are entered in this order, then the row address and column address are entered synchronously with the command, and the write data DQ is input synchronously with the data strobe signal DQS to the data terminal 224. The write data DQ is supplied to the memory cell array 211 via the input / output circuit 215. This write data DQ can be written into the memory cell MC specified by the row and column addresses.

[0062] Clock terminal 223 can supply an external clock signal CK and / or / CK. The external clock signal CK and the external clock signal / CK are complementary to each other, and both are supplied to clock input circuit 235. Clock input circuit 235 can generate an internal clock signal ICLK based on the external clock signals CK and / CK. The internal clock signal ICLK can be used as a timing signal for address latch circuit 232, command decoder 234, and other internal circuits of memory unit 240.

[0063] Power supply terminal 226 can be supplied with power supply potentials VDD and VSS, and can also serve as an internal voltage generation circuit 237. The internal voltage generation circuit 237 can generate various internal potentials, such as VPP, VARY, and VPERI, based on the power supply potentials VDD and VSS. For example, the internal potential VPP can be used in the line decoder 212. The internal potential VARY can be used in the memory cell array 211. The internal potential VPERI can be used in other circuits of the memory cell 240.

[0064] Continue to refer to Figure 2The memory cell 240 also includes a fuse circuit 250 and a polling circuit 260. The fuse circuit 250 can store the address of a defective word line WL. The defective word line WL can be not only a word line WL that is defective itself, but also a word line WL connected to a defective memory cell MC. An address signal ADD (e.g., the row address) during row access is input to the fuse circuit 250. The repair register 214 can also provide the fuse circuit 250 with certain memory addresses to be repaired. Therefore, the fuse circuit 250 can compare the input row address with the memory address in the repair register 214; and, according to the method described herein, the memory address to be repaired can be identified. A hit signal HIT is activated when a memory address is to be repaired based on whether the memory address is high or low priority. For example, when repairing a portion of a memory address associated with low priority, the fuse circuit 250 can blow the fuse associated with the memory address of the corresponding MSB indicating the trained weights of the neural network. In some implementations, fuse circuit 250 may not blow the fuse associated with the memory address of the corresponding LSB indicating the trained weights of the neural network. When repairing portions of memory addresses associated with high priority, fuse circuit 250 may blow all available fuses to repair such defective memory addresses, for example, before repairing any low priority addresses.

[0065] A hit signal (HIT) is supplied to the row decoder 212, which acts as an access control circuit. When the hit signal (HIT) is not activated, the row decoder 212 selects a word line (WL) based on the row address supplied via the address latch circuit 232. When the hit signal (HIT) is activated, the row decoder 212 selects a redundant word line (RWL) based on the hit signal (HIT). When access to the defective word line (WL) is requested, this operation results in an alternative access to the redundant word line (RWL) instead of the defective word line (WL).

[0066] Figure 3This is a block diagram of memory cell 340 arranged according to the examples described herein. Computing system 300 may include memory cell 340. For example, computing system 100 having memory cell 140 may be implemented as computing system 300 having one or more memory cells 340. Memory cell 340 includes memory array 311, similar to memory array 211 of memory cell 240. According to the systems and methods described herein, data may be stored for reading / writing in memory access operations using memory array 311. According to such methods, memory array 311 may depict all or a portion of a memory array storing data associated with low priority (e.g., a low-priority region of the memory array). In the example described, memory cells A3 and A4 355 and C4 360 are defective memory cells that have not been repaired by memory mapping implemented according to memory cell 340. Memory cells A1-D1, A2-D2, A3-D3, and A4-D4 may be associated with physical memory addresses of pages of volatile memory (e.g., DRAM memory). Therefore, in neural network applications, trained weights can be aligned via their corresponding MSBs. As depicted, identifier 350 indicates the alignment of the MSBs of data stored in rows of memory array 311. For example, identifier 350 can align MSBs along pages of memory addressed according to the physical location of memory array 311. When aligning MSBs along identifier 350, trained weights can be stored in each row such that the LSB portions of the weights stored in rows A and C are stored in defective memory cells. For example, two LSBs of a trained weight stored in row A can be stored in defective memory cells A3 and A4 355. Similarly, the LSB of another trained weight stored in row C can be stored in defective memory cell 360.

[0067] Figure 4 This is a flowchart of a repair address generation method 400 arranged according to the example described herein. Method 400 can be implemented by a repair address generator, for example... Figure 1 The repair address generator 120. Method 400 may include block 408, which describes "obtaining a memory command associated with a memory access operation". For example, an operation or procedure performed by a processor (e.g., processor 105) may obtain or receive a memory command from said operation or procedure to read or write memory cells, such as memory cells 140, 240, or 340. A read or write operation of a procedure or program implemented on processor 105 may be a memory access operation that sends a read or write command to memory controller 110. The read or write command may include a corresponding memory access operation (e.g., read or write). For example, memory controller 110 may obtain a write command to write data to memory cell 140. Memory controller 110 may also obtain a read command to read data stored at memory cell 140.

[0068] Box 408 may be followed by box 412, which states "a memory address mapping for memory addresses for memory access operations is generated, partly based on the partial error rate of the memory access operation." The repair address generator of the memory controller (e.g., repair address generator 120) may generate the memory address to be repaired depending on whether some application can operate at a high priority indicating a low bit error rate or a low priority indicating a higher bit error rate. In the examples described herein, the repair address generator may generate memory addresses based on a specified error rate. For example, the specified error rate may be a threshold error rate for a particular application (e.g., a neural network application). The neural network application may utilize stored training weights, and said trained weights may be stored in a low-priority region of memory with a higher bit error rate. Therefore, one or more LSBs of the corresponding trained weights may be stored in defective memory cells that will not be repaired, for example, as indicated by the memory address mapping.

[0069] In some instances, at block 412, the repair address generator may also identify and / or associate certain areas of memory with high or low priority indicating a specified error rate for said areas. For example, the repair address generator may obtain memory access patterns associated with multiple memory access operations, wherein the memory access patterns indicate certain areas of memory cells that are accessed more frequently than other areas of the memory cell. Using said memory address patterns, the repair address generator may identify a first portion of the memory address associated with the areas of memory cells accessed more frequently than other areas of the memory cell to generate said memory address as a high priority memory address map. The repair address generator may also identify a second portion of the memory address not associated with the areas of memory cells accessed more frequently than other areas of the memory cell to generate said memory address as a low priority memory address map. For example, the second portion of the memory address not associated with the areas of memory cells accessed more frequently than other areas of the memory cell may be a memory address where data may be stored for applications that do not require operation at a low bit error rate. For example, a neural network application can tolerate a certain number of bit flips corresponding to a threshold error rate, which may be a specified error rate. This specified error rate may be higher than the error rate of applications operating at low bit error rates, for example, for typical memory access schemes. Advantageously, when generating this memory address mapping indicating addresses to be repaired in a high-priority region and some addresses to be repaired in a low-priority region, method 500 can facilitate efficient use of memory devices with specified low-priority regions that allow applications operating at bit error rates not utilized in typical memory access schemes (e.g., DRAM bit error rates of 10^-19 to 10^-21) but still capable of efficient operation at higher bit error rates. Method 400 ends at box 420 following box 416.

[0070] Figure 5 This is a flowchart of a memory repair method 500 arranged according to the example described herein. Method 500 can be implemented by a memory controller, for example... Figure 1 The memory controller 110; or respectively by, for example Figure 6 and 7The method 500 may be implemented by a processor 605 or processor 705. Method 500 may include block 508, which states "identifying defective addresses provided to the fuse circuit". Fuse circuit 250 may receive a list of defective addresses from the memory controller based on defective memory cells identified in the memory cell array (e.g., memory cell array 211). The fuse circuit may identify such addresses as defective, which may be repaired according to a memory address mapping provided by the memory controller to a repair register (e.g., repair register 214). For example, the memory controller may provide an address to repair register 214 as a memory address mapping. When repair register 214 receives a command from command decoder 234, the memory address stored at repair register 214 may be provided to fuse circuit 250.

[0071] Box 508 may be followed by box 512, which states "compare the identified defective address with a memory address mapping having a priority associated with certain memory addresses." Fuse 250 may compare the identified defective memory address with an address mapping that includes addresses associated with high priority, low priority, or various priorities. For example, a specific memory address of a memory cell in a high-priority region of memory cell 140 (e.g., a region with an access mode associated with high priority) may be mapped to a defective memory cell as provided in the list of defective memory addresses. In some instances, the comparison may involve comparing one or more addresses of the defective memory cell of the memory cell with memory address mappings. Therefore, this comparison match performed by fuse 250 may be indicated by a HIT signal, indicating that repair of the defective memory cell should occur.

[0072] Box 512 may be followed by box 516, which states "Repairing memory addresses associated with high priority". Therefore, a fuse circuit 250 that has compared and determined a matching defective memory address in the high-priority region of memory cell 140 can repair the memory address associated with high priority based on the comparison. For example, the fuse of fuse circuit 250 can be blown such that the defective memory address is mapped to a different memory cell having a memory address associated with the blown fuse. Therefore, when accessing the defective memory address, the blown fuse can route access to a non-defective memory cell in memory cell array 210. In various embodiments, fuse circuit 250 can utilize various loops that prioritize repair in the high-priority region. For example, fuse circuit 250 can prioritize a single memory cell to be repaired in a column or row of the array, such that a specific bit stored at that single memory cell is repaired first, and then other memory cells in the high-priority region can be repaired subsequently.

[0073] Box 516 may be followed by decision box 520, which states "All high-priority repairs completed?". Fuse circuit 250 can continue repairing high-priority areas in a similar manner, also covering all high-priority areas. If all high-priority areas are repaired, then at decision box 520, the process of method 500 proceeds along the 'yes' route to box 524. If not all high-priority areas have been repaired, then the process of method 500 proceeds along the 'no' route to terminate method 500, causing memory cell 140 with fuse circuit 250 to fail, because all fuses of fuse circuit 250 have been used, and at least one high-priority defective memory cell has not yet been repaired. For example, if in the last high-priority area, fuse circuit 250 has no other fuses that need to be blown to repair the last memory cell in the last high-priority area, then method 500 will continue along the 'no' route, thereby terminating memory repair method 500, where memory cell 140 is discarded. Therefore, if not all memory addresses in all high-priority regions are repaired to operate according to a threshold error rate (e.g., a default error rate), then memory cell 140 cannot be utilized. For a typical memory access scheme, this threshold error rate is the low-bit error rate used for reading and writing data to memory. For example, fuse circuit 250 can determine whether the threshold error rate has been exceeded.

[0074] However, advantageously, in some instances, method 500 can proceed along a 'yes' route to block 524, allowing memory cell 140 to be repaired instead of discarded as semiconductor waste, because there are available fuses and additional defective memory addresses associated with one or more low-priority regions of memory cell 140. Accordingly, block 520 may be followed by block 524, which states "repairing memory addresses associated with low priority in memory regions having an error rate for portions of memory access operations." In some instances, if no fuses are available (e.g., all fuses at fuse circuit 250 have blown), then method 500 continues to terminate at block 528, where the memory addresses associated with low priority have not yet been repaired. In this case, fuse circuit 250 can determine whether a fuse element threshold (e.g., the number of available fuses to be blown) has been exceeded. Therefore, block 524 can be considered an optional block of method 500.

[0075] In some instances, although at block 524, fuse circuit 250 may additionally blow a fuse to repair memory addresses associated with low priority areas in the memory region for a specified error rate for certain memory access operations. For example, in neural network applications, defective memory addresses associated with the MSB of trained weights can be repaired. To repair such defective memory addresses, fuse circuit 250 may identify the MSB in the memory address map, where the memory address pointing to the MSB is aligned along the pages or blocks of the memory array. Therefore, fuse circuit 250 may blow the fuse associated with the memory address pointing to the MSB of the low priority area of ​​the memory cell. When repairing the address pointing to the MSB first, some of the defective memory addresses associated with the LSB of trained weights may not be repaired (e.g., there is no additional fuse to be blown in fuse circuit 250). Therefore, for neural network applications accessing low priority areas of the memory array, memory cell 140 may operate for the neural network application at a specified bit error rate, for example, a higher bit error rate than that of high priority areas operating according to the low bit error rate. Method 500 ends at box 528, which follows box 524.

[0076] The boxes included in the described example methods 400 and 500 are for illustrative purposes. In some embodiments, the boxes may be executed in a different order. In some other embodiments, various boxes may be eliminated. In other embodiments, various boxes may be divided into additional boxes, supplemented by other boxes, or combined together to form fewer boxes. Other variations of these particular boxes are considered, including changes in the order of the boxes, changes in the content of boxes that are divided or combined into other boxes, etc.

[0077] Figure 6 This is a schematic diagram of a computing system 600 arranged according to the examples described herein. The computing system 600 may operate according to any embodiment described herein, such as computing system 100. The computing system also includes a processor 605, an I / O interface 670, an internal bus 680, a network interface 690 coupled to a network 695, and a memory unit 640 coupled to the bus 680. The processor 605 may include any type of microprocessor, central processing unit (CPU), application-specific integrated circuit (ASIC), digital signal processor (DSP) implemented as part of a field-programmable gate array (FPGA), system-on-a-chip (SoC), or other hardware to provide processing for system 600.

[0078] The computing system 100 also includes a computing device 602, which may be a smartphone, wearable electronic device, server, computer, machinery, vehicle, or any type of electronic device. The computing device 602 includes a memory controller 610 having a repair address generator 620 and a repair cache 630, both operating according to the functionality described herein with respect to the repair address generator 120 and the repair register 214. The computing device 602 also includes a memory cell 640, which can be like... Figure 1 Memory cell 140 Figure 2 memory cell 240 or Figure 3 It is operated and configured in the same way as memory unit 340.

[0079] The computing device 602 may also include local memory 650, which may be a non-transitory hardware-readable medium 550 containing instructions for repairing memory addresses, the repair being implemented, for example, by methods 400 and / or 500. For example, local memory 650 may store instructions for executing programs, such as method 400 or method 500. Communication between processor 605, I / O interface 670, and network interface 690 is provided via processor internal bus 680. Memory controller 610 may perform a repair operation based on executable instructions stored in memory 650, causing computing device 602 to access repair cache 630 or repair memory cell 640.

[0080] Bus 680 may include one or more physical buses, communication lines / interfaces, and / or point-to-point connections, such as a Peripheral Component Interconnect (PCI) bus. I / O interface 670 may include various user interfaces, including video and / or audio interfaces for users, such as a flat panel display with a microphone. Network interface 690 communicates with other computing devices (such as computing system 600 or a cloud computing server) via network 695. For example, network interface 690 may be a USB interface.

[0081] Figure 7 This is a schematic diagram of a neural network system 702 arranged according to the examples described herein. The computing system 700 may operate according to any embodiment described herein, such as computing system 100. For Figure 7 Other similarly numbered elements, such elements contain elements similar to Figure 6Similar functionality to those numbered elements. The computing system 700 includes a neural network system 702, which can be implemented on a device with a processor, such as a smartphone, wearable electronics, server, computer, machinery, vehicle, or any type of electronic device. For example, the neural network system 702 can be implemented on any type of microprocessor, central processing unit (CPU), application-specific integrated circuit (ASIC), digital signal processor (DSP) implemented as part of a field-programmable gate array (FPGA), system-on-a-chip (SoC), or other hardware to provide processing for the computing system 700. In some instances, the neural network system can be implemented on a processor 705. The neural network system 702 can utilize memory access operations to train and store weights for learning operations to be executed on the neural network system 702.

[0082] The neural network system 702 also includes a repair address generator 720 and a repair cache 730, both of which operate according to the functionality described herein with respect to the repair address generator 120 and the repair register 214. The neural network system 702 also includes a memory unit 740, which can be like... Figure 1 Memory cell 140 Figure 2 memory cell 240 or Figure 3 It is operated and configured in the same way as memory unit 340.

[0083] The neural network system 702 may also include local memory 745, which may be a non-transitory hardware-readable medium 745 containing instructions for training the neural network weights. For example, the neural network system 702 may execute instructions for weight training such that calibration data received from network 795 or I / O interface 770 can be used to train the weights according to an optimization scheme of the neural network (e.g., a least squares algorithm for training the weights). After training the weights, the neural network system 702 may store the trained weights in memory unit 740 according to the instructions for weight training 745.

[0084] Additionally or alternatively, the neural network system 702 may include a local memory 750, which may be a non-transitory hardware-readable medium 750 containing instructions for memory address repair, said repair being implemented, for example, by methods 400 and / or 500. For example, the local memory 750 may store instructions, for example, for executing methods 400 or 500. The neural network system 702 may perform the repair operation according to the executable instructions stored in the memory 750, causing the neural network system 702 to access a repair cache 730 or a repair memory cell 740.

[0085] The various illustrative blocks and modules described herein can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0086] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Computer-readable media includes both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), or optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures, and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor.

[0087] Furthermore, any connection is properly referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave), then the definition of media includes the aforementioned coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology (such as infrared, radio, and microwave). Combinations of the above are also included within the scope of computer-readable media.

[0088] Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0089] Furthermore, as used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list of items preceded by phrases such as "at least one of" or "one or more of"), indicates that the list includes items such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an example step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "at least partially based on".

[0090] As will be understood from the foregoing, although specific examples have been described herein for illustrative purposes, various modifications may be made while retaining the scope of the claimed techniques. The descriptions herein are provided to enable those skilled in the art to make or use this disclosure. In some instances, well-known wireless communication components, circuits, control signals, timing protocols, computing system components, and software operations have not been shown in detail to avoid unnecessarily obscuring the described embodiments of this disclosure. Those skilled in the art will readily understand various modifications to this disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is consistent with the broadest scope of the principles and novel features disclosed herein.

Claims

1. A method comprising: Obtain a memory access pattern associated with multiple memory access operations, the memory access pattern indicating a first area of ​​a memory cell that is accessed more frequently than a second area of ​​the memory cell that stores data for weights of a neural network, the second area of ​​the memory cell being identified as being associated with a specified error rate for storing the weights of the neural network. Obtain a plurality of memory commands associated with the plurality of memory access operations, at least a portion of which are associated with the specified error rate for storing the weights of the neural network; A memory address mapping for the plurality of memory access operations is generated based on the first region of the memory cell and the second region of the memory cell identified as being associated with the specified error rate for storing the weights of the neural network. and The memory address mapping is provided to a memory data register of a memory cell, the memory data register being accessible by the memory cell for repairing at least one of the first region and the second region of the memory cell.

2. The method according to claim 1, further comprising: Accessing the second region of the memory cell based on the memory address mapping to implement at least one of the plurality of memory commands, the second region of the memory cell being associated with the specified error rate for at least the portion of the plurality of memory access operations; and Access the first area of ​​the memory cell to execute another memory command among the plurality of memory commands.

3. The method of claim 1, wherein the memory data register accessible by the memory cell corresponds to a register or local cache of the memory cell.

4. The method of claim 1, wherein the specified error rate corresponds to a threshold error rate for storing the weights of the neural network.

5. The method of claim 4, wherein the threshold error rate for storing the weights of the neural network is based on the bit-flip tolerance of the neural network.

6. The method of claim 1, further comprising: In the memory access mode, a first portion of the memory address associated with the first region of the memory cell that is accessed more frequently than the second region of the memory cell is identified as a high priority of the memory address mapping. and In the memory access mode, the second portion of the memory address associated with the second region of the memory cell is identified as a low priority of the memory address mapping.

7. The method of claim 6, further comprising: In the first portion of the memory address that is the high priority memory address, the most significant bit of each memory address in the first portion of the memory address is identified; and In the memory address mapping, each memory address of the first portion of the memory address is aligned with a memory identifier of the memory address.

8. The method of claim 7, wherein the memory identifier corresponds to a page of the memory cell or a block of the memory cell.

9. The method of claim 1, wherein the memory cell corresponds to at least one of DRAM, SRAM, NAND, resistive memory, or phase-change memory, or any combination thereof.

10. An apparatus comprising: A memory array comprising multiple memory cells, wherein the multiple memory cells include at least one defective memory cell, and each defective memory cell has a defective memory address; A register configured to store a memory address mapping that includes a plurality of memory addresses and indicates which of the plurality of memory addresses are associated with high priority and which are associated with low priority, wherein the high priority indicates a first memory address having a default error rate and wherein the low priority indicates a second memory address having a specified error rate, wherein the default error rate is different from the specified error rate; A memory controller, coupled to the memory array and configured to: The memory address mapping is provided to the register; The defect memory address of the defective memory cell is compared with the memory address mapping; and Based on the comparison between the defective memory address and the memory address mapping of the defective memory cell, at least one of the first memory address associated with the high priority and the second memory address associated with the low priority is repaired. and A fuse circuit configured to store the address of the defect memory.

11. The device of claim 10, wherein the fuse circuit comprises: Multiple fuse elements, each corresponding to a bit in a plurality of bits of the defect memory address.

12. The device of claim 10, wherein the memory controller is further configured to: Identify the address of the defect memory stored in the fuse circuit.

13. The device of claim 10, wherein the memory controller is further configured to: A portion of the repair process for determining the memory address associated with the high priority is performed in the first region of the memory array; and Repair at least one memory address in the second memory address associated with the low priority in the second region of a memory array having a specified bit error rate for certain memory access operations.

14. The apparatus of claim 13, wherein each of the plurality of memory access operations comprises an instruction for a corresponding address of a memory cell among the plurality of memory cells.

15. The device of claim 13, wherein the memory controller is further configured to: It was determined that a fuse element threshold had been exceeded when repairing at least one memory address in the second memory address associated with the low priority; and Repair the extra portion of the memory address associated with the high priority in the third region of the memory array.

16. The device of claim 10, wherein the memory controller is further configured to: A portion of the repair of the memory address associated with the high priority was not completed in the first region of the memory array; and This disables the first region of the memory array.

17. The device according to claim 10, further comprising: A processor or host device coupled to the memory controller, wherein the memory controller is configured to receive memory commands from the processor or the host device.

18. The device according to claim 10, further comprising: A memory interface coupled to the memory controller and configured to communicate with the memory array, wherein the memory controller is configured to provide the memory address mapping to the memory array via the memory interface.

19. A method comprising: Provide memory address mapping to registers that can be accessed by memory cells; The memory address mapping compares one or more addresses of the defective memory cell of the memory cell with the memory address mapping containing multiple memory addresses, and indicates which of the multiple memory addresses are associated with a high priority with a default error rate and which are associated with a low priority, the low priority indicating which memory addresses will be accessed for multiple memory access operations associated with a specified error rate, wherein the default error rate is different from the specified error rate; and At least one memory address among the memory addresses associated with the high priority and the memory addresses associated with the low priority is repaired based at least in part on the comparison.

20. The method of claim 19, wherein the specified error rate corresponds to a threshold error rate for storing the weights of the neural network.

21. The method of claim 20, further comprising repairing the memory address indicating the most significant bit of the weights in the weights of the neural network.

22. The method of claim 21, further comprising: The fuse element that corresponds to the most significant bit of the weight among a plurality of fuse elements is blown.

23. The method of claim 19, wherein the plurality of memory addresses correspond to physical memory addresses or virtual memory addresses.

24. The method of claim 19, further comprising: In response to a memory access operation in one of the plurality of memory access operations, a plurality of memory cells are accessed according to a repaired memory address indicating at least one of the memory addresses associated with the low priority.

25. An apparatus comprising: A memory array comprising a plurality of memory cells, the plurality of memory cells including at least one defective memory cell among a plurality of defective memory cells having a specified error rate in a first region of the memory array, wherein in a memory access mode of the memory array, the first region of the memory array is accessed less frequently than a second region of the memory array to which data is accessed. and A non-transitory computer-readable medium encoded with executable instructions that, when executed, cause the device to identify weights for use in a neural network and store the weights of the neural network in at least one of a plurality of defective memory cells having the specified error rate in the first region of the memory array, wherein at least one least significant bit of the corresponding weight is stored in the corresponding defective memory cell of the plurality of defective memory cells.

26. The device of claim 25, wherein the specified error rate corresponds to a first threshold error rate for storing the weights of the neural network associated with access operations at the memory array.

27. The device of claim 26, wherein the first threshold error rate for storing the weights of the neural network is different from the second threshold error rate associated with additional access operations in the second region of the memory array of the accessed data.

28. The device of claim 27, wherein the non-transitory computer-readable medium is further encoded with executable instructions that, when executed, cause the neural network to repair a portion of the memory address associated with the access operation and to repair the memory address associated with the additional access operation.

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