Application programming interface for indicating stepped memory

Abstract

The invention relates to an application programming interface for indicating strided memory. Apparatuses, systems, and methods for performing thread memory addressing are disclosed. In at least one embodiment, a processor includes one or more circuitry to execute an application programming interface (API) to cause execution of one or more instructions based at least in part on one or more API parameters, the one or more API parameters indicate a size of one or more operands to be used by the one or more instructions.

Description

Technical Field

[0001] Apparatus, systems, and methods for performing thread memory addressing. At least one embodiment relates to execution instructions for executing an application programming interface (API) such that one or more instructions are executed at least in part based on one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. Background Technology

[0002] Parallel threads on processors such as graphics processing units (GPUs) access different memory locations. The methods used to determine these memory locations can be improved. Attached Figure Description

[0003] Figure 1 It is a block diagram illustrating a system for calculating the memory address of a thread according to at least one embodiment;

[0004] Figure 2 This is a block diagram illustrating a system for updating pointers based on the memory address of a thread, according to at least one embodiment;

[0005] Figure 3 The diagram illustrates the kernel according to at least one embodiment and how the kernel is invoked so that the API uses pointer references to different memory addresses in the memory.

[0006] Figure 4 It is a block diagram illustrating a thread initiation operation according to at least one embodiment;

[0007] Figure 5 It is a block diagram illustrating a process for calculating and storing memory addresses using stride length according to at least one embodiment;

[0008] Figure 6 It is a block diagram illustrating a process for updating a pointer according to at least one embodiment;

[0009] Figure 7 It is a block diagram illustrating the process that enables threads to access data elements based on updatable pointers;

[0010] Figure 8 The diagram illustrates a driver and / or runtime according to at least one embodiment, the driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs);

[0011] Figure 9 The illustration shows an example of a system according to at least one embodiment that may include software and hardware for causing to execute one or more instructions;

[0012] Figure 10 An example data center system according to at least one embodiment is shown;

[0013] Figure 11 A system-on-a-chip (SOC) according to at least one embodiment is shown;

[0014] Figure 12A A parallel processor according to at least one embodiment is shown;

[0015] Figure 12B A processing cluster according to at least one embodiment is shown;

[0016] Figure 12C A graphics multiprocessor according to at least one embodiment is shown;

[0017] Figure 13 An accelerator processor according to at least one embodiment is shown;

[0018] Figure 14A A central processing unit according to at least one embodiment is shown;

[0019] Figure 14B The illustration shows an embodiment according to at least one of the embodiments. Figure 14A The core of the central processing unit;

[0020] Figure 15 Another accelerator processor according to at least one embodiment is shown;

[0021] Figure 16 A neuromorphic processor according to at least one embodiment is shown;

[0022] Figure 17 A supercomputer according to at least one embodiment is shown;

[0023] Figure 18 Another accelerator processor according to at least one embodiment is shown;

[0024] Figure 19 Another processor according to at least one embodiment is shown;

[0025] Figure 20 Another accelerator processor according to at least one embodiment is shown;

[0026] Figure 21 A tensor processing unit according to at least one embodiment is shown;

[0027] Figure 22 A RISC-V compatible processor according to at least one embodiment is shown;

[0028] Figure 23A and Figure 23B A language processing unit according to at least one embodiment is shown;

[0029] Figure 24 A software stack of a programming platform according to at least one embodiment is shown;

[0030] Figure 25 Software supported by a programming platform according to at least one embodiment is shown;

[0031] Figure 26 A method for using at least one embodiment is shown. Figure 25 Compiled code executed on the programming platform;

[0032] Figure 27 An example of an autonomous vehicle and its system architecture according to at least one embodiment is shown;

[0033] Figure 28A The inference and / or training logic according to at least one embodiment is illustrated;

[0034] Figure 28B The inference and / or training logic according to at least one embodiment is shown; and

[0035] Figure 28C Training and deployment of a neural network according to at least one embodiment are illustrated. Detailed Implementation

[0036] Numerous specific details are set forth in the following description to provide a more thorough understanding of at least one embodiment. However, it will be apparent to those skilled in the art that the inventive concept can be practiced without one or more of these specific details.

[0037] In at least one embodiment, the API (e.g., cudaLaunchKernel()) is used to cause a thread to execute, wherein the input parameters of the API (e.g., StrideLength) indicate the memory address to be used by the thread to access information that the thread will use. In at least one embodiment, when executed, the API stores one or more memory addresses in a location that each thread is programmed to access. In at least one embodiment, when each thread is executed, the thread reads the location to obtain the memory address to use, rather than performing calculations to generate an address based on its thread identifier. In at least one embodiment, the processor may include one of the processors described below and / or include one or more circuitry for causing one or more instructions to be executed, or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, wherein the one or more API parameters indicate the size of one or more operands to be used by the one or more instructions.

[0038] In at least one embodiment, given a block and thread index, a starting pointer position is calculated, and then several positions are additionally identified based on that starting pointer using 32-bit computation, where the starting position is a row in the image. This means that each thread may need to calculate several starting positions, and each starting position requires computationally expensive computations (e.g., 64-bit operations) to be performed several times across all threads. In at least one embodiment, instead of performing 64-bit addressing operations on each thread, a kernel function executed at startup before the thread performs a read or write operation is used, allowing the kernel to calculate the address of the neighboring element relative to the calculated starting address using a stride dimension.

[0039] In at least one embodiment, a kernel startup API that includes preprocessing memory addresses at least in part based on a stride dimension reduces the amount of configuration the user is responsible for when dispatching tasks to threads to perform operations. In at least one embodiment, the kernel startup API includes an updatable pointer or a displaced pointer. In at least one embodiment, the pointer includes an indication that the pointer is decorated to be updated or displaced. In at least one embodiment, the pointer refers to various memory addresses that the thread will access, avoiding large jumps in user-specified memory address calculations, rather than simply the start or beginning of a memory location.

[0040] In at least one embodiment, 32-bit computation and a stride dimension can be used to access data elements near the starting data element. In at least one embodiment, the stride dimension is available in constant memory, similar to storage as a block dimension as a set of threads and a grid dimension as a set of blocks. In at least one embodiment, by pre-computing the 64-bit addresses of input and output data regions in the context of kernel configuration or kernel startup, subsequently started threads can work in data blocks close to their corresponding pointers. This provides data locality, thereby improving processing speed or consuming fewer computational resources when threads are processing in two-dimensional or three-dimensional contexts, such as images or batches of images in computer vision algorithms.

[0041] In at least one embodiment, the parameter is defined as a pointer that specifies the spacing between memory accesses by different threads. In at least one embodiment, the parameter is defined by StrideLength, which instructs a thread to traverse to access subsequent data elements. In at least one embodiment, the parameter is defined as part of a function invoked by the kernel. In at least one embodiment, the pointer is updated with different memory addresses based on the spacing between memory accesses by different threads.

[0042] In at least one embodiment, as used herein, a pointer is a variable that stores the base memory address or starting memory location of a block of memory that stores data to be accessed by multiple concurrent threads. In at least one embodiment, as used herein, a reference refers to a specific memory location. In at least one embodiment, a pointer is a reference to the starting memory location of a block of memory.

[0043] In at least one embodiment, the size of a memory location within a memory block is determined by the data type stored at that memory location. In at least one embodiment, for example, if a pointer is declared as "int*", then the pointer points to a memory location of size int (e.g., 4 bytes) (the starting memory location of the memory block). In at least one embodiment, the size of the entire memory block pointed to by the pointer at the starting location is determined by the data type of the elements in the block and the number of elements in the block.

[0044] Figure 1This is a block diagram illustrating a system 100 for computing threads according to at least one embodiment. In at least one embodiment, system 100 is a CUDA (Computing Unified Device Architecture) system, which is a parallel computing platform and application programming interface (API). In at least one embodiment, system 100 describes a system for improving computational efficiency by performing operations using a straddle dimension (e.g., operations based on a parallel computing platform). In at least one embodiment, system 100 includes various components that interact to optimize memory addressing and data processing within a processor environment. In at least one embodiment, system 100 enables developers to write programs in languages ​​such as C, C++, and Fortran, where certain functions are designated as GPU "kernels" and executed by parallel GPU threads, thereby significantly accelerating computation compared to traditional CPU processing. In at least one embodiment, system 100 may include a software stack, such as... Figure 24 The software stack 2400 is described.

[0045] In at least one embodiment, API 102 serves as an interface for initiating processor (e.g., GPU) operations. In at least one embodiment, API 102 serves as an interface for initiating CUDA operations. In at least one embodiment, API 102 is combined with... Figure 24 This corresponds to the runtime API "cudaLaunchKernel()" in the described software stack 2400. In at least one embodiment, API 102 utilizes a software layer to communicate with GPU resources, thereby enabling efficient execution of parallel tasks. In at least one embodiment, API 102 supports image processing and real-time video analytics. In at least one embodiment, API 102 supports neural network training by managing data input and output.

[0046] In at least one embodiment, API 102 enables the execution of instructions based on API parameters (including, for example, configuring kernel startup via grid, block, and stride dimensions and / or operand sizes), thereby facilitating the management of data input and output. In at least one embodiment, operand size refers to the size of a variable or value being processed or manipulated during kernel execution in terms of memory or data type. In at least one embodiment, operand size defines how much data is involved in a particular operation, thus impacting performance optimization and memory management when using GPUs for parallel computation. In at least one embodiment, operand size is expressed in various data types, including, for example, integers, single-precision floating-point numbers (float), or double-precision floating-point numbers (double).

[0047] In at least one embodiment, the software program 104 includes a GPU driver 106 that manages hardware interactions. In at least one embodiment, the software program 104 configures GPU resources to perform complex computations. In at least one embodiment, the software program 104 accelerates neural network inference by optimizing kernel startup. In at least one embodiment, the software program 104 enhances object detection and pattern recognition tasks.

[0048] In at least one embodiment, system 100 includes a processor 108 with an execution engine, memory 122, and a streaming processor (SM) 124. In at least one embodiment, processor 102 is a GPU, which is coupled with... Figure 10 and Figure 12A The processors 1008 and 1200 described herein are similar. In at least one embodiment, processor 108 represents a GPU performing parallel computations. In at least one embodiment, processor 108 utilizes multiple cores (such as those within processor 108) to perform high-speed data processing. In at least one embodiment, processor 108 enables neural networks to efficiently process large datasets by utilizing stride pointers. In at least one embodiment, processor 108 supports deep learning model training and deployment.

[0049] In at least one embodiment, execution engine 110 implements instructions, such as configuration parameters for an API. In at least one embodiment, execution engine 110 coordinates task execution within processor 108. In at least one embodiment, execution engine 110 is a parallel computing platform execution engine, such as a CUDA execution engine. In at least one embodiment, execution engine 110 is a component having processor 108 configured to manage the execution of a program (e.g., a kernel). In at least one embodiment, the program executed by processor 108 includes a CUDA program where one or more computational tasks are divided into multiple threads, which are grouped into one or more blocks, which are grouped into one or more grids. In at least one embodiment, the GPU executes threads in parallel, thereby allowing acceleration of computationally intensive tasks such as matrix multiplication, vector addition, and vector dot product. In at least one embodiment, support for functional programming functions in the CUDA programming model enables high-level languages ​​such as C / C++, Fortran, or Python to directly access these functional programming functions without using an intermediate library stack.

[0050] In at least one embodiment, processor 108 is configured to manage program execution according to a framework other than the CUDA programming model. In at least one embodiment, processor 108 may include one or more circuits for causing one or more instructions to be executed, or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. In at least one embodiment, processor 108 is configured to enable code parallelization according to Open Computing Language (OpenCL), Open Multiprocessing (OpenMP), or Message Passing Interface (MPI). In at least one embodiment, processor 108 is configured to implement advanced machine learning (such as through frameworks including TensorFlow or PyTorch). In at least one embodiment, processor 108 is configured to implement large-scale data processing and distributed computing (such as through frameworks including Apache Spark, Hadoop, and MPI).

[0051] In at least one embodiment, the execution engine 110 serves as an orchestration layer within the processor 108 to facilitate parallel processing and ensure efficient program execution. In at least one embodiment, the execution engine 110 manages thread scheduling and resource allocation. In at least one embodiment, the execution engine 110 optimizes neural network layer operations by pre-computing memory addresses. In at least one embodiment, the execution engine 110 facilitates convolutional neural network operations and recurrent neural network operations.

[0052] In at least one embodiment, execution engine 110 can use thread-specific information (e.g., grid dimension and block dimension) along with other parameters provided in the startup configuration (e.g., stride dimension and pointers to memory storing the data these threads will access) to determine the correct memory location in memory (e.g., memory 126) that each thread will access. In at least one embodiment, execution engine 110 performs this calculation once for all threads to generate the necessary memory addresses for each thread, thereby reducing the computational overhead that would otherwise occur if each thread calculated its own address.

[0053] In at least one embodiment, the calculated memory address is then stored in a designated location (such as a combination of...). Figure 12B The described L1 cache or combination Figure 12AThe described L2 cache is made accessible to each thread. In at least one embodiment, when each thread is executed by the streaming multiprocessor 128 or otherwise implemented, the thread reads or otherwise retrieves its corresponding pre-computed memory address. In at least one embodiment, this centralized memory address calculation method helps improve efficiency by offloading the task from individual threads to the execution engine 110.

[0054] In at least one embodiment, execution engine 110 performs memory address calculations for the threads to be started, and then starts those threads using the calculated memory addresses, without storing the addresses in global or shared memory. In at least one embodiment, this approach reduces memory overhead while still offloading memory address calculations from individual threads to execution engine 110.

[0055] In at least one embodiment, execution engine 110 coordinates the scheduling and initiation of threads to perform or otherwise implement specified operations. In at least one embodiment, execution engine 110 schedules threads in a grid / block structure, where each thread is identified by a unique thread and block index. In at least one embodiment, execution engine 110 manages the use of various types of memory (such as global memory and shared memory) on processor 108. In at least one embodiment, global memory 126 is as follows: Figures 12A-12C The memory described. In at least one embodiment, shared memory is combined with... Figures 12A-12C The shared memory 1270 described is similar to memory. In at least one embodiment, the shared memory 1270 is on-chip memory located within a streaming multiprocessor (SM) 128.

[0056] In at least one embodiment, the memory address calculation function 112 calculates the memory location used for data access. In at least one embodiment, the memory address calculation function 112 uses a stride dimension to reduce computational overhead. In at least one embodiment, the memory address calculation function 112 calculates the memory address of the data element that a given thread will begin processing, and the stride length used to update the pointer to a subsequent memory address that the thread will access (such as for a read or write operation). In at least one embodiment, the memory address calculation function 112 improves the efficiency of the neural network by minimizing address computation. In at least one embodiment, the memory address calculation function 112 supports image segmentation and feature extraction.

[0057] In at least one embodiment, execution engine 110 calculates the memory addresses of all parallel threads it initiates. In at least one embodiment, when processor 108 is accessed from the host (e.g., in conjunction with...) Figure 12AWhen a CPU (similar to a CPU) in the described CPU 1202 receives a request 106 to start a thread, in at least one embodiment, the execution engine 110 may execute a memory address calculation function 112 to determine the memory addresses 114, 116, and 118 for each corresponding thread 120, 122, and 124. In at least one embodiment, memory addresses 114, 116, and 118 facilitate efficient data retrieval for training algorithms. In at least one embodiment, memory addresses 114, 116, and 118 support batch processing and data augmentation.

[0058] In at least one embodiment, system 100 can therefore perform the conversion of a pointer to memory 126 into different references to threads 120, 122, 124 by calculating memory addresses 114, 116, 118 in a centralized location for these threads using execution engine 110 or as a result of calling API 102 (such as cudaLaunchKernel()). In at least one embodiment, memory addresses 114, 116, and 118 store data pointers for thread operations, such as data pointers to data elements that the threads will access. In at least one embodiment, memory addresses 114, 116, and 118 reduce the latency for each respective thread 120, 122, 124 to access the required data. In at least one embodiment, memory addresses 114, 116, and 118 provide fast access to the data required by the neural network.

[0059] In at least one embodiment, the streaming multiprocessor (SM) 128 executes multiple threads concurrently. In at least one embodiment, the streaming multiprocessor 128 optimizes resource utilization of the neural network. In at least one embodiment, the SM 128 is a core processing unit within the processor 108 that executes or otherwise implements a large number of threads in parallel. In at least one embodiment, the SM 128 includes multiple execution units, such as those combined with... Figure 20 The tensor core 2006 is described. In at least one embodiment, the streaming multiprocessor 128 accelerates the execution of deep learning models. In at least one embodiment, the streaming multiprocessor 128 supports complex data processing and analysis.

[0060] In at least one embodiment, combined Figure 1 At least one of the described features uses Figure 2-28B The description and / or combination thereof Figure 2-28B Implemented by at least one feature of any or more systems and / or one or more processes described. In at least one embodiment, combined with Figure 1 At least one of the described features is used to achieve Figure 2-28B The description and / or about Figure 2-28BAt least a portion of any or more systems and / or one or more processes described.

[0061] Figure 2 This is a block diagram illustrating a system 200 for calculating memory addresses according to at least one embodiment. In at least one embodiment, system 200 describes a method for enhancing performance on parallel computing platforms (such as for computer vision tasks) by utilizing stride dimension. In at least one embodiment, system 200 includes components for optimizing memory addressing and data processing within a GPU environment (e.g., for performing CUDA-based image processing or neural network tasks). In at least one embodiment, system 200 pre-computes memory addresses using stride dimension, thereby reducing computational overhead. In at least one embodiment, this method allows threads to work on data blocks close to their corresponding pointers. In at least one embodiment, the method is particularly effective for two-dimensional or three-dimensional data (such as images).

[0062] In at least one embodiment, system 200 employs a processor with circuitry to execute an API that executes instructions based on parameters to define pointers that can be updated, such as a modified pointer 206. In at least one embodiment, the processor may include one of the processors discussed herein and / or include one or more circuits for causing one or more instructions to be executed, or otherwise performing any of the operations described above or elsewhere herein, based at least in part on one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. In at least one embodiment, configuring an updatable pointer improves computational efficiency by reducing the need for 64-bit computation. In at least one embodiment, the updatable pointer is defined at kernel startup, which has an initial memory location for threads to access data elements. The memory location may be based on one or more dimensions, for example, dimensions 212, 214, 216 corresponding to a three-dimensional (3D) addressable space (such as a 3D image).

[0063] In at least one embodiment, memory index 202 represents a structure for managing memory location 204. In at least one embodiment, memory index 202 utilizes a mapping system to efficiently access data required by the GPU (such as to support image processing and real-time video analytics).

[0064] In at least one embodiment, memory location 204 describes a specific area accessible to a processor (such as processor 108), namely, memory (including memory 106). In at least one embodiment, memory location 204 stores input and output data for image processing. In at least one embodiment, memory location 204 facilitates efficient data retrieval for neural network training algorithms and batch processing.

[0065] In at least one embodiment, pointer 206 is a reference to a memory address for an operation specific to a given thread. In at least one embodiment, the memory address may include multidimensional components, such as coordinates in the X, Y, and Z dimensions. In at least one embodiment, the starting memory address includes component 208 indicating the X-dimensional coordinates of the memory address of a data element that the thread may access for a read or write operation.

[0066] In at least one embodiment, pointer 206 is subsequently updated to the next memory address specific to a given thread using a step dimension to optimize data access. In at least one embodiment, the subsequent memory address includes a component 210 indicating the subsequent X-dimensional coordinates of the memory address of a data element that the thread might access for a read or write operation. In at least one embodiment, iteration of the loop advances the memory address of pointer 206 by a specified step length for each dimension, such as 212, 214, 216. In at least one embodiment, pointer 206 supports high-resolution image analysis and feature extraction, including a multidimensional addressable space that may include more than Cartesian coordinates, such as taking time into account in the video or using alternative coordinate mapping schemes.

[0067] Figure 3 This is pseudocode 300 illustrating a kernel according to at least one embodiment and how said kernel is invoked so that an API translates a pointer to memory into a reference to a different memory address in said memory. In at least one embodiment, the kernel will be composed of SMs (e.g., as combined with...) in each parallel thread. Figure 1 The SM 128 described is executed. In at least one embodiment, the kernel executes in each parallel thread running on the SM, but on different data stored in different memory locations.

[0068] In at least one embodiment, pseudocode 300 describes a method for enhancing computer vision tasks by leveraging CUDA stride dimensions. In at least one embodiment, pseudocode 300 includes components for optimizing memory addressing and data processing within a GPU environment. In at least one embodiment, pseudocode 300 employs a processor with circuitry to execute API instructions based on API parameters. In at least one embodiment, the processor may include one of the processors discussed herein and / or include one or more circuitry for causing one or more instructions to be executed, or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0069] In at least one embodiment, block 302 represents the kernel boot configuration. In at least one embodiment, block 302 defines the grid dimension, block dimension, and stride dimension, as well as allocates and populates input and output images, and allocates and populates an array of values ​​to be used as an updatable pointer (e.g., pointer 206).

[0070] In at least one embodiment, block 304 describes kernel function definitions. In at least one embodiment, block 304 includes step pointers for input and output data.

[0071] In at least one embodiment, block 306 performs data assignment within the kernel. In at least one embodiment, block 306 uses a stride dimension to access a specific memory location associated with the output image by updating a pointer passed as an argument. In at least one embodiment, the pointer's decorator indicates the specific thread block for which the pointer should be updated, such that the pointer is not necessarily updated for every thread block. In at least one embodiment, the pointer is updated for each thread block. In at least one embodiment, the pointer is updated for each thread within the thread block. In at least one embodiment, each thread receives a different memory address based on its thread position and stride dimension.

[0072] Figure 4 This is a block diagram illustrating a thread initiation operation 400 (“Operation 400”) according to at least one embodiment. In at least one embodiment, Operation 400 is one or more computational operations, which, if executed, cause the processor (e.g., in conjunction with...) to... Figure 1 The processor 108 described is configured and the kernel is started for parallel execution on the processor (e.g., processor 108 or GPU).

[0073] In at least one embodiment, operation 400 includes a kernel startup API call 402 (“Call 402”) and a kernel startup API response 404 (“Response 404”). In at least one embodiment, call 402 is a function call to be executed by one or more software programs (such as the kernel), which are to be executed by or otherwise implemented by a parallel processing unit (e.g., a GPU). In at least one embodiment, call 402 is executed by the kernel (such as in conjunction with...) Figure 2 The kernel described is executed. In at least one embodiment, the kernel launches multiple threads based on a parallel computing platform, including CUDA, OpenCL, Portable Heterogeneous Computing Interface (HIP), PyTorch, and OpenMP.

[0074] In at least one embodiment, retrieval 402 is used as input to receive parameters 406, 408, 410, 412, and 414. In at least one embodiment, these parameters include grid dimension 406, block dimension 408, stride dimension 410, data type 412, and pointer 414.

[0075] In at least one embodiment, grid dimension 408 defines the number of thread blocks in the grid, thereby allowing one-dimensional or more-dimensional (e.g., 1D, 2D, or 3D) grid configurations. In at least one embodiment, grid dimension (10, 10) configures the grid to contain 100 blocks, each potentially containing multiple threads as specified by block dimension 408.

[0076] In at least one embodiment, block dimension 408 specifies the number of threads within each block. In at least one embodiment, the block dimension is provided in a 1D, 2D, or 3D configuration format. For example, in at least one embodiment, block dimension (16, 16) configures each block to contain 256 threads arranged in a 2D grid.

[0077] In at least one embodiment, grid dimension 406 and block dimension 408 can be used to compute thread identifiers (also referred to as global indexes of threads) in the entire thread grid to be launched on one or more SMs.

[0078] In at least one embodiment, stride dimension 410 can indicate the spacing between memory accesses by different threads. In at least one embodiment, stride dimension 410 represents the number of memory elements each thread must skip to reach the data it is assigned to. In at least one embodiment, for example, in a 2D matrix, stride can represent the number of elements in a row. In at least one embodiment, the exact memory reference that each thread should access can be determined by multiplying the stride by a global index to calculate the memory location of the thread. In at least one embodiment, for a 1D array, the stride is 1 because each consecutive element in the array is stored next to the previous element. In at least one embodiment, for a 2D array (matrix), the stride is the number of columns in the matrix, meaning that in order to access an element in the next row, a thread will skip a number of elements equal to the stride (the width of the matrix). In at least one embodiment, for example, if the matrix has 10 columns, the stride would be 10, meaning that a thread accessing an element in row 0, column 0 needs to skip 10 elements to access the corresponding element in row 1, column 0. In at least one embodiment, for a 3D array (volume or tensor), each dimension has a stride (e.g., row stride, depth stride). In at least one embodiment, the row stride can be the number of elements in a row, while the depth stride can be the number of elements in a slice of the 3D array.

[0079] In at least one embodiment, data type 412 indicates the size and type of the data element being processed, such as an integer, a floating-point number, or a more complex structure. In at least one embodiment, since the size of the data type determines how much memory each element occupies, the data type 412 can be used to calculate memory addresses. In at least one embodiment, for example, if the data type is a single-precision floating-point number (e.g., 4 bytes), the memory location for each thread must be adjusted accordingly to take the element size into account.

[0080] In at least one embodiment, pointer 414 represents the starting memory address within a memory block where data is stored. In at least one embodiment, pointer 414 serves as the base address for all memory accesses by a thread. In at least one embodiment, pointer 414, when combined with a thread's global index, stride, and data type, can be used to calculate the memory location for each thread. In at least one embodiment, pointer 414 can point to a memory location that one of these threads wants to access, for example, the thread with thread identifier 0, which identifies the first thread in the first block of the thread grid.

[0081] In at least one embodiment, the CUDA kernel startup API invoked by CUDA kernel startup API call 402 can cause the processor to generate a response 404 including a status parameter 408. In at least one embodiment, the status parameter 408 may be a code, a value, or other information indicating whether the CUDA kernel startup invoked by CUDA kernel startup API call 402 was successful or encountered an error. In at least one embodiment, the processor may include one of the processors discussed herein and / or include one or more circuitry for causing one or more instructions to be executed, or otherwise performing any of the operations described above or elsewhere herein, based at least in part on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0082] In at least one embodiment, combined Figure 4 At least one of the described features is the use of Figure 1-3 and Figure 5-28C The description and / or combination thereof Figure 1-3 and Figure 5-28C Implemented by at least one feature of any or more systems and / or one or more processes described. In at least one embodiment, combined with Figure 4 At least one of the described features is used to achieve Figure 1-3 and Figure 5-28C The description and / or about Figure 1-3 and Figure 5-28C At least a portion of any or more systems and / or one or more processes described.

[0083] Figure 5 This is a block diagram illustrating a process for calculating and storing memory addresses using stride length according to at least one embodiment. In at least one embodiment, process 500 describes a method for optimizing memory addressing in a CUDA environment using stride dimension. In at least one embodiment, process 500 includes the step of improving computational efficiency by reducing the need for threads to perform 64-bit computations to identify subsequent memory addresses for accessing data elements, rather than assigning such computational tasks within an operation performed at kernel startup.

[0084] In at least one embodiment, process 500 employs a processor with circuitry to configure kernel startup parameters for the stride dimension. In at least one embodiment, this configuration allows threads to efficiently access memory locations, thereby improving the performance of computer vision tasks. In at least one embodiment, the processor may include one of the processors discussed herein and / or include one or more circuitry for causing one or more instructions to be executed, or otherwise performing any of the operations described above or elsewhere herein, based at least in part on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0085] In at least one embodiment, block 502 configures kernel startup parameters for the stride dimension. In at least one embodiment, block 502 performs memory traversal within a given dimension of the addressable memory space using a defined stride length. In at least one embodiment, the kernel is as follows: Figure 2 The kernel as described.

[0086] In at least one embodiment, box 504 identifies a given dimension of a memory address. In at least one embodiment, the memory address corresponds to a pixel in an image. In at least one embodiment, box 504 identifies the starting memory address of a data element to be accessed by a given thread within a thread set. In at least one embodiment, box 504 facilitates efficient data access for image processing or neural network training and inference.

[0087] In at least one embodiment, box 506 traverses memory within a given dimension using a stride length. In at least one embodiment, box 506 calculates the memory address of a target data element for a thread to access a thread operation (such as reading or writing to a memory address). In at least one embodiment, box 506 iteratively calculates the memory addresses to be accessed by a given thread, such as memory addresses corresponding to all pixels the thread will access and memory addresses for all images the thread will access. In at least one embodiment, box 506 supports pixel transformation and color adjustment operations. In at least one embodiment, the calculated stride length derived by box 506 is used to update the pointer corresponding to the given thread for subsequent calculations. In at least one embodiment, decision box 510 supports high-resolution image analysis and feature extraction.

[0088] In at least one embodiment, decision box 508 checks whether all memory addresses for all threads have been calculated for a given dimension. In at least one embodiment, decision box 508 ensures the integrity of address calculations before proceeding. In at least one embodiment, decision box 508 facilitates batch processing and real-time video analytics.

[0089] In at least one embodiment, if not all threads compute the corresponding memory address within a given dimension, then box 510 identifies the starting address of the next thread, and boxes 506 and 508 are repeated.

[0090] In at least one embodiment, if all threads have computed the corresponding memory address within a given dimension, process 500 continues to decision box 512 to check whether all dimensions have been addressed. In at least one embodiment, decision box 512 verifies the comprehensive addressing across dimensions. In at least one embodiment, decision box 512 optimizes convolution operations and pooling layers.

[0091] In at least one embodiment, if not all dimensions have corresponding memory addresses computed for the thread set, then box 514 identifies the next dimension and repeats boxes 504-508. In at least one embodiment, box 514 iterates through the dimensions to ensure thorough processing. In at least one embodiment, box 514 supports recurrent neural network operations. In at least one embodiment, if all dimensions have already computed corresponding memory addresses for the thread set, then process 500 continues to box 516.

[0092] In at least one embodiment, box 516 stores an index of the address of each thread that is computed. In at least one embodiment, box 516 maintains a record of the memory locations accessed by the threads. In at least one embodiment, box 516 improves data locality and reduces latency because the stored index of the address can be used by the thread when performing an operation, rather than by the thread computed subsequent memory addresses (if required by subsequent operations).

[0093] In at least one embodiment, process 500 uses a stride dimension to allow for efficient memory management in a processor (e.g., GPU) environment. In at least one embodiment, this innovation minimizes the need for expensive 64-bit computations required for each thread to access each memory address of the corresponding thread. In at least one embodiment, process 500 supports complex data processing and analysis.

[0094] In at least one embodiment, the architecture of process 500 offers significant advantages in computer vision tasks. In at least one embodiment, the system design facilitates efficient execution of neural network models. In at least one embodiment, process 500 improves performance during image processing, such as rendering changes or for recognition and object detection. In at least one embodiment, process 500 enables efficient processing of large-scale datasets. In at least one embodiment, process 500 utilizes stride dimension to improve data access patterns. In at least one embodiment, process 500 contributes to advancements in parallel computing techniques.

[0095] Figure 6This is a block diagram illustrating a process for updating a pointer according to at least one embodiment. In at least one embodiment, process 600 describes a method for optimizing memory addressing in a CUDA environment using stride dimension optimization. In at least one embodiment, process 600 includes the step of improving computational efficiency by reducing the need for 64-bit computation.

[0096] In at least one embodiment, process 600 employs a processor with circuitry to configure kernel startup parameters for the stride dimension. In at least one embodiment, this configuration allows threads to efficiently access memory locations, thereby improving the performance of computer vision tasks. In at least one embodiment, the processor may include one of the processors discussed herein and / or include one or more circuitry for causing one or more instructions to be executed, or otherwise performing any of the operations described above or elsewhere herein, based at least in part on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0097] In at least one embodiment, block 602 is a modified pointer configuration function capable of being updated with straddle dimensions at kernel startup. In at least one embodiment, the kernel is as follows: Figure 2 In at least one embodiment, the pointer is defined as an argument to the function, such that the pointer can be updated using a stride length defined for the dimensional grid of the block.

[0098] In at least one embodiment, block 604 generates pointers affected by the stride dimension for each dimension. In at least one embodiment, block 604 determines the starting memory address for the corresponding thread within the thread set.

[0099] In at least one embodiment, block 606 (such as when a thread performs a read or write operation on the data element located at a memory address including one or more dimensional coordinates) updates the corresponding modified pointer for each dimensional coordinate of the data element to be accessed. In at least one embodiment, block 606 calculates the memory address accessed by the thread. In at least one embodiment, block 606 supports pixel transformation and color adjustment operations.

[0100] In at least one embodiment, box 608 provides an updated pointer to the corresponding thread. In at least one embodiment, the pointer provided as a result of box 608 is specific to the coordinates of one dimension of the multidimensional memory address of the data element to be accessed by the thread. Box 608 facilitates batch processing and real-time video analytics.

[0101] Figure 7This is a diagram illustrating a process that enables threads to access data elements based on updatable pointers. In at least one embodiment, process 700 describes a method for optimizing kernel startup in a CUDA environment using stride dimension. In at least one embodiment, process 700 includes the step of improving computational efficiency by reducing the need for 64-bit computation.

[0102] In at least one embodiment, process 700 employs a processor to configure kernel startup parameters, thereby allowing threads to efficiently access memory locations. In at least one embodiment, this configuration improves the performance of computer vision tasks by utilizing pre-computed memory addresses enabled by kernel startup that defines the stride dimension.

[0103] In at least one embodiment, block 702 includes: receiving from the host a kernel (such as...) that is booting on the device. Figure 2 The request is made by the kernel described herein. In at least one embodiment, block 702 utilizes a processor (such as...) Figure 1 The processor 108 described herein handles incoming requests executed by the kernel. In at least one embodiment, block 702 supports image processing and matrix operations.

[0104] In at least one embodiment, block 704 identifies parameters of the API request. In at least one embodiment, block 704 uses the processor to determine parameters necessary for kernel execution. In at least one embodiment, the processor may include one of the processors discussed herein and / or include one or more circuitry for causing one or more instructions to be executed, or otherwise performing any of the operations described above or elsewhere herein, based at least in part on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0105] In at least one embodiment, block 706 allocates memory for each thread based on parameters in the memory block. In at least one embodiment, block 706 uses a processor to allocate the necessary memory resources. In at least one embodiment, block 706 supports pixel transformation and color adjustment operations.

[0106] In at least one embodiment, block 708 calculates the memory location for each thread based on parameters in the memory block pointed to by the pointer. In at least one embodiment, block 708 uses an execution engine (such as execution engine 110) to perform the computation. In at least one embodiment, block 708 facilitates batch processing and real-time video analytics.

[0107] In at least one embodiment, block 710 stores the calculated memory address in a storage device on the processor, thereby enabling the corresponding pointer to be updated. In at least one embodiment, block 712 initiates a thread that is enabled to access the corresponding memory address based on an updatable pointer using the calculated memory address of the data element to be accessed by each thread. In at least one embodiment, block 712 coordinates thread execution using the updated memory pointer.

[0108] In at least one embodiment, procedure 700 allows CUDA to preprocess pointers at kernel startup, thereby reflecting the stride dimension. In at least one embodiment, this preprocessing reduces computational overhead during execution. In at least one embodiment, procedure 700 supports efficient data handling in multidimensional arrays. In at least one embodiment, the method based on procedure 700 offsets the need for multiple 64-bit computations per thread, thereby reducing computational resource consumption per thread.

[0109] In at least one embodiment, the architecture proposed in Reference Process 700 offers significant advantages in computer vision tasks by reducing the computational cost per thread. In at least one embodiment, the use of stride dimension allows for efficient memory management in processor environments such as GPUs or processors operating on CUDA or similar platforms. In at least one embodiment, this improvement minimizes the need for each thread to perform expensive 64-bit computations on each data element to be accessed, instead redirecting that processing within the kernel startup. In at least one embodiment, Process 700 supports complex data processing and analysis.

[0110] In at least one embodiment, the various components of process 700 work together to optimize processor (e.g., GPU) resource utilization. In at least one embodiment, the system is designed to facilitate efficient execution of neural network models. In at least one embodiment, process 700 improves the performance of image recognition and object detection. In at least one embodiment, process 700 enables efficient processing of large-scale datasets.

[0111] Figure 8 This diagram illustrates a block diagram 800 of a driver and / or runtime according to at least one embodiment, the driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs). In at least one embodiment, the software program 802 is a software module stored on a processor, such as... Figure 1The software module is shown. In at least one embodiment, the software program 802 includes one or more software modules. In at least one embodiment, the software program 802 is a collection of software code, commands, instructions, or other text sequences used to instruct a computing device to perform one or more arithmetic operations and / or invoke one or more other instruction sets (such as one or more APIs 808 or one or more API functions 810) to be executed. In at least one embodiment, the software program is a compiler.

[0112] In at least one embodiment, one or more APIs 808 are software instruction sets that, when executed, cause one or more processors to perform one or more arithmetic operations. In at least one embodiment, one or more APIs 808 are distributed or otherwise provided as part of one or more libraries 806, runtimes 804, drivers, and / or any other grouping of software and / or executable code further described herein. In at least one embodiment, one or more APIs 808 perform one or more arithmetic operations in response to a call to software program 802. In at least one embodiment, the functionality provided by one or more APIs 808 includes one or more software functions 810, such as software functions capable of accelerating one or more portions of software program 802 using one or more parallel processing units (PPUs) such as graphics processing units (GPUs).

[0113] In at least one embodiment, one or more APIs 808 are hardware interfaces to one or more circuits for performing one or more arithmetic operations. In at least one embodiment, the one or more APIs 808 described herein are implemented for performing combinations Figure 1-28C One or more circuits representing one or more of the techniques described. In at least one embodiment, the software program 502 includes instructions that, if executed, cause one or more hardware devices and / or circuits to perform the above-described combination. Figure 1-7 One or more technologies described.

[0114] In at least one embodiment, software program 802 (such as a user-implemented software program) utilizes one or more APIs 808 to perform various computational operations, such as calculating the memory location of a thread, starting a thread, or any computational operation performed by a parallel processing unit (PPU) such as a graphics processing unit (GPU), as further described herein. In at least one embodiment, one or more APIs 808 provide a set of callable functions 810 (referred to herein as APIs, API functions, and / or functions), each of which performs one or more computational operations, such as computational operations related to parallel computing.

[0115] In at least one embodiment, software program 802 interacts with or otherwise communicates with one or more APIs 808 to perform one or more computational operations using one or more PPUs, such as a GPU. In at least one embodiment, the computational operations include at least one or more groups of computational operations to be accelerated by being executed at least partially by the PPUs. In at least one embodiment, software program 802 interacts with one or more APIs 808 to facilitate parallel computation using remote or local interfaces.

[0116] In at least one embodiment, the interface is software instructions that, when executed, provide access to one or more functions 810 provided by one or more APIs 808. In at least one embodiment, when a software developer compiles the software program in conjunction with one or more libraries 506, the software program 802 uses a native interface, the one or more libraries 506 including one or more APIs 808 or otherwise providing access to them. In at least one embodiment, the software program 802 is statically compiled in conjunction with pre-compiled libraries 806 or uncompiled source code including instructions for executing one or more APIs 808. In at least one embodiment, the software program 802 is dynamically compiled, and the one or more software programs are linked using a linker to one or more pre-compiled libraries 806, the one or more pre-compiled libraries 806 including one or more APIs 808.

[0117] In at least one embodiment, when a software developer executes a software program that communicates with a library 806 including one or more APIs 808 via a network or other remote communication medium, the software program 802 uses a remote interface. In at least one embodiment, the library 806 including one or more APIs 808 will be executed by a remote computing service such as a computing resource service provider. In another embodiment, the library 806 including one or more APIs 808 will be executed by any other computing host that provides the one or more APIs 808 to the software program 802.

[0118] In at least one embodiment, software program 802 utilizes one or more APIs 808 to allocate and otherwise manage memory to be used by software program 802. In at least one embodiment, software program 802 utilizes one or more APIs 808 to allocate and otherwise manage memory to be used by one or more portions of software program 802, which are to be accelerated using one or more PPUs such as GPUs or any other accelerators or processors further described herein. In at least one embodiment, software program 802 selects the one or more portions of the one or more neural networks to be deactivated during the training of the one or more neural networks, based at least in part on whether the one or more portions of the one or more neural networks will be used after training the one or more neural networks.

[0119] In at least one embodiment, each of the one or more APIs 808 is an API for facilitating parallel computation. In at least one embodiment, each of the one or more APIs 810 is any other API further described herein. In at least one embodiment, each of the one or more APIs 808 is provided by a driver and / or runtime 804. In at least one embodiment, each of the one or more APIs 810 is provided by a CUDA user-mode driver. In at least one embodiment, each of the one or more APIs 808 is provided by a CUDA runtime. In at least one embodiment, the driver is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 810 of one or more APIs 808 during the loading and execution of one or more portions of the software program 802. In at least one embodiment, runtime 804 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 810 of one or more APIs 808 during the execution of software program 502. In at least one embodiment, software program 802 utilizes one or more APIs 808 implemented by or otherwise provided by the driver and / or runtime 804 to perform combinatorial arithmetic operations, and performs memory access computation operations on threads by software program 802 during execution by one or more PPUs such as a GPU.

[0120] In at least one embodiment, software program 802 utilizes one or more APIs 808 provided by a driver and / or runtime 804 to perform combined arithmetic operations on one or more PPUs, such as a GPU. In at least one embodiment, one or more APIs 808 provide combined arithmetic operations via a driver and / or runtime 804, as described above. In at least one embodiment, software program 802 utilizes one or more APIs 808 provided by a driver and / or runtime 804 to allocate or otherwise reserve one or more blocks of memory 812 for one or more PPUs, such as a GPU. In at least one embodiment, software program 802 utilizes one or more APIs 808 provided by a driver and / or runtime 804 to allocate or otherwise reserve blocks of memory. In at least one embodiment, one or more APIs 808 cause one or more PPUs, such as a GPU, to execute a kernel startup API 814, for example, as described herein. Figure 1 The results of the described API 102. In at least one embodiment, one or more APIs 808 are used to perform the actions described herein in any combination. Figure 1-7 The described thread memory address calculation and thread startup.

[0121] In at least one embodiment, block diagram 800 depicts a processor including one or more circuits for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, block diagram 800 depicts a system including one or more processors for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the API is used to identify one or more expected software outputs, which are then compared with one or more other software outputs to be generated by the software.

[0122] In at least one embodiment, some or all of the processes described herein (or any other processes described, or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions and / or other data, and may be implemented as executable instructions that execute jointly on processor 108 or a combination of processors 108. In at least one embodiment, the executable instructions and / or other data may be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash memory medium).

[0123] Figure 9An example of a system 900 according to at least one embodiment is illustrated. The system 900 may include software and hardware for causing one or more instructions to be executed, or otherwise performing any of the operations described herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The system 900 may include a storage device 902 and one or more processors 908. The storage device 902 may include, for example, memory, a cache, or other storage devices further described herein. The storage device 902 may be separate from one or more processors 908, or the storage device 902 may be included within one or more processors 908 (e.g., in storage device 912). In at least one embodiment, a software program 904 and / or a software library (or instructions) 906 may be stored in memory, a cache, or other storage device and provided to one or more processors 908 to cause one or more circuits of the one or more processors 908 to perform the operations described herein. In at least one embodiment, software program 904 and / or software library (or instructions) 906 may be integrated into one or more circuits of one or more processors 908. Software program 904, which may be used to perform any of the operations described herein, may be stored on storage device 902.

[0124] In at least one embodiment, the software program 904 may include one or more software modules.

[0125] In at least one embodiment, as used in any implementation described herein, unless explicitly stated otherwise from the context or explicitly to the contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software is embodied as a software package, code, and / or instruction set or instructions, and as used in any implementation described herein, “hardware” includes, for example, individually or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware storing instructions executed by the programmable circuitry. In at least one embodiment, modules are collectively or individually embodied as circuitry forming part of a larger system (e.g., integrated circuit (IC), system-on-a-chip (SoC), etc.). In at least one embodiment, a module performs one or more processes associated with a combination of any suitable processing unit and / or processing unit (such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof, including those further described herein).

[0126] In at least one embodiment, software program 904 may include a collection of software code, commands, instructions, or other text sequences used to instruct a computing device to perform one or more arithmetic operations and / or invoke one or more other instruction sets (such as one or more APIs or one or more API functions or instruction set architecture (ISA) level instructions) to be executed or otherwise implemented. In at least one embodiment, an API function initiates a kernel including a configuration of one or more parameters corresponding to various operand sizes (such as grid size, block size, and stride length size). Instructions (e.g., hardware instructions) or microcode may involve ISA level instructions, which may include native ISA instructions or non-native ISA commands. Software program 904 and / or software library (or instruction) 906 (e.g., one or more modules) may be distributed among multiple processors communicating via a bus, network, by writing to shared memory, and / or any suitable communication process (such as the communication process described herein).

[0127] In at least one embodiment, system 900 may include one or more software libraries 906, which may, for example, provide one or more API and / or ISA instructions. In at least one embodiment, one or more API and / or ISA instructions may be used to cause one or more instructions to be executed at least in part based on one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. In at least one embodiment, one or more software libraries 906 may be included in a driver and / or runtime. In at least one embodiment, software library 906 (e.g., including one or more API and / or ISA instructions) may include a set of software instructions that, if executed or otherwise implemented, cause one or more processors 908 to perform one or more arithmetic operations, such as any of the operations described herein. In at least one embodiment, one or more API and / or ISA instructions may be distributed or otherwise provided as part of any other grouping of one or more software libraries 906, runtime, driver, and / or software and / or executable code further described herein. In at least one embodiment, one or more API and / or ISA instructions may perform one or more computational operations in response to a call to software program 904.

[0128] One or more processors 908 may include any number of processors and any suitable processing units and / or combinations of processing units, such as, but not limited to, a central processing unit (“CPU”), a graphics processing unit (“GPU”), or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, parallel processors, GPGPUs, DPUs, and / or variations thereof (including variations further described herein)), such other processors include any processors described herein, such as, but not limited to, those described herein. Figure 1 and Figure 11-23B The processors in the memory device 902. In at least one embodiment, one or more processors 908 may retrieve or fetch instructions (e.g., one or more API and / or ISA instructions) from memory device 902 using, for example, instruction fetch 916 (e.g., for an instruction fetch phase). Instructions may include instructions for causing one or more instructions to be executed at least in part based on one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. In at least one embodiment, one or more processors 908 may include memory device 912 and instruction queue 910 for storing and queuing instructions fetched from memory device 902. In at least one embodiment, the fetched instructions may be decoded by decoder 918 to determine what operation one or more processors 908 should perform (e.g., in an instruction decoding phase). In at least one embodiment, one or more processors 908 may fetch additional operands (data) that can be used for instructions, and the operands may be stored, for example, in registers or memory device 912. In at least one embodiment, micro-operation 920 may perform operations on data stored in one or more registers or memory device 912. For example, each step of an instruction fetched by one or more processors 908 can be broken down during execution, so that one or more processors 908 can execute the instruction step by step through a series of micro-operations 920. In at least one embodiment, the program counter (PC) 914 can store the address of the next instruction and can be updated to point to the next instruction to be executed by one or more processors 908.

[0129] In at least one embodiment, one or more processors 908 may (e.g., during the execution phase) execute instructions. For example, one or more processors 908 may execute operations specified by the instructions, such as arithmetic operations, logical operations, or data transfers. In at least one embodiment, one or more arithmetic units 922 may execute instructions for performing any of the operations described herein. In at least one embodiment, one or more arithmetic units may include one or more ALUs 924 (Arithmetic Logic Units) that can be used to perform arithmetic and logical operations. In at least one embodiment, one or more arithmetic units may include one or more FPUs (Floating Point Units) 926 that can be used to perform floating-point calculations. In at least one embodiment, other circuitry 928 may be used to perform other operations, such as vector operations and / or scalar operations. In at least one embodiment, one or more accelerators 930 may include one or more matrix multiplication accelerators, one or more parallel processing units (PPUs) such as GPUs, or any other accelerators or processors further described herein. In at least one embodiment, software program 904 may utilize one or more API and / or ISA instructions to perform various computational operations, such as matrix multiplication, arithmetic operations, or any other computational operations further described herein, via one or more accelerators 930. In at least one embodiment, one or more computational operations using one or more accelerators 930 may include at least one or more sets of computational operations accelerated by execution at least partially by one or more accelerators 930, including computational operations for causing one or more instructions to be executed at least partially based on one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0130] In at least one embodiment, system 900 can be used to perform functions or operations (such as combining). Figure 1-7 The system 900 includes one or more instructions (the functions or operations described herein). In at least one embodiment, the system 900, including one or more processors, causes one or more circuits to perform one or more instructions and / or otherwise perform the operations described herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. In at least one embodiment, the system 900 is included with Figure 1-7 The system illustrated herein and / or otherwise includes Figure 1-7The systems illustrated herein are used to cause one or more circuits to execute one or more instructions and / or otherwise perform the operations described herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. In at least one embodiment, system 900 includes Figure 10-28C The illustration shows one or more hardware components used to cause one or more circuits to perform one or more instructions and / or otherwise perform the operations described herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0131] Data Center

[0132] Figure 10 An example data center 1000 according to at least one embodiment is illustrated. The data center 1000 may include one or more rooms having racks 1002 and auxiliary equipment for housing one or more racks 1002 and one or more substrates 1004. Racks 1002 may include one or more substrates 1004. Racks 1002 may include enclosures for housing and supporting individual substrates 1004. Operational aspects of racks 1002 may be adjustable at the rack level (corresponding to a group of substrates 1004) or at the substrate level (corresponding to an individual substrate 1004), among other options. Racks 1002 or substrates 1004 may have specific selected maximum operating parameters, such as, but not limited to, power consumption, operating frequency, etc. The data center 1000 may be supported by various cooling systems, such as, but not limited to, cooling towers, cooling loops, pumps, and other support systems. The cooling system may include sensors and controllers for monitoring and managing the cooling characteristics of racks 1002. The substrates 1004 within racks 1002 may draw operating power from one or more power distribution units (PDUs; not shown). PDUs can be arranged within racks 1002, for example, between racks 1002 that include substrates 1004, or within racks 1002 that also house substrates 1004.

[0133] Rack 1002 and substrate 1004 may include subsystems, modules, add-in cards, and other semiconductor components. Substrate 1004 may include one or more computing units 1006, each computing unit 1006 including one or more processors 1008, one or more memories 1010, and an interface controller 1012. Computing unit 1006 may include any number of processors, such as, but not limited to, a central processing unit (“CPU”), a graphics processing unit (“GPU”), or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), including any processors described herein, such as, but not limited to, those described herein. Figure 11-23B The processor in the computing unit 1006 may include one or more memory storage devices 1010 (e.g., dynamic read-only memory, solid-state storage devices, or disk drives), as well as network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power supply modules, and cooling modules, etc. One or more computing units 1006 may be a server having one or more of the aforementioned computing resources.

[0134] Computing unit 1006 may include individual computing unit groups housed in one or more racks (not shown), or in numerous racks within data centers in different geographical locations (also not shown). Individual computing unit groups may include grouped computing, networking, memory, or storage resources that can be configured or allocated to support one or more workloads. Several computing units (e.g., including CPUs and / or other processors) may be grouped within one or more racks to provide computing resources to support one or more workloads. Resource coordinator 1014 may configure or otherwise control one or more computing units 1006 or computing unit groups. Resource coordinator 1014 may include a Software Design Infrastructure (“SDI”) management entity for data center 1000. Resource coordinator 1014 may include hardware, software, or some combination thereof.

[0135] Data center 1000 may include any one or any combination of the framework layer 1020, software layer 1030, and application layer 1040. For example... Figure 10As shown, framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. Framework layer 1020 may include a framework for supporting software 1032 of software layer 1030 and / or one or more applications 1042 of application layer 1040. Software 1032 or application 1042 may respectively include web-based service software or applications, such as, but not limited to, software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. Framework layer 1020 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark. TM (Hereinafter referred to as "Spark"), which can utilize the distributed file system 1028 for large-scale data processing (e.g., "big data"). The job scheduler 1022 may include Spark drivers, which facilitate the scheduling of workloads supported by various layers of the data center 1000. The configuration manager 1024 may be able to configure different layers, such as, but not limited to, the software layer 1030 and the framework layer 1020 (which includes Spark and the distributed file system 1028 for supporting large-scale data processing). The resource manager 1026 may be able to manage clustered or grouped computing units 1006 mapped to or allocated to support the distributed file system 1028 and the job scheduler 1022. The resource manager 1026 may coordinate with the resource coordinator 1014 to manage these mapped or allocated computing resources.

[0136] Software 1032 may be included in software layer 1030, and may include software used by at least a portion of computing units 1006, one or more computing units 1006, groups of computing units 1006, and / or the distributed file system 1028 of framework layer 1020. One or more types of software may include, but are not limited to, internet web search software, email virus scanning software, database software, and streaming video content software.

[0137] Application 1042 may be included in application layer 1040 and may include one or more types of applications used by at least portions of computing unit 1006, one or more computing units 1006, groups of computing units 1006, and / or the distributed file system 1028 of framework layer 1020. One or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0138] Any of the Configuration Manager 1024, Resource Manager 1026, and Resource Coordinator 1014 can implement any number and type of self-modification actions based on any amount and type of data obtained in any technically feasible manner. Self-modification actions can alleviate the burden on data center operators of Data Center 1000 to make potentially erroneous configuration decisions and may avoid underutilized and / or poorly performing portions of the data center.

[0139] Data center 1000 may include tools, services, software, or other resources for training one or more machine learning models according to one or more embodiments described herein, or for using one or more machine learning models to predict or infer information. For example, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above regarding data center 1000. The trained machine learning model corresponding to one or more neural networks can be used with the resources described above regarding data center 1000 to infer or predict information using weight parameters calculated through one or more training techniques described herein.

[0140] Data Center 1000 can use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware (e.g., Figure 11-23B The embodiments described herein can be used to perform some or all of the processes and techniques described elsewhere, such as, but not limited to, training and / or inference using the resources described above. Furthermore, one or more of the software and / or hardware resources described above can be configured as a service to allow a user to train or perform information inference, such as, but not limited to, image recognition, speech recognition, or other artificial intelligence services.

[0141] In at least one embodiment, processor 1008 may include one of the processors described below and / or include one or more circuitry configured to cause one or more instructions to be executed, or otherwise perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. In at least one embodiment, processor 1008 is configured by software 1032 to execute one or more instructions, or otherwise perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. Data center 1000 may use logic, CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware (e.g., Figure 11-23BThe embodiments described above or elsewhere in this document may perform any of the operations described in the examples.

[0142] processor

[0143] The following figures illustrate, but are not limited to, example processors and processing systems that can be used to cause the execution of one or more instructions, or otherwise perform some or all of the processes, operations, and / or techniques described elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. The example processors and processing systems can be software configured to execute one or more instructions, or otherwise perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. Processors and processing systems may include logic, central processing units (CPUs), application-specific integrated circuits (ASICs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), XPUs (i.e., any computing architecture best suited to the needs of the application), or other hardware (e.g., Figure 11-23B The embodiments described herein are used to perform any of the operations described above, below, or elsewhere herein. The processor and / or processing system described herein may include one or more circuitry that can be configured to cause one or more instructions to be executed, or to perform any of the operations described above or elsewhere herein, based at least in part on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. As used herein, one or more circuitry may be software-configured to cause one or more instructions to be executed, or otherwise to perform any of the operations described above or elsewhere herein, based at least in part on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. Figure 28A and Figure 28BThe illustration depicts logic 2815 according to at least one embodiment, which, as described elsewhere herein, can be used in one or more devices to perform operations such as, but not limited to, those discussed herein. For example, logic can refer to any combination of software logic, hardware logic, and / or firmware logic that provides the functionality and / or operations described herein, wherein the logic can be collectively or individually embodied as part of a circuit system forming a larger system, such as an integrated circuit (IC), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), system-on-a-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0144] Figure 11 A processor according to at least one embodiment is illustrated, which is a system-on-a-chip (SOC) 1100 (which may be referred to as a system-on-a-chip, superchip, or other names). SOC 1100 may include processor complex 1110 and processor complex 1140. SOC 1100 may include any number of processor complexes 1110 and / or processor complexes 1140, which may include any number of processors described herein in any combination, such as, but not limited to, processors described herein in any combination. Figure 11-23B The processor in the system. For example, processor 1110 may include a central processing unit (CPU), and processor 1140 may include a graphics processor. Alternatively, processor 1110 may include a graphics processor, and processor 1140 may include a graphics processor. The SOC 1100 may include any number of display controllers 1192, any number of multimedia engines 1194, any number of I / O interfaces 1170, any number of memory controllers 1180, and any number of fabrics 1160 in any combination. For ease of explanation, this document uses reference numbers identifying objects and bracket numbers identifying instances (if required) to denote multiple instances of similar objects. The SOC 1100 may include a processor from Broadcom Corporation, Palo Alto, California.

[0145] Processor complex 1110 may include a CPU, processor complex 1140 may include a GPU, and SOC 1100 may include a processing unit integrating processor complex 1110 and processor complex 1140 onto a single chip. Certain tasks may be assigned to processor complex 1110, while other tasks may be assigned to processor complex 1140. Processor complex 1110 may be configured to execute main control software associated with SOC 1100, such as, but not limited to, an operating system. Processor complex 1110 may be the main processor of SOC 1100, controlling and coordinating the operation of other processors. Processor complex 1110 may issue commands that control the operation of processor complex 1140 to perform some or all of the operations described herein. Processor complex 1110 may be configured to execute host-executable code derived from CUDA or other source code (e.g., HIP source code), while processor complex 1140 may be configured to execute device-executable code derived from CUDA or other source code to perform any of the operations described herein.

[0146] Processor complex 1110 may include cores 1120(1)-1120(4) and cache (e.g., L3 cache) 1130 for storing information for performing the operations described herein. Processor complex 1110 may include any number of cores 1120 in any combination and any number and type of cache. Cores 1120 may be configured to execute instructions of a specific instruction set architecture (“ISA”) to perform some or all of the operations described herein. Each core 1120 may include a CPU core. Cores 1120(1)-1120(4) may be referred to as compute units or arithmetic units. SOC 1100 may include any number of processor complexes 1110, architecture 1160, I / O interface 1170, and memory controller 1180.

[0147] Each core 1120 may include a fetch / decode unit 1122, an integer execution engine 1124, a floating-point execution engine 1126, and an L2 cache 1128. The fetch / decode unit 1122 may fetch instructions to perform some or all of the operations described herein (e.g., but not limited to APIs compiled into instructions) and decode those instructions, generate micro-operations, and dispatch individual micro-instructions to the integer execution engine 1124 and / or the floating-point execution engine 1126. The fetch / decode unit 1122 may concurrently dispatch one micro-instruction to the integer execution engine 1124 and another micro-instruction to the floating-point execution engine 1126. The integer execution engine 1124 may perform integer and memory operations. The floating-point engine 1126 may perform floating-point and vector operations. The fetch / decode unit 1122 may dispatch micro-instructions to one or more execution engines, which may replace both the integer execution engine 1124 and the floating-point execution engine 1126.

[0148] Each core 1120(i) (where i is an integer representing a specific instance of core 1120) can access the L2 cache 1128(i) included in core 1120(i). Each core 1120 included in core complex 1110(j) (where j is an integer representing a specific instance of core complex 1110) can be connected to other cores 1120 included in core complex 1110(j) via the L3 cache 1130(j) included in core complex 1110(j). The cores 1120 included in core complex 1110(j) (where j is an integer representing a specific instance of core complex 1110) can access all L3 caches 1130(j) included in core complex 1110(j). The L3 cache 1130 can include any number of slices.

[0149] Processor complex 1140 may be a graphics complex that can be configured to perform computational operations (e.g., the computational operations described herein) in a highly parallel manner. Processor complex 1140 may be configured to perform graphics pipeline operations, such as, but not limited to, drawing commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. Processor complex 1140 may be configured to perform graphics-independent operations, such as, but not limited to, neural network training and / or simulation. Processor complex 1140 may be configured to perform both graphics-related and graphics-independent operations.

[0150] Processor complex 1140 may include any number of compute units 1150(1)-1150(N) (where N is any integer greater than 1) and L2 cache 1142. The compute units 1150 may share L2 cache 1142, which may store information that will be used to perform some or all of the operations described herein. L2 cache 1142 may be partitioned. Processor complex 1140 may include any number of compute units 1150 and any number (including zero) and type of cache. Processor complex 1140 may include any number of dedicated graphics hardware.

[0151] Each computing unit 1150 may include any number of SIMD units 1152(1)-1152(N) (where N is any integer greater than 1) and shared memory 1154. Each SIMD unit 1152 may implement a SIMD architecture and may be configured to perform some or all of the operations described herein in parallel. Each computing unit 1150 may execute any number of thread blocks, but each thread block may execute on a single computing unit 1150, although in some embodiments, the thread block may execute on multiple computing units. A thread block may include any number of execution threads. A workgroup may be a thread block. Each SIMD unit 1152 may execute a set of threads. A set of threads (e.g., 16 threads), may also be referred to as a warp, subgroup, or wavefront (e.g., used by AMD and Intel), wherein each thread in a warp, warp, subgroup, or wavefront may belong to a single thread block and be configured to process different datasets based on a single instruction set. Prediction may be used to disable one or more threads in a warp, subgroup, or wavefront. A lane may be a thread. A work item can be a thread, such as (but not limited to) an OpenCL thread. Different thread bundles, subgroups, or wavefronts within a thread block can be synchronized together and communicate via shared memory 1154. Each compute unit 1150 can include one or more thread block clusters, where thread block clusters can implement programmable control over locality at a larger granularity than a single thread block of a single streaming multiprocessor (SM). Thread block clusters (also referred to as “clusters”) can support multiple thread blocks running concurrently across streaming multiprocessors, thereby synchronously and cooperatively acquiring, exchanging, or otherwise using data. In at least one embodiment, a streaming multiprocessor (“SM”) can refer to a streaming microprocessor, a streaming processor (“SP”), a streaming processing unit (“SPU”), a compute unit (“CU”), an execution unit (“EU”), and / or a slice, where a slice in this context can refer to a portion of the processing resources within a processing unit (e.g., 16 cores, a ray tracing unit, a thread bootstrap, or a scheduler).

[0152] Structure 1160 may be a system interconnect that facilitates data and control transfers across processor complex 1110, processor complex 1140, I / O interface 1170, memory controller 1180, display controller 1192, and multimedia engine 1194, for example, to perform some or all of the operations described herein. SOC 1100 may include any number and type of system interconnects other than or replacing structure 1160, facilitating data and control transfers across any number and type of directly or indirectly linked components within or outside SOC 1100. I / O interface 1170 may represent any number and type of I / O interfaces (e.g., PCI, PCI extensions (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). Various types of peripheral devices may be coupled to I / O interface 1170. Peripheral devices that may be coupled to I / O interface 1170 may include keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0153] Display controller 1192 can display images on one or more display devices, such as, but not limited to, liquid crystal displays (“LCD”) devices. Multimedia engine 1194 can include any number and type of circuitry related to multimedia, such as, but not limited to, video decoders, video encoders, image signal processors, etc. Memory controller 1180 can facilitate data transfer between SOC 1100 and unified system memory 1190. Processor complex 1110 and processor complex 1140 can share unified system memory 1190. Unified system memory 1190 can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as, but not limited to, synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Unified system memory 1190 can include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, or HDM3.

[0154] The SOC 1100 can implement a memory subsystem including any number and type of memory controllers 1180 and memory devices (e.g., shared memory 1154), which may be dedicated to a single component or shared among multiple components to perform any of the operations described herein. The SOC 1100 can implement a cache subsystem including one or more cache memories (e.g., L2 cache 1128, L3 cache 1130, and L2 cache 1142), each cache memory may be dedicated to any number of components (e.g., core 1120, core complex 1110, SIMD unit 1152, compute unit 1150, and processor complex 1140), or may be shared among any number of components (e.g., core 1120, core complex 1110, SIMD unit 1152, compute unit 1150, and processor complex 1140).

[0155] In at least one embodiment, the SOC 1100 may include one or more circuitry for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The one or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0156] Figure 12A A parallel processor 1200 according to at least one embodiment is illustrated. The parallel processor 1200 may be implemented using one or more circuits and may be referred to as a programmable processor (e.g., CPU and / or GPU), logic, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other hardware (e.g., Figure 11-23B (The embodiments in this document) are used to perform any of the operations described above or elsewhere herein.

[0157] Parallel processor 1200 may include parallel processing unit 1202 for performing any of the operations described above or elsewhere herein. Parallel processing unit 1202 may include I / O unit 1204 that enables communication with other devices, including other instances of parallel processing unit 1202. I / O unit 1204 may be directly connected to other devices. I / O unit 1204 may be connected to other devices via the use of a hub or switch interface, such as, but not limited to, memory hub 1205. The connection between memory hub 1205 and I / O unit 1204 may form a communication link 1213. I / O unit 1204 may be connected to host interface 1206 and memory crossbar switch 1216, wherein host interface 1206 receives commands directed to perform processing operations, and memory crossbar switch 1216 receives commands directed to perform memory operations.

[0158] When host interface 1206 receives a command buffer via I / O unit 1204, host interface 1206 can route work operations to execute these commands to front end 1208. Front end 1208 can be coupled to scheduler 1210 (which may be referred to as sequencer), which is configured to distribute commands or other work items to processing cluster array 1212. Scheduler 1210 can ensure that processing cluster array 1212 is correctly configured and in an active state before tasks are distributed to the cluster of processing cluster array 1212. Scheduler 1210 can be implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 1210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 1212. Host software can validate workloads scheduled on processing cluster array 1212 via one of multiple graphics processing paths. The workload can then be automatically distributed to the processing array cluster 1212 by the scheduler 1210 logic within the microcontroller, which includes the scheduler 1210.

[0159] Processing cluster array 1212 can perform any of the operations described above or elsewhere herein, and may include up to “N” processing clusters (e.g., clusters 1214A, 1214B through 1214N), where “N” represents a positive integer (which may be a different integer “N” than used in other diagrams). Each cluster 1214A-1214N in processing cluster array 1212 can execute a large number of concurrent threads. Scheduler 1210 may use various scheduling and / or work distribution algorithms to distribute work to clusters 1214A-1214N in processing cluster array 1212, which may vary depending on the workload generated by each type of program or computation. Scheduling may be dynamically handled by scheduler 1210 or may be assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 1212. Different clusters 1214A-1214N of processing cluster array 1212 may be assigned to process different types of programs or perform different types of computations.

[0160] The processing cluster array 1212 can be configured to perform various types of parallel processing operations, such as, but not limited to, any of the operations described above or elsewhere herein. The processing cluster array 1212 can be configured to perform general-purpose parallel computing operations. For example, the processing cluster array 1212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations (including physical operations), and performing data transformations.

[0161] Processing cluster array 1212 can be configured to perform parallel graphics processing operations. Processing cluster array 1212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. Processing cluster array 1212 can be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 1202 can transfer data from system memory via I / O unit 1204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1222) during processing and then written back to system memory.

[0162] When the parallel processing unit 1202 is used to perform graphics processing, the scheduler 1210 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1214A-1214N of the processing cluster array 1212. Each part of the processing cluster array 1212 can be configured to perform different types of processing. For example, a first part can be configured to perform vertex shading and topology generation, a second part can be configured to perform tessellation and geometry shading, and a third part can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more clusters 1214A-1214N can be stored in a buffer to allow intermediate data to be transferred between clusters 1214A-1214N for further processing.

[0163] Processing cluster array 1212 can receive processing tasks to be executed via scheduler 1210, which receives commands defining the processing tasks from front end 1208. Processing tasks may include indexes of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., which program to execute). Scheduler 1210 can be configured to retrieve the index corresponding to the task, or can receive the index from front end 1208. Front end 1208 can be configured to ensure that processing cluster array 1212 is configured to be active before the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0164] Each instance of one or more instances of parallel processing unit 1202 may be coupled to parallel processor memory 1222 to perform any of the operations described above or elsewhere herein. Parallel processor memory 1222 may be accessed via memory crossbar switch 1216, which may receive memory requests from processing cluster array 1212 and I / O unit 1204. Memory crossbar switch 1216 may access parallel processor memory 1222 via memory interface 1218. Memory interface 1218 may include multiple partition units (e.g., partition units 1220A, 1220B through 1220N), each partition unit may be coupled to a portion (e.g., a memory cell) of parallel processor memory 1222. The number of partition units 1220A-1220N can be configured to be equal to the number of memory units, such that the first partition unit 1220A has a corresponding first memory unit 1224A, the second partition unit 1220B has a corresponding memory unit 1224B, and the Nth partition unit 1220N has a corresponding Nth memory unit 1224N. The number of partition units 1220A-1220N may not be equal to the number of memory units.

[0165] Memory cells 1224A-1224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as, but not limited to, synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory. Memory cells 1224A-1224N may also include 3D stacked memory, including but not limited to high-bandwidth memory (HBM), HBM2e, or HDM3. Render targets (e.g., but not limited to framebuffers or texture maps) may be stored in memory cells 1224A-1224N, allowing partitioning cells 1220A-1220N to write portions of each render target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 1222. A local instance of the parallel processor memory 1222 may not be included to support a unified memory design that combines system memory with local cache memory.

[0166] Any cluster 1214A-1214N in the processing cluster array 1212 can process data to be written to any memory cell 1224A-1224N within the parallel processor memory 1222. The memory crossbar switch 1216 can be configured to transfer the output of each cluster 1214A-1214N to any partition cell 1220A-1220N, or to another cluster 1214A-1214N on which additional processing operations can be performed. Each cluster 1214A-1214N can communicate with the memory interface 1218 via the memory crossbar switch 1216 to read from or write to various external memory devices. The memory crossbar switch 1216 can be connected to the memory interface 1218 to communicate with the I / O unit 1204, or to a local instance of the parallel processor memory 1222, enabling processing units within different processing clusters 1214A-1214N to communicate with system memory or other memory local to the non-parallel processing unit 1202. The memory crossbar switch 1216 can use virtual channels to separate traffic flows between clusters 1214A-1214N and partition units 1220A-1220N.

[0167] Multiple instances of the parallel processing unit 1202 can be mounted on a single add-in card, or multiple add-in cards can be interconnected. Even if different instances of the parallel processing unit 1202 have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences, these different instances can be configured to interoperate. For example, some instances of the parallel processing unit 1202 may include higher-precision floating-point units relative to other instances. Systems including one or more instances of the parallel processing unit 1202 or the parallel processor 1200 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0168] Figure 12A It also includes a block diagram of a partitioning unit 1220 according to at least one embodiment. The partitioning unit 1220 is... Figure 12AAn example of one of the partition units 1220A-1220N in the parallel processor memory. Partition unit 1220 may include an L2 cache 1221, a frame buffer interface 1225, and a ROP 1226 (raster operation unit). The L2 cache 1221 may be a read / write cache configured to perform load and store operations received from the memory crossbar switch 1216 and the ROP 1226. Read misses and urgent write-back requests may be output from the L2 cache 1221 to the frame buffer interface 1225 for processing. Updates may also be sent to the frame buffer via the frame buffer interface 1225 for processing. The frame buffer interface 1225 may interface with one of the memory cells in the parallel processor memory, such as, but not limited to, Figure 12A The memory cells 1224A-1224N (shown as 1224) are located in the parallel processor memory 1222 (for example, within the parallel processor memory 1222).

[0169] ROP 1226 can be a processing unit that performs raster operations, such as, but not limited to, stenciling, z-testing, blending, etc. ROP 1226 can then output processed graphics data stored in graphics memory. ROP 1226 may include compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more compression algorithms. The type of compression performed by ROP 1226 can vary based on the statistical characteristics of the data to be compressed. For example, incremental color compression is performed on depth and color data on a per-tile basis.

[0170] ROP 1226 can be included in each processing cluster (e.g., Figure 12A The data is stored within clusters 1214A-1214N, not within partition units 1220. Read and write requests for pixel data (not pixel fragment data) can be transferred via memory crossbar switch 1216. Processed graphics data can be displayed on a monitor and routed for further processing by the processor, or routed to... Figure 12A One of the 1200 parallel processing entities in the process is further processed.

[0171] In at least one embodiment, the parallel processor 1200 may include one or more circuitry configured to execute one or more instructions or otherwise perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The one or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0172] Figure 12B A block diagram including a processing cluster 1214 within a parallel processing unit according to at least one embodiment. The processing cluster may be... Figure 12A An instance of one of the processing clusters 1214A-1214N is provided, which can be used to perform any of the operations described above or elsewhere herein. Processing cluster 1214 can be configured to execute many threads in parallel, where a “thread” refers to an instance of a specific program executed on a specific input dataset. Single Instruction Multiple Data (SIMD) instruction issuing techniques can be used to support the parallel execution of a large number of threads without providing multiple independent instruction units. Single Instruction Multiple Thread (SIMT) techniques can be used to support the parallel execution of a large number of typically synchronous threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0173] The operation of cluster 1214 can be controlled via pipeline manager 1232, which distributes processing tasks to SIMT parallel processors. Pipeline manager 1232 can... Figure 12A The scheduler 1210 receives instructions and manages the execution of these instructions via the graphics multiprocessor 1234 and / or texture unit 1236. The graphics multiprocessor 1234 may be an example instance of a SIMT parallel processor. However, the processing cluster 1214 may include various types of SIMT parallel processors with different architectures. The processing cluster 1214 may include one or more instances of the graphics multiprocessor 1234. The graphics multiprocessor 1234 can process data and can use the data cross switch 1240 to distribute the processed data to one of several possible destinations, including other shader units. The pipeline manager 1232 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross switch 1240.

[0174] Each graphics multiprocessor 1234 within the processing cluster 1214 may include a set of identical functional execution logic (e.g., arithmetic logic units, load-memory units, etc.) for performing computations for any of the operations described above or elsewhere herein. The functional execution logic may be configured in a pipelined manner, where new instructions can be issued before previous instructions complete. The functional execution logic may support a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. Different operations can be performed using the same functional unit hardware, and arbitrary combinations of functional units are possible.

[0175] Instructions transmitted to the processing cluster 1214 can form threads, which may also be referred to as thread bundles, subgroups, waves, or wavefronts. A group of threads executing across a set of parallel processing engines can be called a thread group. Thread groups can execute a common program on different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 1234. The number of threads in a thread group can be less than the number of processing engines within the graphics multiprocessor 1234. When the number of threads in a thread group is less than the number of processing engines, one or more processing engines may be idle during the processing cycle of that thread group. The number of threads in a thread group can also be more than the number of processing engines within the graphics multiprocessor 1234. When the number of threads in a thread group is more than the number of processing engines within the graphics multiprocessor 1234, processing can be performed in consecutive clock cycles. Multiple thread groups can execute concurrently on the graphics multiprocessor 1234.

[0176] The graphics multiprocessor 1234 includes an internal cache memory for performing load and store operations, such as, but not limited to, any of the operations described above or elsewhere herein. The graphics multiprocessor 1234 may forgo the internal cache and instead use a cache memory within the processing cluster 1214 (e.g., L1 cache 1248). Each graphics multiprocessor 1234 may also access partition units that can be shared across all processing clusters 1214 (e.g., ...). Figure 12A The L2 cache within partition units 1220A-1220N is used for transferring data between threads. The graphics multiprocessor 1234 can also access off-chip global memory, which may include one or more of the local parallel processor memory and / or system memory. Any memory outside of the parallel processing unit 1202 can be used as global memory. The processing cluster 1214 may include multiple instances of the graphics multiprocessor 1234 and can share common instructions and data, which may be stored in the L1 cache 1248.

[0177] Each processing cluster 1214 may include an MMU 1245 (Memory Management Unit), which can be configured to map virtual addresses to physical addresses. One or more instances of the MMU 1245 may reside in... Figure 12A The MMU 1245 is located within the memory interface 1218. It may include a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles, and optional cache line indexes. The MMU 1245 may include address translation lookup buffers (TLBs) or caches that may reside within the graphics multiprocessor 1234 or L1 1248 cache or processing cluster 1214. Physical addresses can be processed to distribute surface data access locally, allowing for efficient request interleaving between partition units. The cache line indexes can be used to determine whether a request for a cache line is a hit or a miss.

[0178] Processing cluster 1214 can be configured such that each graphics multiprocessor 1234 is coupled to a texture unit 1236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data can be read from an internal texture L1 cache (not shown) or an L1 cache within the graphics multiprocessor 1234, and can be retrieved as needed from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 1234 can output processed tasks to a data crossbar switch 1240 to provide the processed tasks to another processing cluster 1214 for further processing, or store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 1216. Pre-ROP 1242 (pre-raster operation unit) can be configured to receive data from the graphics multiprocessor 1234 and direct the data to ROP units, which can be associated with partitioning units (e.g., ...) described herein. Figure 12A The PreROP 1242 unit is located together with partition units 1220A-1220N. The PreROP 1242 unit can perform color blending optimization, organize pixel color data, and perform address translation.

[0179] In at least one embodiment, the processing cluster 1214 may include one or more circuits for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The one or more circuits may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0180] Figure 12C A graphics multiprocessor 1234 according to at least one embodiment is illustrated, for example, to perform any of the operations described above or elsewhere herein. The graphics multiprocessor 1234 may be coupled to a pipeline manager 1232 of a processing cluster 1214. The graphics multiprocessor 1234 may include an execution pipeline including, but not limited to, an instruction cache 1252 (e.g., which may store instructions, such as, but not limited to, compiled API instructions), instruction units 1254, address mapping units 1256, register files 1258, one or more general-purpose graphics processing unit (GPGPU) cores 1262, and one or more load / store units 1266, one or more of which may perform load / store operations to load / store instructions corresponding to the execution operations. The GPGPU cores 1262 and load / store units 1266 may be coupled to cache memory 1272 and shared memory 1270 via a memory and cache interconnect 1268. The GPGPU cores 1262 may be part of a SoC, such as, but not limited to, [other components]. Figure 11 It is part of the integrated circuit 1100.

[0181] Instruction cache 1252 can receive a stream of instructions to be executed (e.g., perform any operation described above or elsewhere herein) from pipeline manager 1232. Instructions can be cached in instruction cache 1252 and dispatched for execution by instruction unit 1254. Instruction unit 1254 can dispatch instructions into thread groups (e.g., thread bundles, subgroups, wavefronts, or waves), with each thread in the thread group assigned to a different execution unit within GPGPU core 1262. Instructions can access any of the local, shared, or global address spaces by specifying an address within a unified address space. Address mapping unit 1256 can be used to translate addresses in the unified address space into different memory addresses accessible by load / store unit 1266.

[0182] Register file 1258 provides a set of registers for the functional units of graphics multiprocessor 1234. Register file 1258 provides temporary storage for operands on data paths connected to functional units of graphics multiprocessor 1234 (e.g., GPGPU core 1262, load / store unit 1266). Register file 1258 can be partitioned among functional units such that each functional unit is allocated a dedicated portion of register file 1258. Register file 1258 can be partitioned among different thread bundles (which may be referred to as wavefronts, subgroups, and / or waves or threads) executed by graphics multiprocessor 1234.

[0183] Each GPGPU core 1262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1234. The architectures of the GPGPU cores 1262 may be similar or different. A first part of the GPGPU core 1262 may include a single-precision FPU and an integer ALU, while a second part of the GPGPU core may include a double-precision FPU. The FPU may implement IEEE 754-2008 standard floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 1234 may also include one or more fixed-function or special-function units for performing specific functions, such as, but not limited to, copying rectangles or pixel blending operations. One or more of the GPGPU cores 1262 may also include fixed-function or special-function logic.

[0184] The GPGPU core 1262 may include SIMD logic capable of executing a single instruction on multiple sets of data. The GPGPU core 1262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core may be generated by the shader compiler at compile time, or may be automatically generated when executing programs written and compiled for Single Program Multiple Data (SPMD) or SIMT architectures. Multiple threads of the program can be configured for a SIMT execution model that can be executed via a single SIMD instruction. For example, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0185] The memory and cache interconnect 1268 may include an interconnect network that connects each functional unit of the graphics multiprocessor 1234 to the register file 1258 and shared memory 1270. The memory and cache interconnect 1268 may be a crossbar interconnect that allows the load / store unit 1266 to perform load and store operations between the shared memory 1270 and the register file 1258. The register file 1258 may operate at the same frequency as the GPGPU core 1262, thus data transfer between the GPGPU core 1262 and the register file 1258 can have very low latency. The shared memory 1270 can be used to implement communication between threads executing on functional units within the graphics multiprocessor 1234. The cache memory 1272 can be used as a data cache, for example, for caching texture data transferred between functional units and texture units 1236. The shared memory 1270 can also be used as a program-managed cache. In addition to automatically caching the data stored in the cache memory 1272, threads executing on the GPGPU core 1262 can also programmatically store data in shared memory.

[0186] The parallel processor or GPGPU described herein can be communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects, such as, but not limited to, PCIe or NVLink). A System-on-a-Chip (SoC) may include the parallel processor or GPGPU described herein, which executes on the SoC. The GPU may be integrated as a core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. Regardless of the GPU's connection method, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU can then use dedicated circuitry / logic to efficiently process these commands / instructions to perform any of the operations described above or elsewhere herein.

[0187] In at least one embodiment, the graphics multiprocessor 1234 may include one or more circuitry for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The one or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0188] Figure 13A processor 1300 according to at least one embodiment is illustrated. The processor 1300 may include a hybrid architecture processor (e.g., Lunar Lake or Meteor Lake) from Intel Corporation, Santa Clara, California, or other processors sharing at least some of the components described herein. The processor 1300 may include one or more central processing units (CPU 1302), one or more graphics processing units (GPU 1306), and / or one or more neural processing units (NPU 1308), which may be, for example, dedicated AI accelerators for offloading artificial intelligence (AI) workloads from the CPU 1302 and GPU 1306. The processor 1300 may use instructions that, if executed, cause the processor 1300 and / or any of its components to perform some or all of the processes and techniques described elsewhere herein. The processor 1300 may include any number of memory and cache units 1310 for facilitating processing between different components of the processor 1300. The memory and cache 1310 on processor 1300 may include one or more levels of cache (e.g., L1, L2, L3, and / or last-level cache) and high-bandwidth memory (e.g., HBM2e or HBM3) in any combination. Regarding processor 1300 and any components described above or elsewhere herein, one or more APIs described herein may, for example, be compiled into instructions that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device (e.g., cache and / or memory) internal or external to processor 1300. The results of APIs may be stored in storage devices internal or external to processor 1300, including registers, DRAM, flash memory, SRAM, cache, or other memory. One or more APIs described herein may include calls.

[0189] Processor 1300 may include a computing engine as CPU 1302, and may include any number of cores, such as, but not limited to, up to 16 cores / 22 threads. The cores in CPU 1302 may include P-cores (performance), E-cores (high efficiency), and LP-E cores (low-power, high-efficiency). Performance cores can be used for low-latency, single-threaded, compute-intensive workloads, while high-efficiency cores can be used for multi-threaded, less compute-intensive workloads. Low-power, high-efficiency cores can be used for scalable multi-threaded execution and offloading background tasks. P-cores can be used for single-threaded and limited-threaded execution, while E-cores and LP-E cores are used for multi-threaded throughput and power efficiency.

[0190] The GPU 1306 can include any number of graphics engines, such as, but not limited to, those with 8 Xe cores (up to 128 execution units or EUs). Arc TM Graphics engine (Xe LPG). For example... Figure 13 As shown, GPU 1306 may include vector engine 1310 and matrix engine 1312, which, for example, can run FP, INT, and matrix operation tasks simultaneously, individually, or in batches. GPU 1306 may include load / store unit 1314, as well as other memories, such as, but not limited to, instruction cache (I$) 1316 and L1 cache / subsystem local memory (SLM) 1318, which may, for example, store instructions for performing any of the operations described above or elsewhere herein.

[0191] The NPU 1304 may include one or more AI Boost integrates a Neural Processing Unit (NPU). The NPU 1304 can be enumerated as an integrated PCIe device to the host processor. The NPU 1304 may include one or more (e.g., two) Neural Computation Engine (NCE) tiles 1330. Each tile may be configured with any combination of, but not limited to, the following: (e.g., 2000) Multiply-Accumulate (MAC) engines 1334, a post-processing engine (not shown), an AEP processor (not shown), and memory per tile (2MB dedicated SRAM), such as... Figure 13 As shown. For general computing needs, the neural computing engine 1330 may include a disturbance pipeline 1332, an activation function (AF) 1336, a data transformation 1338, a load / store 1340, and a streaming hybrid architecture vector engine (SHAVE) 1328 for high-performance parallel computing, which may include a DMA (Direct Memory Access) engine 1324 for transporting data between system memory DRAM (Dynamic Random Access Memory) 1326 and a software-managed cache. The built-in device MMU (Memory Management Unit) 1322, plus the IOMMU (Input-Output Memory Management Unit) (not shown), can support multiple concurrent hardware contexts and provide secure isolation between execution contexts according to the MCDM (Microsoft Computing Driver Model) architecture. The processor 1300 may also include a media unit (not shown), which may be included on or separate from the XCD or other components of the processor 1300 to enable video playback and video processing of compressed or uncompressed data, such as using HEVC, AV1, VP9, ​​and AVC hardware-accelerated decoding support and HEVC, VP9, ​​and AVC hardware-accelerated encoding support.

[0192] Thread bootstrap ( The Thread Director (which includes firmware built into the processor 1300) can prioritize and manage the distribution of workloads, sending tasks to optimized cores. For example, the Thread Director can tie P cores, E cores, and / or LP-E cores (as described above) together with task scheduling capabilities and the ability to send less demanding tasks to E cores or LP-E cores. Deep learning acceleration ( DLBoost (not shown) can provide built-in AI acceleration for training and inference workloads and may include support for VNNI (for CPU) and DP4a (for GPU) instruction sets. This instruction set can be used with OpenVINO. TM The toolkit and oneAPI are optimized to accelerate INT8 inference. For example, the software stack described elsewhere in this document can be used to leverage OpenVINO. TM The toolkit enables AI inference. The processor 1300 can be configured to execute applications, such as, but not limited to, CUDA programs.

[0193] In at least one embodiment, processor 1300 may include one or more circuitry configured to execute one or more instructions or otherwise perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. One or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0194] Processor 1300 may alternatively include a processor based on Qualcomm's AIEngine Direct architecture from Santa Clara, California, or other processors sharing at least some of the components described herein. It may include any number of NPUs, GPUs, CPUs, and other associated components, such as, but not limited to, an NPU 1304 as a Hexagon NPU, a GPU 1306 as an Adreno GPU, a CPU 1302 as a Kryo or Qualcomm Oryon CPU, and a Qualcomm Sensing Hub (not shown) and a memory subsystem 1310 in any combination. Hexagon NPU 1304 may include power rails, micro-tile inference units, hardware acceleration units, tensor units, scalar units, and vector units (all not shown), which may have dedicated or shared memory (e.g., cache or memory, such as HBM3) for storing, for example, instructions for performing any of the operations described above or elsewhere herein. The Adreno GPU 1306 can provide graphics and parallel processing for AI, in formats including but not limited to 32-bit floating-point (FP32), 16-bit floating-point (FP16), and 8-bit integer (INT8). The Kryo or Qualcomm Oryon CPU 1302 can execute AI workloads and handle the contextualization of ubiquitous generative AI applications. The CPU 1302 may also include an instruction fetch unit, a renaming and dismiss unit, a memory management unit, a vector execution unit, an integer execution unit, and a load and store unit for processing and instruction management. Regarding the processor 1300 and any of its components described above or elsewhere herein, one or more APIs described herein may, for example, be compiled into instructions that may be fetched by the instruction fetch unit, decoded by the processor decoder or equivalent, scheduled (e.g., sequentially or out of order) for execution by the scheduler or equivalent, executed by execution logic or equivalent, reordered, and then dismissed by the renaming and dismiss unit. The API (and / or compiled instructions including the API) can be stored in any storage device (e.g., cache and / or memory) inside or outside the processor 1300. An arbitrary number of CPU cores 1302 can be included in an arbitrary number of CPU clusters, which can be coupled to memory and / or cache, such as, but not limited to, a shared L2 cache. Memory can be separate or shared; for example, the CPU clusters of CPU cores 1302 can be coupled to a memory subsystem 1310, which can include structures capable of reading and writing to memory (e.g., DRAM), system-level caches, and an arbitrary number of memory management units.The Qualcomm sensing hub (not shown) includes a miniature NPU, power rails, and conventional sensors (such as gyroscopes, accelerometers, or even barometers) that support voice and data streaming. The memory subsystem 1310 may include memory and cache on the processor 1300, which may include L1 or more levels of cache (e.g., L1, L2, L3, and / or last-level cache) and high-bandwidth memory (e.g., HBM2e or HBM3) in any combination, for example, for storing information and / or instructions for performing any of the operations described above or elsewhere herein. All or part of the memory and / or cache in the memory subsystem 1310 may be shared or used individually by any component or combination of components on the processor 1300 (e.g., GPU 1306, NPU 1304, and CPU 1302).

[0195] The Qualcomm AI Engine 1300 can be programmed and controlled using a software stack to perform some or all of the operations described herein, including, for example... A neural processing SDK is provided for inference on Android, Linux, and Windows. Developer libraries and services support programming languages, virtual platforms, and compilers. At lower levels of the software stack, system software includes a basic real-time operating system (RTOS), system interfaces, and drivers. The software stack supports various operating systems, including Android, Windows, Linux, and QNX, as well as deployment and monitoring infrastructures such as Prometheus, Kubernetes, and Docker. OpenCL and DirectML are supported for direct cross-platform access to the GPU 1306. For the CPU 1302, LLVM compiler infrastructure optimizations enable accelerated and efficient AI inference. Regarding the Qualcomm AI Engine 1300 and any of its components described above or elsewhere herein, one or more APIs described herein can, for example, be compiled into instructions that can be fetched by instruction fetching logic or equivalents, decoded by processor decoders or equivalents, scheduled (e.g., sequentially or out of order) for execution by a scheduler or equivalent, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. The API (and / or compiled instructions including the API) can be stored in any storage device (e.g., cache and / or memory) inside or outside the Qualcomm AI Engine 1300. The results of the API can be stored in storage devices inside or outside the Qualcomm AI Engine 1300, including registers, DRAM, flash memory, SRAM, cache, or other memory.

[0196] In at least one embodiment, the processor 1300 or the Qualcomm AI engine 1300 may include one or more circuitry configured to execute one or more instructions or otherwise perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The one or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0197] Figure 14A A processor 1400 according to at least one embodiment is illustrated. The processor 1400 may include a Scalable family processor from Intel Corporation, Santa Clara, California, or other processors that share at least some of the components described herein. The processor 1400 may include one or more cores 1412(1)-1412(N) capable of performing the operations described elsewhere herein, where N is any integer greater than 1. Cores 1412(1)-1412(N) may be interconnected using ring and / or mesh interconnects. Utilizing a mesh interconnect architecture, arrays of vertical and horizontal communication paths may allow traversal from one core to another 1412(1)-1412(N) via the shortest path (jumping to the correct row along the vertical path and to the correct column along the horizontal path). For the mesh interconnect, a die may accommodate cores 1412(1)-1412(N) and may include a Converged Mesh Stop Point (CMS) grid that may be associated with cores 1412(1)-1412(N) (e.g., 1:1). Each core can be associated with a low-level cache (LLC) slice 1414(1)-1414(N), or cores 1412(1)-1412(N) can share a cache, such as a low-level cache. LLC 1414(1)-1414(N) can be inclusive or non-inclusive (having blocks not present in the high-level cache) by merging blocks from a higher-level cache (e.g., L2 cache). Each core and LLC slice can include a caching and home agent (CHA) (not shown), which can maintain cache consistency by providing resource scalability via the mesh interconnect. Super Path Interconnect ( UPI 1416 provides cache coherency capabilities. UPI 1416 enables coherent interconnects for scalable systems and allows multiple processors to share a single shared address space via links, such as, but not limited to, two or three UPI links per processor.

[0198] The processor 1400 may also include a system agent 1410, which may house and / or perform various functions, such as, but not limited to, memory management, display functions, and / or input / output (I / O) functions. For example, the processor 1400 may include one or more integrated memory controllers (IMCs) 1408. IMCs 1408 may control and manage memory, such as, but not limited to, different memory types, such as DDR RAM, such as DDR4, or other memory described elsewhere herein. The system agent 1410 may include a display controller (not shown) for supporting one or more displays. The system agent 1410 may also integrate a PCIe 1404 (e.g., up to 20 PCIe lanes), which may, for example, be connected to an external dedicated graphics connector via a DMI bus (e.g., Intel's DMI 3.0 bus) 1406. The system agent 1410 may include an image processing unit (IPU) (not shown) that integrates an on-die image signal processor (ISP). Structure 1402 provides scalability for connecting to other nodes (e.g., processors, such as processor 1400) and can, for example, be connected to Cornelis Networks (…). It can be used together with elements of a scalable system framework that provides performance for high-performance computing (HPC) workloads and the ability to scale to tens of thousands of nodes.

[0199] Figure 14BComponents within a core 1412 according to at least one embodiment are illustrated. The core 1412 may include a front-end 1418, a back-end or execution engine 1432, and a memory subsystem 1442. The front-end 1418 may provide operations (e.g., operations described elsewhere herein) to the execution engine 1432 by decoding instructions stored in memory. For example, the front-end 1418 may include micro-operation (μOps) cache paths and / or traditional paths, and a branch prediction unit 1421 capable of determining path instructions. A traditional path of instructions may include fetching variable-length (e.g., x86) instructions from an L1 instruction cache 1420 and instruction fetch and pre-decode 1422, queuing these instructions into an instruction queue 1424, and decoding the instructions into μOps that can be provided to an allocation queue 1428 using a decoder 1426. Alternatively, the μOps cache path may include a cache that includes decoded μOps (μOps 1430) that can be sent to the allocation queue 1428. The allocation queue 1428 can act as an interface between the front end 1418 and the execution engine 1432, and can provide instructions to the execution engine 1432. For example, one or more APIs described herein can be compiled into instructions that can be stored, processed, and executed by the front end 1418 and the execution engine 1432, and stored in the memory subsystem 1442.

[0200] Execution engine 1432 can receive micro-operations into reordering buffer 1434, which can register, rename, and deregister μOPs. μOPs can be sent from the reordering buffer to scheduler 1436, which can be connected to one or more different execution units 1438, which can be connected to address generation units (AGUs) 1440. Execution units 1438 can perform operations such as basic arithmetic logic unit (ALU) operations, multiplication, division, and / or more complex operations, such as, but not limited to, various vector operations. Scheduler 1436 can manage the queuing of μOPs for one or more execution units 1438 based on, for example, the operations that need to be performed.

[0201] The memory subsystem 1442 can handle load and store requests as well as sorting operations. For example, μOPs may be associated with memory accesses (e.g., load and store), and these μOPs can be sent through dedicated scheduler ports that can perform these memory operations. For example, store and load operations can be sent to load and store buffers 1444. The memory subsystem 1442 may also include shared or separate L1 data and instruction caches 1446, and an L2 cache 1448 that can be used and shared by the L1 data and instruction caches 1446. (As described above regarding...) Figure 14AEach core 1412 can be connected to a slice of a level 3 cache (e.g., LLC1414), which can be shared by all cores 1412.

[0202] In at least one embodiment, processor 1400 may include one or more circuitry configured to execute one or more instructions or otherwise perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The one or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0203] Figure 15 An AI accelerator 1500 according to at least one embodiment is illustrated. Processor 1500 may include a processor with an AI accelerator architecture manufactured by Intel Corporation, Santa Clara, California, or other processors sharing at least some of the components described herein. AI accelerator 1500 may use instructions that, if executed by AI accelerator 1500, cause AI accelerator 1500 to perform some or all of the processes and techniques described elsewhere herein. For example, with respect to AI accelerator 1500 and any components described above or elsewhere herein, one or more APIs described herein may, for example, be compiled into instructions that may be fetched by instruction fetching logic or equivalents, decoded by processor decoders or equivalents, scheduled (e.g., sequentially or out of order) by a scheduler or equivalent for execution, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device internal or external to AI accelerator 1500 (e.g., in cache and / or memory). The results of the API can be stored in internal or external storage devices of the AI ​​accelerator 1500, including registers, DRAM, flash memory, SRAM, cache, or other memory. The AI ​​accelerator 1500 may include one or more compute dies, which may include homogeneous or heterogeneous processors. The compute dies may include one or more central processing units (CPUs), one or more graphics processing units (GPUs), or a combination of both.

[0204] In at least one embodiment, the computational die may include a computational engine for performing AI computations. In at least one embodiment, the computational die of the AI ​​accelerator 1500 may be split into any number (e.g., four) clusters, which may be referred to as DCORE (Deep Learning Core) 1506, and include any number of matrix multiplication engines (MME) 1508, tensor processor cores (TPC) 1510, memory management units 1512, and L2 caches 1514 in any combination. The MME 1508 may perform operations using matrix multiplication, such as fully connected layers, convolutions, and batch general matrix multiplication (GEMM). The MME 1508 may be equipped with a multiplication-accumulation unit (MAC) (not shown), which may perform general matrix multiplication (GEMM) operations, such as, but not limited to, AxB multiplication, which involves generating a tensor C [NxM] from two input tensors A [NxK] and B [KxN]. The MME 1508 may be programmed with array dimensions, positions, data types, and various operands. The MME 1508 can retrieve tensors A and B from memory and pull them into its streaming buffer for parallel matrix multiplication by the MAC. After completion, the MME 1508 can push tensor C back to memory. The TPC 1510 may include any number of scalar units for performing scalar operations, any number of vector units for performing vector operations, any number of register files or local memory units (e.g., vector local memory), and load and store components for instructions, which may be coupled to memory or caches (e.g., HBM, L3 cache, and / or L2 cache) (all not shown). The TPC can support different types of parallel processing, such as Very Long Instruction Word (VLIW) Single Instruction Multiple Data (SIMD) data types such as, but not limited to, FP32, BF16, FP16, and FP8 (both E4M3 and E5M2), UINT32, INT32, UINT16, INT16, UINT8, and INT8 data types. Any number of computational dies can be interconnected. Interconnects that can connect computing dies can be via intermediate bridges, for example, those intermediate bridges that are transparent to software.

[0205] The memory on the AI ​​accelerator 1500 may include one or more levels of cache (e.g., L1, L2, L3, and / or last-level cache) and high-bandwidth memory (e.g., HBM2e or HBM3) in any combination. The memory and / or cache system may be unified or separate. The compute die of the AI ​​accelerator 1500 may include on-chip memory comprising one or more levels (e.g., two levels) of cache. On-chip SRAM or other memory described elsewhere herein may be used as a unified last-level cache (L3) or split into multiple slices of L2 cache accessible to the MME 1508 and TPC 1510 groups. The use of on-chip memory as an L2 or L3 cache is entirely software-configurable, with the software dynamically determining its optimal cache allocation based on I / O tensors. AI accelerator 1500 may include one or more memory management units (MMUs) 1522 for managing memory, such as allowing the AI ​​accelerator 1500 memory subsystem to run in virtual space when accessing VRAM.

[0206] AI accelerator 1500 may include a communication port (e.g., a PCIe Gen5 x16 port) 1502 for communicating with a host and scheduling and synchronization unit 1504. AI accelerator 1500 may include a media unit 1516, which may include any number or combination of media decoder engines (DECs) 1520 and rotation engines (ROTs) 1518. AI accelerator 1500 may include a network unit 1524, which may include any number or combination of network ports 1526 and an accompanying RDMA engine 1528, L2 cache, and memory (e.g., HBM2e or HBM3) stack. AI accelerator 1500 may include a programmable control path entity (not shown) for managing the parallel and efficient execution of the various engines. The control path may include a submission queue (SQ) that can be issued by the runtime system, a completion queue (CQ) that can be used for job completion reporting, a programmable scheduling mechanism that can be used for task scheduling, a programmable hardware synchronization mechanism or "synchronization manager (SM)" that can be used for hardware synchronization, and a programmable interrupt service mechanism or "interrupt manager (INTR)" that can pass asynchronous events to drivers.

[0207] The AI ​​Accelerator 1500 may include media decoding units supporting video formats such as, but not limited to, HEVC, Progressive H.264, SVC base layer, MVC, VP9, ​​JPEG, and Progressive JPEG. The AI ​​Accelerator 1500 may support post-processing of the decoded media stream, such as, but not limited to, image downsizing (image resizing), vertical and horizontal scaling at different scaling ratios, image enlargement, image cropping, bilinear scaling, and Lancos scaling. The AI ​​Accelerator 1500 may implement two post-processing channels per decoder unit, one for scalar (up and down) and the other solely for outputting the original image. The AI ​​Accelerator 1500 may include a hardware rotation engine that performs the following transformations on the input image: 2D rotation, 3D rotation, projection, image warping and de-warping, resampling of the input data at user-defined coordinates, and rescaling.

[0208] The RDMA 1528 based on converged Ethernet on the AI ​​accelerator 1500 enables scaling from a single node (i.e., from a single AI accelerator 1500 to hundreds or thousands of nodes or AI accelerators 1500). The network subsystem 1524 may include... The accelerator 1500 includes an In-Gigabit Ethernet Communication Library (IGCL), a master controller coordinating data movement, and a programmable scheduling mechanism that enables smooth engine activation while maintaining task dependencies. The accelerator network subsystem may include a Gigabit Ethernet NIC port 1526, a Layer 2 MAC (not shown), and an RDMA engine 1528. The AI ​​accelerator 1500 may include an aggregation engine for performing summation activities. All engines in the processor 1500 can run in parallel; for example, the MME 1508, TPC 1510, and NIC 1526 can all operate simultaneously. Dependencies may exist between operations running on different engines; for example, the output of one engine may be used as the input of another engine, and / or the MME, TPC, and NIC may be scheduled to run in parallel. When one engine completes its execution, another engine can be scheduled to begin working on the next operation (executed immediately after its input is ready).

[0209] The AI ​​accelerator 1500 can be operated and controlled using a software layer 1528, which may include low-level components such as, but not limited to, a graph compiler, an automatic kernel fusionist and pre-compiled kernel libraries, and integrations with the AI ​​ecosystem such as, but not limited to, PyTorch, DeepSpeed, Hugging Face, vLLM, Ray, etc., or as described elsewhere in this document regarding software and programming platforms. The software layer 1528 may include implementations of algorithms such as, but not limited to, paged attention, flash attention, etc. The software layer 1528 can generate optimized binary code that implements a given model topology, such as, but not limited to, performing operator fusion, data layout management, parallelization, pipeline and memory management, and graph-level optimization.

[0210] In at least one embodiment, the AI ​​accelerator 1500 may include one or more circuitry for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The one or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0211] This paper describes a neuromorphic computing system employing a multi-core architecture, where each core houses computing elements including neurons, synapses with on-chip learning capabilities, and local memory for storing synaptic weights and routing tables. Figure 16This is a simplified block diagram 1600 illustrating at least a portion of an example of such a neuromorphic computing device 1605 according to at least one embodiment. The neuromorphic computing device 1605 may include a neuromorphic processor from Intel Corporation, Santa Clara, California, or other processors that include at least a portion of the components described herein. As shown in this example, the device 1605 may be equipped with a network 1610 consisting of multiple neural network cores interconnected by a network on the device, thereby potentially defining multiple distinct connections between the cores. For example, the device 1605 may provide a network 1610 of spiking neural network cores, each core communicating via short packet pulse messages sent from one core to another through network channels. Each core (e.g., 1615) may have processing and memory resources, as well as logic, for implementing a number of primitive nonlinear time computation elements, such as, but not limited to, multiple (e.g., more than 1000) distinct artificial neurons (referred to herein as “neurons”). For example, each core may be able to implement multiple neurons concurrently, allowing the neuromorphic core to implement many, many neurons using the device 1605. With respect to the neuromorphic computing device 1605 and any components described above or elsewhere herein, one or more APIs or equivalents described herein may, for example, be compiled into instructions or equivalents that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. The APIs (and / or compiled instructions including the APIs) may be stored in any storage device (e.g., cache and / or memory) internal or external to the neuromorphic computing device 1605. The results of the APIs may be stored in storage devices internal or external to the neuromorphic computing device 1605, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents.

[0212] continue Figure 16For example, neuromorphic computing device 1605 may also include processor 1620 and system memory 1625 for implementing one or more components to manage and provide the functionality of neuromorphic computing device 1605. For instance, a system manager 1630 may be provided to manage the global attributes and operations of neuromorphic computing device 1605 (e.g., attributes affecting core network 1610, multiple cores in network 1610, interconnection of neuromorphic computing device 1605 with other devices, managing access to global system memory 1625, and other potential examples). In one example, system manager 1630 may manage the definition and configuration of specific routing tables for individual routers in network 1610, orchestration of network definitions and attributes to be applied to network 1610 (e.g., weights, attenuation rates, etc.), core synchronization and time multiplexing management, routing input to appropriate cores, and other potential functions.

[0213] As another example, the neuromorphic computing device 1605 may also include a programming interface 1635 through which a user or system can specify the neural network definition to be applied (e.g., via routing tables and individual neuron attributes), implemented by the neuromorphic core grid 1610. A software-based programming tool may be provided with or separately from the neuromorphic computing device 1605, through which a user can provide a definition for a specific neural network to be implemented using the neuromorphic core network 1610. The programming interface 1635 can receive input from a programmer, then generate the corresponding routing table and populate the specified parameters into the local memory of each neuromorphic core (e.g., 1615) to implement the corresponding custom artificial neural network implemented by the neuromorphic core 1615.

[0214] In certain circumstances, the neuromorphic computing device 1605 can advantageously engage and interoperate with other devices, including general-purpose computing devices, to enable specific applications and use cases. Therefore, in some cases, external interface logic 1640 may be provided to communicate with one or more other devices (e.g., via one or more defined communication protocols). External interface 1640 may be used to accept input data from another device or an external memory controller used as an input data source. External interface 1640 may additionally or alternatively be used to allow the results or outputs of computations performed using the neural network implemented using the neuromorphic computing device 1605 to be provided to another device (e.g., another general-purpose processor implementing machine learning algorithms) to enable additional applications and enhancements, among other examples.

[0215] like Figure 16The diagram illustrates a network 1610 interconnected by a network of multiple neural network cores on a device, showing a portion of a network structure interconnecting multiple neuromorphic cores (e.g., 1615a-d). For example, several neuromorphic cores (e.g., 1615a-d) can be provided in a mesh, each core interconnected via a network including multiple routers (e.g., 1650). In one implementation, each neuromorphic core (e.g., 1615a-d) can be connected to a single router (e.g., 1650) in the router array, and each router can be connected to at least one other router (e.g., [other router]). Figure 16 (As shown at 1610 in the diagram). As an example, in one particular implementation, four neuromorphic cores (e.g., 1615a-d) can be connected to a single router (e.g., 1650), and each router 1650 can be connected to two or more other routers to form a multi-core mesh, thereby allowing each neuromorphic core to interconnect with every other neuromorphic core in the neuromorphic computing device 1605. Furthermore, since each neuromorphic core can be configured to implement multiple different neurons, the router network of the neuromorphic computing device 1605 can similarly implement connections or artificial synapses (or simply "synapses") defined between any two of the potential many (e.g., 30,000+) neurons defined by the network definition using the neuromorphic cores 1610 provided in the neuromorphic computing device 1605.

[0216] Figure 16A block diagram of the internal components of an example implementation of a neuromorphic core 1615 is shown. In one example, a single neuromorphic core may implement a number of neurons (e.g., 1024) that share the architectural resources of the neuromorphic core 1615 in a time-division multiplexing manner. In one example, each neuromorphic core 1615 may include a processor block 1655 capable of executing arithmetic functions and routing related to the implementation of the digitally implemented artificial neurons, such as, but not limited to, those explained herein. Each neuromorphic core 1615 may also provide local memory in which routing tables of the neural network can be stored and accessed, accumulated potentials of each cell body of each neuron implemented using core 1615 can be tracked, parameters of each neuron implemented by core 1615 can be recorded, and other data and usage can be recorded. Components or architectural resources of the neuromorphic core 1615 may also include: an input interface 1665 for receiving input spike messages generated by other neurons on other neuromorphic cores; and an output interface 1670 for sending spike messages to other neuromorphic cores via a mesh network 1610. In some instances, the routing logic of the neuromorphic core 1615 can be implemented at least partially using the output interface 1670. Furthermore, in some cases, the core (e.g., 1615) can implement multiple neurons within an example SNN, and some of these neurons can be interconnected. In this case, spiking messages sent between neurons hosted on the core 1615 can forgo communication via the routing structure of the neuromorphic computing device 1605 and can be managed locally within the specific neuromorphic core 1615.

[0217] Each neuromorphic core may also include logic for implementing artificial dendrites 1680 and artificial cell bodies 1685 (hereinafter referred to as “dendrites” and “cell bodies”, respectively) for each neuron 1675. Dendrite 1680 may be a hardware-implemented process for receiving impulses from network 1610. Cell body 1685 may be a hardware-implemented process for receiving the current time-accumulated neurotransmitter mass of each dendrite and evolving the potential states of each dendrite and cell body to generate outgoing impulse messages at appropriate times. Dendrite 1680 may be defined for each connection receiving input from another source (e.g., another neuron). In one implementation, the dendritic process 1680 may receive and process the impulse message as it arrives serially from network 1610 in a time-division multiplexed manner. With the reception of impulses, neuronal activation (tracked using cell body 1685 (and local memory 1660)) may increase. When the activation of a neuron 1675 exceeds a threshold set for neuron 1675, neuron 1675 generates a spike message, which is propagated via output interface 1670 to a fixed set of fan-out neurons. The network distributes the spike messages to all destination neurons, which in turn can update their activation in a transient, time-dependent manner in response. This can lead to some of the destination neurons also exceeding their corresponding thresholds and triggering further spike messages, just as in real biological neural networks.

[0218] As described above, the neuromorphic computing device 1605 can reliably implement spiking-based neural computing models. Such models are also known as spiking neural networks (SNNs). In addition to neuronal and synaptic states, SNNs incorporate temporal concepts. For example, in SNNs, communication occurs via event-driven action potentials or impulses that convey no explicit information other than the impulse timing and the implicit source and destination neuron pairs corresponding to the impulse transmission. The computation of the result of a dynamic nonlinear integral as a weighted impulse input occurs in each neuron. In some implementations, recurrent and dynamic feedback can be incorporated into the SNN computation model. Furthermore, various network connectivity models can be employed to model a wide range of real-world networks or relationships, including fully connected (all-to-all) networks, feedforward trees, completely random projections, "small-world" networks, and other examples. Isomorphic two-dimensional networks at the neuromorphic core (e.g., but not limited to...) Figure 16The network shown in the example can advantageously support all these network models. Since some or all of the cores of the neuromorphic computing device 1605 can be connected, some or all of the neurons defined in a core can also be fully connected via a certain number of router hops. The neuromorphic computing device 1605 may also include fully configurable routing tables for defining various neural networks by allowing neurons in each core to distribute their spurs to any number of cores in the grid 1610 to achieve a completely arbitrary connection graph.

[0219] In improved implementations of systems capable of supporting SNNs, for example, but not limited to... Figure 16 The example illustrates a very large-scale integrated circuit (VLSI) hardware device that can provide high-speed, reliable circuitry to implement SNNs (Spiritual Neural Networks) to model the information processing algorithms used by the brain, but in a more programmable way. For instance, while a biological brain can only perform a specific set of defined behaviors (a consequence of years of development), a neuromorphic processor device can provide the ability to rapidly reprogram all neural parameters. Therefore, a single neuromorphic processor can be used to implement a wider range of behaviors than a single slice of biological brain tissue. This distinction can be achieved by employing neuromorphic processors with neuromorphic designs that are radically different from those found in natural neural circuitry.

[0220] As an example, a neuromorphic processor can implement a spontaneous neural network (SNN) using time-multiplexed computation in both a spiking communication network and the neuronal mechanism of the neuromorphic computing device 1605. Therefore, the physical circuitry of the neuromorphic computing device 1605 can be shared by many neurons to achieve a higher neuron density. Through time multiplexing, the network can connect N cores with a total wiring length of O(N), while the length of discrete point-to-point wiring will be extended to O(N). 2 This significantly reduces wiring resources to accommodate planar and non-plastic VLSI routing techniques, among other examples. In the neuromorphic core, time multiplexing can be implemented through dense memory allocation, for example, using static random access memory (SRAM) with a shared bus, address decoding logic, and other multiplexed logic elements. The state of each neuron can be stored in the processor's memory, where data describing the state of each neuron includes the state of the collective synapse of each neuron, all currents and voltages on its membrane, and other example information (e.g., but not limited to configuration and other information).

[0221] Neuromorphic processors can be implemented in a “digital” manner, unlike other processors that employ more “analog” or “isomorphic” neuromorphic approaches. For example, a digital implementation can use digital adder and multiplier circuitry to integrate synaptic currents, in contrast to an analog isomorphic neuromorphic approach that accumulates charge on capacitors in a manner similar to how neurons accumulate synaptic charge on their lipid membranes. For instance, the accumulated synaptic charge for each neuron can be stored in the local memory of the corresponding core. Furthermore, at the architectural level of an example digital neuromorphic processor, reliable and deterministic operation can be achieved through time synchronization across the core network, ensuring that any two executions of the design, given the same initial conditions and configuration, will produce the same results. Asynchronicity can be reserved at the circuit level to allow individual cores to operate as quickly and freely as possible while maintaining determinism at the system level. Therefore, in neural computing, the concept of time as a time variable can be abstracted away from the “wall clock” time used by the hardware to perform computations. Thus, in some implementations, a time synchronization mechanism can be provided that globally synchronizes the neuromorphic cores at discrete time intervals. The synchronization mechanism allows neural computation to be completed at the fastest speed allowed by the circuit, and there is a difference between the runtime and the biological time for modeling neuromorphic systems.

[0222] In operation, the neuromorphic computing device 1605 can start in an idle state when all neuromorphic cores are inactive. As each core asynchronously loops through its neurons, it generates impulse messages, which are routed by the mesh interconnect to the appropriate destination core containing all destination neurons. The implementation of multiple neurons on a single neuromorphic core can be time-multiplexed, and time steps can be defined, where all impulses involving multiple neurons can be processed and considered using the shared resources of the respective cores. When each core completes its service to its neurons within the corresponding time step, in some implementations, the core can communicate with neighboring cores using synchronization messages (e.g., using a handshake) to refresh the mesh of all transmitted impulse messages, allowing the core to safely determine that all impulses have been serviced within a certain time step. At this point, all cores can be considered synchronized, allowing them to advance their time steps and return to the initial state to begin the next time step.

[0223] Given this context, as described above, a device (e.g., 1605) can be provided to realize an interconnected neuromorphic core grid 1610, wherein core 1615 can realize multiple artificial neurons capable of interconnecting to realize an SNN. Each neuromorphic core (e.g., 1615) can provide two loosely coupled asynchronous processes: an input dendrite process (e.g., 1680) that receives impulses from network 1610 and applies them to the appropriate destination dendritic compartment at an appropriate future time; and an output cell body process (e.g., 1685) that receives the current-time accumulated neurotransmitter mass of each dendritic compartment and evolves the membrane potential state of each dendrite and cell body to generate an outgoing impulse message at an appropriate time (e.g., when the threshold potential of the cell body is reached). It should be noted that, from a biological perspective, the names of dendrites and cell bodies used herein are only approximate to the function of these functions and should not be interpreted too literally.

[0224] In at least one embodiment, the neuromorphic computing device 1605 may include one or more circuitry for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The one or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0225] Figure 17 This is a block diagram of an embodiment of a multi-node network capable of enabling remote memory computing according to any embodiment. System 1700 may represent the node network described herein, for example, the node network may be used to perform some or all of the operations described herein. System 1700 may represent a data center. System 1700 may represent a server farm. System 1700 may represent a data cloud or processing cloud. System 1700 may represent a supercomputer. System 1700 may include tens, hundreds, or thousands of nodes. The nodes of System 1700 may include processors, such as, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), or any combination of processors described herein, such as, but not limited to, processors described herein. Figure 11-23BOther processors in the system. For any processor in System 1700 and any components described above or elsewhere herein, one or more APIs or equivalents described herein may, for example, be compiled into instructions or equivalents that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device (e.g., cache and / or memory) inside or outside the processor or node. The results of APIs may be stored in storage devices inside or outside the processor or node, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents. System 1700 may include more than nine thousand nodes, each node comprising two Intel Xeon Max processors, six Intel Max series GPUs, and a unified memory architecture, such as, but not limited to, the architecture used in Intel's Aurora supercomputer in Santa Clara, California, or other supercomputers that share at least some of the components described herein.

[0226] One or more clients 1702 send requests to system 1700 via network 1704. Network 1704 represents one or more local area networks, wide area networks, or a combination of both. Clients 1702 can be human or machine clients that generate requests for operations to be performed by system 1700. System 1700 executes the application or data computation task requested by client 1702.

[0227] System 1700 may include one or more racks, which represent structural and interconnect resources for housing and interconnecting multiple computing nodes. Rack 1710 may include multiple nodes 1730. Rack 1710 may carry multiple blade assemblies 1720(0)-1720(N-1), where N is an integer greater than or equal to 2. Carrying may refer to providing power, structural or mechanical support, and interconnection. Blades 1720(0)-1720(N-1) may refer to computing resources on a printed circuit board (PCB), where the PCB houses the hardware components of one or more nodes 1730. Blades 1720(0)-1720(N-1) may or may not include a chassis, enclosure, or other “box” besides those provided by rack 1710. Blades 1720(0)-1720(N-1) may include an enclosure with exposed connectors for connection to rack 1710. System 1700 may or may not include rack 1710, and each blade (e.g., 1720(0)) may include a chassis or housing that may be stacked or otherwise closely proximate with other blades and allow nodes 1730 to interconnect. System 1700 may include 10,624 compute blades, comprising 63,744 Intel Max series GPUs and 21,248 Intel Xeon Max CPUs on 166 racks.

[0228] System 1700 may include architecture 1770, which represents one or more interconnectors of nodes 1730. Architecture 1770 may include multiple switches 1772 or routers or other hardware for routing signaling between nodes 1730. Furthermore, architecture 1770 may couple system 1700 to network 1704 for access by client 1702. In addition to routing devices, architecture 1770 may also be considered to include cables or ports or other hardware devices for coupling nodes 1730 together. Architecture 1770 may have one or more associated protocols for managing signaling routing through system 1700. One or more protocols are at least partially dependent on the hardware devices used in system 1700.

[0229] As shown in the figure, rack 1710 may include N blades (e.g., 1720(0)-1720(N-1)). In addition to rack 1710, system 1700 may also include rack 1750. As shown in the figure, rack 1750 may include M blades (e.g., 1760(0)-1760(M-1)). M is not necessarily the same as N; therefore, it is understood that various different hardware device components may be used and coupled together into system 1700 via structure 1770. Blades 1760(0)-1760(M-1) may be the same as or similar to blades 1720(0)-1720(N-1). Node 1730 may be any type of node described herein and is not necessarily of the same type. System 1700 is not limited to homogeneous or non-homogeneous systems.

[0230] The nodes in blade 1720(0) are shown in detail. However, other nodes in system 1700 may be the same or similar. At least some nodes 1730 may be compute nodes, having processor 1732 and memory 1740. A compute node is a node having processing resources (e.g., one or more processors) that executes an operating system and can receive and process one or more tasks. At least some nodes 1730 may include storage server nodes, which have servers as processing resources 1732 and memory 1740. A storage server is a node having more storage resources than a compute node, and instead of having processors for performing tasks, a storage server includes processing resources for managing access to storage nodes within the storage server.

[0231] Node 1730 may include interface controller 1734, which may represent logic for controlling node 1730's access to structure 1770. The logic may include hardware resources for interconnecting to physical interconnect hardware. The logic may include software or firmware logic for managing the interconnect. Interface controller 1734 may include a host structure interface, which may include a structure interface according to any embodiment described herein.

[0232] Node 1730 may include a memory subsystem 1740. Memory 1740 may include a memory computation resource (comp) 1742, which represents the ability of memory 1740 to perform one or more memory computations. System 1700 supports remote memory operations, such as, but not limited to, those described elsewhere herein. Therefore, node 1730 may request a remote node to perform a memory computation, wherein the data used for the computation remains local to the executing node and is not sent via structure 1770 or from memory to the structure interface. In response to the execution of the memory computation, the executing node may provide the result to the requesting node.

[0233] Processor 1732 may include one or more individual processors. Each individual processor may include a single processing unit, a multi-core processing unit, or a combination thereof. A processing unit may include a main processor, such as, but not limited to, a CPU (Central Processing Unit), a peripheral processor (such as, but not limited to, a GPU (Graphics Processing Unit)), or a combination thereof. Memory 1740 may be or include memory devices and memory controllers.

[0234] The term "memory device" can refer to different types of memory. Memory devices generally refer to volatile memory technology. Volatile memory is memory whose state (and the data stored within it) is uncertain if power is interrupted. Non-volatile memory is memory whose state is deterministic even if power is interrupted. Dynamically volatile memory can refresh the data stored in the device to maintain its state. An example of dynamically volatile memory includes DRAM (Dynamic Random Access Memory) or variations thereof, such as, but not limited to, Synchronous DRAM (SDRAM). The memory subsystem described in this article is compatible with a variety of memory technologies, such as, but not limited to, DDR3 (Double Data Rate version 3, originally released by JEDEC (Joint Electron Device Engineering Committee) on June 27, 2007, currently version 21), DDR4 (DDR version 4, initial specification released by JEDEC in September 2012), DDR4E (DDR version 4, extended version, currently under discussion by JEDEC), LPDDR3 (Low Power DDR version 3, JESD209-3B, released by JEDEC in August 2013), and LPDDR4 (Low Power Double Data Rate (LPDDR) version 4). JESD209-4 (originally released by JEDEC in August 2014), WIO2 (Wide I / O2), JESD229-2 (originally released by JEDEC in August 2014), HBM (High Bandwidth DRAM), JESD235 (originally released by JEDEC in October 2013), DDR5 (DDR version 5, currently under discussion by JEDEC), LPDDR5 (currently under discussion by JEDEC), HBM2 (HBM version 2, currently under discussion by JEDEC) or combinations of other memory technologies, as well as technologies derived from or extended based on such specifications.

[0235] In addition to or as an alternative to volatile memory, in one embodiment, a reference to a memory device may refer to a non-volatile memory device whose state is deterministic even when power is interrupted. In one embodiment, a non-volatile memory device is a block-addressable memory device, such as, but not limited to, NAND or NOR technology. Therefore, the memory device may also include future-generation non-volatile devices, such as, but not limited to, three-dimensional cross-point (3DXP) memory devices, other byte-addressable non-volatile memory devices, or memory devices using chalcogenide phase change materials (e.g., chalcogenide glasses). In one embodiment, the memory device may be or include multi-threshold NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM) or switched phase change memory (PCMS), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) incorporating memristor technology, or spin-transfer torque (STT)-MRAM, or any combination of the foregoing, or other memories.

[0236] In at least one embodiment, system 1700 may include one or more circuits for executing one or more instructions or otherwise performing any operation described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. One or more circuits may be software-configured to execute one or more instructions or perform any operation described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0237] Figure 18An accelerated processing unit 1800 according to at least one embodiment is illustrated. The accelerated processing unit 1800 may include a processor based on the CDNA architecture of AMD Inc., Santa Clara, California, or other processors sharing at least some of the components described herein. The accelerated processing unit 1800 may include one or more accelerator complex dies (XCDs) 1804 for performing the operations described elsewhere in this document, such as, but not limited to, graphics processing and / or parallel processing and instruction-level parallel computing, including support for multiple precisions (INT8, FP8, BF16, FP16, TF32, FP32, and FP64) and sparse matrix data (i.e., sparsity). In some cases, the XCD may be referred to as a graphics computing die (GCD). The accelerated processing unit 1800 may include one or more complex computing dies (CCDs) 1806 for performing the operations described elsewhere in this document, such as, but not limited to, operations performed by a host processor. In some cases, the CCD may be referred to as a core complex or CCX, such as, but not limited to, the CCX used in AMD Ryzen processors. XCDs and CCDs can share any type of cache or memory (e.g., one or more memory cells 1802), or a cache or memory can be allocated to each XCD or CCD or group of XCDs or CCDs. For example, AMD Infinity Fabric within the package connects XCDs and CCDs to a shared AMD Infinity Cache 1808, and in some embodiments, to high-bandwidth memory (e.g., HMB3). Accelerated processing unit 1800 may include an AMD MI300a processor comprising three CPU die (or CCD) and six accelerator die (XCD) on top of four input-output dies (IODs) that may be layered on a single silicon die (e.g., via AMD Infinity Fabric) and linked together to eight high-bandwidth DRAM stacks in a ring to form a superchip. For systems using only accelerators, the AMD MI300x processor replaces the CCD with two or more XCDs.

[0238] Accelerated processing unit 1800 may include one or more input / output (I / O) interfaces. For example, XCD 1804 and CCD 1806 may coexist on one or more input-output dies (IODs) 1810, which may include one or more I / O interfaces. IOD 1810 may include any number and type of I / O interfaces (e.g., PCI, PCI expansion (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). Various types of peripheral devices may be coupled to I / O interface 1870. The I / O interfaces of IOD 1810 may also be used to connect one or more accelerated processing units 1800, for example, in a server architecture.

[0239] Accelerated processing unit 1800 may include one or more memory units 1802 for storing instructions and other information for performing the operations described in other parts of this document. Memory units 1802 may include any volatile memory, such as, but not limited to, the memory types described in other parts of this document, and may include, for example, high-bandwidth memory (e.g., HMB3) or high-bandwidth DRAM. The memory associated with accelerated processing unit 1800 (e.g., memory unit 1802) may include system memory, which can be used for, for example, commands, instructions, and constants, as well as input and output. Memory unit 1802 may also include device memory, which can be used for storage and, for example, for commands, instructions, and constants, as well as input and output, as a return buffer, and for private data. Memory unit 1802 may be linked to one or more IODs 1810. In at least one embodiment, L1 cache 1820 initiates a memory hierarchy including a shared L2 cache 1828 (e.g., within an XCD). AMD Infinity Cache TM It is the last-level cache (LLC) located on the active I / O die (IOD). The CCD 1806 and XCD1804 can have independent or shared memory. AMD Infinity architecture and AMD Infinity Fabric TM The technology enables consistent, high-throughput unification of GPU and CPU chip technologies (such as XCD, CCD, and / or CCX) with memory (such as stacked HBM3 memory) in a single device and across multiple device platforms.

[0240] like Figure 18As shown, the XCD 1804 may include a set of shared global resources 1830, which may include a hardware scheduler 1832 and an asynchronous compute engine (ACE) 1824. The ACE 1824 sends tasks (e.g., compute shader workgroups) to compute units (CUs or cores) 1834. Each of the ACEs 1824 (e.g., four) may be associated with a CU 1834 (e.g., 40 CUs), and some CUs 1834 may be disabled for yield management. CUs 1834 may have dedicated caches or shared caches (e.g., L2 caches) 1828 for consolidating all memory traffic on a single die. CU1834 may include threaded and parallel processor cores, including instruction fetching and scheduling using a scheduler (S) 1812, a matrix core unit (MCU) 1816, and a shader core (SC) 1818 (e.g., execution units for scalar, vector, and matrix data types), and a load / store pipeline with an L1 cache 1820 and a local data share (LDS) 1814. The local data share may include, for example, a sticky-note RAM with built-in arithmetic capabilities, allowing data sharing between threads in a workgroup. An instruction cache 1840 (e.g., for storing and providing instructions for performing the operations described elsewhere in this document) and a constant cache 1838 may be connected to one or more CUs and may be shared between two CUs. The matrix core 1816 can handle various data types, such as, but not limited to, INT8, FP8, FP16, BF16, and TF32 data types. Accelerated processing unit 1800 may include computation units 1834, which may be arranged in an array format, such as as a data parallel processor (DPP) array. The hyper-threaded dispatch processor 1842 can communicate with the compute unit 1834, and the command processor 1844 can read commands written by the host to memory-mapped registers in the system memory address space (not shown). When a command is completed, the command processor 1844 can send a hardware-generated interrupt to the host processor (e.g., a CCD). The memory controller 1836 can also directly access all device memories and system memory regions specified by the host. To satisfy read and write requests, the memory controller 1836 can perform the functions of a direct memory access (DMA) controller, including calculating the memory address offset based on the format of the requested data in memory. For example, one or more APIs described herein can be compiled into instructions that can be stored in the instruction cache 1840, then fetched by the instruction fetch logic in the processor 1840, decoded by the processor decoder or equivalent, scheduled (e.g., sequentially or out of order) by the scheduler or equivalent for execution, executed by the execution logic or equivalent, reordered, and then retired by the retirement logic or equivalent.The API (and / or compiled instructions including the API) can be stored in any storage device, either inside or outside the processor 1800 (e.g., in a cache and / or memory). The results of the API can be stored in storage devices, either inside or outside the processor 1800, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents.

[0241] Applications may include programs running on the main processor (e.g., a CCD) and programs running on one or more XCDs (referred to as kernels). Programs can be controlled by host commands that set internal base addresses and other configuration registers, specify data fields on which the accelerator processing unit 1800 can run, invalidate and flush caches on the accelerator processing unit 1800, and cause the accelerator processing unit 1800 to begin executing a program. A kernel can be referred to as a program executed by the accelerator processing unit 1800. Kernels can execute independently on each work item or as a group of work items, referred to as a wavefront, which can execute kernels on all (e.g., 64) work items in a single pass. The computation unit 1834 may include: a scalar arithmetic logic unit (ALU) that can operate on a single value for each wavefront (shared by all work items); a vector ALU that can operate on a unique value for each work item; a local data share 1814 that allows work items within a workgroup to communicate and share data; a scalar memory (not shown) that can transfer data between the scalar general-purpose registers (SGPRs) and memory via cache; and a vector memory that can transfer data between the vector general-purpose registers (VGPRs) and memory, including sampling texture maps. Kernel control flow can be manipulated using scalar ALU instructions, which may include if / else statements, branches, and loops. Scalar ALU (SALU) and memory instructions can operate on the entire wavefront and operate on one or more SGPRs. Vector memory and ALU instructions can operate on all work items in the wavefront simultaneously.

[0242] In at least one embodiment, the accelerated processing unit 1800 may include one or more circuitry configured to execute one or more instructions or otherwise perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The one or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0243] Figure 19Processor 1900 is shown, including, but not limited to, a Zen architecture-based processor (e.g., Zen1, 2, 3, 4, 5, or other architectures) from AMD Inc. of Santa Clara, California, or other processors that share at least some of the components described herein. Processor 1900 includes one or more CPU dies 1902(1)-1902(N), where N is any integer greater than 1. CPU die 1902 may include any number of processor cores 1916 (e.g., for performing any operations described elsewhere herein) and any number of cache memories (e.g., for storing instructions and other information to perform any operations described elsewhere herein). For example, L2 cache unit 1918 may be coupled to processor core 1916, and processor core 1916 may share and / or be individually coupled to L2 cache unit 1918. Processor core 1916 can be coupled to L3 cache 1922 and / or a shared L3 cache, which can be the lowest level cache (LLC) 1922 used to access data and other information used by processor core 1916. One or more processor cores 1916 and one or more L2 cache units 1918 can be included in a core complex (CCX) 1920, which can include (e.g., 32MB) a shared cache (e.g., L3 cache 1922). Core complex 1920 can be manufactured onto a die (CCD or CPU die) 1902. For example, up to 12 core complexes 1920 can be configured in a processor along with 8 CPU dies 1902, providing up to 96 processor cores 1916 for processor 1900. For example, a "Zen 4c" core complex 1920 can include up to 8 cores 1916 and a shared 16MB L3 cache 1922. Two core complexes from these core complexes 1920 can be combined onto a single CPU die 1902, resulting in 16 cores per die and a total of 32MB of L3 cache per die 1922. Up to eight CPU dies 1902 can be combined with I / O units 1904 to provide up to 128 processor cores 1916 for the CPU. Up to four "Zen 4c" dies mentioned above can be combined to provide up to 64 processor cores 1916 for the CPU.

[0244] Processor 1900 may include various configurations for input / output operations, which will be further described herein. I / O unit 1904 may include one or more memory controllers 1906 capable of managing the memory usage of processor 1900 (e.g., DDR5 memory). I / O unit 1904 may include one or more SATA disk controllers for managing storage device 1912, and one or more Compute Express Links (CXL) for providing CPU-to-device and CPU-to-memory connectivity, which can be flexibly assigned to specific functions during server design. TM 1.1+ Memory controller 1914. I / O unit 1904 may include PCIe controller 1908 for connecting peripherals and other components connected to processor 1900. I / O unit 1904 may also include USB port 1910 for connecting to other components separate from processor 1900. CPU die 1902 may support any number of connections to I / O unit 1904, for example, one or two connections. As shown, I / O unit 1904 may include components further described herein, and I / O unit 1904 may be an I / O die accommodating several different components. Memory controller 1906, PCIe controller 1908, USB port 1910, SATA controller 1912 and / or CXL controller 1914 may be individually integrated into any location within processor 1900, or integrated in any group or combination.

[0245] Processor 1900 may include an Infinity Fabric 1924 interconnect (which may be similar to or based on a PCIe architecture) that provides connectivity between the CPU (e.g., CPU dies 1902(1)-1902(N)), graphics processor 1926, inference engine 1932, and other components in a multi-chip architecture (e.g., security processor 1928 and I / O unit 1904). One or more AMD Infinity Fabrics TM Interconnect 1910 can be connected to CPU dies 1902(1)-1902(N) and used as a connection between CPUs. One or more Infinity Fabric connections 1910 can connect each CPU die 1902 to the I / O unit 1910.

[0246] In at least one embodiment, processor 1900 may include a central processing unit (CPU) and other related hardware and software described above and further herein. Processor 1900 may also include a graphics processor 1926. Graphics processor 1926 may be used for image generation and processing, as well as other computations and operations described further herein. Graphics processor 1926 may be based on AMD's RDNA 3 or 3.5 architecture, located in Santa Clara, California. Graphics processor 1926 may include a graphics computing die (GCD) and a memory cache die (MCD). The GCD may include any number of computing units (CUs) for graphics or other processing, such as operations performed by an arithmetic logic unit (ALU) described further herein. Graphics processor 1926 may include an L2 cache available for use by the computing units. The MCD (not shown) may include any number of memory cells and may include a cache (e.g., an L3 cache) and a memory interface for coupling to memory (e.g., memory 1942(1)-(N), where N is an integer). Components within the graphics processor 1926 can be connected using various methods, such as using Infinity Fabric 1924 interconnects, either internally or externally to the graphics processor 1926.

[0247] Inference engine 1932 can provide neural processing capabilities to processor 1900 for computational processes used in neural networks, deep learning, and other artificial intelligence-related operations, which will be further described herein. Processor 1900 may include: a security processor 1928 for managing the security of processor 1900; a display controller 1930 for controlling the display; a system management unit 1934 for managing and operating some or all components on processor 1900; a multimedia engine 1936 for audio and video operations; a fusion controller hub 1938 for managing USB, SATA, and PCIe connections to the processor; and a sensor fusion hub 1940 for managing sensors (e.g., accelerometers). Processor 1900 may also include memory 1942(1)-(N), where N is any integer. Memory may include different memory types, such as LPDDR5 and / or DDR5, or other memory described elsewhere herein.

[0248] To perform the operations further described herein, processor 1900 may include an execution pipeline including a front end that may include a cache for storing instructions (e.g., an L1 cache) (not shown). A branch predictor may modify the instruction stream. Instructions may be decoded by a decoder, dispatched to a back end for execution, and renamed. For example, the instruction fetch and decode pipeline may be dispatched to integer or floating-point execution operations, which may be scheduled by a scheduler and passed to vectors and / or general-purpose registers. Floating-point multipliers and / or addition operations may be processed, and an arithmetic logic unit (ALU) may also be used to perform computations, such as arithmetic and logical operations. The output of the computation unit may be coupled to a load / store queue that may be connected to a cache, such as an L1 cache and / or an L2 cache.

[0249] With respect to processor 1900 and any components described above or elsewhere herein, one or more APIs or equivalents described herein may be compiled, for example, into instructions or equivalents (e.g., AVX-512 instructions based on a SIMD model). These instructions or equivalents may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device (e.g., cache and / or memory) internal or external to processor 1900. The results of the APIs may then be stored in storage devices internal or external to processor 1900, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents.

[0250] In at least one embodiment, processor 1900 may include one or more circuitry configured to execute one or more instructions or otherwise perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. One or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0251] Figure 20 An example of a processing core 2000 is shown, which may implement an Arm architecture (e.g., v9.0-A) or other processors that share at least some of the components described herein. NeoverseTM The V2 Core 2000 can be implemented within a DynamIQ shared unit (DSU) cluster via a DSU-110 interconnect 2054 for connecting one or more cores, for example, for parallel processing. Neoverse TM The V2 core can be implemented as a single core in a DSU cluster configured for direct interconnection, with or without L3 cache, listener filter, or listener control unit (SCU) logic (not shown). Neoverse TMThe V2 core may include a CPU bridge 2052 for connecting core 2000 to the DSU-110 interconnect. This bridge may also connect core 2000 to an external memory system and the remainder of the on-chip system. The L1 instruction memory system 2002 may fetch instructions from instruction cache 2004 and deliver instructions (e.g., one or more compileable APIs described herein) to instruction decoding unit 2010, for example, to perform some or all of the operations described above or elsewhere herein. The L1 instruction memory system 2002 may include L1 instruction cache 2004 (e.g., with 64-byte cache lines), L1 instruction translation back buffer (TLB) 2006 (e.g., natively supporting 4KB, 16KB, 64KB, and 2MB page sizes), and macro operation cache (MOP) 2008 (e.g., a 1536-entry, 4-way skew-associated L0 MOP cache), which may include decoded and optimized instructions for higher performance. Instruction decoding unit 2010 may decode AArch64 instructions into its internal format. The register renaming unit 2012 can perform register renaming to facilitate out-of-order execution and dispatch decoded instructions to various issue queues. The instruction issuing unit 2014 can control when decoded instructions are dispatched to the execution pipeline, and it can include an issue queue for storing instructions to be dispatched to the execution pipeline. The integer execution pipeline 2016 can be included in the execution pipeline and includes an integer execution unit 2018 that can perform arithmetic and logical data processing operations. The vector execution unit 2020 can be included in the execution pipeline and can execute advanced SIMD and floating-point arithmetic (FPU) 2022, execute Scalable Vector Extension (SVE) and Scalable Vector Extension 2 (SVE2) instructions 2024, and can also selectively execute cryptographic instructions 2026. Advanced SIMD may include a media and signal processing architecture that primarily adds instructions for audio, video, 3D graphics, image, and speech processing. The floating-point architecture provides support for single-precision and double-precision floating-point operations. The L1 data memory system 2030 executes load and store instructions, as well as service memory coherence requests. The L1 data memory system 2030 may include an L1 data cache 2032 and a fully associative L1 data TLB 2034, natively supporting 4KB, 16KB, and 64KB page sizes and 2MB and 512MB block sizes. The memory management unit (MMU) 2028 provides fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes, which can be stored in a translation table and saved to the TLB 2034 after address translation. The L2 memory system 2036 may include an L2 cache 2038 and can be connected to the DSU-110 2054 via an asynchronous CPU bridge 2052. TMThe V2 core 2000 supports a range of debugging, testing, and tracing options, including the tracing unit 2042, the tracing buffer 2040, and the embedded logic analyzer (ELA) 2048. Neoverse TM The V2 core 2000 implements the Statistical Analysis Extension (SPE) 2044, which provides a statistical view of the performance characteristics of executed instructions. Software writers can leverage these views to optimize code for better performance. The Performance Monitoring Unit (PMU) 2046 provides a performance monitor that can be configured to collect statistics on the operation of each core and memory system. This information can be used for debugging and code analysis. The General Purpose Interrupt Controller (GIC) CPU interface 2050, when integrated with external allocator components, serves as a resource for supporting and managing interrupts in a cluster system. In a cluster, each Neoverse... TM There can be a CPU bridge 2052 between the V2 core 2000 and the DSU-110 2054. The CPU bridge 2052 can control the buffering and synchronization between the core 2000 and the DSU-110 2054. The CPU bridge 2052 can be asynchronous to allow each core 2000 to use a different frequency, power, and area implementation point. The CPU bridge 2052 can operate synchronously without affecting other interfaces, such as, but not limited to, asynchronous debug and tracing interfaces.

[0252] In at least one embodiment, core 2000 may include one or more circuitry for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. One or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0253] Figure 21 One or more chips including one or more tensor processing units (TPUs) 2100 are shown according to at least one embodiment. Figure 21The TPU 2100 may include an application-specific integrated circuit (ASIC), for example, for performing some or all of the operations described above or elsewhere herein, such as, but not limited to, machine learning workloads that accelerate the execution of matrix operations. The TPU 2100 may be an ASIC from Alphabet Corporation, Mountain View, California. The cloud TPU includes a cloud service that enables the TPU to be used as a scalable resource for processing tasks, such as, but not limited to, machine learning workloads that can run on frameworks such as, but not limited to, TensorFlow, PyTorch, and JAX.

[0254] Chip 2100 may include any number of TPUs, which may include tensor cores 2106. Tensor cores 2106 may include one or more core sequencers 2108, vector processing units (VPUs) 2110, matrix multiplication units (MXUs) 2112(A)-2114(N) (where N is any integer greater than 1), and transpose permutation units 2116. Core sequencer 2108 may fetch instructions (e.g., VLIW (Very Long Instruction Word)) from the instruction memory (Imem) of core 2106, perform scalar operations using scalar data memory (Smem) and scalar registers (Sregs) (not shown), and forward vector instructions to vector processing units (VPUs) 2110. For example, an instruction may initiate eight operations: two scalar operations, two vector ALU operations, vector loading and storing, and queuing data into matrix multiplication and transpose units and a pair of slots for queuing data from them. The VPU 2110 can perform vector operations using a large on-chip vector memory (Vmem) and vector registers (Vregs). The VPU 2110 can stream data to or from the MXU via a decoupled FIFO. The VPU 2110 can collect and distribute data to the Vmem using both data-level parallelism (2D matrix and vector function units) and instruction-level parallelism (8 operations per instruction). Large two-dimensional matrix multiplication units (MXUs) 2112(A)–2112(N) can, for example, use a systolic array to reduce area and power consumption, and use a large, software-controlled on-chip memory instead of a cache. The transpose-reduction-permute unit 2116 can perform (e.g., 128x128) matrix transpose, reduction, and permute on the VPU 2110 channels. A high-bandwidth memory 2104 can be used for on-chip applications and can be coupled to a host queue 2102, for example, via PCIe. One or more chips 2100 can be connected together for computing. For example, one or more chips 2100 can be connected to form a torus, such as a 2D torus. Chips 2100 may also include any number (e.g., four) of inter-core interconnect (ICI) links 2118, which can enable direct connections between chips to form a supercomputer.

[0255] For any processor in chip 2100 and any components described above or elsewhere herein, one or more APIs or equivalents described herein may, for example, be compiled into instructions or equivalents that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device (e.g., cache and / or memory) external to or internal to any processor in chip 2100. The results of the APIs may then be stored in any storage device internal to or external to any processor in chip 2100, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents.

[0256] In at least one embodiment, chip 2100 may include one or more circuits for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. One or more circuits may be software configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0257] Figure 22A vector processor according to at least one embodiment is illustrated. The vector processor 2200 may support the RISC-V standard. The vector processor 2200 may include one or more cores 2210 (e.g., scalar units) and one or more vector processing units (VPUs) 2242 (e.g., vector units), which may, for example, perform some or all of the operations described above or elsewhere herein. The core 2210 may include an Andes Custom Extension (ACE) 2216, which can be used, for example, to deliver custom instructions to the processor 2200 via an ACP 2238. The core 2210 may include a 1-cycle multiplier and a 1-cycle instruction / data local memory (ILM / DLM) for improving parallelism by allowing simultaneous instruction fetching and data access. A memory management unit (MMU) 2224 manages system memory and cache, and provides branch execution, instruction pair issuance, L1 instruction / data cache, and local memory storage. The core 2210 may include a physical memory protection and programmable physical memory attribute unit (PMP / PPMA) 2222. Core 2210 may include a digital signal processor (DSP) 2228 and a floating-point unit (FPU) 2226, as well as a load-memory unit (LSU) 2232 for interaction with memory hierarchies (D$2234 and I$2230). Core 2210 may include a branch prediction unit 2218 and a multiplier unit 2220.

[0258] The vector processing unit (VPU) 2242 may include one or more vector function units (FU) 2246(A)-2246(N) (these vector function units may be linked together for parallel processing), a separate memory path for loading / storing RISC-V vectors (RVVs) via the ACE-RVV 2248 and the AndesStreaming port (ASP) 2244, and a vector load / store unit (VLSU) 2250.

[0259] Vector processor 2200 may include bus interfaces, such as, but not limited to, a cache-accessible L2 cache port 2256, a non-cache-accessible MMIO port 2254, an input-output coherence port (IOCP) 2258 for a cacheless bus master, a local memory access port for accessing ILM / DLM 2212 (which can be coupled to SRAM 2206) and high-bandwidth vector memory (HVM) 2236, and a shared peripheral port (SPP) 2252 for external peripherals. Other memory ports include an LM slave port AXI 2202, an HVM subordinate port AXI 2204, a MEM (AXI) 2262, and an AXI 2260. The trace I / F 2214 can be captured, encoded, and transmitted off-chip via the Inst. trace I / F 2208 (e.g., a record of executed processor instructions). Software tools can use the Inst. trace I / F 2208 to reconstruct the exact execution sequence of a program.

[0260] For any processor in processor 2200 and any components described above or elsewhere herein, one or more APIs or equivalents described herein may, for example, be compiled into instructions or equivalents that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device external to or internal to processor 2200 (e.g., in cache and / or memory). The results of the APIs may then be stored in storage devices internal to or external to processor 2200, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents.

[0261] In at least one embodiment, the vector processor 2200 may include one or more circuitry configured to execute one or more instructions or otherwise perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The one or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0262] Figure 23AA schematic diagram of an example multi-core tiled processor microarchitecture is shown. Figure 23A Multi-core tiled processors in a system can include language processing processors. For example... Figure 23A As shown, each “tile” in the processor architecture is a processing element bundled together using an on-chip network (NoC), which can be used to perform some or all of the operations described above or elsewhere in this document. For example, each tile may have an instruction dispatch 2304 and integer (INT) units 2306 and floating-point (FP) units 2308, a load-memory unit (LSU) 2312 for engaging with a memory hierarchy (data cache (D$) 2310 and instruction cache (I$) 2314), and a network (NET) interface 2316 for communicating with other tiles. Some tiles in processor 2300 may include a memory controller 2302 for managing and controlling memory, as further described herein. Processor 2300 may have a functionally sliced ​​architecture. Processor 2300 may reside on an application-specific integrated circuit (ASIC). Figure 23A The layout of an ASIC can be represented. Processor 2300 may include a coprocessor designed to execute instructions for a predictive model. A predictive model refers to any model configured to make predictions based on input data. The predictive model can use a classifier for classification predictions. The predictive model can be a machine learning model, such as, but not limited to, a tensor flow model, and processor 2300 is a tensor flow processor.

[0263] The processor 2300 can use different microarchitectures, and these microarchitectures will Figure 23B Each tile in the process represents a separate functional unit. Conversely, the functional tiles 2324 of the processor 2300 can be aggregated into multiple functional processing units (hereinafter referred to as "slices") 2304, each corresponding to a specific functional type (e.g., FP / INT 2318, NET 2320, MEM 2322). For example, as... Figure 23B As shown, each slice may correspond to a row of functional tiles extending in a north-south direction. Furthermore, the processor 2300 may also include communication channels for carrying data between tiles in different slices, each communication channel extending horizontally in an east-west direction. Each communication channel may be connected to each slice 2304 of the processor 2300.

[0264] The slices 2304 of processor 2300 may each correspond to different functions and may include arithmetic logic slices (e.g., FP / INT 2318), channel switching slices (e.g., NET 2320), and memory slices (e.g., MEM 2322). Arithmetic logic units can perform one or more arithmetic and / or logical operations on data received via communication channels to generate output data. Examples of arithmetic logic units may be matrix multiplication units and vector multiplication units. Memory slices include memory units that store data. Memory slices can provide data to other slices via communication channels. Memory slices can also receive data from other slices via communication channels. Channel switching slices can configurably route data from one communication channel to any other communication channel. For example, data from a first channel can be provided to a second channel via a channel switching slice. In some embodiments, a channel switching slice can be implemented as a crossbar switch. Each slice 2304 also includes its own instruction queue (not shown) for storing instructions and an instruction control unit (ICU) for controlling instruction execution. Instructions in a given instruction queue can only be executed by a tile in its associated functional slice and not by other slices of processor 2300.

[0265] By arranging the tiles of processor 2300 into different functional slices 2304, the on-chip instruction and control flow of processor 2300 can be separated from the data flow. For example, according to some embodiments, Figure 23B One of the arrows illustrates the instruction flow within the processor architecture. According to at least one embodiment, Figure 23B Another arrow in the diagram illustrates the data flow within the processor architecture. As shown, instruction and control flow can flow across the tiles of processor 2300 in a first direction (e.g., north-south along the length of a functional slice, as indicated by the first arrow), while data flow can flow across the tiles of processor 2300 in a second direction (e.g., east-west across a functional slice, as indicated by the second arrow), which is perpendicular to the first direction.

[0266] Different functional slices of processor 2300 can correspond to MEM 2322 (memory), VXM (vector execution module), MXM (matrix execution module), NIM (numerical interpretation module), and SXM (swapping and permutation module). Each slice can include N tiles, all of which can be controlled by the same instruction control unit (ICU) (not shown). Each slice can operate completely independently and can only be coordinated using barrier-like synchronization primitives or by the compiler using tractable determinism. Each tile of processor 2300 can correspond to an execution unit organized as ×MSIMD tiles. For example, each tile of the on-chip memory of processor 2300 can be organized to atomically store L-element vectors. Therefore, MEM slices with N tiles can work together to store or process large vectors (e.g., with a total of N×M elements).

[0267] Tiles within a slice can execute instructions in an "interleaved" manner, where instructions can be issued tile-by-tile within the slice over N cycle periods. Functional slices can be physically arranged on the chip to allow for efficient data flow for pipelined execution over hundreds of cycles for common patterns. The data flow can perform a single "u-turn" (direction change) corresponding to a single matrix operation before being written back to memory; in some embodiments, a particular data flow can change direction multiple times before writing the resulting data back to memory (due to multiple matrix and vector operations).

[0268] When using a processor 2300 with a function slice architecture (e.g., a TSP), the TSP compiler (not shown) generates an explicit plan of how the processor 2300 can execute programs (e.g., microprograms). The compiler can specify when each operation will be executed, which function slices will perform the work, and which STREAM registers will hold operands. The compiler can maintain a high-fidelity (cycle-accurate) model of the processor 2300 (e.g., the TSP) hardware state so that microprograms can coordinate data flow.

[0269] Processor 2300 (e.g., TSP) can use a web-hosted compiler that takes a model (e.g., an ML model, such as, but not limited to, a TensorFlow model) as input and issues a proprietary stream of instructions for processor 2300 (e.g., TSP). The compiler is responsible for coordinating the program's control and data flow and specifying any instruction-level parallelism by explicitly bundling instructions that can and should be executed concurrently so that they can be dispatched together. The main hardware architecture includes an architecture-visible streaming register file (STREAM), described in more detail below, which acts as a conduit for operands to flow from MEM slices (e.g., SRAM) to functional slices (and vice versa).

[0270] The MEM 2322 of the processor 2300 can be used as: (1) a storage for model parameters, microprograms, and data on which they operate; and (2) an on-chip network (NoC) for transferring data operands from the MEM to functional slices and returning computation results to the MEM. In some embodiments, the on-chip memory may consume approximately 75% of the chip area of ​​the processor 2300. In some embodiments, the on-chip memory of the MEM tile may include SRAM instead of DRAM due to the bandwidth requirements of the processor 2300. The on-chip memory capacity of the processor 2300 may be determined by: (i) the number of ML models that can reside on the chip simultaneously, (ii) the size of any given model, and (iii) partitioning of large models for adaptation to a multi-chip system. In some embodiments, the MEM system of the processor 2300 may provide multiple memory slices organized into two distinct hemispheres (referred to as “MEM WEST” and “MEM EAST”, respectively).

[0271] The memory slices in each hemisphere can be mirrored, such that the slices are physically numbered {0,...L} in the eastern hemisphere and {L,...0} in the western hemisphere, such that memory slice 0 in each hemisphere corresponds to the slice of the VXM slice closest to the hemisphere, where each hemisphere comprises L slices. Data transfer towards the chip center can be referred to as inward, while data transfer towards the outer edge of the chip (easternmost or westernmost) can be referred to as outward. Although the memory hemispheres of processor 2300 can be referred to as east and west, it is understood that other names may be used to refer to different memory hemispheres in other embodiments.

[0272] In some embodiments, streaming register files (referred to as STREAMS) transfer operands and results between the SRAM of the MEM slices of the processor 2300 and the functional slices. In some embodiments, multiple MEM slices (e.g., 2 to 10 adjacent MEM slices) can be physically organized into sets. Each slice set can be located between a pair of STREAMS register files, allowing each slice to read from or write to the STREAMS registers in either direction. By placing the STREAMS register files between sets of MEM slices, the number of cycles required to transfer data operands across hemispheres can be reduced (e.g., reduced by a factor corresponding to the number of slices per set). The number of slices per set can be configured based on the distance of data transfer within a single clock cycle.

[0273] for Figure 23AAny processor and any components described above or elsewhere herein, one or more APIs or equivalents described herein may, for example, be compiled into instructions or equivalents that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. The API (and / or compiled instructions including the API) may be stored in any storage device internal or external to processor 2300 (e.g., in cache and / or memory). The results of the API may then be stored in storage devices internal or external to processor 2300, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents.

[0274] In at least one embodiment, processor 2300 may include one or more circuitry configured to execute one or more instructions or otherwise perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. The one or more circuitry may be software-configured to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0275] Software Structure

[0276] The following figures illustrate, in a non-limiting manner, examples of software structures for implementing at least one embodiment.

[0277] Figure 24 A software stack of a programming platform according to at least one embodiment is illustrated. The programming platform may include a platform for accelerating computational tasks by utilizing hardware on a computing system. In at least one embodiment, software developers can access the programming platform through libraries, compiler instructions, and / or extensions to programming languages. The programming platform may be CUDA, Radeon Open Computing Platform (“ROCm”), OpenCL (OpenCL... TM Developed by the Khronos Group), SYCL, or Intel OneAPI.

[0278] The software stack 2400 of the programming platform can provide an execution environment for the application 2401. The application 2401 may include any computer software that can be launched on the software stack 2400. The application 2401 may include artificial intelligence (“AI”) / machine learning (“ML”) applications, high-performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0279] Application 2401 and software stack 2400 run on hardware 2408. Hardware 2408 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices supporting programming platforms. Software stack 2400 may be vendor-specific and compatible only with vendor-specific devices, such as CUDA, ROCm, OneAPI, OpenCL, or other implementations. Hardware 2408 may include a host connected to one or more devices that can be accessed via application programming interface (“API”) calls to perform computational tasks. In at least one embodiment, the devices within hardware 2408 may include GPUs, FPGAs, AI engines, or other computing devices (but may also include CPUs) and their memory, while the host within hardware 2408 may include CPUs (but may also include computing devices) and their memory. For any hardware 2408 described above or elsewhere herein, the one or more APIs described herein may, for example, be compiled into instructions that may be fetched by instruction fetching logic, decoded by a processor decoder, scheduled (e.g., sequentially or out of order) for execution by a scheduler, executed by execution logic, reordered, and then retired by retirement logic. The API (and / or compiled instructions including the API) may be stored in any storage device (e.g., cache and / or memory) internal or external to the hardware 2408. The results of the API may be stored in storage devices internal or external to the hardware 2408, including registers, DRAM, flash memory, SRAM, cache, or other memory. One or more APIs described herein may receive calls. One or more APIs described herein may communicate with a library or a portion of a library to perform the function described by the call. One or more APIs described herein may receive calls and communicate with a library or a portion of a library to perform the function described by the call.

[0280] The software stack 2400 of the programming platform may include multiple libraries 2403, a runtime 2405, optional drivers / interfaces 2407, and device kernel drivers 2408. Each library 2403 may include data and programming code that can be used by computer programs and utilized during software development. Library 2403 may include pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. Library 2403 may include functionality optimized for execution on one or more types of devices. Library 2403 may include functionality for performing mathematical, deep learning, and / or other types of operations on the device. Library 2403 may be associated with corresponding APIs 2402, which may include one or more APIs for exposing the functionality implemented in library 2403. A processor (e.g., CPU, GPU) may execute, call, or otherwise use one or more APIs to determine kernel priority. For example, a first kernel (e.g., a parent kernel) may launch a second kernel (e.g., a child kernel), and the processor may use the second kernel to launch an additional kernel (e.g., a grandchild kernel) independent of the first kernel. The processor can execute APIs or call APIs from memory to support dynamic stream priorities (e.g., updating priorities when performing operations using streams). For example, when the processor executes the API, it allows the programmer to copy stream priorities from one stream to one or more other streams.

[0281] Software stack 2400 may include APIs that support dynamic stream prioritization (e.g., updating priority while performing operations on the stream), allowing programmers to set the stream's priority at any time after the stream is created. Software stack 2400 may include APIs that support dynamic stream prioritization (e.g., updating priority while performing operations on the stream), allowing programmers to obtain the stream's current priority, where the priority is one of several attributes of the stream. Software stack 2400 may include APIs that support dynamic stream prioritization (e.g., updating priority while performing operations on the stream), allowing programmers to obtain the stream's current priority as a single attribute. Software stack 2400 may include APIs that support dynamic stream prioritization (e.g., updating priority while performing operations on the stream), allowing programmers to start the kernel to perform operations on the stream at a set priority, which may be different from the stream priority. Software stack 2400 may include an API for indicating whether an object (e.g., a thread synchronization object, such as, but not limited to, a barrier) tracks whether all data movement operations of a set of threads running on the GPU have a specified state after a specified time period, wherein the specified state may be a state indicating that data has been moved and is ready for use, and is specified using expected parity values ​​as input to the API.

[0282] Software stack 2400 may include one or more APIs for updating the kernel. The processor may execute APIs or call APIs from memory to update existing APIs, thereby supporting a context-independent kernel. This allows programmers to add kernel nodes to a graph without a graph context, so that the graph context can be dynamically associated with the kernel at runtime. Software stack 2400 may include one or more APIs that allow programmers to obtain kernel identifiers and graph contexts as separate parameters from kernel nodes, thereby enabling parameter retrieval from both the kernel and the context-independent kernel. Software stack 2400 may include one or more APIs that use parallel processors (e.g., but not limited to one or more graphics processing units) to initiate task graphs (e.g., task graphs) and execute one or more task graphs (e.g., including one or more programs).

[0283] Software stack 2400 may include one or more APIs for associating one or more instructions with one or more memory sorting operations (e.g., but not limited to fence or memory barrier operations). Instructions may be associated with one or more domains, causing memory sorting operations to execute in association with one or more specific domains without interfering with instructions in other domains. APIs may indicate that a thread has reached (e.g., reached a thread synchronization barrier) or completed a certain phase of work associated with an asynchronous data movement operation on the GPU. Software stack 2400 may include one or more APIs that allow programmers to manually indicate an expected transaction count when a thread completes a certain phase of work; this transaction count can be used to update an object used to track whether all data movement operations for a set of threads have been completed.

[0284] Application 2401 can be written as source code and then compiled into executable code, as described below. Figure 25 and Figure 26 As discussed in more detail, the executable code of application 2401 can run, at least partially, within the execution environment provided by software stack 2400. During the execution of application 2401, code that needs to run on the device (rather than the host) may be encountered. In this case, runtime 2405 can be invoked to load and launch the required code on the device. Runtime 2405 can include any technically feasible runtime system capable of supporting the execution of application 2401.

[0285] Runtime 2405 can be implemented as one or more runtime libraries associated with the corresponding API (which is shown as API 2404). One or more such runtime libraries may include functions for memory management, execution control, device management, error handling, and / or synchronization, etc. Memory management functions may include functions for allocating, dealing with, and copying device memory, as well as functions for transferring data between host memory and device memory. Execution control functions may include functions for launching functions on the device (sometimes referred to as "kernels" when the function is a global function that can be called from the host) and setting attribute values ​​in buffers maintained by the runtime libraries so that a given function can be executed on the device.

[0286] The runtime library and the corresponding API 2404 can be implemented in any technically feasible manner. One (or any number) APIs can expose a set of low-level functions for fine-grained control of the device, while another (or any number) APIs can expose a set of high-level functions for such functions. High-level runtime APIs can be built on top of low-level APIs. One or more runtime APIs can be language-specific APIs, which can be layered on top of language-independent runtime APIs.

[0287] Optional drivers or interfaces 2407 can be implemented, for example, for CUDA and ROCm implementations, which will be described further below. Optional drivers / interfaces 2407 can be associated with optional driver or interface APIs, such as, but not limited to, CUDA and / or ROCm APIs.

[0288] One or more processors disclosed in the “processing system” may execute, access, or otherwise use the software stack 2400. For example, the system-on-a-chip 1100, parallel processor 1200, graphics multiprocessor 1234, processor 1300, processor 1400, accelerator 1500, neuromorphic processor 1605, supercomputer 1700, acceleration processing unit 1800, processor 1900, processor 2000, tensor processing unit 2100, processor 2200, and language processing unit 2300 may execute, use, call, or otherwise implement (e.g., by accessing memory) one or more APIs included in the software stack 2400.

[0289] Device kernel driver 2408 can be configured to facilitate communication with underlying devices. Device kernel driver 2408 can provide low-level functionality for APIs (such as, but not limited to, API 2404) and / or other software. Device kernel driver 2408 can be configured to compile intermediate representation (“IR”) code into binary code at runtime. For CUDA or other implementations (such as, but not limited to, ROCm, OneAPI, or OpenCL), device kernel driver 2408 can compile non-hardware-specific parallel thread execution (“PTX”) IR code into binary code for a specific target device at runtime (and cache the compiled binary code), which is sometimes referred to as “finalized” code. Doing so allows the finalized code to run on a target device that may not have existed when the source code was initially compiled into PTX code. Alternatively, device source code can be compiled into binary code offline without device kernel driver 2408 compiling the IR code at runtime.

[0290] Processors described elsewhere in this document (e.g., but not limited to) Figure 11-23B The processor (in the document) may include one or more circuitry for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. One or more circuitry may be configured by software (e.g., software stack 2400) to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0291] According to at least one embodiment, Figure 24 The software stack 2400 can execute in a CUDA implementation. The CUDA software stack 2400, on which application 2401 can be launched, may include CUDA libraries 2403, CUDA runtime 2405, CUDA driver 2407, and device kernel driver 2408. The CUDA software stack 2400 can execute on hardware (e.g., a graphics multiprocessor 1234), which may include a CUDA-enabled GPU developed by NVIDIA Corporation, located in Santa Clara, California.

[0292] Application 2401, CUDA runtime 2405, and device kernel driver 2408 can perform the functions described above and elsewhere in this document. CUDA driver 2407 may include a library (libcuda.so) that implements CUDA driver API 2406. Similar to CUDA runtime API 2404 implemented by the CUDA runtime library (cudart), CUDA driver API 2406 exposes functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. CUDA driver API 2406 differs from CUDA runtime API 2404 in that CUDA runtime API 2404 simplifies device code management by providing implicit initialization, context (similar to processes) management, and module (similar to dynamically loaded libraries) management. Compared to the high-level CUDA runtime API 2404, CUDA driver API 2406 can serve as a low-level API, providing finer-grained device control, especially in terms of context and module loading. CUDA Driver API 2406 can expose context management functions not exposed in CUDA Runtime API 2404. CUDA Driver API 2406 can also be language-agnostic, supporting technologies such as OpenCL in addition to CUDA Runtime API 2404. Furthermore, development libraries, including CUDA Runtime 2405, can be considered separate from driver components, including user-mode CUDA Driver 2407 and kernel-mode device driver 2408 (sometimes referred to as the "display" driver).

[0293] CUDA library 2403 may include mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which parallel computing applications (such as, but not limited to, application 2401) may utilize. CUDA library 2403 may include mathematical libraries, such as, but not limited to, the cuBLAS library (an implementation of the basic linear algebra subroutine (“BLAS”) for performing linear algebra operations), the cuFFT library (for computing the Fast Fourier Transform (“FFT”)), and the cuRAND library (for generating random numbers), etc. CUDA library 2403 may include deep learning libraries, such as, but not limited to, the cuDNN primitive library for deep neural networks and the TensorRT platform for high-performance deep learning inference, etc.

[0294] In at least one embodiment, the processor described elsewhere herein (e.g., but not limited to Figure) Figure 11-23BThe processor (in the document) may include one or more circuitry for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. One or more circuitry may be configured by software (e.g., software stack 2400) to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0295] According to at least one embodiment, Figure 24 The software stack 2400 can execute in the ROCm implementation. Application 2401 can be launched on the ROCm software stack 2400, which includes a language runtime 2403, a system runtime 2405, a thunk 2407, and a ROCm kernel driver 2408. The ROCm software stack 2400 executes on hardware 2409, which may include a ROCm-enabled GPU developed by AMD Inc. of Santa Clara, California.

[0296] Application 2401 is executable and can be combined with the above. Figure 24 Similar functionality to that discussed. Furthermore, the language runtime 2403 and system runtime 2405 can execute functions in conjunction with the above. Figure 24The discussed runtime 2405 has similar functionality. The difference between the language runtime 2403 and the system runtime 2405 is that the system runtime 2405 is a language-independent runtime that implements the ROCr System Runtime API 2404 and uses the Heterogeneous System Architecture (“HSA”) runtime API. The HSA runtime API may include a streamlined user-mode API that exposes interfaces for accessing and interacting with the AMD GPU, including functions for memory management, execution control via kernel architecture dispatch, error handling, system and agent information, and runtime initialization and shutdown. Unlike the system runtime 2405, the language runtime 2403 may be an implementation of the language-specific runtime API 2402, which sits in a layer above the ROCr System Runtime API 2404. The language runtime API may include the Heterogeneous Computing Portable Interface (“HIP”) language runtime API, the Heterogeneous Computing Compiler (“HCC”) language runtime API, or the OpenCL API, etc. HIP is an extension of the C++ programming language, offering a functionally similar version to the CUDA mechanism. Furthermore, the HIP runtime API can include features related to the above. Figure 24 The discussion covers functions similar to those in the CUDA runtime API, such as, but not limited to, memory management, execution control, device management, error handling, and synchronization.

[0297] The Thunk(ROCt)2407 can be interface 2406, which is used to interact with the underlying ROCm driver 2408. The ROCm driver 2408 can be the ROCk driver, a combination of the AMD GPU driver and the HSA core driver (amdkfd). The AMD GPU driver can be a device core driver developed by AMD for GPUs, performing functions similar to those described above. Figure 24 The device kernel driver discussed is similar to the 2409. An HSA kernel driver can be a driver that allows different types of processors to share system resources more efficiently through hardware features.

[0298] Various libraries (not shown) may be included in the ROCm software stack 2400 on top of the language runtime 2403, and provide integration with the above. Figure 24 The discussion focuses on functionality similar to CUDA library 2403. Various libraries can include mathematical libraries, deep learning libraries, and / or other libraries, such as, but not limited to, the hipBLAS library which implements functionality similar to CUDA cuBLAS, the rocFFT library for computing FFTs similar to CUDA cuFFT, etc.

[0299] Processors described elsewhere in this document (e.g., but not limited to) Figure 11-23BThe processor (in the document) may include one or more circuitry for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. One or more circuitry may be configured by software (e.g., software stack 2400) to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0300] According to at least one embodiment, Figure 24 The software stack 2400 can execute in an OpenCL implementation. The OpenCL software stack 2400, on which the application 2401 can be launched, may include the OpenCL framework 2403, the OpenCL runtime 2405, and a driver 2408. The OpenCL software stack 2400 can execute on non-vendor-specific hardware 2409. Because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required for interoperability with the hardware of those vendors.

[0301] Application 2401, OpenCL runtime 2405, device kernel driver 2408, and hardware 2409 can execute in combination with the above. Figure 24 Other implementations of the application 2401, runtime 2405, device kernel driver 2408, and hardware 2409 discussed have similar functionality. The application 2401 may also include an OpenCL kernel (not shown), whose code will execute on the device.

[0302] OpenCL can define a "platform" that allows a host to control devices connected to it. The OpenCL framework provides platform-level APIs and runtime APIs, shown as Platform API 2402 and Runtime API 2404, respectively. Runtime API 2404 uses contexts to manage kernel execution on devices. Each identified device can be associated with a corresponding context, which Runtime API 2404 uses to manage the device's command queue, program objects, kernel objects, shared memory objects, and so on. Platform API 2402 exposes functions that allow the use of device contexts to select and initialize devices, submit work to devices via command queues, and enable data transfer with devices. In addition, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions.

[0303] The OpenCL framework 2403 may also include a compiler (not shown). Source code can be compiled offline before application execution or online during application execution. Unlike CUDA and ROCm, OpenCL applications can be compiled online by a compiler representing any number of compilers that can be used to compile source code and / or IR code (e.g., but not limited to Standard Portable Intermediate Representation (“SPIR-V”) code) into binary code. Alternatively, OpenCL applications can be compiled offline before execution.

[0304] In at least one embodiment, the processor described elsewhere herein (e.g., but not limited to) Figure 11-23B The processor (in the document) may include one or more circuitry for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. One or more circuitry may be configured by software (e.g., software stack 2400) to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0305] According to at least one embodiment, the software may be supported by a programming platform configured to support various programming models, middleware and / or libraries, and frameworks that the application may rely on. The application may be an AI / ML application implemented using, for example, a deep learning framework (e.g., but not limited to, MXNet, PyTorch, or TensorFlow), which may rely on libraries such as, but not limited to, cuDNN, the NVIDIA Collective Communication Library (“NCCL”), and / or the NVIDIA Developer Data Loading Library (“DALI”) CUDA library to provide accelerated computation on the underlying hardware.

[0306] The programming platform can be a combination of the above. Figure 24The platform described is one of CUDA, ROCm, or OpenCL. The programming platform can support various programming models, which can be abstractions of the underlying computing system that allow the expression of algorithms and data structures. Programming models can expose features of the underlying hardware to improve performance. Programming models may include CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++AMP”), Open Multiprocessing (“OpenMP”), Open Accelerators (“OpenACC”), and / or Vulkan Compute.

[0307] Libraries and / or middleware can provide abstract implementations of programming models. Such libraries may include data and programming code that computer programs can use and leverage during software development. Such middleware may include software that provides services to applications beyond those offered by the programming platform. Libraries and / or middleware may include cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Furthermore, libraries and / or middleware may include the NCCL and ROCm communication collection library (“RCCL”) libraries that provide communication routines for GPUs, the MIOpen library for accelerating deep learning, and / or the Eigen library for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0308] Application frameworks may depend on libraries and / or middleware. Each application framework can be a software framework that provides a standard structure for implementing application software. Returning to the AI / ML example discussed above, AI / ML applications can be implemented using frameworks such as, but not limited to, deep learning frameworks like Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet.

[0309] In at least one embodiment, the processor described elsewhere herein (e.g., but not limited to) Figure 11-23B The processor (in the document) may include one or more circuitry for executing one or more instructions or otherwise performing any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions. One or more circuitry may be configured by software (e.g., the programming platform described herein) to execute one or more instructions or perform any of the operations described above or elsewhere herein, at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

[0310] Figure 25 The method for using at least one embodiment in the above is shown. Figure 24 The compiled code is executed on one of the programming platforms shown. Compiler 2501 is configured to receive source code 2500, compile source code 2500, and output executable file 2510. Compiler 2501 can be configured to convert source code 2500 into host executable code 2507 for execution on a host and device executable code 2508 for execution on a device. Source code 2500 can be compiled offline before executing the application or online during application execution. Source code 2500 can include code in any programming language supported by compiler 2501, such as, but not limited to, C++, C, Fortran, etc. Source code 2500 can be included in a single source file containing both host code and device code, indicating the location of the device code. The single source file can be a .cu file including CUDA code, or a .hip.cpp file including HIP code, or a file in other formats including both host code and device code. Alternatively, source code 2500 can include multiple source files instead of a single source file, with host code and device code separated into these files. Compiler 2501 includes or can access one or more libraries to identify API call sequences to execute a single fused API, wherein the single fused API is a combination of two or more APIs. In at least one embodiment, compiler 2501 may be an NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or an HCC compiler for compiling HIP code in .hip.cpp files, or other compilers.

[0311] Compiler 2501 can be configured to compile source code 2500 into host executable code 2507 for execution on a host and device executable code 2508 for execution on a device. The operations performed by compiler 2501 include parsing source code 2500 into an abstract system tree (AST), performing optimizations, and generating executable code. When source code 2500 comprises a single source file, compiler 2501 can separate the device code from the host code in that single source file, compile the device code and host code into device executable code 2508 and host executable code 2507 respectively, and link the device executable code 2508 and host executable code 2507 together to form a single file.

[0312] Compiler 2501 may include compiler front-end 2502, host compiler 2505, device compiler 2506, and linker 2509. Compiler front-end 2502 may be configured to separate device code 2504 from host code 2503 in source code 2500. In at least one embodiment, device code 2504 may be compiled by device compiler 2506 into device executable code 2508, which may include binary code or IR code as described above. Separately, host code 2503 may be compiled by host compiler 2505 into host executable code 2507. For other compilers such as NVCC (e.g., but not limited to oneAPI, ROCm, and OpenCL compilers), host compiler 2505 may be a general-purpose C / C++ compiler that outputs native object code, while device compiler 2506 may be a low-level virtual machine (“LLVM”) based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. For HCC, both host compiler 2505 and device compiler 2506 may be LLVM based compilers that output object binary code.

[0313] After compiling source code 2500 into host executable code 2507 and device executable code 2508, linker 2509 can link host executable code 2507 and device executable code 2508 together to form executable file 2510. The host's native object code and the device's PTX or binary code can be linked together in an executable and linkable format (“ELF”) file, a container format for storing object code. Host executable code 2507 and device executable code 2508 can take any suitable format, such as, but not limited to, binary code and / or IR code. In at least one embodiment, for CUDA, host executable code 2507 may include native object code, while device executable code 2508 may include code in a PTX intermediate representation. In at least one embodiment, for ROCm, both host executable code 2507 and device executable code 2508 can include object binary code. Other implementations (e.g., but not limited to oneAPI, OpenCL) are considered and can be performed similarly to the CUDA and ROCm implementations described above.

[0314] Source code 2500 can be converted before compilation. The source code is passed through a conversion tool (not shown) that converts source code 2500 into the converted source code. Compiler 2501 can be used to compile the converted source code into host executable code 2507 and device executable code 2508, a process similar to compiler 2501 compiling source code 2500 into host executable code 2507 and device executable code 2508, as described above. Figure 25The discussion.

[0315] The transformations performed by the transformation tools can be used to port Source Code 2500 to environments different from the environment it was originally intended to run in. The transformation tools may include a HIP converter, which "hipify" CUDA code intended for the CUDA platform into HIP code that can be compiled and executed on the ROCm platform. The transformation of Source Code 2500 may include parsing Source Code 2500 and translating calls to APIs provided by one programming model (e.g., CUDA) into corresponding calls to APIs provided by another programming model (e.g., HIP), as described below. Figure 26 Let's discuss this in more detail. Returning to the example of HIP-enhanced CUDA code, calls to the CUDA runtime API, CUDA driver API, and / or CUDA libraries can be translated into corresponding HIP API calls. The automatic conversion performed by conversion tool 2501 may sometimes be incomplete, requiring additional manual intervention to fully port source code 2500.

[0316] The techniques described herein can utilize various methods of converting one type of code into another to achieve interoperability between different device architectures. For example, compiler 2501 or other compilers described herein can convert a high-level language (e.g., source code abstracting hardware) into a low-level language (e.g., machine code or intermediate representation). Source code can be scanned, parsed, converted into an abstract syntax tree for semantic analysis, then converted into intermediate code, and finally into machine code or assembly language. Compiler 2501 or other compilers described herein may include a transpiler, for example, that can convert one type of source code into another type of source code, or one type of machine code into another type of machine code. Source code can be parsed and converted into an abstract syntax tree, which can then be converted into an intermediate model, which can be converted into an abstract syntax tree of the target language and can generate code. Compiler 2501 or other compilers described herein can be used to achieve interoperability between different device architectures. For example, an application for one platform (e.g., a CUDA application) can be compiled into code for implementation on another platform (e.g., an AMD processor, an Intel processor, or another processor). Source code 2500 may include source code for one platform (e.g., CUDA). Compiler 2501 can compile source code 2500 into an executable file 2510 that can be used by another platform (e.g., AMD or Intel). Programming toolkits can allow applications intended for one platform (e.g., CUDA) to be compiled (e.g., natively compiled) for another platform (e.g., AMD or Intel). For example, the GPGPU programming toolkit can allow CUDA applications to be compiled natively for AMD GPUs. Programs (e.g., CUDA programs) or their build systems do not require modification or conversion to another language before being compiled into code for another platform. The compiler can accept the same command-line options and programming cognates (e.g., CUDA cognates) as another compiler (e.g., nvcc for CUDA), serving as a direct replacement for emulation toolkit (e.g., NVIDIACUDA toolkit) installations, so existing build tools and scripts (e.g., cmake) work without further modification. In at least one embodiment, an nvcc-cognate CUDA can be compiled for AMD GPUs (including PTXasm) using an nvcc-compatible compiler. Implementations of the CUDA runtime and driver APIs for AMD GPUs can be used. Libraries (e.g., open-source wrapper libraries) can provide APIs by delegating to the corresponding ROCm libraries, such as the "CUDA-X" API. Example implementations include SCALE from Spectral Compute in London, UK.SCALE allows programs written in CUDA languages ​​to be directly compiled into low-level languages ​​(e.g., machine code) for AMD GPUs. SCALE can create one or more directories that can be used to emulate the NVIDIA CUDA toolkit (from the build system's perspective) by indicating that the build system's CUDA installation path is provided by SCALE, not by NVIDIA. Additional implementations may include a Clang compiler that provides language front-ends and tooling infrastructure for languages ​​in the C language family (C, C++, Objective C / C++, OpenCL, CUDA, and RenderScript). In at least one embodiment, the compilers and / or transpilers described herein (e.g., but not limited to compiler 2501, compiler 2505, and / or compiler 2506) may include one or more circuitry for compiling code (e.g., CUDA, HIP, OpenCL, OneAPI, or others) such that one or more instructions are executed, or any of the operations described above or elsewhere herein, at least in part, based on one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. In at least one embodiment, the compiler and / or translator described herein (e.g., but not limited to compiler 2501, compiler 2505, and / or compiler 2506) may include one or more circuits for translating code (e.g., CUDA source code) into one or more other types of code (e.g., CUDA machine code and / or code for another platform, such as an AMD or Intel processor) to such that one or more instructions are executed and / or any of the operations described above or elsewhere herein are performed, at least in part based on one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0317] Figure 26 A system 2600 is shown, configured to compile and execute CUDA source code 2610 using different types of processing units according to at least one embodiment. The system 2600 includes CUDA source code 2610, CUDA compiler 2650, host executable code 2670(1), host executable code 2670(2), CUDA device executable code 2684, CPU 2690, CUDA-enabled GPU 2694, GPU 2692, CUDA to HIP conversion tool 2620, HIP source code 2630, HIP compiler driver 2640, HCC 2660, and HCC device executable code 2682.

[0318] CUDA source code 2610 can be a collection of human-readable code in the CUDA programming language. The CUDA programming language can be an extension of the C++ programming language, including mechanisms for defining device code and distinguishing between device code and host code. Device code can include source code that, after compilation, can be executed in parallel on a device. A device can be a processor optimized for parallel instruction processing, such as, but not limited to, a CUDA-enabled GPU 2690, GPU 2692, or other GPGPUs. Host code is source code that, after compilation, can be executed on a host machine. A host machine is a processor optimized for sequential instruction processing, such as, but not limited to, a CPU 2690.

[0319] CUDA source code 2610 may include any number (including zero) of global functions 2612, any number (including zero) of device functions 2614, any number (including zero) of host functions 2616, and any number (including zero) of host / device functions 2618. Global functions 2612, device functions 2614, host functions 2616, and host / device functions 2618 can be mixed within CUDA source code 2610. Each global function 2612 can be executed on the device and can be called from the host. Therefore, one or more global functions 2612 can act as entry points for the device. Each global function 2612 can be a kernel. In a technique called dynamic parallelism, one or more global functions 2612 can define a kernel that can be executed on the device and called from the device. During execution, the kernel can be executed in parallel N times by N different threads on the device (where N is any positive integer).

[0320] Each device function 2614 can be executed on a device and can only be called from that device. Each host function 2616 can be executed on a host and can only be called from that host. Each host / device function 2616 can define a host version of a function that can be executed on a host and called only from that host, and a device version of a function that can be executed on a device and called only from that device.

[0321] CUDA source code 2610 can also include any number of calls to any number of functions, which can be defined through CUDA runtime API 2602. CUDA runtime API 2602 can include any number of functions that execute on the host to allocate and deallocate device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. CUDA source code 2610 can also include any number of calls to any number of functions, which can be specified in any number of other CUDA APIs. CUDA APIs can be any API designed for use by CUDA code. CUDA APIs can include CUDA runtime API 2602, CUDA driver APIs, APIs for any number of CUDA libraries, etc., including any APIs described elsewhere in this document. Compared to CUDA runtime API 2602, CUDA driver APIs can be lower-level APIs but can provide more fine-grained control over devices. Examples of CUDA libraries include cuBLAS, cuFFT, cURAND, cuDNN, etc.

[0322] The CUDA compiler 2650 can compile input CUDA code (e.g., CUDA source code 2610) to generate host executable code 2670(1) and CUDA device executable code 2684. The CUDA compiler 2650 can be, but is not limited to, an NVCC. The host executable code 2670(1) can be a compiled version of the host code included in the input source code, which can be executed on a CPU 2690. The CPU 2690 can be any processor optimized for sequential instruction processing.

[0323] CUDA device executable code 2684 may be a compiled version of the device code included in the input source code, which can be executed on a CUDA-enabled GPU 2694. CUDA device executable code 2684 may include binary code. CUDA device executable code 2684 may include IR code (e.g., but not limited to PTX code), which is further compiled at runtime by the device driver into binary code for a specific target device (e.g., a CUDA-enabled GPU 2694). CUDA-enabled GPU 2694 may include any processor optimized for parallel instruction processing and supporting CUDA. CUDA-enabled GPU 2694 may be developed by NVIDIA Corporation, located in Santa Clara, California.

[0324] The CUDA to HIP conversion tool 2620 can be configured to convert CUDA source code 2610 into functionally similar HIP source code 2630. The HIP source code 2630 may include a collection of human-readable code written in the HIP programming language. The HIP code may include human-readable code written in the HIP programming language. The HIP programming language may include extensions to the C++ programming language that include functionally similar versions of the CUDA mechanisms for defining device code and distinguishing it from host code. The HIP programming language may include a subset of the functionality of the CUDA programming language. For example, the HIP programming language may include mechanisms for defining global functions 2612, but such HIP programming languages ​​may lack support for dynamic parallelism, so the global function 2612 defined in the HIP code may only be called from the host.

[0325] HIP source code 2630 may include any number (including zero) of global functions 2612, any number (including zero) of device functions 2614, any number (including zero) of host functions 2616, and any number (including zero) of host / device functions 2618. HIP source code 2630 may also include any number of calls to any number of functions specified in the HIP runtime API 2632. The HIP runtime API 2632 may include functionally similar versions of a subset of functions contained in the CUDA runtime API 2602. HIP source code 2630 may also include any number of calls to any number of functions specified in any number of other HIP APIs. The HIP API can be any API designed for use by HIP code and / or ROCm. The HIP API may include the HIP runtime API 2632, the HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, etc.

[0326] The CUDA to HIP conversion tool 2620 can convert each kernel call in CUDA code from CUDA syntax to HIP syntax, and can convert any number of other CUDA calls in CUDA code into any number of other functionally similar HIP calls. CUDA calls can include calls to functions specified in the CUDA API, and HIP calls can include calls to functions specified in the HIP API. The CUDA to HIP conversion tool 2620 can convert any number of calls to functions specified in the CUDA runtime API 2602 into any number of calls to functions specified in the HIP runtime API 2632.

[0327] The CUDA to HIP conversion tool 2620 may include a tool called hipify-perl, which performs a text-based conversion process. The CUDA to HIP conversion tool 2620 may also include a tool called hipify-clang, which, compared to hipify-perl, performs a more complex and robust conversion process, including parsing the CUDA code using clang (a compiler front-end) and then converting the resulting symbols. Converting CUDA code to HIP code may include modifications beyond those performed by the CUDA to HIP conversion tool 2620 (e.g., manual editing).

[0328] HIP compiler driver 2640 may include a front-end that identifies target device 2646 and then configures a compiler compatible with target device 2646 to compile HIP source code 2630. Target device 2646 may include a processor optimized for parallel instruction processing. HIP compiler driver 2640 may identify target device 2646 in any technically feasible manner.

[0329] If the target device 2646 is CUDA compatible (e.g., a CUDA-enabled GPU 2694), the HIP compiler driver 2640 can generate HIP / NVCC compilation commands 2642. The HIP / NVCC compilation commands 2642 can configure the CUDA compiler 2650 to compile HIP source code 2630 using a HIP-to-CUDA translation header and the CUDA runtime library. In response to the HIP / NVCC compilation commands 2642, the CUDA compiler 2650 can generate host executable code 2670(1) and CUDA device executable code 2684.

[0330] If the target device 2646 is incompatible with CUDA, the HIP compiler driver 2640 can generate HIP / HCC compilation command 2644. HIP / HCC compilation command 2644 can configure HCC 2660 to compile HIP source code 2630 using the HCC header and HIP / HCC runtime library. In response to HIP / HCC compilation command 2644, HCC 2660 can generate host executable code 2670(2) and HCC device executable code 2682. HCC device executable code 2682 can be a compiled version of the device code included in HIP source code 2630, which can be executed on GPU 2692. GPU 2692 can be any processor optimized for parallel instruction processing, incompatible with CUDA, and compatible with HCC. GPU 2692 can be developed by AMD Inc., located in Santa Clara, California. GPU 2692 can include GPU 2692 that does not support CUDA.

[0331] For illustrative purposes only, Figure 26 Three different flows, which can be implemented in at least one embodiment, for compiling CUDA source code 2610 for execution on CPU 2690 and various devices are described. A direct CUDA stream can compile CUDA source code 2610 for execution on CPU 2690 and CUDA-enabled GPU 2694 without converting CUDA source code 2610 to HIP source code 2630. An indirect CUDA stream can convert CUDA source code 2610 to HIP source code 2630 and then compile HIP source code 2630 for execution on CPU 2690 and CUDA-enabled GPU 2694. A CUDA / HCC stream can convert CUDA source code 2610 to HIP source code 2630 and then compile HIP source code 2630 for execution on CPU 2690 and GPU 2692.

[0332] The achievable direct CUDA stream is represented by dashed lines and a series of bubbles labeled A1-A3. As shown in bubble A1, CUDA compiler 2650 can receive CUDA source code 2610 and CUDA compilation command 2648, which configures CUDA compiler 2650 to compile CUDA source code 2610. The CUDA source code 2610 available for direct CUDA stream can be written in a CUDA programming language based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In response to CUDA compilation command 2648, CUDA compiler 2650 can generate host executable code 2670(1) and CUDA device executable code 2684 (shown in bubble A2). As shown in bubble A3, host executable code 2670(1) and CUDA device executable code 2684 can be executed on CPU 2690 and CUDA-enabled GPU 2694, respectively. CUDA device executable code 2684 may include binary code. CUDA device executable code 2684 may include PTX code and may be further compiled at runtime into binary code for a specific target device.

[0333] The achievable indirect CUDA streams are represented by dashed lines and a series of bubbles labeled B1-B6. As shown in bubble B1, the CUDA-to-HIP conversion tool 2620 can receive CUDA source code 2610. As shown in bubble B2, the CUDA-to-HIP conversion tool 2620 can convert CUDA source code 2610 into HIP source code 2630. As shown in bubble B3, the HIP compiler driver 2640 can receive HIP source code 2630 and determine that the target device 2646 supports CUDA.

[0334] As indicated by bubble B4, the HIP compiler driver 2640 can generate HIP / NVCC compilation command 2642 and transfer HIP / NVCC compilation command 2642 and HIP source code 2630 to CUDA compiler 2650. HIP / NVCC compilation command 2642 can configure CUDA compiler 2650 to compile HIP source code 2630 using HIP to CUDA translation header and CUDA runtime library. HIP to CUDA translation header can convert any number of mechanisms (e.g., functions) specified in any number of HIP APIs to any number of mechanisms specified in any number of CUDA APIs. CUDA compiler 2650 can combine HIP to CUDA translation header and CUDA runtime library corresponding to CUDA runtime API 2602 to generate host executable code 2670(1) and CUDA device executable code 2684. In response to HIP / NVCC compilation command 2642, CUDA compiler 2650 can generate host executable code 2670(1) and CUDA device executable code 2684 (represented by bubble B5). As shown in bubble B6, host executable code 2670(1) and CUDA device executable code 2684 can be executed on CPU 2690 and CUDA-enabled GPU 2694, respectively. CUDA device executable code 2684 may include binary code. CUDA device executable code 2684 may include PTX code and can be further compiled at runtime into binary code for a specific target device.

[0335] The implementable CUDA / HCC streams are represented by solid lines and a series of bubbles labeled C1-C6. As shown in bubble C1, the CUDA-to-HIP conversion tool 2620 can receive CUDA source code 2610. As shown in bubble C2, the CUDA-to-HIP conversion tool 2620 can convert CUDA source code 2610 into HIP source code 2630. As shown in bubble C3, the HIP compiler driver 2640 can receive HIP source code 2630 and can determine that the target device 2646 does not support CUDA.

[0336] HIP compiler driver 2640 can generate HIP / HCC compilation command 2644 and transfer HIP / HCC compilation command 2644 and HIP source code 2630 to HCC 2660 (shown by bubble labeled C4). HIP / HCC compilation command 2644 can configure HCC 2660 to compile HIP source code 2630 using HCC header files and HIP / HCC runtime library. HIP / HCC runtime library may correspond to HIP runtime API 2632. HCC header may include any number and type of HIP and HCC interoperability mechanisms. In response to HIP / HCC compilation command 2644, HCC 2660 can generate host executable code 2670(2) and HCC device executable code 2682 (shown by bubble labeled C5). As shown in the bubble labeled C6, host executable code 2670(2) and HCC device executable code 2682 can be executed on CPU 2690 and GPU 2692, respectively.

[0337] After converting CUDA source code 2610 to HIP source code 2630, executable code for a CUDA-enabled GPU 2694 or GPU 2692 can be generated using HIP compiler driver 2640 without re-executing the CUDA to HIP conversion tool 2620. CUDA to HIP conversion tool 2620 can convert CUDA source code 2610 to HIP source code 2630 and then store the HIP source code 2630 in memory. HIP compiler driver 2640 can then configure HCC 2660 to generate host executable code 2670(2) and HCC device executable code 2682 based on the HIP source code 2630. In at least one embodiment, HIP compiler driver 2640 subsequently configures CUDA compiler 2650 to generate host executable code 2670(1) and CUDA device executable code 2684 based on the stored HIP source code 2630.

[0338] According to at least one embodiment, the example kernel may be derived from... Figure 26 The CUDA to HIP conversion tool 2620 is used for conversion. The CUDA source code 2610 divides the overall problem that a given kernel is designed to solve into relatively coarse subproblems, which can be solved independently using thread blocks. Each thread block contains any number of threads. Each subproblem can be divided into relatively fine pieces, which can be solved collaboratively in parallel by threads within the thread block. Threads within a thread block can cooperate by sharing data via shared memory and synchronizing execution to coordinate memory access.

[0339] CUDA source code 2610 can organize thread blocks associated with a given kernel into one-dimensional, two-dimensional, or three-dimensional thread block grids. Each thread block contains any number of threads, and the grid contains any number of thread blocks.

[0340] A kernel can be a function defined in device code using the "__global__" declaration specifier. The dimensions of the raster of kernels and their associated streams that execute a given kernel call can be specified using the CUDA kernel startup syntax. The CUDA kernel startup syntax is specified as "KernelName <<<GridSize,BlockSize,SharedMemorySize,Stream> >>

[0341] (KernelArguments);". The execution configuration syntax can include a "<<<...>>>" structure between the kernel name ("KernelName") and the parenthesized list of kernel parameters ("KernelArguments"). The CUDA kernel boot syntax can include the CUDA boot function syntax, instead of the execution configuration syntax.

[0342] "GridSize" can be of type dim3 and specifies the dimensions and size of the grid. The dim3 type can be a CUDA-defined structure containing unsigned integers x, y, and z. If z is not specified, it defaults to 1. If y is not specified, it defaults to 1. The number of thread blocks in the grid can be equal to the product of GridSize.x, GridSize.y, and GridSize.z. "BlockSize" can be of type dim3 and specifies the dimensions and size of each thread block. The number of threads per thread block can be equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. Each thread executing the kernel can be assigned a unique thread ID, which can be accessed in the kernel via built-in variables such as "threadIdx".

[0343] Regarding the CUDA kernel startup syntax, "SharedMemorySize" is an optional argument that, in addition to statically allocated memory, can specify the number of bytes in shared memory dynamically allocated per thread block for a given kernel call. The default value for SharedMemorySize is zero. Regarding the CUDA kernel startup syntax, "Stream" is also an optional argument that specifies the associated stream; the default value is zero to specify the default stream. A stream can be a sequence of commands executed sequentially (which may be emitted by different host threads). Different streams can execute commands out of order or concurrently.

[0344] CUDA source code 2610 may include the kernel definition and main function of the example kernel "MatAdd". The main function may be host code that executes on the host machine and includes a kernel call that causes the MatAdd kernel to execute on the device. The MatAdd kernel can add two NxN matrices A and B, where N is a positive integer, and store the result in matrix C. The main function can define the threadsPerBlock variable as 16x16 and the numBlocks variable as N / 16 x N / 16. Then, the main function can specify the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);”. According to the CUDA kernel startup syntax, the kernel MatAdd can be executed using a thread block grid of dimensions N / 16 x N / 16, where each thread block is 16x16. Each thread block can contain 256 threads, and a grid with enough thread blocks can be created so that there is one thread per matrix element, and each thread in such a grid can execute the kernel MatAdd to perform a pairwise addition.

[0345] When converting CUDA source code 2610 to HIP source code 2630, the CUDA-to-HIP conversion tool 2620 can convert each kernel call in CUDA source code 2610 from CUDA kernel startup syntax to HIP kernel startup syntax, and can convert any number of other CUDA calls in source code 2610 into any number of other functionally similar HIP calls. The HIP kernel startup syntax can be specified as "hipLaunchKernelGGL(KernelName,GridSize,BlockSize,SharedMemorySize,Stream,KernelArguments);". Each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in the HIP kernel startup syntax as it does in the CUDA kernel startup syntax (described earlier in this document). The arguments SharedMemorySize and Stream can be required in the HIP kernel startup syntax, but optional in the CUDA kernel startup syntax.

[0346] A portion of the HIP source code 2630 can be identical to a portion of the CUDA source code 2610 shown, except for the kernel call that causes the kernel MatAdd to execute on the device. The kernel MatAdd can be defined in the HIP source code 2630 using the same "__global__" declaration specifier as used in the CUDA source code 2610. The kernel call in the HIP source code 2630 can be "hipLaunchKernelGGL(MatAdd,numBlocks,threadsPerBlock,0,0,A,B,C);", while the corresponding kernel call in the CUDA source code 2610 is "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);

[0347] Other implementations are conceivable, and these can be implemented similarly to the CUDA and HIP implementations described above, such as oneAPI, OpenCL, and other programming platforms. Code can be converted in any direction. For example, CUDA can be converted to HIP, and CUDA can be converted to OpenCL. SnuCL-Tr and CUCL can be used to convert OpenCL to CUDA or CUDA to OpenCL, respectively. Compiled code or intermediate representations (such as CUDA PTX code) can also be converted to run on other processor platforms (such as AMD or Intel). For example, conversion tools (such as ZLUDA) can be used to convert PTX code to run on Intel or AMD processors.

[0348] The techniques described herein can utilize the oneAPI programming model. The oneAPI programming model can refer to a programming model used to interact with various computing accelerator architectures. OneAPI can refer to an application programming interface (API) designed to interact with various computing accelerator architectures. The oneAPI programming model can use the DPC++ programming language. The DPC++ programming language can refer to a high-level language used for data-parallel programming productivity. The DPC++ programming language can be at least partially based on the C and / or C++ programming languages. The oneAPI programming model can be, but is not limited to, a programming model developed by Intel Corporation of Santa Clara, California.

[0349] OneAPI and / or the oneAPI programming model can be used to interact with a variety of accelerators, GPUs, processors, and / or their variant architectures. OneAPI may include a set of libraries that implement various functions. OneAPI may include at least the oneAPIDPC++ library, the oneAPI math kernel library, the oneAPI data analysis library, the oneAPI deep neural network library, the oneAPI collection communication library, the oneAPI thread building block library, the oneAPI video processing library, and / or their variants.

[0350] The oneAPIDPC++ library (also known as oneDPL) can be a library that implements algorithms and functions to accelerate DPC++ kernel programming. oneDPL can implement one or more Standard Template Library (STL) functions. OneDPL can implement one or more parallel STL functions. OneDPL can provide a set of library classes and functions, such as, but not limited to, parallel algorithms, iterators, function object classes, range-based APIs, and / or variations thereof. OneDPL can implement one or more classes and / or functions from the C++ Standard Library. OneDPL can implement one or more random number generator functions.

[0351] The oneAPI math kernel library (also known as oneMKL) can be a library that implements various optimized and parallelized routines for various mathematical functions and / or operations. OneMKL can implement one or more Basic Linear Algebra Subroutines (BLAS) and / or Linear Algebra Packages (LAPACK) dense linear algebra routines. OneMKL can implement one or more sparse BLAS linear algebra routines. OneMKL can implement one or more random number generators (RNGs). OneMKL can implement one or more vector math (VM) routines for performing mathematical operations on vectors. OneMKL can implement one or more Fast Fourier Transform (FFT) functions.

[0352] The OneAPI data analysis library (also known as oneDAL) can include libraries for implementing various data analysis applications and distributed computing. OneDAL can implement various algorithms for data analysis preprocessing, transformation, analysis, modeling, validation, and decision-making, including batch, online, and distributed computing processing modes. OneDAL can implement various C++ and / or Java APIs as well as various connectors for connecting to one or more data sources. OneDAL can implement the DPC++ API extension to the traditional C++ interface and support GPU usage for various algorithms.

[0353] The OneAPI Deep Neural Network Library (also known as oneDNN) can include libraries that implement various deep learning functions. OneDNN can implement various neural networks, machine learning and deep learning functions, algorithms and / or variations thereof.

[0354] The OneAPI collection communication library (also known as oneCCL) can include libraries that implement a variety of applications for deep learning and machine learning workloads. OneCCL can be built on lower-level communication middleware, such as, but not limited to, message passing interfaces (MPI) and libfabrics. OneCCL can support a set of deep learning-specific optimizations, such as, but not limited to, priority ordering, persistence operations, out-of-order execution, and / or variations thereof. OneCCL can implement a variety of CPU and GPU functionalities.

[0355] The OneAPI Thread Building Blocks library (also known as oneTBB) can include libraries that implement various parallel processes for a wide range of applications. OneTBB can be used for task-based shared parallel programming on a host machine. OneTBB can implement general-purpose parallel algorithms. OneTBB can implement concurrent containers. OneTBB can implement scalable memory allocators. OneTBB can implement work-stealing task schedulers. OneTBB can implement low-level synchronization primitives. OneTBB can be compiler-independent and can be used on a variety of processors, such as, but not limited to, GPUs, PPUs, CPUs, and / or variants thereof.

[0356] The OneAPI video processing library (also known as oneVPL) can include libraries for accelerating video processing in one or more applications. OneVPL can implement a variety of video decoding, encoding, and processing functions. OneVPL can implement various functions for media pipelines on CPUs, GPUs, and other accelerators. OneVPL can implement device discovery and selection in media-centric and video analytics workloads. OneVPL can implement API primitives for zero-copy buffer sharing.

[0357] The oneAPI programming model can use the DPC++ programming language. The DPC++ programming language can include a version of a programming language that is functionally similar to the CUDA mechanism to define device code and distinguish it from host code. The DPC++ programming language can include a subset of the functionality of the CUDA programming language. One or more CUDA programming model operations can be performed using the oneAPI programming model utilizing the DPC++ programming language.

[0358] Any application programming interface (API) described herein can be compiled by a compiler, interpreter, or other software tool into one or more instructions, operations, or other signals. Compilation may include generating one or more machine-executable instructions, operations, or other signals from source code. An API compiled into one or more instructions, operations, or other signals, when executed, may enable one or more processors (e.g., but not limited to...) Figure 11-23BThe processor described herein or any other logic circuit further described herein performs one or more computational operations.

[0359] In at least one embodiment, the transformation tools described elsewhere herein (e.g., but not limited to) may include one or more circuitry for transforming CUDA code such that one or more instructions are executed, at least in part, based on one or more API parameters, for use with HIP, oneAPI, OpenCL, or any other language for performing any operations described above or elsewhere herein, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions. One or more circuitry may be software-configurable to transform CUDA code such that one or more instructions are executed, at least in part, based on one or more API parameters, for use with HIP, oneAPI, OpenCL, or any other language for performing any operations described above or elsewhere herein, the one or more API parameters indicating the size of one or more operands to be used by said one or more instructions.

[0360] Autonomous vehicles

[0361] Figure 27 An example of an autonomous vehicle 2700 according to at least one embodiment is shown. The autonomous vehicle 2700 (alternately referred to herein as "vehicle 2700") can be a passenger vehicle, such as, but not limited to, a sedan, truck, bus, and / or other type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 2700 can be a semi-trailer tractor for transporting goods. Vehicle 2700 can be an aircraft, robotic vehicle, or other type of vehicle.

[0362] Autonomous vehicles can be described according to their automation levels, which are defined by the National Highway Traffic Safety Administration (NHTSA) (a division of the U.S. Department of Transportation) and the Society of Automotive Engineers (SAE) in their "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In at least one embodiment, vehicle 2700 can achieve functionality at one or more levels of autonomy, from Level 1 to Level 5. For example, in at least one embodiment, depending on the embodiment, vehicle 2700 can achieve conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0363] Vehicle 2700 may include components such as, but not limited to, chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle parts. Vehicle 2700 may include a propulsion system 2750, such as, but not limited to, an internal combustion engine, a hybrid power plant, an all-electric motor, and / or other propulsion system types. Propulsion system 2750 may be connected to the drivetrain of vehicle 2700 (which may include a transmission) to propel vehicle 2700. Propulsion system 2750 may be controlled based on signals received from throttle / accelerator 2752.

[0364] A steering system 2754 (which may include a steering wheel) is used to maneuver the vehicle 2700 (e.g., to travel along a desired path or route) while the propulsion system 2750 is in operation (e.g., when the vehicle 2700 is in motion). The steering system 2754 may receive signals from the steering actuator 2756. The steering wheel is optional for fully automated (Level 5) functionality. A brake sensor system 2746 may be used to operate the vehicle brakes in response to signals received from the brake actuator 2748 and / or brake sensors.

[0365] Controller 2736 may include one or more system-on-a-chip (“SoC”) and / or graphics processing units (“GPUs”) that can provide signals (e.g., signals representing commands) to one or more components and / or systems of vehicle 2700. For example, controller 2736 may send signals to operate vehicle brakes via brake actuator 2748, steering system 2754 via steering actuator 2756, and propulsion system 2750 via throttle / accelerator 2752. Controller 2736 may include one or more onboard (e.g., integrated) computing devices for processing sensor signals and outputting operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 2700. Controller 2736 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. A single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0366] The controller 2736 may provide signals for controlling one or more components and / or systems of the vehicle 2700 in response to sensor data (e.g., sensor inputs) received from one or more sensors. Sensor data can be received from, for example, a Global Navigation Satellite System (“GNSS”) sensor 2758 (e.g., a Global Positioning System sensor), a RADAR (radar) sensor 2760, an ultrasonic sensor 2762, a LIDAR (light radar) sensor 2764, an Inertial Measurement Unit (“IMU”) sensor 2766 (e.g., an accelerometer, a gyroscope, one or more magnetic compasses, a magnetometer, etc.), a microphone 2796, a stereo camera 2768, a wide-angle camera 2770 (e.g., a fisheye camera), an infrared camera 2772, a surround-view camera 2774 (e.g., a 360-degree camera), a long-range camera 2798, a medium-range camera 2776, a speed sensor 2744 (e.g., for measuring the speed of vehicle 2700), a vibration sensor 2742, a steering sensor 2740, a braking sensor (e.g., as part of a braking sensor system 2746), and / or other types of sensors.

[0367] One or more controllers 2736 may receive input (e.g., represented by input data) from the instrument panel 2732 of the vehicle 2700 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 2734, an audible annunciator, a speaker, and / or via other components of the vehicle 2700. Output may include, but is not limited to, vehicle speed, rate, time, map data (e.g., a high-resolution map (not shown), location data (e.g., the location of the vehicle 2700, such as, but not limited to, its location on a map), direction, the location of other vehicles (e.g., occupying a grid), information about objects, and the status of objects perceived by the controllers 2736. For example, the HMI display 2734 may display information about the presence of one or more objects (e.g., street signs, warning signs, traffic light changes, etc.) and / or information about driving actions that the vehicle has performed, is performing, or will perform (e.g., changing lanes now, exiting from exit 34B in two miles, etc.).

[0368] Figure 27 Every component, feature, and system of the vehicle 2700 can be connected via bus 2702. Bus 2702 may include a CAN data interface (also referred to herein as the "CAN bus"). CAN can be a network within the vehicle 2700 used to assist in the control of various features and functions of the vehicle 2700, such as, but not limited to, the activation of brakes, acceleration, braking, steering, windshield wipers, etc. Bus 2702 can be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). Bus 2702 can be read to locate steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. Bus 2702 can be an ASIL B compliant CAN bus.

[0369] In addition to CAN, or as an alternative to CAN, FlexRay and / or Ethernet protocols may be used. Bus 2702 may consist of any number of buses, including zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. Two or more buses may be used to perform different functions and / or for redundancy. For example, a first bus may be used for collision avoidance functions, and a second bus may be used for actuation control. Each bus in bus 2702 may communicate with any component of vehicle 2700, and two or more buses of bus 2702 may communicate with corresponding components. Any number of System-on-Chip (“SoC”) 2704 (e.g., but not limited to SoC 2704(A) and SoC 2704(B)), each controller 2736, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of vehicle 2700) and may be connected to a common bus, such as a CAN bus.

[0370] According to at least one embodiment, for Figure 27 The autonomous vehicle 2700 can place any number of cameras at any chosen camera locations and within any field of view. The cameras and corresponding fields of view are an exemplary embodiment and are not intended to be limiting. For example, additional and / or alternative cameras may be included, and / or the cameras may be located at different locations within the vehicle 2700.

[0371] The camera type may include a digital camera suitable for components and / or systems in vehicle 2700. The camera may operate under Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. According to embodiments, the camera type may support any image capture rate, such as, but not limited to, 60 frames per second (fps), 1220 fps, 240 fps, etc. The camera may be able to use a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-to-clear-to-clear (“RCCC”) color filter array, a red-to-clear-to-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. Transparent pixel cameras (e.g., but not limited to cameras with RCCC, RCCB, and / or RBGC color filter arrays) may be used to enhance sensitivity.

[0372] One or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, a multi-function monochrome camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. One or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0373] One or more cameras can be mounted in mounting assemblies, such as, but not limited to, custom-designed (3D-printed) assemblies, to eliminate stray light and reflections inside the vehicle 2700 (e.g., dashboard ...

Claims

1. A processor comprising one or more circuits for executing an application programming interface (API) such that one or more instructions are executed at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

2. The processor of claim 1, wherein the one or more circuits are further configured to execute the API to calculate one or more storage locations associated with one or more threads, at least in part based on pointers to the starting storage location in the memory block.

3. The processor of claim 1, wherein the one or more parameters of the API include one or more of the following: a pointer to memory storage in a memory block, a data type of data stored in the memory block, one or more stride dimensions, one or more grid dimensions, or one or more block dimensions.

4. The processor of claim 1, wherein the one or more circuits are further configured to execute the API to initiate one or more threads to access one or more storage locations.

5. The processor of claim 1, wherein each of the one or more operands corresponds to a change in one dimension of a multidimensional memory address.

6. The processor of claim 1, wherein the one or more circuits are configured to execute the API in response to a request to initiate one or more threads from the central processing unit.

7. The processor of claim 1, wherein the one or more circuits are configured to execute the API on a graphics processing unit (GPU).

8. A method comprising: Execute an application programming interface (API) to cause one or more circuits to execute the API so that one or more instructions are executed at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

9. The method of claim 8, further comprising: The API is executed to compute, at least in part, different storage locations in the memory block associated with each of one or more threads, based on pointers to the starting storage locations in the memory block.

10. The method of claim 8, wherein the one or more parameters of the API are received from a request invoked on the central processing unit to start one or more threads on the graphics processing unit.

11. The method of claim 8, further comprising: Execute the API to launch one or more threads on one or more streaming multiprocessors to access one or more storage locations.

12. The method of claim 8, wherein one or more threads are parallel threads in one or more blocks of a thread grid for accessing data stored in global memory.

13. The method of claim 8, further comprising: The API is executed in response to a request to start one or more threads from the central processing unit.

14. The method of claim 8, wherein each of one or more threads includes a kernel declared using a reference type parameter.

15. A system comprising: One or more processors are configured to execute an application programming interface (API) such that one or more instructions are executed at least in part based on one or more API parameters, the one or more API parameters indicating the size of one or more operands to be used by the one or more instructions.

16. The system of claim 15, wherein the one or more processors are further configured to execute the API to launch one or more threads to use one or more storage locations based on the size of the one or more operands.

17. The system of claim 15, wherein the one or more processors are further configured to launch one or more threads on one or more streaming multiprocessors to access different storage locations in a memory block.

18. The system of claim 15, wherein the one or more processors is one or more graphics processing units.

19. The system of claim 15, wherein the one or more instructions relate to more than one storage location accessible based on the starting position and the size of the one or more operands.

20. The system of claim 15, wherein the one or more processors are configured to execute the API in response to a request to initiate one or more threads from the central processing unit.

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