RC oscillator

Abstract

An embodiment of the present application discloses an RC oscillator that can employ a first amplifier and a second amplifier to amplify the difference between a first voltage and a second voltage. The first amplifier can include a first amplifier circuit and a second amplifier circuit. The first amplifier circuit and the second amplifier circuit can reuse the same voltage-to-current conversion circuit. The RC oscillator disclosed in the embodiment of the present application not only avoids noise introduced by the first amplifier but also reduces the internal noise of the RC oscillator, thereby reducing the jitter of the clock signal.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuits, and in particular to an RC oscillator. Background Art

[0002] Many portable electronic devices require a low-noise oscillator. For example, an oscillator can serve as a system clock. Oscillators can be categorized as resistor-capacitor (RC) oscillators, inductor-capacitor (LC) oscillators, and quartz crystal oscillators.

[0003] An RC oscillator generates an oscillating signal by charging and discharging a capacitor. The frequency of the oscillating signal can be adjusted by adjusting the value of the resistor or capacitor. Compared to other oscillators, RC oscillators are widely used due to their relatively simple structure, small size, low cost, and minimal external components.

[0004] However, the RC oscillator in the prior art has process deviations and noise interference in the internal modules, which results in large frequency jitter and deviation of the clock signal finally outputted. Summary of the Invention

[0005] The embodiment of the present application provides an RC oscillator, which can reduce the internal noise of the RC oscillator and reduce the jitter of the clock signal.

[0006] In a first aspect, an embodiment of the present application provides an integrated circuit comprising: a first amplifier and a second amplifier; wherein: the first amplifier comprises: a first input terminal, a second input terminal, a first amplifying circuit, a second amplifying circuit, a first output terminal and a second output terminal; the first input terminal is used to input a first voltage V REF The second input terminal is used to input the second voltage V PERIOD ; The first output terminal is used to output the third voltage V P , the third voltage V P The first voltage V REF The voltage after passing through the first amplifier circuit; the second output terminal is used to output the fourth voltage V N , the fourth voltage V N The second voltage V PERIOD The voltage after passing through the second amplifier circuit; wherein the first amplifier circuit and the second amplifier circuit share a voltage-current conversion circuit; the second amplifier includes a third input terminal, a fourth input terminal and a third output terminal; the third input terminal is used to input a third voltage V P The fourth input terminal is used to input the fourth voltage V N The third output terminal is used to output the fifth voltage V OUT .

[0007] Specifically, the voltage-to-current conversion circuit is used to convert the first voltage V inputted from the first input terminal into REF Or the second voltage V inputted from the second input terminal PERIOD Converted into current.

[0008] Specifically, the second amplifier is a differential amplifier, the third input terminal is a positive input terminal of the differential amplifier, and the fourth input terminal is a negative input terminal of the differential amplifier.

[0009] In the embodiments of the present application, the first and second amplifier circuits share a common voltage-to-current conversion circuit, amplifying the first and second voltages before inputting them into a differential amplifier. This not only amplifies the difference between the first and second voltages but also cancels out noise introduced by the voltage-to-current conversion circuit. If this integrated circuit is used in an RC oscillator, amplifying the difference between the first and second voltages allows the RC oscillator to track relatively low-amplitude frequency variations within the low- and medium-frequency bands, thereby reducing output jitter caused by these frequency variations.

[0010] In a possible implementation, the integrated circuit may further include: a low-pass filter and a voltage-controlled oscillator. OUT The control voltage V is obtained through a low-pass filter CTRL ; Control voltage V CTRL The clock signal is obtained through a voltage controlled oscillator.

[0011] Specifically, the frequency of the clock signal and the control voltage V CTRL is proportional to the value of .

[0012] The integrated circuit provided in the embodiment of the present application can filter out the high-frequency noise of the output voltage of the second amplifier through a low-pass filter, and enable the above-mentioned clock signal to be continuously modulated through the voltage-controlled oscillator, thereby improving the adjustment accuracy of the integrated circuit and reducing the random jitter of the clock signal.

[0013] In another possible implementation, the integrated circuit further includes a pulse generator configured to generate a control signal for controlling the first amplifier according to the clock signal.

[0014] Specifically, the control signal includes: a first clock signal, a second clock signal and a reset signal; the voltage-current conversion circuit includes: a first switch (S15), a second switch (S16), a first capacitor (C14) and a MOS transistor (N11); the first switch (S15) and the second switch (S16) are both high-level conduction switches, and the first switch (S15) and the second switch (S16) are both controlled by the reset signal; the first capacitor and the second switch (S16) are connected in parallel, the first end of the first capacitor (C14) is connected to the source of the MOS transistor (N11), and the second end of the first capacitor (C14) is grounded; and the gate of the MOS transistor (N11) is grounded through the first switch (S15).

[0015] Specifically, the control signal further includes: a first sampling signal; the first amplifier circuit includes: a third switch (S14), a voltage-current conversion circuit, a fourth switch (S17), a fifth switch (S19), a sixth switch (S21), a second capacitor (C18) and a third capacitor (C16); the third switch (S14), the fourth switch (S17), the fifth switch (S19) and the sixth switch (S21) are all high-level conduction switches, the third switch (S14) and the fourth switch (S17) are controlled by the first clock signal, the fifth switch (S19) is controlled by the first sampling signal, and the sixth switch (S21) is controlled by the reset signal; the first input The first end of the MOS transistor (N11) is connected to the gate of the MOS transistor (N11) through a third switch (S14); the drain of the MOS transistor (N11) is connected to the first end of the second capacitor (C18) through a fourth switch (S17), and the second end of the second capacitor (C18) is grounded; the third capacitor (C16) is connected in parallel with the sixth switch (S21), the first end of the third capacitor (C16) is connected to the power supply, and the second end of the third capacitor (C16) is connected to the first end of the second capacitor (C18); the fifth switch (S19) is connected to the first end of the second capacitor (C18); when the fifth switch (S19) is closed, the voltage at the first end of the second capacitor (C18) is the third voltage V P .

[0016] Specifically, the control signal also includes a second sampling signal; the second amplifier circuit includes: a seventh switch (S13), a voltage-current conversion circuit, an eighth switch (S18), a ninth switch (S20), a tenth switch (S22), a fourth capacitor (C15) and a fifth capacitor (C17); the seventh switch (S13), the eighth switch (S18), the ninth switch (S20) and the tenth switch (S22) are all high-level conduction switches, the seventh switch (S13) and the eighth switch (S18) are controlled by the second clock signal, the ninth switch (S20) is controlled by the second sampling signal, and the tenth switch (S22) is controlled by the reset signal; the second input The input end is connected to the gate of the MOS tube (N11) through the seventh switch (S13); the drain of the MOS tube (N11) is connected to the first end of the fourth capacitor (C15) through the eighth switch (S18), and the second end of the fourth capacitor (C15) is grounded; the fifth capacitor (C17) is connected in parallel with the tenth switch (S22), the first end of the fifth capacitor (C17) is connected to the power supply, and the second end of the fifth capacitor (C17) is connected to the first end of the fourth capacitor (C15); the ninth switch (S20) is connected to the first end of the fourth capacitor (C15); when the ninth switch (S20) is closed, the voltage at the first end of the fourth capacitor (C15) is the fourth voltage V N .

[0017] The present invention provides an exemplary detailed circuit structure of a first amplifier circuit and a second amplifier circuit, as well as a detailed circuit structure of a voltage-to-current conversion circuit that is multiplexed between the first and second amplifier circuits. By using the same voltage-to-current conversion circuit, the noise current generated by the voltage-to-current conversion circuit can be offset at the two differential input terminals of the second amplifier. The difference between the first and second voltages can also be amplified, reducing the internal noise of the RC oscillator and the jitter of the output clock signal.

[0018] In another possible implementation, the integrated circuit further includes: a second voltage generator; the pulse generator is further configured to generate a charging signal and a discharging signal for controlling the second voltage generator according to a clock signal; the second voltage generator includes: a first resistor (R13), a sixth capacitor (C13), an eleventh switch (S11), and a twelfth switch (S12); the eleventh switch (S11) and the twelfth switch (S12) are both high-level on switches, the eleventh switch (S11) is controlled by a charging signal, and the twelfth switch (S12) is controlled by a discharging signal; a first end of the first resistor (R13) is connected to a power supply through the eleventh switch (S11), a second end of the first resistor (R13) is connected to a first end of the sixth capacitor (C13), and the sixth capacitor (C13) is connected in parallel to the twelfth switch (S12); the second voltage V PERIOD is the voltage at the first terminal of the sixth capacitor (C13).

[0019] The second voltage generator in the integrated circuit provided in the embodiment of the present application generates a second voltage related to the frequency of the current charging signal through the charging and discharging of the resistor and capacitor, which can reduce the ripple of the second voltage and thus reduce the control signal V caused by the ripple. CTRL to reduce the jitter of the clock signal.

[0020] In another possible implementation, the second voltage generator further includes: a seventh capacitor (C12) and a thirteenth switch (S10); the thirteenth switch (S10) is a high-level on-switch, and the thirteenth switch (S10) is controlled by a second clock signal; a first end of the seventh capacitor (C12) is connected to a second end of the sixth capacitor (C13), and a second end of the seventh capacitor (C12) is connected to a first end of the first resistor (R13) via the thirteenth switch (S10).

[0021] In the embodiment of the present application, the second voltage generator is connected to the seventh capacitor so that the voltage at the first end of the first resistor becomes a low-speed node after the eleventh switch is disconnected, and the remaining charge flows to the seventh capacitor to ensure that the second voltage V PERIOD Stability and reduced clock signal jitter.

[0022] In another possible implementation, the high-level pulse width of the discharge signal is smaller than the low-level pulse width of the charge signal.

[0023] In another possible implementation, after the charging signal changes from a high level to a low level, a preset period of time passes before the discharging signal changes from a low level to a high level.

[0024] In another possible implementation, the charging signal and the discharging signal are signals of a frequency-divided clock signal, that is, the periods of the charging signal and the discharging signal are twice that of the clock signal.

[0025] In another possible implementation, the period of the first clock signal and the second clock signal is twice the period of the clock signal.

[0026] In another possible implementation, the period of the first sampling signal and the second sampling signal is twice the period of the clock signal.

[0027] For example, the period of the clock signal and reset signal is 20.83 nS, and the period of the charge signal, discharge signal, first clock signal, second clock signal, first sampling signal, and second sampling signal is 41.6 nS. The preset duration during which the charge signal and discharge signal are simultaneously low is 10 nS, the duration during which the first clock signal and second clock signal are both high is 5.2 nS, the duration during which the first sampling signal and second sampling signal are high is 2 nS, and the duration during which the reset signal is high is 12.8 nS. The preset duration during which the charge signal and discharge signal are simultaneously low, and the duration during which the first sampling signal, second sampling signal, first clock signal, and second clock signal are high, can be adjusted to accommodate process fluctuations without affecting the accuracy of the system output.

[0028] In another possible implementation, the high-level pulse width of the first clock signal is equal to the high-level pulse width of the second clock signal; the high-level pulse width of the first clock signal and the high-level pulse width of the second clock signal are both smaller than the high-level pulse width of the charging signal.

[0029] In another possible implementation, the charging signal changes from low level to high level, triggering the first clock signal to change from low level to high level; the charging signal changes from high level to low level, triggering the second clock signal to change from low level to high level.

[0030] In another possible implementation, the first clock signal changes from a high level to a low level, triggering the first sampling signal to change from a low level to a high level; the second clock signal changes from a high level to a low level, triggering the second sampling signal to change from a low level to a high level; the high-level pulse width of the first sampling signal and the high-level pulse width of the second sampling signal are both smaller than the high-level pulse width of the first clock signal.

[0031] Exemplarily, the high-level pulse width of the first sampling signal and the high-level pulse width of the second sampling signal are one tenth of the period of the clock signal.

[0032] In another possible implementation, when the first clock signal and the second clock signal are both at a low level, the reset signal is at a high level.

[0033] Possibly, the frequency of the reset signal is equal to the frequency of the clock signal.

[0034] In another possible implementation, the duration during which the charging signal and the discharging signal are simultaneously at a low level is greater than or equal to the sum of the duration during which the second clock signal is at a high level and the duration during which the second sampling signal is at a high level.

[0035] In another possible implementation, the MOS transistor N11 is an N-type MOS transistor.

[0036] In another possible implementation, the MOS transistor N11 is a P-type MOS transistor.

[0037] In a second aspect, an embodiment of the present application provides an RC oscillator, which includes the integrated circuit provided by the first aspect or any implementation manner of the first aspect.

[0038] It can be understood that the beneficial effects that can be achieved by the RC oscillator provided in the second aspect mentioned above can refer to the beneficial effects in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A structural diagram of an exemplary RC oscillator provided in an embodiment of the present application;

[0040] Figure 2 A timing diagram of the relationship between various signals provided in the embodiments of the present application;

[0041] Figure 3 A circuit diagram of an exemplary first voltage generator provided in an embodiment of the present application;

[0042] Figure 4 A circuit diagram of an exemplary second voltage generator provided in an embodiment of the present application;

[0043] Figure 5 A circuit diagram of another exemplary second voltage generator provided in an embodiment of the present application;

[0044] Figure 6 A circuit diagram of an exemplary first amplifier provided in an embodiment of the present application;

[0045] Figure 7 A circuit diagram of an exemplary low-pass filter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and in detail below with reference to the accompanying drawings.

[0047] See first Figure 1 . Figure 1 It is an exemplary RC oscillator provided in an embodiment of the present application.

[0048] like Figure 1 As shown, the RC oscillator 10 may include: a first voltage generator 110, a second voltage generator 120, a first amplifier 130, a second amplifier 140, a low-pass filter 150, a voltage-controlled oscillator 160, and a pulse generator 170. Among them:

[0049] The first voltage generator 110 can be used to generate a first voltage V REF .

[0050] The second voltage generator 120 can be used to generate a second voltage V PERIOD The second voltage generator 120 may be, but is not limited to, composed of a resistor and a capacitor. The second voltage may be a voltage related to the charge-discharge frequency generated by the charge-discharge of the resistor and the capacitor.

[0051] The first amplifier 130 and the second amplifier 140 can be used to amplify the difference between the first voltage and the second voltage to output a fifth voltage V OUT .

[0052] The low-pass filter 150 can be used to filter out the fifth voltage V OUT The high-frequency noise in the control voltage V CTRL .

[0053] The voltage controlled oscillator 160 can be used to control the voltage V CTRL Output clock signal CLK. The frequency of clock signal CLK is related to control voltage V CTRL is proportional to the value of .

[0054] The pulse generator 170 may be configured to output a signal for controlling the second voltage generator 120 and the first amplifier 130 according to the clock signal CLK.

[0055] Specifically, the signal for controlling the second voltage generator 120 may include a charging signal and a discharging signal. Furthermore, the signal for controlling the second voltage generator 120 may also include a second clock signal.

[0056] The signals for controlling the first amplifier 130 may include: a first clock signal, a second clock signal, a first sampling signal, a second sampling signal, and a reset signal.

[0057] When the frequency of the clock signal output by the RC oscillator 10 increases, the charging time of the charging signal decreases, and the second voltage V PERIOD The second voltage V PERIOD After passing through the first amplifier 130, the fourth voltage V N Increase. The third voltage V P is a fixed value, then the third voltage V P and the fourth voltage V N The difference will be reduced. After the difference is amplified by the second amplifier 140, the fifth voltage V OUT The fifth voltage V OUT After passing through the low-pass filter 150, the control voltage V CTRL Decreases. Since the frequency of the clock signal CLK is related to the control voltage V CTRL The value is proportional to the control voltage V CTRLWhen the voltage controlled oscillator 160 decreases, the frequency of the clock signal output by the voltage controlled oscillator 160 decreases, forming a negative feedback, thereby stabilizing the frequency.

[0058] When the frequency of the clock signal output by the RC oscillator 10 decreases and the charging time of the charging signal increases, the second voltage V PERIOD Increase. The second voltage V PERIOD After passing through the first amplifier 130, the fourth voltage V N The third voltage V P is a fixed value, then the third voltage V P and the fourth voltage V N The difference will increase. After the difference is amplified by the second amplifier 140, the fifth voltage V OUT The fifth voltage V OUT After passing through the low-pass filter 150, the control voltage V CTRL Increase. Since the frequency of the clock signal CLK is related to the control voltage V CTRL The value is proportional to the control voltage V CTRL When increases, the frequency of the clock signal output by the voltage-controlled oscillator 160 increases, forming a negative feedback, thereby stabilizing the frequency.

[0059] Next, the relationship between the above-mentioned clock signal, charging signal, discharging signal, first clock signal, second clock signal, first sampling signal, second sampling signal and reset signal will be described.

[0060] Figure 2 The timing relationship of several signals generated by the pulse generator is shown.

[0061] like Figure 2 As shown, the charging signal is a two-frequency signal of the clock signal. After the charging signal changes from a high level to a low level, after a preset time period, the discharge signal changes from a low level to a high level. The low-level pulse width of the charging signal is greater than the high-level pulse width of the discharge signal. Therefore, within the preset time period, the charging signal and the discharge signal are simultaneously low. The preset time period can be, for example, one-quarter of the cycle of the charging signal or the discharge signal. The ratio of the preset time period to the cycle of the charging signal or the discharge signal can fluctuate with the process. When the process fluctuates within a certain range, the preset time period can be adjusted adaptively without affecting the accuracy of the system output.

[0062] Assuming that the period of the clock signal is 20.83 nS, the period of the charging signal and the discharging signal may be 41.6 nS (twice the period of the clock signal), and the preset duration for the charging signal and the discharging signal to be simultaneously low may be 10 nS.

[0063] The change of the charging signal from low level to high level can trigger the first clock signal to change from low level to high level. The change of the charging signal from high level to low level can trigger the second clock signal to change from low level to high level. Specifically, the sum of the high level duration of the second clock signal and the high level duration of the second sampling signal is less than or equal to the duration during which the charging signal and the discharging signal are both low level, that is, the above-mentioned preset duration. The high level pulse width of the first clock signal can be equal to the high level pulse width of the second clock signal, and the high level pulse width of the first clock signal and the high level pulse width of the second clock signal are both less than the high level pulse width of the charging signal. Exemplarily, the high level pulse width of the first clock signal or the high level pulse width of the second clock signal can be one eighth of the charging signal cycle.

[0064] The change of the first clock signal from a high level to a low level can trigger the change of the first sampling signal from a low level to a high level, and the change of the second clock signal from a high level to a low level can trigger the change of the second sampling signal from a low level to a high level. Specifically, the sum of the high level duration of the second clock signal and the high level duration of the second sampling signal is less than or equal to the duration during which the charging signal and the discharging signal are simultaneously at a low level, that is, the above-mentioned preset duration. The high level pulse width of the first sampling signal can be equal to the high level pulse width of the second sampling signal. The high level pulse width of the first sampling signal and the high level pulse width of the second sampling signal can both be less than the high level pulse width of the first clock signal. Furthermore, the high level pulse width of the first sampling signal and the high level pulse width of the second sampling signal can be one tenth of the clock signal period.

[0065] When the first clock signal and the second clock signal are both at a low level, the reset signal is at a high level. The frequency of the reset signal may be equal to the frequency of the clock signal.

[0066] Based on the timing relationship of the above-mentioned signals, the circuit structure of each component included in the RC oscillator 10 is described below.

[0067] See first Figure 3 . Figure 3 The circuit structure of the first voltage generator is exemplarily shown.

[0068] like Figure 3 As shown, the first voltage generator 110 may include: a resistor R11, a resistor R12, and a capacitor C11. The first end of the resistor R11 is connected to the power supply, the second end of the resistor R11 is connected to the first end of the resistor R12, and the resistor R12 is connected in parallel with the capacitor C11. The voltage at the second end of the resistor R11 is the first voltage V REF .

[0069] Specifically, the first voltage V REF The power supply is generated by voltage division through resistors R11 and R12. Capacitor C11 is a filter capacitor that can be used to filter out high-frequency noise from the power supply.

[0070] Figure 4 An exemplary circuit structure of the second voltage generator is shown.

[0071] like Figure 4 As shown, the second voltage generator 120 may include: a first resistor R13, a sixth capacitor C13, an eleventh switch S11, and a twelfth switch S12.

[0072] Specifically, the eleventh switch S11 and the twelfth switch S12 are both high-level conductive switches. The eleventh switch S11 is controlled by the charging signal, and the twelfth switch S12 is controlled by the discharging signal.

[0073] That is, the eleventh switch S11 is closed when the charging signal is high, and is opened when the charging signal is low. The twelfth switch S12 is closed when the discharging signal is high, and is opened when the discharging signal is low.

[0074] Possibly, the eleventh switch S11 and the twelfth switch S12 may be NPN transistors, which are turned on when the base of the NPN transistor is at a high level.

[0075] Possibly, the eleventh switch S11 and the twelfth switch S12 may be NMOS transistors, which are turned on when the gates of the NMOS transistors are at a high level.

[0076] Specifically, the first end of the first resistor R13 is connected to the power supply through the eleventh switch S11, the second end of the first resistor R13 is connected to the first end of the sixth capacitor C13, and the sixth capacitor C13 is connected in parallel with the twelfth switch S12. PERIOD is the voltage at the first terminal of the sixth capacitor C13.

[0077] Specifically, when the charging signal is at a high level, the discharging signal is at a low level. At this time, the eleventh switch S11 is closed and the twelfth switch S12 is disconnected. The power supply can charge the sixth capacitor C13 through the first resistor R13, and the charging time is one clock cycle (the charging signal is a two-frequency division of the clock signal). When one clock cycle ends, the charging signal is at a low level and the eleventh switch is disconnected. The voltage at the first end of the sixth capacitor C13 will remain unchanged and wait to be sampled by the subsequent circuit (i.e., the first amplifier 130). The voltage at the first end of the sixth capacitor C13 is the second voltage V PERIOD Among them, V PERIOD The calculation formula is as follows:

[0078]

[0079] Among them, V 电源is the voltage value of the power supply, period is the duration of the high level of the charging signal (equal to the clock signal period), R13 is the resistance value of the first resistor, and C13 is the capacitance value of the sixth capacitor.

[0080] During the sampling process, the charging signal and the discharging signal are both at low level. The duration during which the charging signal and the discharging signal are both at low level can be referred to as a preset duration.

[0081] When the subsequent circuit completes sampling, the discharge signal changes from a low level to a high level, the twelfth switch S12 closes, the sixth capacitor C13 begins to discharge, and the voltage on the sixth capacitor C13 can become 0. When the next charging cycle arrives, the discharge signal can change from a high level to a low level, and the charge signal can change from a low level to a high level at the same time.

[0082] Further, Figure 5 Another circuit structure of the second voltage generator is exemplarily shown.

[0083] like Figure 5 As shown, the second voltage generator 120 may include, in addition to the first resistor R13 , the sixth capacitor C13 , the eleventh switch S11 , and the twelfth switch S12 , a seventh capacitor C12 and a thirteenth switch S10 .

[0084] The thirteenth switch S10 is similar to the eleventh switch S11 and the twelfth switch S12 and can be a high-level conductive switch. The thirteenth switch S10 is controlled by the second clock signal.

[0085] That is, the thirteenth switch S10 is closed when the second clock signal is at a high level, and the thirteenth switch S10 is opened when the second clock signal is at a low level.

[0086] Specifically, from Figure 2 The timing relationship between the various signals shown in the figure shows that when the second clock signal is high, the charging signal and the discharging signal are both low. If the second clock signal is high, the thirteenth switch S10 is closed, S11 is open, the seventh capacitor C12 is connected to the circuit, and V R The residual charge at this point can flow to the seventh capacitor C12, making V R The point becomes a low-speed node to ensure that the second voltage V sampled by the subsequent circuit is PERIOD Maintain stability and reduce jitter of clock signals.

[0087] Figure 6 The circuit structure of the first amplifier is exemplarily shown.

[0088] like Figure 6As shown, the first amplifier 130 may include a first input terminal, a second input terminal, a first amplifying circuit, a second amplifying circuit, a first output terminal, and a second output terminal. The first amplifying circuit and the second amplifying circuit may share a voltage-to-current conversion circuit.

[0089] The first input terminal is connected to the first voltage generator 110 and is used to input the first voltage V generated by the first voltage generator 110. REF .

[0090] The second input terminal is connected to the second voltage generator 120 and is used to input the second voltage V generated by the second voltage generator 120. PERIOD .

[0091] The first output terminal is used to output a third voltage V P The third voltage V P is the first voltage V REF The voltage output after passing through the first amplifier circuit.

[0092] The second output terminal is used to output a fourth voltage V N The fourth voltage V N The second voltage V PERIOD The voltage output after passing through the second amplifier circuit.

[0093] Next, we will introduce the structures of the voltage-current conversion circuit, the first amplifier circuit and the second amplifier circuit in turn, and then combine the structures of the voltage-current conversion circuit, the first amplifier circuit and the second amplifier circuit and Figure 2 The timing relationship between the various signals shown introduces the operation process of the first amplifier.

[0094] See also Figure 6 The voltage-current conversion circuit may include: a first switch S15, a second switch S16, a first capacitor C14 and a MOS transistor N11.

[0095] The first switch S15 and the second switch S16 are both high-level conductive switches and are controlled by a reset signal.

[0096] That is, the first switch S15 and the second switch S16 are both closed when the reset signal is at a high level, and the first switch S15 and the second switch S16 are both opened when the reset signal is at a low level.

[0097] The first capacitor C14 is connected in parallel with the second switch S16, a first terminal of the first capacitor C14 is connected to the source of the MOS transistor N11, a second terminal of the first capacitor C14 is grounded, and a gate of the MOS transistor N11 is grounded via the first switch S15.

[0098] The MOS transistor N11 may be an N-type MOS transistor.

[0099] Please refer again Figure 6 The first amplifying circuit may include: a third switch S14, a voltage-current conversion circuit, a fourth switch S17, a fifth switch S19, a sixth switch S21, a second capacitor C18, and a third capacitor C16.

[0100] The third switch S14, the fourth switch S17, the fifth switch S19 and the sixth switch S21 are all high-level conductive switches. The third switch S14 and the fourth switch S17 are controlled by the first clock signal, the fifth switch S19 is controlled by the first sampling signal, and the sixth switch S21 is controlled by the reset signal.

[0101] That is, the third switch S14 and the fourth switch S17 are both closed when the first clock signal is at a high level, and are both opened when the first clock signal is at a low level. The fifth switch S19 is closed when the first sampling signal is at a high level, and is opened when the first sampling signal is at a low level. The sixth switch S21 is closed when the reset signal is at a high level, and is opened when the reset signal is at a low level.

[0102] The first input terminal is connected to the gate of the MOS transistor N11 through the third switch S14. The drain of the MOS transistor N11 is connected to the first terminal of the second capacitor C18 through the fourth switch S17. The second terminal of the second capacitor C18 is grounded.

[0103] The third capacitor C16 is connected in parallel with the sixth switch S21. The first end of the third capacitor C16 is connected to the power supply, and the second end of the third capacitor C16 is connected to the first end of the second capacitor C18. When the fifth switch S19 is closed, the voltage at the first end of the second capacitor C18 is the third voltage V P .

[0104] Please refer again Figure 6 The second amplifying circuit may include: a seventh switch S13, a voltage-current conversion circuit, an eighth switch S18, a ninth switch S20, a tenth switch S22, a fourth capacitor C15, and a fifth capacitor C17.

[0105] The seventh switch S13, the eighth switch S18, the ninth switch S20 and the tenth switch S22 are all high-level conductive switches. The seventh switch S13 and the eighth switch S18 are controlled by the second clock signal, the ninth switch S20 is controlled by the second sampling signal, and the tenth switch S22 is controlled by the reset signal.

[0106] That is, the seventh switch S13 and the eighth switch S18 are both closed when the second clock signal is at a high level, and are both opened when the second clock signal is at a low level. The ninth switch S20 is closed when the second sampling signal is at a high level, and is opened when the second sampling signal is at a low level. The tenth switch S22 is closed when the reset signal is at a high level, and is opened when the reset signal is at a low level.

[0107] The second input terminal is connected to the gate of the MOS transistor N11 through the seventh switch S13. The drain of the MOS transistor N11 is connected to the first terminal of the fourth capacitor C15 through the eighth switch S18. The second terminal of the fourth capacitor C15 is grounded.

[0108] The fifth capacitor C17 is connected in parallel with the tenth switch S22. The first end of the fifth capacitor C17 is connected to the power supply, and the second end of the fifth capacitor C17 is connected to the first end of the fourth capacitor C15. When the ninth switch S20 is closed, the voltage at the first end of the fourth capacitor C15 is the fourth voltage V N .

[0109] The second capacitor C18 and the fourth capacitor C15 have the same capacitance, and the third capacitor C16 and the fifth capacitor C17 have the same capacitance.

[0110] Next, the voltage-current conversion circuit, the first amplifier circuit and the second amplifier circuit are combined with the structure and Figure 2 The timing relationship between the various signals shown introduces the operation process of the first amplifier.

[0111] Still refer to Figure 6 When the first clock signal is high, the reset signal and the first sampling signal are both low. At this time, the third switch S14 and the fourth switch S17 are closed, and the first switch S15, the second switch S16, the sixth switch S21 and the fifth switch S19 are all open. The voltage V GATE That is the first voltage V REF MOS tube N11 can turn the first voltage V REF The MOS transistor N11 charges the first capacitor C14, and the fourth switch S17 is closed to discharge the current of the MOS transistor N11 to the second capacitor C18 and the third capacitor C16.

[0112] When the first clock signal changes from high level to low level, the third switch S14 and the fourth switch S17 are disconnected, the first capacitor C14 stops charging, and the second capacitor C18 and the third capacitor C16 stop discharging. The first sampling signal changes from low level to high level, and the voltage at the first end of the second capacitor C18 is the third voltage V P After the first sampling signal changes back to a low level, the fifth switch S19 is disconnected, and the third voltage VP Will be maintained, at this time the second clock signal has not yet become high level, the reset signal becomes high level, the first switch S15 is closed, the voltage V GATE The second switch S16 is closed to reset the charge on the first capacitor C14, and the sixth switch S21 is closed to reset the charge on the third capacitor C16.

[0113] When the second clock signal is high, the reset signal and the second sampling signal are both low. At this time, the seventh switch S13 and the eighth switch S18 are closed, and the first switch S15, the second switch S16, the tenth switch S22 and the ninth switch S20 are all open. The voltage V GATE The second voltage V PERIOD MOS tube N11 can turn the second voltage V PERIOD The MOS transistor N11 charges the first capacitor C14, and the eighth switch S18 is closed to discharge the current of the MOS transistor N11 to the fourth capacitor C15 and the fifth capacitor C17.

[0114] When the second clock signal changes from high level to low level, S13 and S18 are disconnected, the first capacitor C14 stops charging, and the fourth capacitor C15 and the fifth capacitor C17 stop discharging. The second sampling signal changes from low level to high level, and the voltage at the first end of the fourth capacitor C15 is the fourth voltage V N After the second sampling signal changes back to a low level, the ninth switch S20 is disconnected, and the fourth voltage V N Will be maintained, at this time the first clock signal has not yet become high level, the reset signal becomes high level, the first switch S15 is closed, the voltage V GATE The second switch S16 is closed to reset the charge on the first capacitor C14, and the tenth switch S22 is closed to reset the charge on the fifth capacitor C17.

[0115] If the first voltage V REF and the second voltage V PERIOD There is a difference between the discharge voltages of the MOS tube N11 to the second capacitor C18 and the fourth capacitor C15, so that the third voltage V P and the fourth voltage V N There are differences between them.

[0116] Specifically, the gain A1 of the first amplifier 130 is defined as follows:

[0117]

[0118] The specific expression of the gain A1 of the first amplifier 130 is as follows:

[0119]

[0120] in, is the ratio of the high level duration of the first clock signal to the period of the first clock signal, or is the ratio of the high-level duration of the second clock signal to the period of the second clock signal; Gm is the transconductance of the MOS transistor N11 (the current change value generated by the unit voltage change); Freq is the frequency of the first clock signal or the second clock signal; Cap is the capacitance of the third capacitor C16 or the fifth capacitor C17.

[0121] When a low-frequency noise voltage exists in the MOS transistor N11, the noise current generated by the MOS transistor N11 will affect the third voltage V P and the fourth voltage V N Produces the same voltage change.

[0122] The second amplifier 140 is a differential amplifier, which is used to amplify the third voltage V P and the fourth voltage difference V N The second amplifier 140 may include a third input terminal, a fourth input terminal and a third output terminal. The third input terminal may be connected to the first output terminal of the first amplifier 130 for inputting a third voltage V P The fourth input terminal can be connected to the second output terminal of the first amplifier 130 for inputting a fourth voltage V N The third output terminal can be used to output a fifth voltage V OUT .

[0123] When the second amplifier 140 is connected to the third voltage V P and the fourth voltage V N When performing differential amplification, the noise generated by MOS tube N11 can be P -V N The calculation is canceled.

[0124] The closed-loop noise N of the second amplifier 140, the low-pass filter 150, and the voltage-controlled oscillator 160 in the loop can be expressed as follows:

[0125]

[0126] Wherein, Noise is the equivalent input noise of the second amplifier 140, the low-pass filter 150, and the voltage-controlled oscillator 160 to the input end of the second-stage amplifier, T is the loop gain, and A RC is the gain of the second voltage generator, and A1 is the gain of the first amplifier 130 .

[0127] It can be seen from equation (4) that the higher the gain of the first amplifier 130 , the smaller the noise N of the second amplifier 140 .

[0128] Therefore, the first amplifier 130 can not only avoid the noise introduced by itself, but also reduce the noise of the second amplifier 140, the low-pass filter 150, and the voltage-controlled oscillator 160, thereby reducing the internal noise of the RC oscillator and the jitter of the clock signal.

[0129] Figure 7 The circuit structure of the low-pass filter 150 is exemplarily shown.

[0130] like Figure 7 As shown, the low-pass filter 150 may include: a resistor R15, a capacitor C19, and a capacitor C20.

[0131] The first end of the resistor R15 is connected to the third output end of the second amplifier 140 for inputting the fifth voltage V OUT The second end of R15 can be connected to the first end of capacitor C19, the second end of capacitor C19 can be connected to the first end of capacitor C20, and the second end of capacitor C20 can be connected to the first end of R15. The second end of capacitor C20 can be connected to the first end of resistor R15. The second end of capacitor C20 can be connected to voltage-controlled oscillator 160, and the voltage at the second end of capacitor C20 is the control voltage V CTRL .

[0132] Specifically, capacitor C19 serves as the main filtering capacitor, providing the primary pole for RC oscillator 10. Due to the presence of two amplifiers in RC oscillator 10, namely, first amplifier 130 and second amplifier 140, two poles are generated in RC oscillator 10. To ensure the stability of RC oscillator 10, capacitor C19 and resistor R15 are connected in series to create a zero point, which can be used to offset the primary pole generated by first amplifier 130. Capacitor C20 and resistor R15 create a high-frequency pole (this pole is well outside the system bandwidth and will not affect loop stability), which can be used to filter out high-frequency ripple in RC oscillator 10.

[0133] The switches involved in the aforementioned embodiments of the present application are all high-level conduction switches. However, the switches involved in the embodiments of the present application may also be low-level conduction switches.

[0134] Possibly, the low-level conduction switch may be a PNP transistor, which is turned on when the base of the PNP transistor is at a low level.

[0135] Possibly, the low-level conduction switch may also be a PMOS transistor. When the gate of the PMOS transistor is at a low level, the PMOS transistor is turned on.

[0136] When all switches are turned on at a low level, the signals generated by pulse generator 170 have the opposite high level compared to the signals generated when the switches are turned on at a high level. That is, if the signal generated by pulse generator 170 is high when the switches are turned on at a high level, it will be low when the switches are turned on at a low level. If the signal generated by pulse generator 170 is low when the switches are turned on at a high level, it will be high when the switches are turned on at a low level. This is not detailed here.

[0137] The MOS transistor N11 involved in the aforementioned embodiments of the present application is an N-type MOS transistor. However, the present application is not limited thereto and the MOS transistor N11 involved in the embodiments of the present application may also be a P-type MOS transistor.

[0138] In the case where the MOS transistor N11 is a P-type MOS transistor, except that the source of the MOS transistor N11 is connected to the power supply via the first capacitor C14 and the first end of the third capacitor C16 or the fifth capacitor C17 is grounded, the other components in the first amplifier 130 and the connection relationship of each component are the same as those in FIG. Figure 6 The consistency shown is not repeated here.

[0139] The above is merely a specific implementation of this embodiment, but the scope of protection of this embodiment is not limited thereto. Any changes or substitutions within the technical scope disclosed in this embodiment should be included in the scope of protection of this embodiment. Therefore, the scope of protection of this embodiment should be based on the scope of protection of the claims.

Claims

1. An integrated circuit, characterized in that: The integrated circuit comprises: a first amplifier and a second amplifier; wherein: The first amplifier includes: a first input terminal, a second input terminal, a first amplifying circuit, a second amplifying circuit, a first output terminal and a second output terminal; The first input terminal is used to input a first voltage V REF The second input terminal is used to input a second voltage V PERIOD ; The first output terminal is used to output a third voltage V P , the third voltage V P The first voltage V REF the voltage after passing through the first amplifying circuit; The second output terminal is used to output a fourth voltage V N , the fourth voltage V N The second voltage V PERIOD the voltage after passing through the second amplifying circuit; Wherein, the first amplifying circuit and the second amplifying circuit share a voltage-to-current conversion circuit; The second amplifier includes a third input terminal, a fourth input terminal and a third output terminal; The third input terminal is used to input the third voltage V P ; The fourth input terminal is used to input the fourth voltage V N ; The third output terminal is used to output a fifth voltage V OUT ; The integrated circuit further includes: a voltage controlled oscillator; the voltage controlled oscillator is configured to generate a voltage based on the fifth voltage V OUT Get the clock signal.

2. The integrated circuit according to claim 1, wherein: The integrated circuit further comprises: a low-pass filter; wherein: The fifth voltage V OUT The control voltage V is obtained by the low-pass filter CTRL ; The control voltage V CTRL A clock signal is obtained through the voltage-controlled oscillator.

3. The integrated circuit according to claim 2, wherein: The integrated circuit further includes: a pulse generator; The pulse generator is configured to generate a control signal for controlling the first amplifier according to the clock signal.

4. The integrated circuit according to claim 3, wherein: The control signal includes a first clock signal, a second clock signal and a reset signal; The voltage-current conversion circuit includes: a first switch (S15), a second switch (S16), a first capacitor (C14) and a MOS transistor (N11); The first switch (S15) and the second switch (S16) are both high-level conduction switches, and the first switch (S15) and the second switch (S16) are both controlled by the reset signal; The first capacitor is connected in parallel to the second switch (S16), a first end of the first capacitor (C14) is connected to the source of the MOS transistor (N11), and a second end of the first capacitor (C14) is grounded; The gate of the MOS transistor (N11) is grounded through the first switch (S15).

5. The integrated circuit according to claim 4, wherein: The control signal also includes: a first sampling signal; The first amplifying circuit includes: a third switch (S14), the voltage-current conversion circuit, a fourth switch (S17), a fifth switch (S19), a sixth switch (S21), a second capacitor (C18) and a third capacitor (C16); The third switch (S14), the fourth switch (S17), the fifth switch (S19) and the sixth switch (S21) are all high-level conduction switches, the third switch (S14) and the fourth switch (S17) are controlled by the first clock signal, the fifth switch (S19) is controlled by the first sampling signal, and the sixth switch (S21) is controlled by the reset signal; The first input end is connected to the gate of the MOS transistor (N11) through the third switch (S14); The drain of the MOS transistor (N11) is connected to the first end of the second capacitor (C18) through the fourth switch (S17), and the second end of the second capacitor (C18) is grounded; The third capacitor (C16) is connected in parallel to the sixth switch (S21), a first end of the third capacitor (C16) is connected to a power supply, and a second end of the third capacitor (C16) is connected to a first end of the second capacitor (C18); The fifth switch (S19) is connected to the first end of the second capacitor (C18); when the fifth switch (S19) is closed, the voltage at the first end of the second capacitor (C18) is the third voltage V P .

6. The integrated circuit according to claim 5, wherein: The control signal also includes a second sampling signal; The second amplifying circuit includes: a seventh switch (S13), the voltage-current conversion circuit, an eighth switch (S18), a ninth switch (S20), a tenth switch (S22), a fourth capacitor (C15) and a fifth capacitor (C17); The seventh switch (S13), the eighth switch (S18), the ninth switch (S20) and the tenth switch (S22) are all high-level conduction switches, the seventh switch (S13) and the eighth switch (S18) are controlled by the second clock signal, the ninth switch (S20) is controlled by the second sampling signal, and the tenth switch (S22) is controlled by the reset signal; The second input end is connected to the gate of the MOS transistor (N11) through the seventh switch (S13); The drain of the MOS transistor (N11) is connected to the first end of the fourth capacitor (C15) through the eighth switch (S18), and the second end of the fourth capacitor (C15) is grounded; The fifth capacitor (C17) is connected in parallel to the tenth switch (S22), a first end of the fifth capacitor (C17) is connected to the power supply, and a second end of the fifth capacitor (C17) is connected to the first end of the fourth capacitor (C15); The ninth switch (S20) is connected to the first end of the fourth capacitor (C15); when the ninth switch (S20) is closed, the voltage at the first end of the fourth capacitor (C15) is the fourth voltage V N .

7. The integrated circuit according to claim 5 or 6, characterized in that The integrated circuit further includes: a second voltage generator; The pulse generator is further configured to generate a charging signal and a discharging signal for controlling the second voltage generator according to the clock signal; The second voltage generator includes: a first resistor (R13), a sixth capacitor (C13), an eleventh switch (S11) and a twelfth switch (S12); The eleventh switch (S11) and the twelfth switch (S12) are both high-level conduction switches, the eleventh switch (S11) is controlled by the charging signal, and the twelfth switch (S12) is controlled by the discharging signal; A first end of the first resistor (R13) is connected to the power supply via the eleventh switch (S11), a second end of the first resistor (R13) is connected to a first end of the sixth capacitor (C13), and the sixth capacitor (C13) is connected in parallel to the twelfth switch (S12); The second voltage V PERIOD is the voltage at the first terminal of the sixth capacitor (C13).

8. The integrated circuit according to claim 7, wherein: The second voltage generator further includes: a seventh capacitor (C12) and a thirteenth switch (S10); The thirteenth switch (S10) is a high-level conductive switch, and the thirteenth switch (S10) is controlled by the second clock signal; The first end of the seventh capacitor (C12) is connected to the second end of the sixth capacitor (C13), and the second end of the seventh capacitor (C12) is connected to the first end of the first resistor (R13) through the thirteenth switch (S10).

9. The integrated circuit according to claim 7, wherein: The high-level pulse width of the discharge signal is smaller than the low-level pulse width of the charge signal.

10. The integrated circuit according to claim 8, wherein: The high-level pulse width of the discharge signal is smaller than the low-level pulse width of the charge signal.

11. The integrated circuit according to claim 7, wherein: The high level pulse width of the first clock signal is equal to the high level pulse width of the second clock signal; The high-level pulse width of the first clock signal and the high-level pulse width of the second clock signal are both smaller than the high-level pulse width of the charging signal.

12. The integrated circuit according to claim 8 or 9, characterized in that The high level pulse width of the first clock signal is equal to the high level pulse width of the second clock signal; The high-level pulse width of the first clock signal and the high-level pulse width of the second clock signal are both smaller than the high-level pulse width of the charging signal.

13. The integrated circuit according to claim 6, wherein: The high-level pulse width of the first sampling signal and the high-level pulse width of the second sampling signal are both smaller than the high-level pulse width of the first clock signal.

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