Method and apparatus for generating a timing library, and electronic device

Abstract

The present invention discloses a method and apparatus for generating a timing library, and an electronic device. Among them, the method includes: obtaining predetermined information of a target process corner, and generating a timing template based on the predetermined information; performing timing simulation on a kernel module corresponding to the timing template under the target process corner to obtain delay information of each path in a relevant path corresponding to an interface in the kernel module; integrating the delay information of each path into the timing template to obtain timing constraint information of the interface in the kernel module; integrating the predetermined information and the timing constraint information into a library file of the target process corner to obtain a timing library of the target process corner. The present invention solves the technical problem in the related art that when generating a timing library file, since a large number of simulations need to be performed using a high-precision simulation software to scan the timing relationship of the interfaces of the kernel module, the development cycle of the timing library is relatively long.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular, to a method and apparatus for generating a timing library, and an electronic device. Background Art

[0002] In the chip design of the semi-custom process, it is often necessary to call the intellectual property (IP) core modules implemented by the full-custom process. During this call process, the full-custom IP needs to provide corresponding netlist, timing information, power consumption information and other files. Among them, the timing information and power consumption information can both be provided in the lib file. It is equivalent to the lib file provided by the process library in the semi-custom process. Figure 1 It is a schematic diagram of the top-level circuit according to the prior art, as Figure 1 shown. The top-level circuit consists of four semi-custom sub-modules and one full-custom sub-module. The full-custom sub-module needs to provide a timing library file to complete the semi-custom process at the top level.

[0003] The traditional method for generating a timing library file usually needs to use a high-precision simulation software to scan the timing relationship of the interface through a large number of simulations. Figure 2 It is a schematic diagram of the method for generating a timing library file according to the prior art. For the timing data input port, as Figure 2 shown, it is necessary to scan the relationship between the data input and the clock and observe the data output to determine the timing relationship of the data input port relative to the clock input port. For example, the timing of a trigger data input port in the timing library is simply described as follows: 1). Input name, direction, input transition time, port capacitance information; 2). Timing information definition, including: associated clock definition, timing type; 3). Sub-type definition of the timing two-dimensional lookup table, including the definition of the setup time two-dimensional table relative to the clock and the hold time two-dimensional definition, etc.

[0004] Since the high-precision timing simulation at the module level takes a long time, and the scanning method requires multiple simulations. For a module with multiple ports, the extraction of its timing library is very time-consuming and laborious. For example, scanning the setup and hold times at 10 ps steps within ±200 ps requires 40 simulation scans. Assuming that at least 3 process corners need to be scanned, and the transition times of the data input and clock input are scanned at least 3 points each, then at least 40×3×3 = 360 scans are required.

[0005] In addition, Figure 3 It is a schematic diagram of a pure combinational logic path according to the prior art, as Figure 3 shown. For a pure combinational logic path, it is also necessary to scan the input transition time and the output load to obtain the corresponding delay.

[0006] For the timing output port, it is also necessary to scan the output rising delay, output falling delay, output rising transition time, and output falling transition time relative to the clock port.

[0007] In view of the problem in the related art that when generating a timing library file, a large number of simulations need to be performed using a high-precision simulation software to scan the timing relationship of the kernel module interface, resulting in a long development cycle of the timing library, no effective solution has been proposed yet. Summary of the Invention

[0008] Embodiments of the present invention provide a method and apparatus for generating a timing library, and an electronic device, so as to at least solve the technical problem in the related art that when generating a timing library file, a large number of simulations need to be performed using a high-precision simulation software to scan the timing relationship of the kernel module interface, resulting in a long development cycle of the timing library.

[0009] According to one aspect of the embodiments of the present invention, a method for generating a timing library is provided, including: obtaining predetermined information of a target process corner, and generating a timing template based on the predetermined information; performing timing simulation on a kernel module corresponding to the timing template under the target process corner to obtain delay information of each path in relevant paths corresponding to interfaces in the kernel module; integrating the delay information of each path into the timing template to obtain timing constraint information of the interfaces in the kernel module; and integrating the predetermined information and the timing constraint information into a library file of the target process corner to obtain a timing library of the target process corner.

[0010] Optionally, obtaining predetermined information of a target process corner, and generating a timing template based on the predetermined information includes: screening the standard cell library based on the target process corner to obtain the predetermined information from the standard cell library, where the predetermined information includes: general information corresponding to the target process corner, and device timing information related to the timing template; and generating the timing template based on the predetermined information.

[0011] Optionally, performing timing simulation on a kernel module corresponding to the timing template under the target process corner to obtain delay information of each path in relevant paths corresponding to interfaces in the kernel module includes: simulating the interfaces in the kernel module using a predetermined software to obtain timing information of the interfaces in the kernel module; and obtaining delay information of each path in relevant paths corresponding to the interfaces in the kernel module based on the timing information.

[0012] Optionally, the relevant paths corresponding to the interfaces in the kernel module include: a first path from the input port to the internal trigger of the kernel module, a second path from the input port directly to the output port through the combinational logic within the kernel module, and a third path from the internal trigger of the kernel module to the output port.

[0013] Optionally, the first path targets the data input port of the trigger within the kernel module and uses the clock port within the kernel module as the reference port. Under the target process corner, perform timing simulation on the kernel module where the timing template is located to obtain the delay information of the first path, including: performing timing simulation on the kernel module to respectively obtain the delay one of the combinational logic on the first path and the delay two of the clock tree on the first path; taking the delay difference between the delay one and the delay two as the delay information of the first path.

[0014] Optionally, the second path targets the buffer in the standard cell library. Under the target process corner, perform timing simulation on the kernel module where the timing template is located to obtain the delay information of the second path, including: determining the delay three of the output port of the buffer with the same size as the last stage of the combinational logic on the second path in the standard cell library; performing timing simulation on the kernel module to obtain the delay four of the combinational logic on the second path; taking the sum of the delay three and the delay four as the delay information of the second path.

[0015] Optionally, the third path targets the data output port of the trigger within the kernel module and uses the clock port within the kernel module as the reference port. Under the target process corner, perform timing simulation on the kernel module where the timing template is located to obtain the delay information of the third path, including: performing timing simulation on the kernel module to respectively obtain the delay five of the combinational logic on the third path and the delay six of the clock tree on the third path; taking the delay sum of the delay five and the delay six as the delay information of the third path.

[0016] Optionally, integrate the delay information of each path into the timing template to obtain the timing constraint information of the interface in the kernel module, including: determining the compensation value of the delay information of each path; integrating the delay information of each path and the compensation value of the delay information of each path into the timing template to obtain the timing constraint information of the interface in the kernel module.

[0017] According to another aspect of the embodiments of the present invention, there is also provided a device for generating a timing library, including: a generating module, configured to obtain predetermined information of a target process corner and generate a timing template based on the predetermined information; a simulation module, configured to perform timing simulation on a kernel module corresponding to the timing template at the target process corner to obtain delay information of each path in relevant paths corresponding to interfaces in the kernel module; an integrating module, configured to integrate the delay information of each path into the timing template to obtain timing constraint information of interfaces in the kernel module; and an obtaining module, configured to integrate the predetermined information and the timing constraint information into a library file of the target process corner to obtain a timing library of the target process corner.

[0018] Optionally, the generating module includes: a screening unit, configured to screen the standard cell library based on the target process corner to obtain the predetermined information from the standard cell library, where the predetermined information includes: general information corresponding to the target process corner and device timing information related to the timing template; and a generating unit, configured to generate the timing template based on the predetermined information.

[0019] Optionally, the simulation module includes: a first simulation unit, configured to simulate an interface in the kernel module by using predetermined software to obtain timing information of the interface in the kernel module; and an obtaining unit, configured to obtain delay information of each path in relevant paths corresponding to the interface in the kernel module based on the timing information.

[0020] Optionally, the relevant paths corresponding to the interfaces in the kernel module include: a first path from an input port to a trigger inside the kernel module, a second path from the input port directly to an output port through combinational logic inside the kernel module, and a third path from the trigger inside the kernel module to the output port.

[0021] Optionally, the first path takes a data input port of a trigger inside the kernel module as a target port and a clock port inside the kernel module as a reference port. The simulation module includes: a second simulation unit, configured to perform timing simulation on the kernel module to respectively obtain a delay one of combinational logic on the first path and a delay two of a clock tree on the first path; and a first determining unit, configured to use a delay difference between the delay one and the delay two as the delay information of the first path.

[0022] Optionally, the second path targets a buffer in a standard cell library. The simulation module includes: a second determination unit configured to determine a delay three of an output port of a buffer having the same size as the last stage of the combinational logic on the second path in the standard cell library; a third simulation unit configured to perform a timing simulation on the kernel module to obtain a delay four of the combinational logic on the second path; and a third determination unit configured to use the sum of the delay three and the delay four as the delay information of the second path.

[0023] Optionally, the third path targets a data output port of a flip-flop in the kernel module and uses a clock port in the kernel module as a reference port. The simulation module includes: a fourth simulation unit configured to perform a timing simulation on the kernel module to respectively obtain a delay five of the combinational logic on the third path and a delay six of a clock tree on the third path; and a fourth determination unit configured to use the sum of the delay five and the delay six as the delay information of the third path.

[0024] Optionally, the integration module includes: a fifth determination unit configured to determine a compensation value for the delay information of each path; and an integration unit configured to integrate the delay information of each path and the compensation value for the delay information of each path into the timing template to obtain the timing constraint information of the interfaces in the kernel module.

[0025] According to another aspect of an embodiment of the present invention, there is also provided a computer-readable storage medium storing a program file that can be executed to implement the method for generating a timing library as described in any one of the above.

[0026] According to another aspect of an embodiment of the present invention, there is also provided an electronic device including: a memory and a processor, where the memory stores program instructions, and the processor retrieves the program instructions from the memory to execute the method for generating a timing library as described in any one of the above.

[0027] In an embodiment of the present invention, predetermined information of a target process corner is obtained, and a timing template is generated based on the predetermined information; at the target process corner, timing simulation is performed on a kernel module corresponding to the timing template, and delay information of each path in a relevant path corresponding to an interface in the kernel module is obtained; the delay information of each path is integrated into the timing template to obtain timing constraint information of the interface in the kernel module; the predetermined information and the timing constraint information are integrated into a library file of the target process corner to obtain a timing library of the target process corner. Through the method for generating a timing library provided by the embodiment of the present invention, the purpose of obtaining relevant information of a target process corner, integrating the delay information obtained by performing timing simulation on a core module corresponding to a timing template based on the relevant information into a library file of the target process corner, and obtaining a timing library of the target process corner is achieved, the development duration of the timing library is reduced, the development cycle of the timing library is shortened, the technical effect of improving the development efficiency of the timing library is achieved, and further the technical problem that in the related art, when generating a timing library file, since a large number of simulations need to be performed using a high-precision simulation software to scan the timing relationship of the interfaces of the kernel module, the development cycle of the timing library is relatively long is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings described herein are used to provide a further understanding of the present invention, and constitute a part of this application. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute an improper limitation to the present invention. In the drawings:

[0029] Figure 1 is a schematic diagram of a top-level circuit according to the prior art;

[0030] Figure 2 is a schematic diagram of a method for generating a timing library file according to the prior art;

[0031] Figure 3 is a schematic diagram of a purely combinational logic path according to the prior art;

[0032] Figure 4 is a schematic diagram of a kernel module according to an embodiment of the present invention;

[0033] Figure 5 is a flowchart of a method for generating a timing library according to an embodiment of the present invention;

[0034] Figure 6 is a schematic diagram of an optional kernel module according to an embodiment of the present invention;

[0035] Figure 7 is a schematic diagram of a device for generating a timing library according to an embodiment of the present invention;

[0036] Figure 8 is a schematic diagram of a program file according to an embodiment of the present invention;

[0037] Figure 9 Schematic diagram of an electronic device according to an embodiment of the present invention. Detailed implementation manners

[0038] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0040] Embodiment 1

[0041] In terms of structure, a timing library file usually consists of two parts. The first part defines the basic attributes of the physical unit library, including: library name, operating conditions, lookup table format, voltage, current, capacitance, time and other basic units, voltage percentages of circuit propagation time and signal transition time, etc.; the second part defines the basic information of each unit, including the timing and power consumption of the unit, usually represented in the form of a lookup table.

[0042] For the first part, the library name can be defined by oneself, and the other parts can be obtained by referring to the standard cell library. The CELL in the library can be defined as a fully-customized sub-module. The area of the CELL adopts the real information of the layout, and the leakage of the CELL can be obtained through simulation.

[0043] For the second part, first, the paths of one's own modules can be divided. Usually, the timing paths related to an interface of a module can be divided into three categories: <1> input port to internal flip-flop, <2> input directly to output through combinational logic, <3> internal flip-flop to output port. Figure 4 Schematic diagram of a kernel module according to an embodiment of the present invention, as Figure 4As shown, <1> represents the timing path from the input port to the internal flip-flop, <2> represents the timing path from the input directly to the output through combinational logic, and <3> represents the timing path from the internal flip-flop to the output port.

[0044] For the timing path <1> from the input port to the internal flip-flop, the D (data input) port of the flip-flop in the standard cell library can be used as a template, and the reference port is the clock port. By simulating the delays of the combinational logic and the clock tree, and then subtracting the delay of the clock tree from the delay of the combinational logic to obtain the delay difference. When generating the setup time constraint in the timing library, this delay difference is added, and when generating the hold time in the timing library, this delay difference is subtracted. At the same time, a certain margin is added to both the setup time and the hold time.

[0045] For the timing path <2> from the input through combinational logic directly to the output, the BUF in the standard cell library can be used as a template. The constraint information of the combinational data input port in the timing library is represented by the input port of the BUF with the same size as the first stage of the combinational logic in the standard cell library. When generating the delay information of the output port in the timing library, it is represented by the output port of the BUF in the standard cell library with the same size as the last stage of the combinational logic, and the delay of the simulated combinational logic is added at the same time.

[0046] It should be noted that for the transmission transition time of the output port in the timing library, it is represented by the transmission transition time of the output port of the BUF in the standard cell library with the same size as the last stage of the combinational logic.

[0047] For the timing path <3> from the internal flip-flop to the output port, the Q (data output) port of the flip-flop in the standard cell library can be used as a template, and the reference port is the clock port. By simulating the delays of the combinational logic and the clock tree, and then adding the delay of the clock tree to the delay of the combinational logic to obtain the delay sum. When generating the delay information of the output port in the timing library, it is the delay of the Q port of the flip-flop with the same driving ability as the previous stage of the output port plus the sum of the delays of the previous combinational logic and the clock tree.

[0048] It should be noted that for the transmission transition time of the output port in the timing library, it is represented by the transmission transition time of the Q port of the flip-flop in the standard cell library with the same size as the last stage of the combinational logic.

[0049] According to an embodiment of the present invention, a method embodiment of a method for generating a timing library is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0050] Figure 5is a flowchart of a method for generating a timing library according to an embodiment of the present invention, as Figure 5 shown, the method for generating the timing library includes the following steps:

[0051] Step S502, obtain predetermined information of a target process corner, and generate a timing template based on the predetermined information.

[0052] Optionally, the predetermined information of the target process corner can be obtained from a standard cell library, where the standard cell library includes a layout library, a symbol library, a circuit logic library, etc., including combinational logic, sequential logic, functional units, and special type units, and is a basic part in the back-end design process of an integrated circuit chip. Using pre-designed and optimized library cells for automatic logic synthesis and layout and routing can greatly improve the design efficiency and accelerate the time for the product to enter the market.

[0053] In an alternative embodiment, obtaining the predetermined information of the target process corner from the standard cell library and generating a timing template based on the predetermined information may include: screening the standard cell library based on the target process corner to obtain the predetermined information from the standard cell library, where the predetermined information includes: general information corresponding to the target process corner, device timing information related to the timing template; generating a timing template based on the predetermined information.

[0054] For example, after determining the target process corner, the general information in the standard cell library under the target process corner and the timing information of the devices related to the design can be selected, and a timing template is generated based on this information.

[0055] In this embodiment, the general information and the timing information of the devices related to the design can be obtained from the standard cell library first, and the information obtained from the standard cell library is used to generate a timing template, which improves the efficiency of generating the timing library and does not require a large number of scans of the kernel module interface using simulation software, thereby saving the time for generating the timing library.

[0056] As can be seen from the above, in the embodiment of the present invention, the basic information of the timing library can be generated with reference to the standard cell library. As follows, the library name can be defined by oneself, and the CELL name can adopt the module name of the fully-customized sub-module. For example, the basic information of the timing library can be defined in the following ways: 1). Library name; 2). Delay type; 3). Definition of time unit, voltage unit, current unit, resistance unit, and capacitance unit; 4). Definition of input and output level thresholds; 5). Definition of the transmission transition time flip point; 6). Definition of the operating condition name; 7). Temperature definition; 8). Voltage definition; 9) Definition of various look-up table templates; 10). Definition of the wire load model; 11). Definition of the unit name, etc.

[0057] Step S504: At the target process corner, perform timing simulation on the kernel module corresponding to the timing template to obtain the delay information of each path in the relevant paths corresponding to the interfaces in the kernel module.

[0058] As an alternative embodiment, at the target process corner, perform timing simulation on the kernel module corresponding to the timing template to obtain the delay information of each path in the relevant paths corresponding to the interfaces in the kernel module, including: using a predetermined software to simulate the interfaces in the kernel module to obtain the timing information of the interfaces in the kernel module; and obtaining the delay information of each path in the relevant paths corresponding to the interfaces in the kernel module based on the timing information.

[0059] In this embodiment, a predetermined software (e.g., high-precision simulation software) can be used to scan the interfaces in the kernel module, thereby obtaining the timing information of the interfaces in the kernel module; then, based on the scanned timing information, the delay information of each path in the relevant paths corresponding to the interfaces in the kernel module is obtained.

[0060] Step S506: Integrate the delay information of each path into the timing template to obtain the timing constraint information of the interfaces in the kernel module.

[0061] Step S508: Integrate the predetermined information and the timing constraint information into the library file of the target process corner to obtain the timing library of the target process corner.

[0062] As can be seen from the above, in the embodiments of the present invention, the predetermined information corresponding to the target process corner can be obtained from the standard cell library, and the timing template is generated based on this predetermined information; and at this target process corner, perform timing simulation on the kernel module corresponding to the timing template to obtain the delay information of each path in the relevant paths corresponding to the interfaces in the kernel module; then integrate the delay information of each path into the timing module to obtain the timing constraint information of the interfaces in the kernel module, and then integrate the predetermined information and the timing constraint information into the library file of the target process corner to obtain the timing library of the target process corner, achieving the purpose of obtaining the relevant information of the target process corner from the standard cell library, integrating the delay information obtained by performing timing simulation on the core module corresponding to the timing template generated based on the relevant information into the library file of the target process corner, and obtaining the timing library of the target process corner, reducing the development duration of the timing library, shortening the development cycle of the timing library, and achieving the technical effect of improving the development efficiency of the timing library.

[0063] Therefore, through the method for generating a timing library provided by the embodiments of the present invention, the technical problem in the related art that the development cycle of the timing library is relatively long due to the need to use a high-precision simulation software to perform a large number of simulations to scan the timing relationship of the interfaces of the kernel module when generating the timing library file is solved.

[0064] As an alternative embodiment, the relevant paths corresponding to the interfaces in the kernel module include: a first path from the input port to the internal trigger in the kernel module, a second path from the input port directly to the output port through the combinational logic in the kernel module, and a third path from the internal trigger in the kernel module to the output port.

[0065] In each path in this embodiment, as shown in Figure 4 the timing path <1> representing the path from the input port to the internal trigger, the timing path <2> representing the path where the input directly reaches the output through the combinational logic, and the timing path <3> representing the path from the internal trigger to the output port.

[0066] Next, in conjunction with the accompanying drawings, the methods for obtaining the delay information of the above-mentioned first path, second path, and third path in the embodiments of the present invention will be described. Figure 6 is a schematic diagram of an optional kernel module according to an embodiment of the present invention. As shown in Figure 6 in the first path, the target port is IN1 and the reference port is CLK1; in the second path, the target port is IN2 and the output port is OUT1; in the third path, the target port is the input port of the trigger in the kernel module, the reference port is the clock port CLK2 of the kernel module, and the output port is OUT2.

[0067] As an alternative embodiment, the first path uses the data input port of the trigger in the kernel module as the target port and the clock port in the kernel module as the reference port. Under the target process corner, timing simulation is performed on the kernel module where the timing template is located to obtain the delay information of the first path, including: performing timing simulation on the kernel module to separately obtain the delay one of the combinational logic on the first path and the delay two of the clock tree on the first path; taking the delay difference between the delay one and the delay two as the delay information of the first path.

[0068] In this embodiment, for the target port IN1, in the standard cell library, a trigger with the same size of the D and CK ports and the same combinational logic and the first stage of the clock tree can be selected. Taking the setup time when the IN1 pin becomes 0 relative to the falling edge of the clock as an example, the timing description of the D port in the standard cell library can include the following information: the timing type is the setup time relative to the falling edge of the clk, and the timing of the falling edge of the input terminal. Figure 6 Here, the delay difference between the combinational logic and the clock tree is 200 - 100 = 100 ps = 0.1 ns. If a margin of 150 ps = 0.15 ns is reserved, it is necessary to add 0.1 ns and then 0.15 ns to the originally required setup times s1_1, s1_2...

[0069]

[0070] ​As an alternative embodiment, the second path uses the buffer in the standard cell library as the target port. Under the target process corner, a timing simulation is performed on the kernel module where the timing template is located to obtain the delay information of the second path, including: determining the delay three of the output port of the buffer with the same size as the last stage of the combinational logic on the second path in the standard cell library; performing a timing simulation on the kernel module to obtain the delay four of the combinational logic on the second path; and taking the sum of the delay three and the delay four as the delay information of the second path.

[0071] In this embodiment, for CLK1 / CLK2 / IN2, it only needs to be defined according to the input pins of the BUF with the same size in the standard cell library. For example, the following information can be defined: the capacitance, direction, and the maximum acceptable input transition time of the CLK1 port.

[0072] For OUT1, it can be defined according to the output pins of the BUF with the same size in the standard cell library plus the corresponding combinational logic delay. For example, the timing definition for the OUT1 port can include: 1). Port name definition; 2). Port direction definition; 3). Maximum capacitance definition; 4). Minimum capacitance definition; 5). Maximum transition time definition; 6). Timing definition, including the corresponding timing port, the timing type is combinational logic type, and the falling delay timing two-dimensional lookup table definition.

[0073] Since the combinational logic delay is 500ps = 0.5ns, the timing library description of OUT1 obtained after addition needs to increase by 0.5ns on the basis of the original two-dimensional timing tables d1_1, d1_2...

[0074] As an alternative embodiment, the third path uses the data output port of the flip-flop in the kernel module as the target port and the clock port in the kernel module as the reference port. Under the target process corner, a timing simulation is performed on the kernel module where the timing template is located to obtain the delay information of the third path, including: performing a timing simulation on the kernel module to obtain the delay five of the combinational logic on the third path and the delay six of the clock tree on the third path respectively; and taking the sum of the delay five and the delay six as the delay information of the third path.

[0075] In this embodiment, for OUT2, a timing library can be generated by using the delay of the Q port of the flip-flop with the same driving ability as the previous stage of the output port plus the sum of the previous combinational logic and clock tree delays.

[0076] That is, in the embodiment of the present invention, for the third path, from the internal trigger to the output port, the Q (data output) port of the flip-flop in the standard cell library is used as a template, and the reference port is the clock port. By simulating the delay of the combinational logic and the clock tree after the flip-flop output, and then adding the delay of the combinational logic and the delay of the clock tree to obtain the sum of delays. When generating the delay information of the output port in the timing library, the delay of the Q port of the flip-flop with the same driving ability as the previous stage of the output port is added to the sum of the previous combinational logic and the clock tree delays.

[0077] Among them, the description of the Q port of the flip-flop in the standard cell library may include the following definitions: 1). Port name; 2). Port direction; 3). Maximum load capacitance; 4). Maximum transition time; 5). Timing information, for example, the relevant clock pin, timing type, two-dimensional lookup table of delay information corresponding to the rising and falling flips of the output port, and two-dimensional lookup table of transition time corresponding to the rising and falling flips of the output port.

[0078] For the simulated clock tree delay of 150 ps and combinational logic delay of 250 ps, 400 ps = 0.4 ns needs to be added. That is, 0.4 ns of delay is added to the values d1_1, d1_2... in the two-dimensional lookup table of delay information corresponding to the rising and falling flips of the output port.

[0079] For other process corners, the timing library can be generated using the same method.

[0080] In an alternative embodiment, the delay information of each path is integrated into the timing template to obtain the timing constraint information of the interface in the kernel module, including: determining the compensation value of the delay information of each path; integrating the delay information of each path and the compensation value of the delay information of each path into the timing template to obtain the timing constraint information of the interface in the kernel module.

[0081] Since the timing information provided in the embodiment of the present invention is not all obtained by high-precision simulation, there will be a certain deviation in the timing information. To ensure that the deviation affects the timing analysis of the corresponding interface module, a certain margin is reserved for the corresponding timing information. For example, if the calculated required setup time is 500 ps, a margin of 100 ps can be reserved, and the required setup time marked in the final timing library is 600 ps.

[0082] Through the method for generating a timing library provided by the embodiments of the present invention, a timing library can be developed based on a standard cell library as a template, and the corresponding delays can be obtained through simulation, and the timing information can be obtained by fitting with the standard target. Moreover, a certain margin is reserved in the timing library to ensure the design requirements, which is a relatively simple method for quickly generating a timing library and can accelerate project development. It fits the relative timing library of the module ports by using the timing of the standard cell library with the same process as a template and combining the timing simulation containing the physical information of the layout. Since it uses the standard cell library as a template, only the corresponding delay information needs to be simulated at three process corners, and then a certain margin is reserved to quickly obtain a relatively accurate timing library. That is, by using the method for generating a timing library provided by the embodiments of the present invention and using the standard cell library as a template, a relatively accurate timing library can be obtained with only a small amount of simulation, which greatly reduces the workload of library building in actual projects and also shortens the development cycle.

[0083] Embodiment 2

[0084] According to another aspect of the embodiments of the present invention, a device for generating a timing library is further provided. Figure 7 is a schematic diagram of the device for generating a timing library according to the embodiments of the present invention, as Figure 7 shown. The device for generating a timing library may include: a generation module 71, a simulation module 73, an integration module 75, and an acquisition module 77. The device for generating a timing library will be described below.

[0085] The generation module 71 is configured to obtain predetermined information of a target process corner and generate a timing template based on the predetermined information.

[0086] The simulation module 73 is configured to perform timing simulation on the core module corresponding to the timing template at the target process corner to obtain the delay information of each path in the relevant paths corresponding to the interfaces in the core module.

[0087] The integration module 75 is configured to integrate the delay information of each path into the timing template to obtain the timing constraint information of the interfaces in the core module.

[0088] The acquisition module 77 is configured to integrate the predetermined information and the timing constraint information into the library file of the target process corner to obtain the timing library of the target process corner.

[0089] It should be noted here that the above-mentioned generation module 71, simulation module 73, integration module 75, and acquisition module 77 correspond to steps S502 to S504 in Embodiment 1. The examples and application scenarios implemented by the above modules and the corresponding steps are the same, but are not limited to the content disclosed in Embodiment 1 above. It should be noted that the above modules, as part of the device, can be executed in a computer system such as a set of computer executable instructions.

[0090] As can be seen from the above, in the embodiment of the present invention, the generation module can obtain the predetermined information of the target process corner and generate a timing template based on the predetermined information; then, the simulation module performs timing simulation on the kernel module corresponding to the timing template at the target process corner to obtain the delay information of each path in the relevant paths corresponding to the interfaces in the kernel module; then, the integration module integrates the delay information of each path into the timing template to obtain the timing constraint information of the interfaces in the kernel module; and the acquisition module is used to integrate the predetermined information and the timing constraint information into the library file of the target process corner to obtain the timing library of the target process corner. Through the timing library generation device provided by the embodiment of the present invention, the purpose of obtaining the relevant information of the target process corner, integrating the delay information obtained by performing timing simulation on the core module corresponding to the timing template based on the relevant information into the library file of the target process corner, and obtaining the timing library of the target process corner is achieved, the development duration of the timing library is reduced, the development cycle of the timing library is shortened, the technical effect of improving the development efficiency of the timing library is achieved, and the technical problem in the related art that the development cycle of the timing library is relatively long due to the need to use a high-precision simulation software to perform a large number of simulations to scan the timing relationship of the interfaces of the kernel module when generating the timing library file is solved.

[0091] Optionally, the generation module includes: a screening unit for screening the standard cell library based on the target process corner to obtain the predetermined information from the standard cell library, where the predetermined information includes: general information corresponding to the target process corner and device timing information related to the timing template; a generation unit for generating a timing template based on the predetermined information.

[0092] Optionally, the simulation module includes: a first simulation unit for simulating the interfaces in the kernel module using a predetermined software to obtain the timing information of the interfaces in the kernel module; an acquisition unit for obtaining the delay information of each path in the relevant paths corresponding to the interfaces in the kernel module based on the timing information.

[0093] Optionally, the relevant paths corresponding to the interfaces in the kernel module include: a first path from the input port to the internal flip-flop of the kernel module, a second path from the input port directly to the output port through the combinational logic in the kernel module, and a third path from the internal flip-flop of the kernel module to the output port.

[0094] Optionally, for the first path with the data input port of the flip-flop in the kernel module as the target port and the clock port in the kernel module as the reference port, the simulation module includes: a second simulation unit for performing timing simulation on the kernel module to obtain the delay one of the combinational logic on the first path and the delay two of the clock tree on the first path respectively; a first determination unit for taking the delay difference between the delay one and the delay two as the delay information of the first path.

[0095] Optionally, the second path targets the buffer in the standard cell library as the target port. The simulation module includes: a second determination unit configured to determine the delay three of the output port of the buffer with the same size as the last stage of the combinational logic on the second path in the standard cell library; a third simulation unit configured to perform timing simulation on the kernel module to obtain the delay four of the combinational logic on the second path; and a third determination unit configured to use the sum of the delay three and the delay four as the delay information of the second path.

[0096] Optionally, the third path targets the data output port of the flip-flop in the kernel module as the target port and the clock port in the kernel module as the reference port. The simulation module includes: a fourth simulation unit configured to perform timing simulation on the kernel module to respectively obtain the delay five of the combinational logic on the third path and the delay six of the clock tree on the third path; and a fourth determination unit configured to use the sum of the delay five and the delay six as the delay information of the third path.

[0097] Optionally, the integration module includes: a fifth determination unit configured to determine the compensation value of the delay information of each path; and an integration unit configured to integrate the delay information of each path and the compensation value of the delay information of each path into the timing template to obtain the timing constraint information of the interface in the kernel module.

[0098] Embodiment 3

[0099] According to another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium. The computer-readable storage medium of the present application stores a program file 803 (as shown in Figure 8 ) that can implement all the above methods (i.e., the method for generating a timing library). The program file 803 can be stored in the above storage medium in the form of a software product, including several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods in various embodiments of the present application. The foregoing storage device includes: various media that can store program codes such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc, or a terminal device such as a computer, a server, a mobile phone, or a tablet.

[0100] Embodiment 4

[0101] According to another aspect of the embodiments of the present invention, there is also provided an electronic device. Figure 9 It is a schematic diagram of the electronic device according to the embodiments of the present invention. As shown in Figure 9 , the electronic device includes a memory 901 and a processor 902 that are connected to each other.

[0102] The memory 901 is used to store program instructions for implementing the method for generating the timing library according to any one of the above.

[0103] The processor 902 is used to execute the program instructions stored in the memory 901.

[0104] Among them, the processor 902 can also be called a CPU (Central Processing Unit, central processing unit). The processor 902 may be an integrated circuit chip with signal processing capabilities. The processor 902 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0105] The memory 901 can be a memory module, a TF card, etc., and can store all the information in the electronic device, including the input original data, computer programs, intermediate operation results, and final operation results are all saved in the memory. It stores and retrieves information according to the positions specified by the controller. With the memory, the electronic device has a memory function and can ensure normal operation. The memory of the electronic device can be classified into a main memory (RAM) and an auxiliary memory (external memory) according to its use, and there is also a classification method of dividing it into an external memory and an internal memory. The external memory is usually a magnetic medium or an optical disc, etc., and can store information for a long time. The RAM refers to the storage component on the motherboard, which is used to store the data and programs being executed currently, but only used to temporarily store programs and data. When the power is turned off or interrupted, the data will be lost.

[0106] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages and disadvantages of the embodiments.

[0107] In the above embodiments of the present invention, the descriptions of each embodiment have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0108] In the several embodiments provided by the present application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only illustrative. For example, the division of the units can be a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the couplings or direct couplings or communication connections shown or discussed with each other can be through some interfaces, and the indirect couplings or communication connections of the units or modules can be in an electrical or other form.

[0109] The unit described as a separation component may or may not be physically separated. The component displayed as a unit may or may not be a physical unit, that is, it may be located in one place or may be distributed across multiple units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0110] In addition, each functional unit in various embodiments of the present invention may be integrated into one processing unit, may exist separately as individual physical units, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0111] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), mobile hard disks, magnetic disks or optical discs and other various media that can store program codes.

[0112] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A method for generating a timing library, characterized in that, Including: Obtain the predetermined information of the target process corner, and generate a timing template based on the predetermined information; Under the target process corner, perform timing simulation on the kernel module corresponding to the timing template, and obtain the delay information of each path in the relevant path corresponding to the interface in the kernel module; Integrate the delay information of each path into the timing template to obtain the timing constraint information of the interface in the kernel module; Integrate the predetermined information and the timing constraint information into the library file of the target process corner to obtain the timing library of the target process corner; Obtain the predetermined information of the target process corner, and generate a timing template based on the predetermined information, including: screening the standard cell library based on the target process corner to obtain the predetermined information from the standard cell library, where the predetermined information includes: general information corresponding to the target process corner, device timing information related to the timing template; generate the timing template based on the predetermined information; The relevant paths corresponding to the interface in the kernel module include: a first path from the input port to the internal flip-flop of the kernel module, a second path from the input port directly to the output port through the combinational logic in the kernel module, and a third path from the internal flip-flop of the kernel module to the output port; Integrate the delay information of each path into the timing template to obtain the timing constraint information of the interface in the kernel module, including: determining the compensation value of the delay information of each path; integrating the delay information of each path and the compensation value of the delay information of each path into the timing template to obtain the timing constraint information of the interface in the kernel module.

2. The method according to claim 1, wherein Under the target process corner, perform timing simulation on the kernel module corresponding to the timing template, and obtain the delay information of each path in the relevant path corresponding to the interface in the kernel module, including: Use predetermined software to simulate the interface in the kernel module to obtain the timing information of the interface in the kernel module; Obtain the delay information of each path in the relevant path corresponding to the interface in the kernel module based on the timing information.

3. The method according to claim 1, characterized in that, The first path takes the data input port of the flip-flop in the kernel module as the target port and the clock port in the kernel module as the reference port. Under the target process corner, perform timing simulation on the kernel module where the timing template is located to obtain the delay information of the first path, including: Perform timing simulation on the kernel module to obtain the delay one of the combinational logic on the first path and the delay two of the clock tree on the first path respectively; Take the delay difference between the delay one and the delay two as the delay information of the first path.

4. The method according to claim 1, wherein The second path takes the buffer in the standard cell library as the target port. Under the target process corner, perform timing simulation on the kernel module where the timing template is located to obtain the delay information of the second path, including: Determine the delay three of the output port of the buffer with the same size as the last stage of the combinational logic on the second path in the standard cell library; Perform timing simulation on the kernel module to obtain the delay four of the combinational logic on the second path; Use the sum of the said delay three and the said delay four as the delay information of the second path.

5. The method according to claim 1, characterized in that, The third path targets the data output port of the flip-flop in the kernel module and uses the clock port in the kernel module as the reference port. Under the target process corner, perform timing simulation on the kernel module where the timing template is located to obtain the delay information of the third path, including: Perform timing simulation on the kernel module to respectively obtain the delay five of the combinational logic on the third path and the delay six of the clock tree on the third path; Use the sum of the delay five and the delay six as the delay information of the third path.

6. A device for generating a timing library, characterized in that, Include: A generation module, configured to obtain the predetermined information of the target process corner and generate a timing template based on the predetermined information; A simulation module, configured to perform timing simulation on the kernel module corresponding to the timing template under the target process corner to obtain the delay information of each path in the relevant paths corresponding to the interfaces in the kernel module; An integration module, configured to integrate the delay information of each path into the timing template to obtain the timing constraint information of the interfaces in the kernel module; An acquisition module, configured to integrate the predetermined information and the timing constraint information into the library file of the target process corner to obtain the timing library of the target process corner; The generation module includes: a screening unit, configured to screen the standard cell library at the target process corner to obtain the predetermined information from the standard cell library, where the predetermined information includes: general information corresponding to the target process corner and device timing information related to the timing template; a generation unit, configured to generate the timing template based on the predetermined information; The relevant paths corresponding to the interfaces in the kernel module include: a first path from the input port to the flip-flop inside the kernel module, a second path from the input port directly to the output port through the combinational logic inside the kernel module, and a third path from the flip-flop inside the kernel module to the output port; The integration module includes: a fifth determination unit, configured to determine the compensation value of the delay information of each path; an integration unit, configured to integrate the delay information of each path and the compensation value of the delay information of each path into the timing template to obtain the timing constraint information of the interfaces in the kernel module.

7. A computer-readable storage medium, characterized in that Stores a program file that can be executed to implement the method for generating a timing library as described in any one of claims 1 to 5.

8. An electronic device, characterized in that, Include: A memory and a processor, where the memory stores program instructions, and the processor retrieves the program instructions from the memory to execute the method for generating a timing library as described in any one of claims 1 to 5.

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