Column bus driving method for micro display device

Abstract

A method for generating a column signal for use by a pixel array, the method comprising connecting two or more controllable bus buffers in series. The output of each of the two or more controllable bus buffers drives an associated node. The method also includes providing a column data signal to an input of a series-connected string of two or more controllable bus buffers. The method also includes sequentially enabling each of the controllable bus buffers in the series-connected string of two or more controllable bus buffers so that each node is sequentially driven. Each node is electrically coupled to an input of an associated controllable local output buffer. The method also includes sequentially enabling each of the controllable local output buffers in an order associated with the sequential enabling of the controllable bus buffers.

Description

[0001] This application is a divisional application of a patent application with an international application date of February 5, 2015, an international application number of PCT / US2015 / 014628, a national application number of 201580007349.0, and an invention name of “Column bus driving method for a micro display device”.

[0002] Related Applications

[0003] This application claims the benefit of U.S. Provisional Application No. 61 / 935,928, filed on February 5, 2014. The entire teachings of the above application are incorporated herein by reference. Background Art

[0004] Mobile computing devices such as notebook PCs, smart phones, and tablet computing devices are now common tools for producing, analyzing, communicating, and consuming data in business and personal life. As the ease of acquiring digital information increases with high-speed wireless communication technologies becoming ubiquitous, consumers continue to embrace a mobile digital lifestyle. Popular uses of mobile computing devices include displaying large amounts of high-resolution computer graphics information and video content that are typically streamed wirelessly to the device.

[0005] While these devices typically include display screens, the preferred high-resolution, large format display visual experience cannot be easily replicated in such mobile devices because the physical size of such devices is limited to improve mobility. Another disadvantage of the above device types is that the user interface is hand-dependent, typically requiring the user to use a keyboard (physical or virtual) or a touch screen display to enter data or make selections.

[0006] As a result, consumers are looking for hands-free, high-quality, portable, color display solutions to augment or replace their hand-reliant mobile devices. Such display solutions have practical size and weight limitations, which therefore limit available power resources (e.g., battery size). Given limited power resources, reducing the power consumption of the display will increase the amount of time the display can operate on a single charge of the associated power resource. Summary of the invention

[0007] Recently developed microdisplays can provide large format, high resolution color pictures and streaming video in a very small form factor. One application for such a display can be integrated into a wireless headset computer that is worn on the user's head with the display within the user's field of view and in a form factor similar to eyeglasses, audio headphones, or video goggles.

[0008] A "wireless computing headset" device, also referred to herein as a headset computer (HSC) or head mounted display (HMD), includes one or more small, high-resolution microdisplays and associated optics to magnify the image. The high-resolution microdisplays may provide Super Video Graphics Array (SVGA) (800x600) resolution or Extended Graphics Array (XGA) (1024x768) resolution, or higher resolutions known in the art.

[0009] Wireless computing headsets contain one or more wireless computing and communication interfaces that enable data and streaming video capabilities, and provide greater convenience and mobility over hand-reliant devices.

[0010] For more information about such devices, see the following pending patent applications: U.S. application No. 12 / 348,648, filed on January 5, 2009, entitled “Mobile Wireless Display Software Platform for Controlling Other Systems and Devices,” PCT International Application No. PCT / US09 / 38601, filed on March 27, 2009, entitled “Handheld Wireless Display Devices Having High Resolution Display Suitable For Use as a Mobile Internet Device,” and U.S. application No. 61 / 638,419, filed on April 25, 2012, entitled “Improved Headset Computer,” each of which is incorporated herein by reference in its entirety.

[0011] As used herein, “HSC” headset computer, “HMD” head mounted display device, and “wireless computing headset” device may be used interchangeably.

[0012] Embodiments described herein reduce power to a microdisplay, such as embodiments associated with HSC, by selectively enabling and disabling buffers that drive information signals to a pixel array of a microdisplay. An enable control signal to the buffer enables the buffer only when the buffer is needed for driving information to the pixel array.

[0013] In one aspect, the present invention can be a method of generating a column signal for use by a pixel array, the method comprising connecting two or more controllable bus buffers in series. The output of each of the two or more controllable bus buffers drives an associated node. The method also includes providing a column data signal to an input of a series-connected string of the two or more controllable bus buffers, and sequentially enabling each of the controllable bus buffers in the series-connected string of the two or more controllable bus buffers. Each node is driven sequentially with respect to time.

[0014] In one embodiment, for the sequential enabling, the controllable bus buffer receiving the column signal is enabled first. In another embodiment, for the sequential enabling, each enabled controllable bus buffer remains enabled when the next subsequent controllable bus buffer is enabled. In one embodiment, for the sequential enabling, the controllable bus buffer receiving the column signal is enabled last.

[0015] In one embodiment, each node is electrically coupled to an input of an associated controllable local output buffer. Another embodiment further comprises sequentially enabling each of the controllable local output buffers in an order associated with the sequential enabling of the controllable bus buffers. Another embodiment further comprises disabling each of the controllable bus buffers that is not enabled and disabling each of the controllable local output buffers that is not enabled.

[0016] In one embodiment, the controllable bus buffers that are not enabled output a high impedance state. In another embodiment, the controllable bus buffers that are not enabled output a fixed logic state. Another embodiment also includes coordinating the sequential enabling of each controllable bus buffer and each local output buffer with a scan mode associated with the pixel array.

[0017] In another aspect, the present invention may be a column driver for a pixel array, comprising two or more controllable bus buffers and two or more controllable local output buffers connected in series, each controllable bus buffer having an output that drives an associated node, each controllable local output buffer having an input electrically coupled to one of the associated nodes, and each controllable local output buffer having an output that drives one or more columns of the pixel array. The column driver may also include an enable controller that drives one or more bus enable inputs of the two or more controllable bus buffers and drives one or more local output enable inputs of the two or more controllable local output buffers. The enable controller sequentially enables each controllable bus buffer in the series-connected string of the two or more controllable bus buffers so that each node is driven according to a bus sequence.

[0018] In one embodiment, the controller is configured to maintain each controllable bus buffer enabled when a next subsequent controllable bus buffer is enabled.

[0019] In another embodiment, the enabling controller is a state machine. In another embodiment, the enabling controller is a code driven processor.

[0020] In one embodiment, each local output buffer outputs a high impedance state when not enabled. In another embodiment, each local output buffer outputs a fixed logic state when not enabled.

[0021] In one embodiment, one or more columns of the pixel array include one or more DACs, such that the local output buffer drives at least one DAC.

[0022] In another embodiment, the enable controller sequentially enables each controllable local output buffer so that each of the one or more columns of the pixel array is driven according to a local output sequence. In another embodiment, the bus sequence is related to the local output sequence.

[0023] In one embodiment, the two or more controllable bus buffers include a first controllable bus buffer having an input receiving a column data signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The foregoing will be apparent from the following more particular description of example embodiments of the invention as illustrated in the accompanying drawings in which like reference numerals refer to the same parts throughout the different views. The drawings are not necessarily drawn to scale, emphasis instead being placed upon illustrating embodiments of the invention.

[0025] Figure 1 A simple example of a micro display according to the present embodiment is shown.

[0026] Figure 2 Show Figure 1 An enlarged view of the column driver is shown in FIG.

[0027] Figure 3 Show Figure 1 Example of a digital to analog converter in a column driver.

[0028] Figure 4 An example of a column driver architecture is shown.

[0029] Figure 5 An example of a column driver architecture in accordance with the described embodiments is shown. DETAILED DESCRIPTION

[0030] A description of example embodiments of the invention follows.

[0031] The microdisplay described herein can be used in many mobile communication and computing applications such as a headset computer. An example of such a headset computer is disclosed in U.S. Patent Application No. 14 / 540,905, filed on November 13, 2014, entitled “Text Selection Using HMD Head-Tracker and Voice-Command,” the entire contents of which are incorporated herein by reference.

[0032] If Figure 1 As shown in the example embodiment of FIG. 1 , the microdisplay described herein generally includes a pixel array 102 driven by a plurality of data and control signals. In this simple example, the microdisplay 100 includes 20 columns and 16 rows of a total of 320 pixels. As mentioned above, actual practical microdisplays generally have more pixels (e.g., XGA with 1024 columns and 768 rows).

[0033] The microdisplay includes a column driver 104 and a row driver 106 that together provide information to a pixel array 102. The column driver 104 typically provides image information to the pixels, and the row driver 106 provides control information to the pixels.

[0034] The column driver signal 108 for a particular column of pixels 110 may include multiple signals. Figure 2 An enlarged view of column driver 104 is shown for a red-green-blue (RGB) pixel array.

[0035] Figure 2 The first two pixels 202 are shown for a single column 204 of the array. Each pixel 202 includes a red component 206, a green component 208, and a blue component 210. For each column, the column driver 104 drives three information signals; a red signal 212, a green signal 214, and a blue signal 216. These information signals extend to all pixels in the column 204.

[0036] The information signal that drives the pixel is typically an analog signal that is generated from the digital signal by a digital-to-analog converter (DAC). Figure 3 An example of such conversion for one pixel column is shown. Digital buffer 302 drives 30 bits of information (10 bits of red information, 10 bits of green information, and 10 bits of blue information) and provides the 30 bits to a three-channel DAC 304. Each channel within the three-channel DAC 304 converts 10 bits of information into an analog signal; in other words, the three-channel DAC 304 includes a 10-bit red DAC 306, a 10-bit green DAC 308, and a 10-bit blue DAC 310.

[0037] Because the column driver 104 drives a large number of columns in a typical pixel array (eg, up to 1024 or more), the digital portion of the column driver driving the DAC may consist of multiple buses or chains of buses. Figure 4 An example of such a column driver architecture is shown in FIG. 4. An information signal bus 402 is provided to a bus buffer 404, the output of which is provided to another buffer, and so on. The bus may be, for example, as described above. Figure 3 The output of each buffer 404 is referred to as a node - in this example, the nodes are referred to as Node_1 406, Node_2 408, Node_3 410, and Node_N 412.

[0038] Each of the nodes is provided to an input of a controlled (also referred to as controllable) local output buffer (ie, a buffer having an output that can be enabled or disabled by a control signal applied to the buffer).

[0039] exist Figure 4 4, Node_1 406 is applied to the input of a controlled buffer 414 to produce a local output bus OUT_LOCAL_1 416. Similarly, Node_2 408 is used to form a local output bus OUT_LOCAL_2 418, Node_3 410 is used to produce a local output bus OUT_LOCAL_3 420, and so on.

[0040] Similar to Figure 3 In the example shown in , these local output buses are used to drive DACs or groups of DACs. Each local output bus may be required to drive a large number of DACs (e.g., 64 or more DACs corresponding to 64 or more pixel columns).

[0041] One technique for reducing the power used by the microdisplay is to selectively enable a buffer group to selectively drive an associated local output bus so that the buffer group drives only when the buffer group is needed. When the buffer is not driving the associated local output bus, the buffer is set to drive a high impedance state or a fixed logic level (e.g., logic low).

[0042] Figure 4 This technique is illustrated in timing diagram 424 of Signals EN_1, EN_2, EN_3 through EN_N are used to selectively enable outputs 416, 418, 420 through 422, respectively, with respect to time.

[0043] Figure 5 Techniques for further reducing the power required by a microdisplay in accordance with the described embodiments are shown. Figure 5In the example embodiment of FIG. 4 , bus buffers 404 for Node_1 406, Node_2 408, Node_3 410, and Node_N 412 are generated (according to Figure 4 ) is replaced by a controllable bus buffer. Figure 4 The bus buffer 404 in the 406 bus cannot be controlled, so the bus buffer 404 is always enabled, and the outputs Node_1 406, Node_2 408, Node_3 410, and Node_N 412 are constantly driven. The total capacitance associated with driving these nodes is quite significant, especially for micro display arrays with a large number of pixels and wide information data fields (e.g., the example 3×10 bit RGB array described herein).

[0044] The amount of power required by the buffer is related to the active capacitance of the driver multiplied by the square of the voltage being driven (i.e., CV 2 ). Reducing capacitance thus reduces power. The described embodiments reduce the capacitance of driver 404 by replacing those buffers with controlled buffers, and only enabling the controlled buffers when they are needed.

[0045] Figure 5 An example embodiment of a local bus portion of a column driver architecture for a pixel array according to one aspect of the present invention is shown. According to a timing diagram 514, the embodiment controls the activation of input signals PSEN_1 506, PSEN_2 508, PSEN_3 510 to PSEN_N 512 to the corresponding buffer 504. Figure 4 Similarly, when the enable signal (e.g., EN_1) is active, it enables the output of the associated buffer. The PSEN signal is not explicitly shown in Figure 5 However, the PSEN signal is inherently illustrated by the presence or absence of pulses in the Node_1, Node_2, ... Node_N signal lines. When the PSEN_N signal is active (enabled), the Node_N pulse is present. When the PSEN_N signal is inactive (disabled), the Node_N pulse is absent.

[0046] For scanning from left to right, when EN_1 is active, signal PSEN_1 506 is active. Figure 5 As shown in the timing diagram of , when EN_1 is active, only Node_1 is active (i.e., generates a pulse). Although the "inactive" of Node_2, Node_3 to Node_N is shown as "low", Figure 5 In the case where the associated buffer is not enabled, the output may alternatively be in an indeterminate "high impedance" state.

[0047] When EN_2 is active, both PSEN_1 and PSEN_2 are active. Figure 5 As shown in , during the time when EN_2 is active, both Node_1 and Node_2 generate pulses, while Node_3 to Node_N are shown to be inactive.

[0048] When EN_3 is active, PSEN_1 and PSEN_2 and PSEN_3 are active, so Node_1, Node_2 and Node_3 have pulses, while Node_N is inactive for all nodes N greater than 3. Similarly, enable signals EN_4 to EN_N are sequentially activated until all N nodes include drive data (in this example, pulses).

[0049] In the described embodiments, Figure 5 As shown in , enable signals EN_1 to EN_N and PSEN_1 to PSEN_N may be generated by an enable controller 520. The enable controller may be a simple state machine, a combinational logic block driven by a counter, a processor or controller driven by software or firmware code, or any other such signal generator known in the art.

[0050] As about Figure 5 The described sequential activation of buffers 505, such that the output nodes of the buffers are not all constantly activated, may reduce the power requirements of buffers 505 (averaged over time) by 40% or more.

[0051] For scanning from right to left, the above process can be performed in reverse. In other words, initially all PSEN_Ns can be activated to start, and then each PSEN_N can be deactivated one by one (e.g., first PSEN_N-1, then PSEN_N-2, etc.) until all PSEN_Ns are deactivated (and their corresponding buffers 504 are not enabled).

[0052] It will be clear that one or more of the embodiments described herein can be implemented in many different forms of software and hardware. The software code and / or dedicated hardware used to implement the embodiments described herein do not limit the present invention. Therefore, the operation and behavior of the embodiments are described without reference to specific software code and / or dedicated hardware - it is understood that people will be able to design software and / or hardware that implements the embodiments based on the description herein.

[0053] In addition, some embodiments of the present invention can be implemented as logic that performs one or more functions. The logic can be hardware-based, software-based, or a combination of hardware-based and software-based. Some or all of the logic can be stored on one or more tangible computer-readable storage media, and can include computer-executable instructions that can be executed by a controller or processor. Computer-executable instructions can include instructions that implement one or more embodiments of the present invention. Tangible computer-readable storage media can be volatile or non-volatile, and can include, for example, flash memory, dynamic memory, removable disk, and non-removable disk.

[0054] While the invention has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention as encompassed by the following claims.

Claims

1. A micro display device, comprising: Pixel array; A column driver associated with the pixel array comprises: two or more controllable bus buffers connected in series to form a series-connected string of two or more controllable bus buffers, each controllable bus buffer having a first output driving an associated node and also having a bus enable input; two or more controllable local output buffers, each controllable local output buffer having an input electrically coupled to one of the associated nodes and having a second output driving one or more columns of the pixel array and further having a local output enable input; and an enable controller configured to generate a first enable signal for driving respective bus enable inputs of the series-connected string of two or more controllable bus buffers and a second enable signal for driving respective local output enable inputs of the two or more controllable local output buffers; wherein a first output of one controllable bus buffer of the series-connected string is connected to an input of a subsequent controllable bus buffer of the series-connected string, and the enable controller sequentially enables each controllable bus buffer in the series-connected string of two or more controllable bus buffers such that each node is driven according to a bus sequence by the first enable signal.

2. A micro display device according to claim 1, wherein the enable controller is configured to maintain each controllable bus buffer as enabled when a next subsequent controllable bus buffer is enabled.

3. The micro display device of claim 1, wherein the enable controller is a state machine.

4. The micro display device of claim 1, wherein the enabling controller is a code driven processor.

5. The micro display device of claim 1, wherein each controllable local output buffer outputs a high impedance state when not enabled.

6. The micro display device of claim 1, wherein each controllable local output buffer outputs a fixed logic state when not enabled.

7. A micro display device according to claim 1, wherein the one or more columns of the pixel array include one or more DACs, such that the controllable local output buffer drives at least one DAC.

8. The micro display device of claim 1, wherein the enable controller sequentially enables each controllable local output buffer so that each of the one or more columns of the pixel array is driven according to a local output sequence.

9. A micro display device according to claim 8, wherein the bus sequence is related to the local output sequence.

10. The microdisplay device of claim 1, wherein the two or more controllable bus buffers include a first controllable bus buffer having an input for receiving a column data signal.

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