A memristor and its preparation method and application

Abstract

The present invention discloses a memristor and its preparation method and application. The memristor includes a top electrode, a resistive switching layer and a bottom electrode arranged in sequence from top to bottom. The bottom electrode is a silicon-containing substrate, and the resistive switching layer is a natural oxide layer formed on the surface of the silicon-containing substrate. The memristor in the present invention uses a natural oxide layer as the resistive switching layer. The natural oxide layer is formed by natural oxidation in air and has the advantages of thin thickness, almost perfect contact interface with the silicon-containing substrate, smooth surface at the atomic level, no need for artificial preparation, low cost, and compatibility with complementary metal oxide semiconductor processes. It overcomes the technical prejudice generally believed in the field that the natural oxide layer on the surface of the silicon-containing substrate is not conducive to the performance of the memristor. In addition, the memristor in the present invention has three properties: excellent data retention capability, high stability, and analog switching characteristics.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic devices, and in particular to a memristor and a preparation method and application thereof. Background Art

[0002] A memristor is a device whose electrical conductance can be modulated by an electric field. It consists of a three-layer structure: a top electrode, a resistive switching layer, and a bottom electrode. Similar to the presynaptic membrane, synaptic cleft, and postsynaptic membrane of a synapse, it is considered an ideal device for simulating synapses. A common memristor is the metal cation memristor (ECM). This device typically consists of three layers: an active metal top electrode layer (such as Ag or Cu), a resistive switching layer (such as SiOx or TaOx), and an inert bottom electrode layer (such as Au, Pt, or doped Si). When a positive voltage is applied to the top electrode of the device, the active metal is injected into the insulating layer to form a metal conductive filament (CF) connecting the top and bottom electrodes, causing the device to enter a low-resistance state (LRS). This process is known as the SET process. When a reverse voltage is applied to the top electrode, the metal ions migrate in the opposite direction, breaking the conductive filament and returning the device to a high-resistance state (HRS). This process is known as the RESET process. Due to the relatively low activation energy of active metals, ECM devices offer fast switching speeds, low switching voltages, and a high current-to-switching ratio. However, the low activation energy of active metals can also lead to diffusion-induced fracture of the CF when no bias is applied, resulting in a short retention time of the device's LRS. Because the formation and fracture of CFs in the resistive switching layer are random, ECM devices also commonly suffer from poor cycling stability and large variability between devices. Furthermore, artificially fabricated resistive switching layers are generally thick, making the device prone to overshoot when subjected to a forward bias. This instantaneous formation of a single, robust CF in the resistive switching layer causes the device to abruptly shift from HRS to LRS, failing to simulate the continuous weight changes of synapses. This is one of the factors that limits the application of ECM devices in brain-inspired computing. Overall, ECM devices generally suffer from short data retention times, poor stability, and abrupt switching characteristics. Furthermore, the resistive switching layers of existing ECM devices are fabricated through methods such as physical deposition, chemical deposition, and solution spin coating, resulting in complex manufacturing processes and high costs.

[0003] To improve the data retention time of ECM devices, some researchers inserted a layer of graphene two-dimensional material with nanopore defects between the active metal top electrode and the resistive switching layer. Although the data retention time of the device was improved, the device still exhibited abrupt switching characteristics. At the same time, the cumbersome operation and high failure rate of the two-dimensional material transfer process made this method temporarily difficult to further large-scale application. To improve the cyclic stability of ECM devices, some researchers used multilayer two-dimensional material PdSe2 as the resistive switching layer material and created grain boundaries in the PdSe2 material through electron beam etching. The presence of grain boundaries can prevent the CF from completely diffusing away during the RESET process. The CF remaining in the grain boundaries can serve as a skeleton to guide the growth of CF during the next round of SET process. Therefore, the cyclic stability of the ECM device has been improved, but the device still exhibits abrupt switching characteristics. To achieve analog switching characteristics in ECM devices, some researchers have directly doped nanoscale active metal clusters into the resistive switching layer. When a forward voltage is applied to the device, the metal clusters migrate, forming multiple thin CFs in the resistive switching layer rather than a single, robust CF. The formation and breaking of each CF only contributes a portion of the overall conductance change. This method achieves analog switching characteristics in ECM devices, but the thin CFs may result in poor data retention. In short, existing technologies can only enable ECM devices to possess one of the three characteristics of high stability, long data retention time, and analog switching characteristics, but cannot simultaneously achieve high stability, long data retention time, and analog switching characteristics. Summary of the Invention

[0004] In order to overcome the problems existing in the prior art, one of the objectives of the present invention is to provide a memristor.

[0005] A second object of the present invention is to provide a method for preparing a memristor.

[0006] A third object of the present invention is to provide an application of a memristor.

[0007] The inventive concept of this invention is as follows: During the fabrication of existing memristors, the native oxide layer formed on a silicon-containing substrate is first removed by chemical methods, and then a resistive switching layer is formed on the silicon-containing substrate. When the inventors used the native oxide layer as the resistive switching layer, they unexpectedly discovered that the native oxide layer and the silicon-containing substrate form a nearly perfect contact interface. The native oxide layer has an atomically smooth surface and is ultra-thin. This ultra-thin resistive switching layer can suppress the formation of a single CF, allowing multiple CFs to form. This results in a memristor that combines high stability, long data retention, and analog switching characteristics.

[0008] In order to achieve the above object, the technical solution adopted by the present invention is:

[0009] A first aspect of the present invention provides a memristor comprising a top electrode, a resistive switching layer and a bottom electrode arranged in sequence from top to bottom, wherein the bottom electrode is a silicon-containing substrate, and the resistive switching layer is a natural oxide layer formed on the surface of the silicon-containing substrate.

[0010] Preferably, the natural oxide layer is silicon oxide.

[0011] Preferably, the natural oxide layer is SiO x , x is 0.6~0.8.

[0012] Preferably, the method for forming the natural oxide layer is to place the silicon substrate in an atmospheric environment with a temperature of 20-25°C and a humidity of 70%-80% for natural oxidation for 5-10 days, until the thickness of the oxide layer stabilizes. Because the formation of the natural oxide layer has a self-limiting effect, that is, when the external environmental conditions are relatively fixed, the thickness of the natural oxide layer will be relatively fixed and will not oxidize further. Under the above-mentioned environmental conditions, the thickness of the natural oxide layer formed on the surface of the silicon substrate is 2.7±0.2nm, and the surface of the formed natural oxide layer is atomically smooth.

[0013] Preferably, the thickness of the natural oxide layer is 0.1 to 4 nm; more preferably, the thickness of the natural oxide layer is 1 to 4 nm; even more preferably, the thickness of the natural oxide layer is 2 to 3 nm; even more preferably, the thickness of the natural oxide layer is 2.5 to 3 nm; even more preferably, the thickness of the natural oxide layer is 2.7 nm ± 0.1 nm. If a natural oxide layer of different thickness is required, the oxidation conditions are adjusted. Under different oxidation conditions, the thickness of the natural oxide layer obtained is also different. For example, if a natural oxide layer with a thickness of less than 2.7 nm is required, the ambient humidity and temperature are reduced. If a thickness greater than 2.7 nm is required, the ambient humidity and temperature are increased. Since the formation of the natural oxide layer has a self-limiting effect, the thickness of the naturally formed natural oxide layer will not exceed 4 nm.

[0014] Preferably, the silicon-containing substrate includes at least one of a doped p-type silicon-containing substrate and a doped n-type silicon-containing substrate; further preferably, the silicon-containing substrate is a doped p-type silicon-containing substrate; still further preferably, the silicon-containing substrate is at least one of a lightly doped p-type silicon-containing substrate and a heavily doped p-type silicon-containing substrate; more preferably, the silicon-containing substrate is a heavily doped p-type silicon-containing substrate.

[0015] Preferably, the heavily doped p-type silicon-containing substrate is at least one of a boron-doped silicon substrate, a gallium-doped silicon substrate, and an aluminum-doped silicon substrate; further preferably, the heavily doped p-type silicon-containing substrate is a boron-doped silicon substrate.

[0016] Preferably, the resistivity of the silicon-containing substrate is 0.009 to 0.015 Ω·cm; further preferably, the resistivity of the silicon-containing substrate is 0.012 to 0.015 Ω·cm.

[0017] Preferably, the top electrode is a noble metal electrode layer.

[0018] Preferably, the noble metal electrode layer is a gold-silver composite electrode layer.

[0019] Preferably, the mass ratio of gold to silver in the gold-silver composite electrode layer is 1:(0.01-1); further preferably, the mass ratio of gold to silver in the gold-silver composite electrode layer is 1:(0.05-0.2); and even more preferably, the mass ratio of gold to silver in the gold-silver composite electrode layer is 1:(0.08-0.12). When the mass ratio of gold to silver in the gold-silver composite electrode layer is 1:(0.08-0.12), the data retention time performance and cycle stability performance of the memristor are optimal.

[0020] Preferably, the gold-silver composite electrode layer comprises silver nanoclusters and a gold coating layer, and the silver nanoclusters are located in the gold coating layer; further preferably, the silver nanoclusters are located in the gold coating layer near the resistive switching layer.

[0021] After thermally evaporating a gold-silver composite electrode layer onto the resistive switching layer, the inventors tested the performance of the memristor and found that the gold-silver composite electrode layer can further improve the data retention capability of the memristor. The inventors' research found that the gold-silver composite electrode layer is composed of active Ag nanoclusters and an inert Au coating layer. When a positive voltage is applied, the inert Au metal will not enter the resistive switching layer, while the active Ag metal will enter the resistive switching layer to form CFs. In other words, the barrier effect of Au limits the number of CFs formed by Ag injection into the resistive switching layer. Because the number of CFs is reduced, the size of each CF increases in order to achieve the corresponding conductivity state. Larger CFs are less likely to break due to diffusion, resulting in the memristor having excellent data retention capability. Furthermore, the increased size of the CF leads to more residual Ag nanoparticles in the resistive switching layer after the RESET process. These residual Ag nanoparticles not only serve as a framework to guide the growth of the CF during the next SET process, but also act similarly to built-in electrodes, effectively reducing the effective thickness of the native oxide layer as the resistive switching layer. This reduction in the effective thickness of the resistive switching layer increases the conductance of the memristor at high resistance, thereby mitigating the problem of sudden changes in the memristor's conductance, thus enabling the memristor to behave like an analog switch. By combining a gold-silver composite electrode layer with the native oxide layer, the robustness of each CF in the resistive switching layer is increased, effectively forming a suitable number and robustness of CFs in the resistive switching layer, thereby achieving a memristor with high stability, long data retention, and analog switching characteristics.

[0022] Preferably, the particle size of the silver nanoclusters is 20 to 80 nm.

[0023] A second aspect of the present invention provides a method for preparing the memristor provided in the first aspect of the present invention, comprising the following steps:

[0024] forming a native oxide layer on a surface of a silicon-containing substrate;

[0025] The memristor is manufactured by thermally evaporating the noble metal material of the noble metal electrode layer onto the native oxide layer.

[0026] Preferably, the pressure of the thermal evaporation is 1×10 -3 ~3×10 -3 Pa; further preferably, the pressure of the thermal evaporation is 2×10 -3 ~3×10 -3 Pa; further preferably, the pressure of the thermal evaporation is 2.5×10 -3 Pa.

[0027] Preferably, the thermal evaporation is performed on an evaporation boat.

[0028] Preferably, the noble metal material of the noble metal electrode layer is placed on an evaporation boat, and the silicon-containing substrate with the resistive switching layer is placed above the evaporation boat, with the resistive switching layer facing the evaporation boat.

[0029] Preferably, the resistive switching layer is located 8 to 12 cm above the evaporation boat; further preferably, the resistive switching layer is located 9 to 11 cm above the evaporation boat.

[0030] The third aspect of the present invention provides an application of the memristor provided in the first aspect of the present invention in a memory or a brain-like computing chip.

[0031] The present invention has the following advantages: the memristor employs a native oxide layer as the resistive switching layer. This layer offers advantages such as a nearly perfect interface with the silicon substrate, an atomically smooth surface, no need for manual fabrication, low cost, and compatibility with CMOS (complementary metal oxide semiconductor) processes. This overcomes the common technical prejudice that native oxide layers on silicon substrates are detrimental to memristor performance. Furthermore, the memristor exhibits excellent data retention, high stability, and analog switching characteristics.

[0032] In addition, compared with the artificially synthesized resistive switching layer, the natural oxide layer in the present invention is ultra-thin and will not experience overshoot when subjected to a forward bias, thereby avoiding the instantaneous formation of a single, robust CF.

[0033] The memristor of the present invention adopts a simple thermal evaporation method to form a gold-silver composite electrode layer on the resistive layer of the memristor. The manufacturing process is simple, easy to operate, low in cost, environmentally friendly, and the preparation method is highly repeatable and stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of the structure of the memristor in Examples 1 to 4;

[0035] Figure 2 Flow chart for preparing the memristor in Examples 1 to 4;

[0036] Figure 3 TEM image of the cross section of the memristor in Example 3;

[0037] Figure 4 is an AFM image of the native oxide layer in Example 3;

[0038] Figure 5 Schematic diagram of the change in morphology of the conductive filaments inside the resistive layer when the memristor switches between high and low resistance states in Example 3;

[0039] Figure 6 is a graph showing the relationship between the conductance and retention time of the memristor in Example 3 in different low-resistance states;

[0040] Figure 7 is a graph showing 100 consecutive IV cycles of the memristor in Example 3;

[0041] Figure 8 FIG1 is a diagram showing the switching ratio fluctuation of the memristor in Example 3 during 100 consecutive IV cycles;

[0042] Figure 9 This is a diagram showing the turn-on voltage fluctuation of the memristor in Example 3 during 100 consecutive IV cycles;

[0043] Figure 10 : This is the cumulative probability distribution diagram of the turn-on voltage of 80 memristors in Example 3;

[0044] Figure 11 : This is the cumulative probability distribution diagram of the high and low resistance state conductance of the 80 memristors in Example 3;

[0045] Figure 12 is a graph showing 100 consecutive IV cycles of the memristor in Example 1;

[0046] Figure 13 is a graph showing the relationship between the conductance and retention time of the memristor in Example 1 in different low-resistance states;

[0047] Figure 14is a graph showing 100 consecutive IV cycles of the memristor in Example 2;

[0048] Figure 15 is a graph showing the relationship between the conductance and retention time of the memristor in Example 2 in different low-resistance states;

[0049] Figure 16 is a graph showing 100 consecutive IV cycles of the memristor in Example 4;

[0050] Figure 17 is a graph showing the relationship between the conductance and retention time of the memristor in Example 4 in different low-resistance states;

[0051] Figure 18 is a graph showing 100 consecutive IV cycles of the memristor in Comparative Example 1;

[0052] Figure 19 Continuous conductance regulation characteristic diagram of the memristor in Example 3;

[0053] Figure 20 Element distribution diagram of the gold-silver composite electrode layer in Example 3;

[0054] Figure 21 Element distribution diagram of the memristor in Example 3. DETAILED DESCRIPTION

[0055] The following is a detailed description of the specific implementation of the present invention with reference to the accompanying drawings and examples, but the implementation and protection of the present invention are not limited thereto. It should be noted that if there are processes that are not specifically described in detail below, they can be implemented or understood by those skilled in the art with reference to the existing technology. Explanation of terms in the present invention: ECM is a metal cation memristor; LRS is a low resistance state; HRS is a high resistance state; CF is a conductive filament; the sudden change in the conductivity of the memristor is a characteristic that cannot be continuously adjusted; the analog type is a characteristic that the conductivity of the memristor can be continuously adjusted.

[0056] The structural diagram of the memristor in Examples 1 to 4 is shown in FIG. Figure 1 The natural oxide layer on the memristor in Examples 1 to 4 is formed under the following environmental conditions:

[0057] The formation process of the natural oxide layer is as follows: the p++-Si substrate is exposed to the atmospheric environment for 7 days. At this time, the air humidity is 78% and the temperature is 21.8±0.5℃. The oxygen in the air contacts the surface of the p++-Si substrate, and the oxygen molecules slowly react with silicon atoms to form an initial SiOx layer. Since the initial SiOx layer prevents oxygen from directly contacting the surface of the p++-Si substrate, the subsequent oxidation process is that oxygen diffuses through the initial SiOx layer to oxidize the inner layer. However, the naturally formed initial SiOx layer is uniform and dense, with good shielding properties, so the natural oxidation process will not continue. In the atmospheric environment of Guangzhou, the thickness of SiOx formed on the surface of the p++-Si substrate is 2.7±0.2nm.

[0058] Example 1

[0059] The memristor in this example includes a top electrode 1, a resistive switching layer 2, and a bottom electrode 3, which are arranged in sequence from top to bottom. The top electrode 1 is a gold-silver composite electrode layer, the bottom electrode 3 is a boron-heavily doped p-type silicon-containing substrate (p++-Si substrate), and the resistive switching layer 2 is a natural oxide layer formed on the boron-heavily doped p-type silicon-containing substrate with a layer thickness of 2.7nm±0.2nm. The resistivity of the boron-heavily doped p-type Si substrate is 0.015Ω.cm.

[0060] The method for preparing the memristor in this example includes the following steps:

[0061] The p++-Si substrate with the natural oxide layer was placed upside down 10 cm above the thermal evaporation boat, with the natural oxide layer facing the evaporation boat. A 2.5 mg Ag block and a 50 mg Au block were placed in the thermal evaporation boat. The chamber pressure of the thermal evaporation coating instrument was adjusted to 2.5×10 -3 After the temperature reaches 0.05 Pa, the evaporation boat is heated to 1062℃ at a heating rate of 1000℃ / min and maintained for about 10s until the Ag block and the Au block are melted and fully mixed to form Ag and Au melts. Then the temperature of the evaporation boat is further increased to 1132℃ at a heating rate of 100℃ / s and maintained for about 20s until the Ag and Au melts are completely evaporated to the natural oxide layer (SiO x ) surface. Since the evaporation temperature of Ag is lower than that of Au, Ag will evaporate to the natural oxide layer (SiO x ) surface, and then Au fills the gaps between the Ag nanoclusters to form a gold-silver nanocomposite conductive layer.

[0062] Example 2

[0063] The memristor in this example includes a top electrode 1, a resistive switching layer 2, and a bottom electrode 3, arranged in sequence from top to bottom. The top electrode 1 is a gold-silver composite electrode layer, the bottom electrode 3 is a boron-heavily doped p-type silicon-containing substrate (p++-Si substrate), and the resistive switching layer 2 is a natural oxide layer formed by air oxidation on the boron-heavily doped p-type silicon-containing substrate. The layer thickness is 2.7 nm ± 0.2 nm, and the resistivity of the boron-heavily doped p-type Si substrate is 0.015 Ω·cm.

[0064] The method for preparing the memristor in this example includes the following steps:

[0065] The p++-Si substrate with the natural oxide layer was placed upside down 10 cm above the thermal evaporation boat, with the natural oxide layer facing the evaporation boat. A 3.3 mg Ag block and a 50 mg Au block were placed in the thermal evaporation boat. The chamber pressure of the thermal evaporation coating instrument was adjusted to 2.5×10 -3 After the temperature reaches 0.05 Pa, the evaporation boat is heated to 1062℃ at a heating rate of 1000℃ / min and maintained for about 10s until the Ag block and the Au block are melted and fully mixed to form Ag and Au melts. Then the temperature of the evaporation boat is further increased to 1132℃ at a heating rate of 100℃ / s and maintained for about 20s until the Ag and Au melts are completely evaporated to the surface of the natural oxide layer (SiOx). Since the evaporation temperature of Ag is lower than that of Au, Ag will evaporate to the natural oxide layer (SiOx) first. x ) surface, and then Au fills the gaps between the Ag nanoclusters to form a gold-silver nanocomposite conductive layer.

[0066] Example 3

[0067] The memristor in this example includes a top electrode 1, a resistive switching layer 2, and a bottom electrode 3, arranged in sequence from top to bottom. The top electrode 1 is a gold-silver composite electrode layer, the bottom electrode 3 is a boron-heavily doped p-type silicon-containing substrate (p++-Si substrate), and the resistive switching layer 2 is a natural oxide layer formed by air oxidation on the boron-heavily doped p-type silicon-containing substrate. The layer thickness is 2.7 nm ± 0.2 nm, and the resistivity of the boron-heavily doped p-type Si substrate is 0.015 Ω·cm.

[0068] The method for preparing the memristor in this example includes the following steps:

[0069] The p++-Si substrate with the natural oxide layer was placed upside down 10 cm above the thermal evaporation boat, with the natural oxide layer facing the evaporation boat. A 5 mg Ag block and a 50 mg Au block were placed in the thermal evaporation boat. The chamber pressure of the thermal evaporation coating instrument was adjusted to 2.5×10 -3After the temperature reaches 0.05 Pa, the evaporation boat is heated to 1062℃ at a heating rate of 1000℃ / min and maintained for about 10s until the Ag and Au blocks are melted and fully mixed to form Ag and Au melts. Then the temperature of the evaporation boat is further increased to 1132℃ at a heating rate of 100℃ / s and maintained for about 20s until the Ag and Au melts are completely evaporated to the surface of the natural oxide layer (SiOx). Since the boiling point of Ag is lower than that of Au, Ag will evaporate to the natural oxide layer (SiOx) first. x ) surface, and then Au fills the gaps between the Ag nanoclusters to form a gold-silver nanocomposite conductive layer.

[0070] Example 4

[0071] The memristor in this example includes a top electrode 1, a resistive switching layer 2, and a bottom electrode 3, arranged in sequence from top to bottom. The top electrode 1 is a gold-silver composite electrode layer, the bottom electrode 3 is a boron-heavily doped p-type silicon-containing substrate (p++-Si substrate), and the resistive switching layer 2 is a natural oxide layer formed by air oxidation on the boron-heavily doped p-type silicon-containing substrate. The layer thickness is 2.7 nm ± 0.2 nm, and the resistivity of the boron-heavily doped p-type Si substrate is 0.015 Ω·cm.

[0072] The method for preparing the memristor in this example includes the following steps:

[0073] The p++-Si substrate with the natural oxide layer was placed upside down 10 cm above the thermal evaporation boat, with the natural oxide layer facing the evaporation boat. A 10 mg Ag block and a 50 mg Au block were placed in the thermal evaporation boat. The chamber pressure of the thermal evaporation coating instrument was adjusted to 2.5×10 -3 After the temperature reaches 0.05 Pa, the evaporation boat is heated to 1062℃ at a heating rate of 1000℃ / min and maintained for about 10s until the Ag and Au blocks are melted and fully mixed to form Ag and Au melts. Then the temperature of the evaporation boat is further increased to 1132℃ at a heating rate of 100℃ / s and maintained for about 20s until the Ag and Au melts are completely evaporated to the surface of the natural oxide layer (SiOx). Since the boiling point of Ag is lower than that of Au, Ag will evaporate to the natural oxide layer (SiOx) first. x ) surface, and then Au fills the gaps between the Ag nanoclusters to form a gold-silver nanocomposite conductive layer.

[0074] The preparation flow chart of the memristor in Examples 1 to 4 is shown in Figure 2 shown.

[0075] Comparative Example 1

[0076] In this example, a memristor with a thicker SiOx layer is prepared using traditional thermal oxidation. The specific preparation method is as follows:

[0077] A p++-Si substrate was placed in a tubular annealing furnace and thermally oxidized at 680°C for 1 minute in a pure oxygen atmosphere. The temperature was ramped at 10°C / min and cooled naturally. The resulting SiOx layer had a thickness of approximately 20 nm. The top electrode 1 was prepared using the same method as in Example 3, resulting in a memristor with a structure consisting of a gold-silver composite electrode layer, a thermally oxidized SiOx layer, and a p++-Si substrate.

[0078] Performance testing:

[0079] (1) Morphology test:

[0080] Figure 3 This is a cross-sectional TEM image of the memristor prepared in Example 3. Figure 3 It can be seen that a native oxide layer (SiOx) with a thickness of 2.7nm±0.2nm is naturally formed on the p++-Si substrate. There is an almost perfect contact interface between the native oxide layer (SiOx) and the p++-Si. In contrast, when the resistive switching layer is artificially made, the contact interface between SiOx and the silicon substrate can easily be damaged due to factors such as the preparation process. Excessive contact defects will lead to a significant decline in the performance of the memristor. Figure 4 The AFM image of the natural oxide layer in Example 3 is shown in FIG. Figure 4 As can be seen in the figure, the root mean square roughness (RMS) of the native oxide layer (SiOx) is as low as 0.253nm. The atomically smooth native oxide layer (SiOx) on the resistive switching layer surface is beneficial for the uniformity of memristor performance. In contrast, artificially fabricated resistive switching layers, especially those produced by spin coating, have difficulty ensuring consistent roughness across different regions of the film. Using a native oxide layer (SiOx) as the resistive switching layer for memristors also offers the advantages of low cost, no need for additional artificial preparation, and compatibility with complementary metal oxide semiconductor (CMOS) processes. Currently, when fabricating memristors using doped Si substrates as the bottom electrode, those skilled in the art generally believe that the native oxide layer (SiOx) on the Si substrate surface is detrimental to memristor fabrication. Therefore, they first remove the native oxide layer (SiOx) through chemical etching, followed by the deposition of a separate resistive switching layer. The present invention directly utilizes the native oxide layer (SiOx) as the resistive switching layer, overcoming this technical bias in memristor fabrication.

[0081] (2) Data retention capability test:

[0082] Figure 5This is a schematic diagram of the change in the morphology of the conductive filaments inside the resistive layer when the memristor in Example 3 switches between high and low resistance states. The Ag conductive filaments originate from the Ag nanoclusters in the gold-silver composite electrode layer, and the Ag nanoclusters are blocked by the Au filling layer. Therefore, the number of Ag conductive filaments formed in the native oxide layer (SiOx) will be limited. In order to successfully enter the low resistance state, the size of each CF will become relatively larger. A more robust CF is not easily broken due to Ag diffusion. Therefore, the memristor in Example 3 of the present invention has excellent data retention capability. Figure 6 is a diagram showing the relationship between the conductance and retention time of the memristor in Example 3 in different low-resistance states, Figure 6 It can be seen that the memristor in Example 3 exhibits a data retention capability of more than 1 hour in different low-resistance states.

[0083] (3) Cyclic stability test:

[0084] The more robust CF in the resistive switching layer of the present invention will also cause more Ag nanoparticles to remain in the native oxide layer (SiOx) of the memristor after the RESET process. The residual Ag nanoparticles can act as a skeleton to guide the growth of CF during the next SET process. Figure 5 As shown in FIG. 3 , the growth of the CF of the resistive switching layer in the present invention is more controllable rather than random. Figures 7 to 9 As shown, the memristor in Example 3 was subjected to 100 consecutive current (I)-voltage (V) cycles, and then its switching ratio fluctuation and turn-on voltage fluctuation were tested. The test results showed that the switching ratio fluctuation (standard deviation Δ / mean μ) was as low as 31.14%, and the turn-on voltage fluctuation was as low as 7.63%. The memristor in Example 3 of the present invention exhibited excellent cycling stability.

[0085] In addition, the differences between different batches of memristors are also very low. According to the preparation method of the memristor in Example 3, two batches of memristors were made, with 40 memristors in each batch, for a total of 80 memristors. Then, the cumulative probability distribution of the turn-on voltage and the cumulative probability distribution of the high and low resistance state conductance of the 80 memristors were tested. The test results are as follows: Figure 10 and Figure 11 As shown in the figure, the switching ratio fluctuation and turn-on voltage fluctuation of the 40 memristors in the first batch are 19.58% and 7.04% respectively, and the switching ratio fluctuation and turn-on voltage fluctuation of the 40 memristors in the second batch are also as low as 10.33% and 10.00%, indicating that the guiding effect of the residual Ag nanoparticles in the resistive layer gives the memristor excellent cycling stability and stability between memristor production batches.

[0086] The memristor in Example 1 was subjected to 100 consecutive IV cycles, and the test results are shown in FIG. Figure 12 As shown, from Figure 12It can be seen that the degree of overlap of each cycle curve is not high, that is, the cycle stability is worse than that of Example 3. Then the data retention time of the memristor in Example 1 in different low resistance states is tested. The specific test results are shown in Figure 13 As shown by Figure 13 It can be seen that: as time goes by, the conductivity of each resistance state decays, that is, the data retention time performance deteriorates relative to Example 3. The reason for the poor performance of the memristor in Example 1 is that the mass of Au in the gold-silver composite electrode layer is 50 mg, the mass of Ag is 2.5 mg, and the mass ratio of Au:Ag is 1:0.05. At this time, the Ag content is too small, and the size and number of Ag nanoclusters in the gold-silver composite electrode layer are too low. In theory, a smaller number of Ag nanoclusters will make the conductive filaments formed in the resistive layer more robust. However, since the size of the Ag nanoclusters is also reduced, it is insufficient to provide enough silver atoms to form sufficiently robust conductive filaments. Therefore, Figure 12 and Figure 13 As shown, the cycle stability and data retention time performance of the memristor in Example 1 are both reduced.

[0087] The memristor in Example 2 was subjected to 100 consecutive IV cycles, and the test results are shown in FIG. Figure 14 As shown, from Figure 14 It can be seen that the degree of overlap of each cycle curve is not very high, that is, the cycle stability is worse than that of Example 3. Then the data retention time of the memristor in Example 2 in different low resistance states is tested. The specific test results are shown in Figure 15 As shown by Figure 15 It can be seen that: as time goes by, the conductivity of some resistance states decays, that is, the data retention time performance deteriorates relative to Example 3. The reason for the poor performance of the memristor in Example 2 is that the mass of Au in the gold-silver composite electrode layer is 50 mg, and the mass of Ag is 3.3 mg. At this time, the Ag content is relatively small, and the size and number of Ag nanoclusters in the gold-silver composite electrode layer are relatively low. In theory, a smaller number of Ag nanoclusters can form more robust conductive filaments in the resistive layer. However, since the size of the Ag nanoclusters is also reduced, it is insufficient to provide enough silver atoms to form sufficiently robust conductive filaments. Therefore, Figure 14 and Figure 15 As shown, the cycle stability and data retention time performance of the memristor in Example 2 are reduced.

[0088] The memristor in Example 4 was subjected to 100 consecutive IV cycles, and the test results are shown in FIG. Figure 16 As shown, from Figure 16 It can be seen that the degree of overlap of each cycle curve is not very high, that is, the cycle stability is worse than that of Example 3. Then the data retention time of the memristor in Example 4 in different low resistance states is tested. The specific test results are shown in Figure 17As shown by Figure 17 It can be seen that: as time passes, the conductivity of each resistance state decays, that is, the data retention time performance deteriorates relative to Example 3. The reason for the poor performance of the memristor in Example 4 is that the mass of Au in the gold-silver composite electrode layer is 50 mg, and the mass of Ag is 10 mg. Relatively speaking, the proportion of Ag content is still relatively large, and the size and number of Ag nanoclusters in the gold-silver composite electrode layer are still relatively large, that is, the ability of the Au coating layer to limit the number of Ag conductive filaments is still relatively weak. When the memristor is working, the number of conductive filaments formed in the resistive switching layer is still large and relatively thin. Therefore, Figure 16 and Figure 17 As shown, the cycle stability and data retention time performance of the memristor in Example 4 are both worse than those in Example 3.

[0089] The memristor in comparative example 1 was subjected to 100 consecutive IV cycles, and the test results are shown in FIG. Figure 18 As shown, when the resistive switching layer becomes thicker, even if a gold-silver composite electrode layer is used as the top electrode, the memristor will still exhibit abrupt switching characteristics and poor cycling stability. A thicker resistive switching layer will negate the role of the gold-silver composite electrode layer in forming robust conductive filaments in the resistive switching layer. This is because the conductive filaments in the resistive switching layer increase in length and become less robust. Therefore, after the reset process, the number of residual Ag nanoparticles in the resistive switching layer decreases, and they cannot form a skeleton to guide the subsequent growth of conductive filaments, resulting in a decrease in the cycling stability of the memristor. Moreover, the small number of residual Ag nanoparticles cannot effectively reduce the effective thickness of the resistive switching layer, and the conductance of the memristor in the high-resistance state cannot be regulated. Therefore, the memristor in Comparative Example 1 exhibits abrupt switching characteristics.

[0090] Comparing the cycling stability and data retention performance of the memristors in Examples 1 to 4 shows that the Ag content in the gold-silver composite electrode layer must be moderate, and the ratio of Ag to Au must be within an appropriate range. Too much or too little Ag can affect the performance of the memristor. Overall, the cycling stability of Examples 1 to 4 is significantly improved compared to Comparative Example 1.

[0091] (4) Analog switch characteristic test:

[0092] Since the thickness of the native oxide layer (SiOx) is ultra-thin, the residual Ag nanoparticles can effectively regulate the effective thickness of the native oxide layer (SiOx) as the resistive switching layer. Therefore, the gradual growth or breakage of CF can gradually increase or decrease the overall conductance of the memristor. Figure 19As shown, when 50 SET voltage pulses (4V, 1ms) and 50 RESET voltage pulses (-3V, 1ms) are continuously applied to the memristor in Example 3 of the present invention, the conductance of the memristor can continuously increase or decrease, that is, the memristor exhibits analog switching characteristics.

[0093] (5) Element distribution test:

[0094] The EDS element distribution diagram of the gold-silver composite electrode layer in test example 3 is shown in FIG. Figure 20 ,Depend on Figure 20 It can be seen that in the gold-silver composite electrode layer, the Au coating layer is wrapped around the Ag nanoclusters.

[0095] TEM image and EDS element distribution diagram of the memristor in test embodiment 3, see Figure 21 ,Depend on Figure 21 It can be seen that there are both Ag and Au elements above the SiOx layer (see Figure 21 This further confirms that the Ag nanoclusters are located in the Au coating layer and are close to the resistive switching layer.

[0096] While the embodiments of the present invention have been described in detail above, the present invention is not limited to the embodiments described above. Various modifications may be made within the scope of knowledge possessed by a person skilled in the art without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof may be combined with one another unless there is a conflict.

Claims

1. A memristor, characterized in that: The invention comprises a top electrode, a resistive switching layer and a bottom electrode arranged in sequence from top to bottom, wherein the bottom electrode is a silicon-containing substrate, the resistive switching layer is a natural oxide layer formed on the surface of the silicon-containing substrate; the natural oxide layer is silicon oxide; the thickness of the natural oxide layer is 0.1 to 4 nm; the top electrode is a noble metal electrode layer; the noble metal electrode layer is a gold-silver composite electrode layer; the gold-silver composite electrode layer comprises silver nanoclusters and a gold coating layer, and the silver nanoclusters are located in the gold coating layer near the resistive switching layer.

2. The memristor according to claim 1, wherein: The natural oxide layer is SiO x , x is 0.6~0.

8.

3. The memristor according to claim 1, wherein: The mass ratio of gold to silver in the gold-silver composite electrode layer is 1:(0.01-1).

4. The method for preparing a memristor according to any one of claims 1 to 3, characterized in that: The following steps are involved: forming a native oxide layer on a surface of a silicon-containing substrate; The memristor is manufactured by thermally evaporating the noble metal material of the noble metal electrode layer onto the native oxide layer.

5. Application of the memristor according to any one of claims 1 to 3 in a memory or a brain-like computing chip.

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