Non-volatile memory circuit that can serve as the main memory access for a processing circuit

Abstract

A non-volatile storage circuit (22) is provided as a main storage accessible to a processing circuit (4), such as a register, a cache, a scratchpad memory, a TLB, or an on-chip RAM. When information stored in a given area (149) of the non-volatile storage circuit is not in use, a power control circuit (147) powers down the given area. This provides more frequent opportunities for energy saving compared to using volatile storage to implement the main storage.

Description

Background Art Technical Field

[0001] The present technology relates to the field of data processing. Technical Background

[0003] A data processing device may have a processing circuit that performs data processing in response to instructions. The processing circuit may refer to a main storage circuit when performing its data processing. Summary of the Invention

[0004] At least some examples provide an apparatus that includes:

[0005] A processing circuit configured to perform data processing in response to instructions;

[0006] A non-volatile storage circuit that can be accessed by the processing circuit as a main storage; and

[0007] A power control circuit configured to power off a given area when information stored in the given area of the non-volatile storage circuit is not in use.

[0008] At least some examples provide an apparatus that includes:

[0009] Means for performing data processing in response to instructions;

[0010] Means for non-volatile storage as a main storage, the non-volatile storage being accessible by the means for performing data processing; and

[0011] Means for powering off a given area when information stored in the given area of the means for non-volatile storage is not in use.

[0012] At least some examples provide a data processing method that includes:

[0013] Using a processing circuit to perform data processing in response to instructions;

[0014] Accessing a non-volatile storage circuit as a main storage of the processing circuit; and

[0015] Powering off a given area when information stored in the given area of the non-volatile storage circuit is not in use.

[0016] Further aspects, features, and advantages of the present technology will be apparent from the following description of examples read in conjunction with the drawings. Brief Description of the Drawings

[0017] Figure 1 An example of a data processing system is shown;

[0018] Figure 2 Shows an example where each of a plurality of threads processed by a processing circuit has a corresponding thread - specific register storage area implemented using non - volatile storage;

[0019] Figure 3 Shows an example having a thread - specific cache path implemented using non - volatile storage;

[0020] Figure 4 Shows an example of providing a thread - specific area of random access memory (RAM) using non - volatile storage;

[0021] Figure 5 Shows an example of control logic for controlling whether a region of non - volatile main storage is powered on or off according to the activity of a processing circuit;

[0022] Figure 6 Shows an example of powering off the storage area of a given thread when the thread stops;

[0023] Figure 7 Shows an example of a region in non - volatile storage for storing states associated with different operating states;

[0024] Figure 8 Shows examples of different subsets of architectural registers that can be implemented using non - volatile storage such that they can be powered off when processing program code that does not require that particular subset of registers;

[0025] Figure 9 Shows the use of non - volatile storage for storing context associated with a hardware thread; and

[0026] Figure 10 Is a flowchart showing a method of controlling power - on and power - off of a region of a non - volatile storage circuit used as main storage by a processing circuit. Detailed Description

[0027] A computing system may have a processing circuit that performs data processing in response to instructions. The system may have a storage circuit for storing data. Computing storage is generally considered to include primary storage and secondary storage. Primary storage stores the program code and working data of software processed by the processing circuit. For example, primary storage may include registers for storing the architectural state of the processing circuit, cache memory, on-chip random access memory (RAM), and other storage structures directly accessible by the processing circuit, such as a translation lookaside buffer (TLB). In contrast, secondary storage provides a large storage capacity for storing data and program code that is not related to the program currently being processed and has not been specifically requested for access by the processing circuit, but is retained for potential future use. Generally, secondary storage cannot be directly accessed by the processing circuit, but can be accessed using an input / output channel. Thus, when the processing circuit needs to execute a given software, the program code and working data of the software can be copied from secondary storage to primary storage before the processing circuit begins to execute the software. During software execution, the processing circuit may generate additional data that can be temporarily stored in primary storage while the software is being executed. When the program execution of a given software is completed, if any data generated by the software needs to be retained, that data needs to be written to secondary storage, otherwise the data may be overwritten in primary storage when other software is being executed on the processing circuit.

[0028] The storage circuit can be volatile or non-volatile. Volatile storage circuits can be implemented using technologies such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). If power is not supplied to the memory cells, the volatile storage circuit will eventually lose the information it stores. In contrast, a non-volatile storage circuit can retain its information even when the power to the memory cells is cut off. Examples of non-volatile memory storage include flash memory, ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), etc.

[0029] Access to a volatile storage circuit is generally much faster than access to a non-volatile storage circuit. For the primary storage of a processing circuit that needs to be frequently accessed on an instruction-by-instruction basis, volatile storage technologies such as SRAM are typically used. Non-volatile storage is generally considered unsuitable for use as primary storage because the access speed of non-volatile storage is considered too slow for use as primary storage.

[0030] However, the present inventors recognize that non-volatile storage technologies are becoming available that can begin to provide access speeds and endurance levels that are suitable for some application areas even when used as main storage. For example, non-volatile memory technologies such as correlated electron random access memory (CeRAM) can provide higher access speeds than previous non-volatile memory technologies. Also, even with other slower forms of non-volatile memory technology, it is recognized that with the increasing expansion of the Internet of Things, there is an increasing demand for low processing power devices that do not require a high level of performance but do require higher energy efficiency, as they can be powered by batteries or ambient energy harvesting and thus have an extremely limited energy budget. For such application areas, performance is not the primary criterion, and thus, even at the cost of lower performance, it is attractive from an energy saving perspective to use non-volatile memory storage as main storage. Accordingly, it is proposed to use non-volatile memory as the main storage of a processing circuit rather than just as auxiliary storage.

[0031] By using a non-volatile storage circuit as the main storage of a processing circuit, this provides a greater opportunity for energy savings compared to the case of using a volatile storage circuit to implement main storage. Accordingly, a power control circuit is provided to power down a given area of the non-volatile (main) storage circuit when the information stored in that given area is not being used.

[0032] In a typical data processing system, all program code and working data sets associated with a thread for which processing has started but not yet terminated will need to be retained in a volatile storage circuit such as SRAM, and even when a particular thread is not actively issuing instructions or reading / writing its data, this volatile storage circuit will consume a significant amount of power while continuing to power the SRAM cells storing the code / data. In a typical system, once a thread is initialized by writing its working data and instructions to main storage, the data and instructions associated with that thread will continue to be stored in volatile main storage until the thread is deactivated.

[0033] Conversely, when a non-volatile storage circuit is used as the main storage, it means that when a thread has been initialized and not yet terminated and is generally being processed, during a relatively short time window when the thread is not actively issuing instructions or reading / writing its data, the area of the non-volatile storage circuit that stores the code / data for that thread can be powered off. Compared with the case of using a volatile storage circuit, using non-volatile storage for the main storage makes it practical to power on and off areas of the main storage on a more frequent basis. This is because the non-volatile storage circuit continues to maintain its state even when not powered on. Thus, when powering off a given area of the non-volatile main storage circuit, there is no need to save the data to a powered-on area or auxiliary storage for possible future use. Generally, state save and restore operations (for copying data to another location and restoring it when needed again later) can result in significant latency and power, which limits the frequency of powering off traditional volatile storage. Conversely, by using non-volatile storage as the main storage, this avoids the state save / restore latency, and thus it is feasible to turn off storage areas more frequently. This can significantly reduce the total power consumption of the processing circuit and the main storage.

[0034] When powering off a given area of a non-volatile storage circuit used as the main storage, the power control circuit can ignore saving the information stored in the given area to a powered-on storage area of a volatile or non-volatile storage circuit or to auxiliary storage. This is not possible for main storage implemented using volatile memory technology.

[0035] The power control circuit can power off a given area of the non-volatile storage circuit while the processing circuit continues to perform active data processing in response to instructions. Thus, when processing continues on the processing circuit, it is still possible to power off the area of the main storage that stores information not used for a given period.

[0036] The information stored in the powered-off given area of the non-volatile storage circuit can include working data or instructions related to an active thread that has not yet terminated. The working data and instructions of an active non-terminated thread typically need to be retained in a volatile storage circuit until the thread terminates, which would require the storage units storing that information to be powered on. By instead using a non-volatile storage circuit as the main storage for the processing circuit, this allows information related to non-terminated threads to be retained in powered-off storage when not currently being used by the processing circuit.

[0037] It should be understood that not all of the main storage of the processing circuit needs to be implemented using a non-volatile storage circuit. There may also be some volatile storage circuits that can be provided to provide faster access to specific information. However, by implementing at least some of the main storage using a non-volatile storage circuit, this can significantly reduce power consumption by providing more opportunities to power off regions of the main storage in a relatively short period of time without incurring overhead during execution of state save and restore.

[0038] The non-volatile storage circuit can be the main storage directly accessible by the processing circuit on an instruction-by-instruction basis.

[0039] A non-volatile storage circuit can be used to implement various types of main storage. For example, the non-volatile storage circuit can be used as a register for storing the architectural state of the processing circuit, as a cache, as a scratchpad memory, as a prediction structure for storing prediction states, and / or as a random access memory serving as the main storage, where the prediction states are used to control speculative execution of instructions by the processing circuit. The prediction structure can include a branch prediction structure, a data prefetcher structure, an instruction prefetcher structure, or other predictive mechanisms for controlling speculative execution. The cache can be a data cache, an instruction cache, or a cache of control information, such as a translation lookaside buffer (TLB) for caching address translation data. The scratchpad memory can be a data scratchpad memory or an instruction scratchpad memory.

[0040] In one example, the processing circuit can directly obtain operands for executing instructions from the non-volatile storage circuit and directly store the results of the executed instructions into the non-volatile storage circuit. For example, the non-volatile storage circuit can be used as registers of the processing circuit that are directly accessed by the execution units of the processing circuit to obtain the required operands and write back the results of the executed instructions. This approach is very counterintuitive to those skilled in the art because non-volatile storage is generally considered too slow for directly reading instruction operands or directly writing instruction results. However, the inventors recognize that with newer non-volatile storage technologies and the growing demand for processing systems that can operate with a very low power budget regardless of performance cost, providing some registers that use non-volatile storage can be useful such that they can be powered on and off quickly without state save and restore to provide more energy-saving opportunities.

[0041] In one example, a power control circuit can control whether a given region of a non-volatile memory circuit is in a powered-on state or a powered-off state on a per-cycle basis. For example, in each cycle, the power control circuit can detect whether there is a request to read or write information in the given region or any other reason why the given region needs to be powered on, and in cycles where there is no requirement to use the information in the given region, the given region can be powered off. Thus, by using a non-volatile memory circuit for main storage, this enables more frequent power-off decisions to be made on a per-cycle basis, which is not practical for volatile memory circuits.

[0042] In one example, the processing circuit can be a multi-threaded processor that can support the processing of instructions from two or more different execution threads. The non-volatile memory circuit can include two or more thread-specific storage regions, each thread-specific storage region dedicated to storing information associated with the corresponding thread processed by the processing circuit. By providing thread-specific storage regions, this makes it more efficient to manage the power-off of regions of the non-volatile memory when the information is not being used.

[0043] For example, although multiple threads may all be in progress, have been initialized by the operating system, and have not terminated, and thus the processing circuit needs to retain the working data and instructions for each of these threads, at any given time, not all threads may be actively issuing instructions to the execution units of the processing circuit or requiring read or write services in the main memory. When a given thread is not actively issuing instructions or reading or writing data, and there is no other reason to maintain power to the respective storage regions of that thread, then the respective storage regions of that thread can be powered off to save energy.

[0044] Thus, when none of the multiple power-on conditions are met for a given thread, the power control circuit can control the given thread-specific storage region associated with the given thread to be in a powered-off state during the cycle. If any of these power-on conditions occur for the given thread in a particular cycle, the storage region of the corresponding thread is powered on. For example, the power-on conditions can at least include:

[0045] · The given thread or a supervisory process that needs to access the given thread-specific storage region. Thus, when the given thread (or the supervisory process that supervises the thread) needs to access the given thread-specific storage region, then that region is powered on; and

[0046] · In response to a memory access initiated in an earlier cycle, returning information to be written to the given thread-specific storage region. Thus, if information has been returned from the memory in response to an earlier issued read / load request, the corresponding thread-specific storage region can be powered on to allow the loaded information (data or instructions) to be written to the storage region of the thread.

[0047] Another example of a power-up condition can be a situation where there is a request for an access address from an external source (external to the processing circuitry), where the address corresponds to information stored in a thread-specific storage area associated with a thread, and for which the power-up condition would not otherwise be satisfied. For example, if a second processing element requests an address of information stored in a given thread-specific storage area, then that storage area may need to be powered up to allow the external request to be serviced.

[0048] It should be understood that there may also be other power-up conditions that, for a given thread, can cause respective storage areas of the non-volatile main storage of that thread to be powered up.

[0049] On the other hand, during a period in which no power-up condition occurs for a given thread, the thread-specific storage area of that thread can be powered down to save energy. The power-up / power-down of the thread-specific storage area can occur at relatively short intervals, even at the granularity of a single cycle, since using non-volatile storage means that no state save / restore operations are required.

[0050] Thread-specific storage areas can be implemented for many different types of main storage. For example, these can be thread-specific collections of register storage for storing sets of architectural state associated with different threads. Also, the thread-specific storage area can be a region of a cache (e.g., a cache way), or a thread-specific region within on-chip RAM.

[0051] In some examples, when multiple active threads including a given thread are being executed, only the given thread is allowed access to its own thread-specific storage area, and other processes are not allowed access to the thread-specific storage area of the given thread.

[0052] In other embodiments, the given thread associated with a given thread-specific storage area may not be the only software process capable of accessing the non-volatile storage area, since a supervisory process for supervising the given thread may be allowed access to the thread-specific storage area associated with the given thread. For example, the supervisory process can be an operating system that supervises the execution of multiple applications, or a hypervisor that supervises the execution of multiple guest operating systems or virtual machines. Thus, when multiple active threads including a given thread are being processed, the thread-specific storage area associated with the given thread can be accessed by the given thread itself, but not by active threads other than the given thread. On the other hand, when the supervisory process for supervising the given thread is being processed, the thread-specific storage area for any thread being supervised by the supervisory process can be accessed by the supervisory process.

[0053] In addition to the thread-specific storage area, the device may further include a shared storage area of the main storage, which can be accessed by more than one thread. The shared storage area can be implemented using volatile storage circuitry or non-volatile storage circuitry. In some cases, since the shared storage area can be expected to be accessed more frequently than the thread-specific storage area because the shared storage area can be accessed by any thread, it may be desirable to use volatile storage circuitry for the shared area because the likelihood of not requiring the shared storage area is low, and this can improve performance by reducing access time. Alternatively, if power saving is a more important consideration, non-volatile storage can also be used to implement the shared storage area to allow further power saving by powering it down when it is not required by any thread.

[0054] For the thread-specific storage area of non-volatile storage used as register storage, this enables the storage circuitry for storing the architectural state data of the thread to be powered down during periods when the corresponding thread is not actively issuing instructions or reading from or writing to its architectural state, thereby saving energy.

[0055] In an example where the non-volatile storage circuitry includes a cache containing the thread-specific storage area, when the thread-specific storage area for a given thread is powered down and the area stores dirty information (the dirty information is different from the corresponding data at the same address saved in a subsequent level of the memory system), there is no need to write the dirty information back to the memory. This is because, unlike volatile storage, when the non-volatile storage area is powered down, the dirty information will be retained, so if the processing element later attempts to access the same address, the given thread-specific storage area can be powered up again to allow access to the dirty information, which provides the latest version of the data associated with the specified address. By avoiding the write-back to the underlying memory, this can reduce the memory bandwidth requirement and save power.

[0056] For the cache example, in response to a request issued by another processing element other than the processing circuitry, when the request specifies an address corresponding to the information in the currently powered-down thread-specific storage area, the thread-specific storage area of the cache can be powered up to allow the external request to be serviced. For example, the external request can be a snoop request issued according to a coherence protocol in response to an access to the specified address triggered by another processing element. The receipt of such an external request can be one of the power-up conditions for determining when the thread-specific storage area of the cache needs to be powered up.

[0057] In some examples, a non-volatile storage circuit may have multiple hardware thread storage areas, each hardware thread storage area for storing context information associated with a corresponding one of the multiple hardware threads, and a processing circuit may support processing instructions of at least one active thread selected from the multiple hardware threads. The maximum number of supported active threads may be less than the maximum number of supported hardware threads.

[0058] For example, the processing circuit may have a register storage (implemented using volatile or non-volatile storage) for storing the architectural state of a single thread or multiple threads. Instructions related to the active threads whose architectural state is stored in the register storage may be allowed to be fetched for processing. However, the non-volatile storage circuit (as main storage, e.g., RAM) may store context information of a certain number of hardware threads, the number being greater than the number of active threads (one or more) supported by the processing circuit. A thread scheduler may select which of the hardware threads are scheduled as active threads.

[0059] When a context switch occurs from a first thread to a second thread, the register state of the first thread may be copied from the registers to the hardware thread storage area associated with the first thread in non-volatile storage, and the register state of the second thread may be copied from the hardware thread storage area associated with the second thread to the registers. The hardware thread storage areas may be powered down when not needed. For example, during a cycle of saving the hardware thread state to a given hardware thread storage area or restoring the hardware thread state from a given hardware thread storage area, the given hardware thread storage area may be powered on, but the given thread storage area may be powered down during other cycles.

[0060] If a volatile storage technology such as SRAM is used to implement the hardware thread storage areas, this will tend to limit the maximum number of supported hardware threads because maintaining the set of context information for each thread will result in power consumption when powering on the SRAM cells storing the context of that thread, even when that thread is not selected as one of the active threads. In contrast, by using non-volatile storage for the hardware thread storage areas, for a given power budget, this allows the maximum number of hardware threads to be much larger because when there is no context-switching of hardware threads, there is no need to maintain power to the hardware thread storage areas, but the contents of those areas can still be maintained.

[0061] Sometimes, when processing a given execution thread, the processing circuitry may encounter a stop event that indicates that the thread cannot proceed until the stop event is resolved. In a typical processing system, the architectural state, working data, and instructions of a given thread may be stored in registers, caches, or other structures implemented using volatile storage, and this information will need to be preserved for when processing of the thread can continue after the stop has been resolved. And if the period during which the thread is stopped is too short to justify state save / restore, then typically the storage areas that store the state / instructions / data of the thread will remain powered during the thread stop. Thus, typical processing systems do not take advantage of energy-saving opportunities to power down the information areas that store information associated with a given thread when resolving a stop event.

[0062] In contrast, when using non-volatile storage to implement the main storage of a processor, since state save is not required, it is much faster to power down the memory, and thus when a given thread encounters a stop event, the power control circuitry can power down at least a portion of the area of the non-volatile storage circuitry that stores information associated with the stopped thread until the stop can be resolved. This can achieve more frequent energy-saving windows when a thread stops. If each thread has its own thread-specific storage area in the non-volatile storage circuitry, then this approach can be particularly useful as it makes it more straightforward to identify which portion of the non-volatile storage can be powered down when a given thread is stopped.

[0063] For example, the stop event can be any one or more of the following: a memory access that requires a wait time longer than a given threshold; a miss in a given level of cache; a memory access that requires access to data stored in secondary storage; an event indicating that a given thread is waiting for a synchronization variable (such as a lock) to indicate that the given thread is allowed to access a shared variable, where exclusive access to the shared variable is controlled based on the synchronization variable; an event indicating that a given thread is waiting to receive a message from another thread; and a given thread executing a wait event instruction. All of these events can cause the thread to stop for a period of time during which the thread cannot proceed until the stop event is resolved. Thus, these events provide an opportunity for energy savings by powering down the area of non-volatile storage that stores the instructions / data or architectural state of the stopped thread.

[0064] Another energy-saving opportunity can be in a system where a processing circuit supports processing instructions in one of multiple operating states. For example, the processing circuit can have operating states with different privilege levels, and different software processes can execute at the corresponding privilege levels. For example, application-level software can execute in the lowest-privilege operating state, operating system or virtual machine software can execute in a higher-privilege operating state, and hypervisor software for managing virtual machines or operating systems can operate in an even higher-privilege operating state. Generally, each software process executing in a different operating state can have its own working data set, instruction set, and architectural register state. In a typical system using volatile main storage, when switching between operating states, all information associated with the respective operating states needs to be retained in powered storage cells. If any registers are shared for access across different operating states, some form of state save / restore may be required when switching operating states.

[0065] However, by using non-volatile memory main storage, this means that the instructions, working data, and / or architectural state associated with processes executing in different operating states can be maintained in corresponding regions of non-volatile storage, which can be easily powered on / off without state save / restore while still retaining the information. When the processing circuit is processing instructions in the current operating state, the power control circuit can power off the regions of the non-volatile storage circuit that store information associated with at least one operating state other than the current operating state. Thus, power can be saved by powering off the storage regions that store the state associated with exception levels or other operating states other than the current operating state.

[0066] In another example, energy savings can be provided by powering off non-volatile storage that stores a subset of the architectural state that is not currently needed for a given thread or the thread being processed. For example, while the instruction set architecture supported by the processing circuit can define a certain number of registers for storing architectural state data that must be provided in hardware, not all of these registers may be used by a particular program. For example, the registers can include floating-point registers or vector registers, or certain types of control states, which are not needed by all programs (these are just some examples). Thus, for a given subset of program code that does not use the registers, the power control circuit can power off the corresponding regions of non-volatile storage while the program code is being actively processed. Even if these registers are still storing the register state that may be needed by an earlier part of the program code or other execution threads, these regions can be powered off because the state will be retained in non-volatile storage, and thus there is no need to save the state to memory before powering off the registers.

[0067] Thus, in general, a non-volatile storage circuit may include registers for storing the architectural state of a processing circuit, and in response to a thread or a portion of a thread that does not require a subset of the architectural state, a power control circuit may power down the region of the non-volatile storage that stores that subset of the architectural state.

[0068] When a thread or a portion of a thread does not require a corresponding region of non-volatile storage, the subset of the architectural state for which the corresponding region may be powered down may include at least one of the following: a floating-point register state for storing floating-point values or a floating-point control state for controlling the processing of floating-point values; a vector register state for storing vector values or a vector control state for controlling vector value processing; a control register state for initializing and controlling system functions; a status register state including an indication of historical events (e.g., exceptions, errors, and / or performance indications); and a control register state including control information for an operating state other than the current operating state.

[0069] The power control circuit may determine in different ways whether a particular thread or a portion of a thread requires a particular subset of the architectural state. In one example, the power control circuit may make this decision based on hint information specified by the program code for the thread or the portion of the thread. For example, the program code may be annotated by a compiler such that the machine binary code of the program code includes an indication of whether the program will use a particular subset of the architectural state. The power control circuit may use this hint to control powering down of a given subset of registers when not needed. Alternatively, rather than identifying at compile time whether registers are used, the processing circuit may have a monitoring circuit for collecting monitoring information about the operation of a given thread. Thus, a decision on whether to continue powering a given register set of an active thread may be made based on the monitoring information collected by the monitoring circuit at runtime about previous instances of the executing thread or that portion of the thread.

[0070] The techniques discussed above may be applied to main storage used by a main processing element such as a CPU (central processing). However, the non-volatile storage circuit may also be used for a main storage structure (e.g., registers, caches, or TLBs) in a coprocessor or a hardware accelerator to which the main processor may offload specific processing functions that can be executed more efficiently by the coprocessor or the hardware accelerator. For example, a coprocessor or a hardware accelerator may have custom hardware dedicated to executing certain processing functions faster than using general-purpose instructions on the main processor. For example, a coprocessor or a hardware accelerator may be a graphics processor, a floating-point processor dedicated to floating-point operations, a vector processor dedicated to executing vector operations, or a hardware accelerator for specific tasks such as cryptographic operations, digital signal processing, artificial intelligence, data compression, regular expression search, etc.

[0071] Accordingly, during cycles in which the main processor does not use the coprocessor or hardware accelerator, the power control circuit can power down the main storage structure of the coprocessor or hardware accelerator. In a system where volatile storage is used for coprocessor or hardware accelerator storage, if the coprocessor or hardware accelerator is being stopped from use and no longer needs to store any active state, the storage can be powered down only. In the present technology where non-volatile storage is used to implement the main storage structure of the coprocessor hardware accelerator, registers / caches / TLBs, etc. of the coprocessor or hardware accelerator can be powered down for a short time when not effectively used by the main processor, even if the coprocessor or hardware accelerator will continue to process in future cycles and the state needs to be retained. Thus, even during a relatively short inactive window, the hardware accelerator or coprocessor storage can be turned off to save energy.

[0072] It should be understood that some of the techniques discussed above, such as powering down regions of storage that store information associated with threads that are not currently issuing instructions or reading / writing memory, powering down storage regions that store information associated with subsets of unused registers, or powering down storage regions associated with processes operating in an operating state other than the current operating state, can also be applied to hardware accelerators or coprocessors, and not just to main processors such as CPUs.

[0073] Figure 1 An example of a data processing system 2 is schematically shown, which has a plurality of processing elements, including a main processing element (CPU) 4 and a hardware accelerator / coprocessor 12. The processing elements 4, 12 perform data processing in response to instructions. The CPU 4 includes a plurality of internal main storage units, which include a register file 6 for storing architectural state, an instruction cache 8 for storing instructions fetched from the memory system, and a data cache 10 for storing data from the memory system. A hardware accelerator / coprocessor 12 can be provided for performing dedicated processing functions according to the requirements of the CPU 4, such as graphics operations, vector processing, floating-point operations, cryptographic operations, etc. The accelerator 12 also includes a register file 16 and a cache 18.

[0074] The CPU 4 and the accelerator 12 share access to a plurality of shared storage units, which include a level 2 cache 20 and a random access memory (RAM) 22 accessible via an internal bus 24. If a data request misses in the shared level 2 cache, data can be fetched from a main memory 26 accessed via a memory controller 28 coupled to a memory bus 30. The processing elements 4, 12 can also access auxiliary storage via an input / output channel 32, which can be accessed via a bus bridge 34 coupled to the internal bus 24.

[0075] Register files 6, 16, caches 8, 10, 18, 20, and RAM 22 are all examples of main storage that can be accessed by the CPU 4 or the hardware accelerator 12 on an instruction-by-instruction basis. In addition to Figure 1 the storage types shown in, other examples of main storage units that can be non-volatile include translation lookaside buffers (TLBs) for caching address translation data from the memory system, or scratchpad memories that can be accessed by the CPU in a manner similar to instruction data caches 8, 10, but unlike caches, scratchpad memories do not implement a replacement policy, such that data assigned to an address mapped to a scratchpad memory will remain stored in the scratchpad memory until explicitly rewritten by the processor, rather than being dynamically replaced in the cache based on recency of use or some other cache allocation policy. Also, the main storage unit can include a predictive storage structure for storing predictive states that are used to predict aspects of program execution (such as branch outcomes, branch target addresses, data / instruction fetch addresses, etc.), and this program execution can be used to perform speculative operations before the actual behavior is known. For example, the predictive storage structure can be a branch prediction state storage, a prefetch state storage, etc.

[0076] Accordingly, the main storage is used to store the instructions, working data, and architectural state required to support execution during program run-time, as well as any control data used by the pipeline to control program execution, such as address translation state and predictive state. In contrast, the secondary storage accessible via the input / output channel 32 is used for long-term backup storage of information that has not been specifically requested by the CPU / accelerator to be copied into the main storage, such as code / data related to currently unexecuted programs and data defining user items not currently needed, such as images, documents, etc.

[0077] In the technologies discussed in this application, at least some of the main storage units 6, 8, 10, 16, 18, 20, 22 can be implemented using non-volatile memory storage. This provides an opportunity to quickly remove power from these non-volatile storage units without losing the information stored in these non-volatile storage units, thus achieving greater energy savings. Subsequent examples illustrate many potential uses of non-volatile storage circuits as the main storage of a processor.

[0078] Figure 2Shows an example of the registers and execution units of a multi-threaded processing element 4 that supports executing instructions from a certain number of threads 0 to n. The processing element 4 has multiple thread-specific register storage areas 40 and thread-specific instruction queues 42, each dedicated to an individual thread. The instruction queues 42 and register files 40 of the respective threads can be implemented using non-volatile storage circuits. The multi-threaded processor maintains multiple instances of the complete architectural state for each ongoing thread. For some specific implementations, the number of threads supported at one time can be relatively high, such as up to 32 or 64 threads. In a typical system, the set of architectural states for each thread can be stored in volatile storage such as SRAM. Even though the registers within the pipeline in the CPU itself cannot store all the sets of thread states, however, the volatile storage within the cache or RAM can be used to store the states related to the ongoing initialized threads, and this volatile storage consumes power to maintain the set of architectural states for each thread even when the ongoing thread is not currently issuing any instructions or reading / writing to the volatile storage.

[0079] Compared with such a typical system, Figure 2 Shows a method in which non-volatile storage blocks 40, 42 are used as the register file and instruction queue for each thread. This means that when a given thread is not actively issuing instructions or reading / writing data, the register file 40 and instruction queue 42 of the given thread can be powered off only to save power when not in immediate use (while the thread still remains ongoing and the state / instructions of the thread still need to be retained). A non-volatile power control circuit 44 can be provided to control the timing at which the respective segments of the main storage for a given thread are powered on or off. The timing of powering on / off the non-volatile thread-specific storage areas 40, 42 for each thread can be controlled on a per-cycle basis, even supporting power-off windows as short as a few clock cycles, which is not possible for volatile storage. This provides a greater opportunity for energy savings.

[0080] Therefore, Figure 2 Shows an example where the non-volatile storage includes some storage areas 40 from which the execution unit 46 directly obtains the operands of the instructions being executed, and the results of those executed instructions are directly written back to these storage areas via the result bus 48. In a typical system, such storage would be implemented using volatile storage, but here it is implemented using non-volatile storage.

[0081] In summary, in a multi-threaded processor, the state of each thread may be located in a non-volatile memory block 40 or a "state block", including any register file, program counter, stack pointer, etc. Each thread has a state block 40, so there will be multiple state blocks, one for each thread. When a thread is issuing an instruction, or when an instruction is writing a result to the state block, or when a load unit is transferring an operand to the thread, or when a monitoring process needs to access the state block, the state block of that thread is powered on. For any cycle in which none of these events occur (or any other event that requires access to the state block of the thread), the state block may be powered off.

[0082] Figure 3 Another example is shown using non-volatile storage as the main storage of the processing circuit. In this example, the caches 8, 10, 18, 20 of the CPU 4 or the hardware accelerator or coprocessor 12 may be implemented using multiple thread-specific storage areas (restricted cache paths) 50, each thread-specific storage area dedicated to an individual thread and implemented using non-volatile storage. In addition, the caches 8, 10, 18, 20 may also include some common cache paths 52, which are shared among the threads and may be implemented using non-volatile or volatile storage. In a cycle where a given thread is not currently accessing the cache and there is no other reason to maintain access to the specific storage area 50 of the given thread (e.g., no request from monitoring software to access the cache or access caused by an external agent), the storage area 50 of the thread may be powered off by the non-volatile power control circuit 54 to save energy. Even if the information stored in the individual areas of the thread is dirty (which is different from the underlying data at the same address from another location in the memory system), the thread-specific storage area 50 may be powered off anyway without performing any cleaning of the dirty data on the memory system, which saves energy and reduces the bandwidth on the memory channel. Even when powered off, if another process or external agent requests access to the address of the dirty data in the powered-off storage area 50, the access request or snoop request for that address may cause the corresponding thread-specific storage area 50 to be powered on again to access the dirty data, because the dirty data will be preserved in the non-volatile storage area even when not powered. Therefore, by avoiding unnecessary cleaning operations, this can also provide further energy savings and also free up memory bandwidth for other accesses.

[0083] In summary, in a multi-threaded processor, each thread may access one or more shared cache regions 52 of volatile or non-volatile memory and a separate non-shared cache 50 of non-volatile memory dedicated to that specific thread (also referred to herein as an "exclusive thread cache"). During any cycle in which the exclusive thread cache 50 is not accessed by the thread or by a monitoring process, the exclusive thread cache is powered off.

[0084] For data that needs to be accessed by multiple threads, the provision of the shared cache 52 can be more efficient because this avoids replicating the shared data in the exclusive thread caches 50 of multiple threads.

[0085] A similar approach can be used for the TLB or other address translation caches for caching address translation data (e.g., page table entries) from memory. That is, Figure 3 the cache in the example of can be a TLB. A shared TLB may or may not be included. The exclusive thread translation cache 50 of a given thread can be powered off during any cycle when the thread is not performing a memory access that requires translation, there is no request for a TLB maintenance operation that would require accessing the exclusive translation cache, and there is no supervisor process that needs to access the exclusive thread translation cache 50.

[0086] Similarly, a similar approach can be used for the prediction structures of the processor core 4, such as branch prediction tables, data or instruction prefetch tables, or other prediction mechanisms. Such a prediction mechanism can maintain a storage structure that stores the prediction state, which is updated based on the actual results of the instructions executed by the processor core 4 and is used to predict the results of these instructions before the actual instruction behavior of the fetched instructions is known. In a manner similar to Figure 3 the cache example of, the prediction structure can be divided into thread-specific regions 50 implemented in non-volatile memory, and when a given thread is not currently issuing instructions or reading / writing the prediction state, the thread-specific region 50 associated with the given thread can be powered off. When the thread-specific region 50 is powered off, the corresponding prediction state remains in the non-volatile storage region when a prediction is needed for the given thread for use in subsequent cycles, so powering off the thread-specific region that stores the prediction does not affect performance or prediction success rate. This provides another opportunity for energy savings.

[0087] Although a shared region 52 for predictive storage may be provided in addition to the thread-specific regions 50, this is not necessary and may not be preferred because, unlike the cache example, for predictive storage, the benefits of sharing the prediction state between threads can be less because the prediction behavior can be very different for the same address in different execution threads. Thus, in some embodiments, the prediction state storage may not have a shared region 52.

[0088] In a similar manner, Figure 4An example is shown of how on-chip RAM 22 is partitioned into exclusive thread memory 60 that can only be accessed by associated threads or supervisor processes and shared RAM 62 that can be accessed by any of a plurality of threads. In a manner similar to the cache example, during cycles in which the exclusive thread memory 60 for a particular thread is not being accessed by the associated thread or supervisor process, the non-volatile power control circuit 64 can power down that region of the exclusive thread memory 60 to save power. However, when threads need to interact using shared data, the common RAM bank 62 can be used.

[0089] In Figure 3 and Figure 4 's example, when the exclusive regions 50, 60 of a given thread of the cache or memory have been powered down, multiple events can cause the regions to be powered up again by the power control circuits 54, 64. These events can include read / write requests issued by the thread associated with the thread-specific regions 50, 60 or by the supervisor access, or can include requests received from an external source such as another processing element or external device that specify the address of information stored in the thread-specific regions 50, 60. For example, the external request can be a snoop request issued according to a coherence protocol. Also, other examples of events that cause power up can be an external interrupt, or a notification that a message has been received from an external agent.

[0090] Thus, as Figure 5 shown, Figures 2 to 4 the non-volatile power control circuits 44, 54, 64 in the example of can receive a plurality of inputs 68 for controlling whether a given region of non-volatile storage is in a powered-up state or a powered-down state. It should be understood that the powered-up and powered-down states can be any two of two or more power states supported by the non-volatile storage region, where the storage circuit consumes less power in the powered-down state than in the powered-up state. In some cases, there can be more than two power states associated with different power consumption levels, and the control inputs 68 can be used to control the transition between any two of these states. In some examples, the powered-down state can be a state in which power supply to the non-volatile storage region is cut off.

[0091] The control inputs may include a global power control signal that indicates whether there is any active processing at a corresponding processing element, and if there is no active processing at all, this global power control signal may be used to power down the corresponding storage area. Additionally, the power control input 68 may include signals indicating thread-specific events, such as a thread execution control signal indicating which threads are actively issuing instructions, and a thread load control signal indicating which threads are requesting load / store operations to load information from or store information to the cache or memory. Another input may be a data return signal indicating which threads have data returned from the memory system in response to an earlier load operation issued by the thread. Based on the various control inputs 68, the power control circuits 44, 54, 64 generate power output control signals 70 that are sent to the non-volatile storage itself and any read / write ports used to interact with the storage to control whether those elements are powered on or off. The power control logic 44, 54, 64 may control on a per-cycle basis whether the non-volatile storage area is powered on or off such that the storage area may be powered down for a relatively small number of cycles at a time, where, for example, rapid transitions between powered-on and powered-off states occur based on the per-instruction activity of each individual thread.

[0092] In other examples, it may be preferable to not incur the overhead of detecting the per-cycle activity of individual threads, but rather to control power-on / power-off at a coarser granularity. For example, the main storage structure may be powered down in response to certain stop events during the processing of a given thread, where these stop events indicate that the thread is unlikely to progress for some period of time. Thus, as Figure 6 shown, when processing a given thread X and encountering a stop event at point 100, the non-volatile storage area of the main storage that stores information associated with thread X may be powered down. When the stop is resolved at point 102, the thread storage may then be powered on again.

[0093] For example, the stop event may be any of the following events:

[0094] · Thread X issues a memory access request that results in a miss in a certain level of cache (e.g., a miss in the level 2 shared cache 20, requiring access to the slower memory 26, or a miss in the TLB of the processor core 4, thus requiring a page table walk to extract address translation data from memory);

[0095] · A memory access that requires a wait time longer than a given threshold;

[0096] · A memory access that requires access to data in secondary storage via the I / O channel 32;

[0097] · Thread X identifies a synchronization variable (e.g., a lock), indicating that another thread currently holds the lock and thus has exclusive access to the shared variable, and thus Thread X will have to wait for the other thread to release the lock before it can gain access to the shared variable;

[0098] · Thread X waits to receive a message from another thread or an external device before it can proceed with subsequent processing; and / or

[0099] · A given thread X executes a Wait for Event (WFE) instruction. When the WFE instruction is executed, the processing circuitry does not execute any other instructions of the thread until the event register indicates that one of a certain class of event types has occurred. Events that cause the event register to be set by the hardware can include the following: receiving an interrupt; for example, when debugging is enabled, issuing a debug entry request to the processor, or another processor issuing a "send event" notification.

[0100] Thus, for all these types of events and for other examples of stop events, Thread X may not be able to make any progress until the stop is resolved, so when a stop event is detected, the power control circuit can power down the region of the non-volatile main storage that stores the information of the stopped Thread X. This can be done without the need to save the internal state of Thread X to the powered-on region of the (volatile or non-volatile) storage, because the state will be preserved in the powered-down non-volatile storage region, and thus this power-down operation results in little overhead. Even if the stop is resolved immediately after the non-volatile storage region is powered down, since there is no state recovery overhead, only the non-volatile storage region needs to be powered up again, with little impact on performance.

[0101] Figure 7 Another example is shown where a non-volatile state storage block 120 is maintained for different operating states such as the Exception Level (EL). As Figure 7As shown, processing element 4 can support the processing of multiple different exception levels 110 (EL0 - EL3), which can be associated with different privilege levels (in this example, EL3 has the highest privilege and EL0 has the lowest privilege). For example, exception level EL0 can be used to execute application code, exception level EL1 can be used to execute operating system code, exception level EL2 can be used to execute hypervisor code, and exception level EL3 can be used to execute security monitor code to manage the transition between secure and less secure operating states. Each of the corresponding software processes executed at different exception levels can have its own set of architectural states, but when at any particular exception level, many of these states may not be in use because the processes at exception levels different from the current exception level are not currently issuing instructions for execution. In a typical processing system using volatile main storage, each of the sets of architectural states associated with processes in different operating states will need to be maintained in SRAM or other volatile storage, even when the processor is not currently executing software from a given exception level, so the storage of architectural states associated with processes at exception levels other than the current exception level still consumes power.

[0102] In contrast, as Figure 7 shown, non-volatile storage 120 can be used to provide multiple register state storage areas, each dedicated to storing the state of a given exception level. By this method, when processing code at, for example, exception level EL1, the registers 120 associated with EL0, EL2, or EL3 can be powered off when not in use while still maintaining the states associated with these exception levels. Note that in addition to the exception level-specific registers 120, there can be some common control registers 122 that remain powered regardless of the current exception level, and the common control registers can store the control states required for all exception levels.

[0103] Although all the examples shown above are discussed with respect to CPU 4 accessing non-volatile storage, similar examples can be used for operations performed by hardware accelerators or coprocessors. Thus, register files, caches, or other structures in a coprocessor or hardware accelerator can also benefit from being easily and quickly powered off while maintaining their contents.

[0104] As Figure 8 shown, within the register files 6, 16 of a given processing element 4, 12, there can be multiple different types of register subsets for storing specific types of architectural states. For example, the registers can include:

[0105] · Integer registers 130, which are used to store integer operands;

[0106] · A floating-point register 132 for storing floating-point operands and control status for controlling floating-point processing;

[0107] · A vector register 134 for storing vector operands including multiple data elements and for storing vector control status for controlling vector processing;

[0108] · A control register 136 for storing control status data for controlling processor operations;

[0109] · A status register 138 for storing information about historical events encountered by the processor, such as exception status information 140 about previously occurring exceptions, error status information 142 indicating any possible faults or errors that may have occurred, and performance indicators 144 for tracking the performance of the processor; and / or

[0110] · A control register 146 for storing information used by an operating state other than the current operating state.

[0111] Not all software requires Figure 8 all of the types of registers shown. For example, while most software may use integer register 130, software that does not involve any floating-point or vector processing does not need to use floating-point register 132 or vector register 134. Similarly, certain types of software may not use certain types of control status information 136 or status register 138. Also, when executing code in one operating state, the control register 146 for other operating states may not be needed.

[0112] Thus, when performing processing that does not require access to a particular subset of the architectural registers defined in the instruction set architecture according to a given execution thread (or a portion of a thread), the non-volatile storage circuit associated with the unneeded registers can be powered down while still retaining the information in those registers in case the thread later needs to access that information. The other registers used by the current thread can still be powered on.

[0113] For example, software binary code can be annotated with hint information to indicate that the software, for example, will not use floating-point register 132, and the power control circuit can use this hint to determine that it can power down the floating-point register when switching to the software. Even if other processes have previously stored information in floating-point register 132, when floating-point register 132 is powered down, it is not necessary to save the previous floating-point state to memory because non-volatile storage retains the information even during power-down. Similar examples can be applied to Figure 8 the other types of registers shown.

[0114] Moreover, in some cases, even if the software binary code is not annotated with hints, performance indicator 144 or other monitoring information can be used to track which threads or which parts of a thread are using a particular subset of registers, and this monitoring information can be used by the power control circuit to determine which registers can be powered down when not being used by a given portion of the program code to be executed.

[0115] Figure 9 Another example showing the use of non-volatile storage as the on-chip main storage is presented. In this example, non-volatile storage is used to store context information of multiple hardware threads. In this example, processing element 4 has register storage 6 for storing the architectural state (context information) of a certain number of active threads. Although not shown for the sake of brevity in Figure 9 processing element 4 may also have caches 8, 10 as shown in Figure 1 Register storage 6 can be implemented using volatile storage (such as SRAM) or non-volatile storage. If the core is a single-threaded core, register 6 can have the capacity to store the state of only a single thread at a time. Alternatively, processing element 4 can be a multi-threaded core that has register storage 6 sufficient to store multiple sets of architectural states for two or more active threads. If multi-threaded core 4 uses non-volatile storage for register storage 6, for example, this can be implemented similar to the example of Figure 6

[0116] In the Figure 9 example, the device includes an area of on-chip non-volatile main storage that is part of RAM 22, which includes multiple hardware thread areas 149 for storing context information of a specific number of hardware threads. The number of hardware thread areas 149 can be greater than the number of active threads for which register storage 6 is provided in processing element 4.

[0117] A hardware thread scheduler 148 is provided to manage which of the hardware threads is selected as the active thread to be processed by processing element 4. Any known hardware thread management scheme can be used to select which hardware thread is active. When a context switch is made from processing the first hardware thread as the active thread to processing the second hardware thread instead of the first hardware thread as the active thread, the architectural state of the first hardware thread is copied from register 6 to the hardware thread storage area 149 associated with the first hardware thread, and the architectural state of the second hardware thread is copied from the hardware thread storage area 149 associated with the second hardware thread to register 6. For a given hardware thread storage area, during cycles in which the associated hardware thread does not require state saving or restoration, the corresponding hardware thread storage area 149 can be powered down by power control circuit 147.

[0118] In summary, non-volatile storage can be used to store the hardware thread context state. For example, this allows the hardware thread scheduler 148 to coordinate hardware threads without interruption between computing cycles, and the machine can be powered off between computing cycles without losing content. The low latency and large capacity of on-chip NVRAM storage allow for a large number of resident contexts, and fast context switching is achieved by accessing the context in on-chip memory while copying the on-chip memory to the register file. In this way, the context states of more threads than can be run simultaneously can be stored on the chip, and threads can be quickly swapped in and out for execution on the processing circuit 4.

[0119] Figure 10 is a flowchart showing a method of controlling power-on or power-off of a non-volatile storage circuit used as a main storage. At step 150, data processing is performed on the processing elements 4, 12 using the non-volatile storage circuit as a main storage (e.g., register, cache, TLB, RAM, or scratchpad memory).

[0120] At step 152, the power control circuits 44, 54, 64 determine whether a given area of the non-volatile storage circuit is not being used in the current cycle. If no read / write information is required in the current cycle, the information can be considered unused even if the associated thread is still in progress. Also, if the information pertains to a stopped thread, or a subset of register states not required by a given code section, or if the corresponding thread is not currently issuing an instruction in the current cycle, the information can be considered unused. When a given area is identified as unused, then at step 154, that area of the non-volatile storage circuit is powered off. No state save operation is required at step 154 because the contents of the powered-off area will be retained even without power.

[0121] At step 156, the power control circuits 44, 54, 64 check for an event indicating that the information in a given area of the non-volatile storage is needed again, such as for a read or write operation issued by the corresponding thread, or because the stop has been resolved, or because an external request for the information in the powered-off area of the storage has been received. If a given area of the non-volatile storage is needed again, then at step 158 that area is powered on again (no state restoration to the given area is required).

[0122] In this application, the phrase "configured to..." is used to mean that an element of a device has a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device element needs to be changed in any way to provide the defined operation.

[0123] Although the exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the present invention is not limited to those exact embodiments, and various changes and modifications can be made by those skilled in the art without departing from the scope and essence of the present invention as defined by the appended claims.

Claims

1. A data processing device, the device comprising: A processing circuit for performing data processing in response to instructions; A non-volatile storage circuit that can be accessed by the processing circuit as a main storage; And A power control circuit for powering down a given area stored in the non-volatile storage circuit used as the main storage when the information in the given area is not being used; The processing circuit is configured to process instructions from multiple threads; The non-volatile storage circuit includes multiple thread-specific storage areas, each storing information associated with a corresponding one of the multiple threads; The power control circuit is configured to control the given thread-specific storage area associated with a given thread to be powered down during a cycle when multiple power-on conditions are not met; And The multiple power-on conditions at least include: The given thread or a supervision process that needs to access the given thread-specific storage area; And In response to a memory access initiated in an earlier cycle, returning information to be written to the given thread-specific storage area.

2. The device according to claim 1, wherein, The processing circuit is configured to directly obtain operands for executing instructions from the non-volatile storage circuit and directly store the results of the instructions into the non-volatile storage circuit.

3. The device according to any one of claims 1 and 2, wherein, When powering down the given area of the non-volatile storage circuit, the power control circuit is configured to ignore saving the information stored in the given area to a powered-on storage area or to an auxiliary storage.

4. The device according to claim 1, wherein, The power control circuit is configured to control whether the given area of the non-volatile storage circuit is in a powered-on state or a powered-down state on a per-cycle basis.

5. The device according to claim 1, wherein, The processing circuit is configured to use the non-volatile storage circuit as at least one of the following: A register for storing the architectural state of the processing circuit; A cache; A scratchpad memory; and A prediction structure for storing a prediction state used to control speculative execution of instructions by the processing circuit.

6. The device according to claim 1, wherein: When processing multiple active threads including a given thread, the thread-specific storage area associated with the given thread is accessible to the given thread and inaccessible to active threads other than the given thread; and When processing a supervision process for supervising the given thread, the thread-specific storage area associated with the given thread is accessible.

7. The device according to claim 1, comprising a shared storage area of the main storage that can be accessed by more than one of the plurality of threads.

8. The device according to any one of claims 1, 6 and 7, wherein, The non-volatile storage circuit includes a cache, and the cache includes the multiple thread-specific storage areas; and When powering down a given thread-specific storage area of the cache, when the given thread-specific storage area includes dirty information, the power control circuit is configured to ignore writing the dirty information back to the memory.

9. The device according to any one of claims 1, 6 and 7, wherein, The non-volatile storage circuit includes a cache, and the cache includes the multiple thread-specific storage areas; and In response to a memory access request issued by another processing element other than the processing circuit, when the request specifies an address corresponding to information in a given thread-specific storage area of the cache that has been powered off, the power control circuit is configured to power on the given thread-specific storage area to allow the request to be serviced.

10. The device according to claim 1, wherein, The non-volatile storage circuit includes a plurality of hardware thread storage areas, each hardware thread storage area for storing context information associated with a corresponding one of the plurality of hardware threads; and The processing circuit is configured to process instructions from at least one active thread selected from the plurality of hardware threads.

11. A data processing device, the device comprising: A processing circuit for performing data processing in response to instructions; A non-volatile storage circuit accessible by the processing circuit as a main storage; and A power control circuit for powering off a given area of the non-volatile storage circuit when the information stored in the given area used as the main storage is not in use, In response to a stop event occurring during the processing of instructions from a given thread, the power control circuit is configured to power off at least a portion of the area of the non-volatile storage circuit storing information associated with the given thread; and The stop event includes at least one of the following events: A memory access that requires a waiting time longer than a given threshold; A miss in a given level of cache; A memory access that requires accessing data stored in secondary storage; An event indicating that the given thread is waiting for a synchronization variable to indicate that the given thread is allowed to access a shared variable, where exclusive access to the shared variable is controlled based on the synchronization variable; An event indicating that the given thread is waiting to receive a message from another thread or an external device; and The given thread executes a wait event instruction.

12. A data processing device, the device comprising: A processing circuit for performing data processing in response to instructions; A non-volatile storage circuit accessible by the processing circuit as a main storage; and A power control circuit for powering off a given area of the non-volatile storage circuit when the information stored in the given area used as the main storage is not in use, The processing circuit is configured to process instructions in one of a plurality of operating states; and When the processing circuit processes instructions in the current operating state, the power control circuit is configured to power off the area of the non-volatile storage circuit for storing information associated with at least one operating state other than the current operating state; The non-volatile storage circuit includes registers for storing the architectural state of the processing circuit, where the architectural state includes context information; and In response to a thread or a portion of a thread that does not require a subset of the architectural state, the power control circuit is configured to power off the area of the non-volatile storage circuit for storing the subset of the architectural state; The subset of the architectural state includes at least one of the following: A floating-point register status including floating-point values or a floating-point control status for controlling the processing of the floating-point values; and A vector register status including vector values or a vector control status for controlling the processing of the vector values; A control register status for initializing and controlling system functions; A status register status including an indication of historical events; and A control register status including control information of an operation status other than the current operation status.

13. The device according to claim 12, wherein, The power control circuit is configured to determine whether the thread or the portion of the thread needs the subset of the architectural state based on at least one of the following: Hint information specified by the program code of the thread or the portion of the thread; and Monitoring information collected by the monitoring circuit regarding a previous instance of executing the thread or the portion of the thread.

14. A data processing device, the device comprising: A device for performing data processing in response to instruction execution; A device for non-volatile storage as a main storage, the non-volatile storage being accessible by the device for performing data processing; and A device for powering down a given area of the non-volatile storage used as the main storage when the information stored in the given area is not in use, The device for performing data processing is configured to process instructions from multiple threads; The device for non-volatile storage includes multiple thread-specific storage areas, each thread-specific storage area storing information associated with a corresponding thread of the multiple threads; The device for powering down a given area of the non-volatile storage is configured to control the given thread-specific storage area associated with a given thread to be in a powered-down state during a period when multiple power-on conditions are not met; and The multiple power-on conditions at least include: The given thread or a regulatory process that needs to access the given thread-specific storage area; and In response to a memory access initiated in an earlier period, return information to be written to the given thread-specific storage area.

15. A data processing method, the data processing method comprising: Using a processing circuit, perform data processing in response to instruction execution; Access a non-volatile storage circuit as the main storage of the processing circuit; and When the information stored in a given area of the non-volatile storage circuit used as the main storage is not in use, use a power control circuit to power down the given area, The processing circuit is configured to process instructions from multiple threads; The non-volatile storage circuit includes multiple thread-specific storage areas, each thread-specific storage area storing information associated with a corresponding thread of the multiple threads; The power control circuit is configured to control the given thread-specific storage area associated with a given thread to be in a powered-down state during a period when multiple power-on conditions are not met; and The multiple power-on conditions at least include: The given thread or a regulatory process that needs to access the given thread-specific storage area; and In response to a memory access initiated in an earlier period, return information to be written to the given thread-specific storage area.

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